adder_sel func added
This commit is contained in:
Laraib Khan
parent
a1acaaa217
commit
6b63669e0c
File diff suppressed because it is too large
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@ -2,37 +2,37 @@ module exu_div_cls(
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input [32:0] io_operand,
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output [4:0] io_cls
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);
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wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 775:63]
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wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 935:63]
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wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 935:63]
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wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
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@ -97,37 +97,37 @@ module exu_div_cls(
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wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
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wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
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wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
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wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 777:25]
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wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 778:76]
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wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 778:76]
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wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 778:76]
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wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 778:76]
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wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 778:76]
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wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 778:76]
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wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 778:76]
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wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 778:76]
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wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 778:76]
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wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 778:76]
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wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 778:76]
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wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 778:76]
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wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 778:76]
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wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 778:76]
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wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 778:76]
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wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 778:76]
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wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 778:76]
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wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 778:76]
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wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 937:25]
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wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 938:76]
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wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 938:76]
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wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 938:76]
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wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 938:76]
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wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 938:76]
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wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 938:76]
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wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 938:76]
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wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 938:76]
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wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 938:76]
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wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 938:76]
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wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 938:76]
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wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 938:76]
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wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 938:76]
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wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 938:76]
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wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 938:76]
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wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 938:76]
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wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 938:76]
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wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 938:76]
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wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 938:76]
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wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
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wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
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wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
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@ -190,8 +190,8 @@ module exu_div_cls(
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wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
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wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
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wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
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wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 777:44]
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assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 779:10]
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wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 937:44]
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assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 939:10]
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endmodule
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module rvclkhdr(
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input io_clk,
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@ -237,10 +237,10 @@ module exu_div_new_3bit_fullshortq(
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reg [63:0] _RAND_9;
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reg [31:0] _RAND_10;
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`endif // RANDOMIZE_REG_INIT
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wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 718:21]
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wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 718:21]
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wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 721:20]
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wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 721:20]
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wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 721:21]
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wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 721:21]
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wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 724:20]
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wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 724:20]
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wire rvclkhdr_io_clk; // @[lib.scala 390:23]
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wire rvclkhdr_io_en; // @[lib.scala 390:23]
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wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
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@ -320,15 +320,15 @@ module exu_div_new_3bit_fullshortq(
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wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 618:80]
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wire [6:0] _T_1042 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
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wire [6:0] _T_1043 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
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wire [6:0] _T_1045 = _T_1042 - _T_1043; // @[exu_div_ctl.scala 727:42]
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wire [6:0] dw_shortq_raw = _T_1045 + 7'h1; // @[exu_div_ctl.scala 727:62]
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wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 728:19]
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wire _T_1051 = ~shortq[5]; // @[exu_div_ctl.scala 729:31]
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wire _T_1052 = valid_ff & _T_1051; // @[exu_div_ctl.scala 729:29]
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wire _T_1054 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 729:58]
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wire _T_1055 = ~_T_1054; // @[exu_div_ctl.scala 729:44]
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wire _T_1056 = _T_1052 & _T_1055; // @[exu_div_ctl.scala 729:42]
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wire shortq_enable = _T_1056 & _T; // @[exu_div_ctl.scala 729:73]
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wire [6:0] _T_1045 = _T_1042 - _T_1043; // @[exu_div_ctl.scala 730:42]
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wire [6:0] dw_shortq_raw = _T_1045 + 7'h1; // @[exu_div_ctl.scala 730:62]
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wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 731:19]
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wire _T_1051 = ~shortq[5]; // @[exu_div_ctl.scala 732:31]
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wire _T_1052 = valid_ff & _T_1051; // @[exu_div_ctl.scala 732:29]
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wire _T_1054 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 732:58]
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wire _T_1055 = ~_T_1054; // @[exu_div_ctl.scala 732:44]
|
||||
wire _T_1056 = _T_1052 & _T_1055; // @[exu_div_ctl.scala 732:42]
|
||||
wire shortq_enable = _T_1056 & _T; // @[exu_div_ctl.scala 732:73]
|
||||
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 618:95]
|
||||
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 618:93]
|
||||
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||
|
|
@ -360,98 +360,98 @@ module exu_div_new_3bit_fullshortq(
|
|||
reg [32:0] r_ff; // @[Reg.scala 27:20]
|
||||
wire [36:0] _T_164 = {r_ff[32],r_ff,a_ff[32:30]}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_166 = {b_ff[34:0],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_168 = _T_164 + _T_166; // @[exu_div_ctl.scala 644:58]
|
||||
wire [36:0] _T_168 = _T_164 + _T_166; // @[exu_div_ctl.scala 647:58]
|
||||
wire [36:0] _T_170 = {b_ff[35:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_172 = _T_168 + _T_170; // @[exu_div_ctl.scala 644:85]
|
||||
wire [36:0] adder7_out = _T_172 + b_ff; // @[exu_div_ctl.scala 644:107]
|
||||
wire _T_175 = ~adder7_out[36]; // @[exu_div_ctl.scala 645:24]
|
||||
wire _T_176 = _T_175 ^ control_ff[2]; // @[exu_div_ctl.scala 645:40]
|
||||
wire _T_178 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 645:75]
|
||||
wire _T_179 = adder7_out == 37'h0; // @[exu_div_ctl.scala 645:98]
|
||||
wire _T_180 = _T_178 & _T_179; // @[exu_div_ctl.scala 645:84]
|
||||
wire _T_181 = _T_176 | _T_180; // @[exu_div_ctl.scala 645:60]
|
||||
wire _T_183 = ~_T_172[36]; // @[exu_div_ctl.scala 646:23]
|
||||
wire _T_184 = _T_183 ^ control_ff[2]; // @[exu_div_ctl.scala 646:39]
|
||||
wire _T_187 = _T_172 == 37'h0; // @[exu_div_ctl.scala 646:97]
|
||||
wire _T_188 = _T_178 & _T_187; // @[exu_div_ctl.scala 646:83]
|
||||
wire _T_189 = _T_184 | _T_188; // @[exu_div_ctl.scala 646:59]
|
||||
wire [36:0] adder5_out = _T_168 + b_ff; // @[exu_div_ctl.scala 642:85]
|
||||
wire _T_191 = ~adder5_out[36]; // @[exu_div_ctl.scala 647:23]
|
||||
wire _T_192 = _T_191 ^ control_ff[2]; // @[exu_div_ctl.scala 647:39]
|
||||
wire _T_195 = adder5_out == 37'h0; // @[exu_div_ctl.scala 647:97]
|
||||
wire _T_196 = _T_178 & _T_195; // @[exu_div_ctl.scala 647:83]
|
||||
wire _T_197 = _T_192 | _T_196; // @[exu_div_ctl.scala 647:59]
|
||||
wire _T_199 = ~_T_168[36]; // @[exu_div_ctl.scala 648:23]
|
||||
wire _T_200 = _T_199 ^ control_ff[2]; // @[exu_div_ctl.scala 648:39]
|
||||
wire _T_203 = _T_168 == 37'h0; // @[exu_div_ctl.scala 648:97]
|
||||
wire _T_204 = _T_178 & _T_203; // @[exu_div_ctl.scala 648:83]
|
||||
wire _T_205 = _T_200 | _T_204; // @[exu_div_ctl.scala 648:59]
|
||||
wire [36:0] _T_172 = _T_168 + _T_170; // @[exu_div_ctl.scala 647:85]
|
||||
wire [36:0] adder7_out = _T_172 + b_ff; // @[exu_div_ctl.scala 647:107]
|
||||
wire _T_175 = ~adder7_out[36]; // @[exu_div_ctl.scala 648:24]
|
||||
wire _T_176 = _T_175 ^ control_ff[2]; // @[exu_div_ctl.scala 648:40]
|
||||
wire _T_178 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 648:75]
|
||||
wire _T_179 = adder7_out == 37'h0; // @[exu_div_ctl.scala 648:98]
|
||||
wire _T_180 = _T_178 & _T_179; // @[exu_div_ctl.scala 648:84]
|
||||
wire _T_181 = _T_176 | _T_180; // @[exu_div_ctl.scala 648:60]
|
||||
wire _T_183 = ~_T_172[36]; // @[exu_div_ctl.scala 649:23]
|
||||
wire _T_184 = _T_183 ^ control_ff[2]; // @[exu_div_ctl.scala 649:39]
|
||||
wire _T_187 = _T_172 == 37'h0; // @[exu_div_ctl.scala 649:97]
|
||||
wire _T_188 = _T_178 & _T_187; // @[exu_div_ctl.scala 649:83]
|
||||
wire _T_189 = _T_184 | _T_188; // @[exu_div_ctl.scala 649:59]
|
||||
wire [36:0] adder5_out = _T_168 + b_ff; // @[exu_div_ctl.scala 645:85]
|
||||
wire _T_191 = ~adder5_out[36]; // @[exu_div_ctl.scala 650:23]
|
||||
wire _T_192 = _T_191 ^ control_ff[2]; // @[exu_div_ctl.scala 650:39]
|
||||
wire _T_195 = adder5_out == 37'h0; // @[exu_div_ctl.scala 650:97]
|
||||
wire _T_196 = _T_178 & _T_195; // @[exu_div_ctl.scala 650:83]
|
||||
wire _T_197 = _T_192 | _T_196; // @[exu_div_ctl.scala 650:59]
|
||||
wire _T_199 = ~_T_168[36]; // @[exu_div_ctl.scala 651:23]
|
||||
wire _T_200 = _T_199 ^ control_ff[2]; // @[exu_div_ctl.scala 651:39]
|
||||
wire _T_203 = _T_168 == 37'h0; // @[exu_div_ctl.scala 651:97]
|
||||
wire _T_204 = _T_178 & _T_203; // @[exu_div_ctl.scala 651:83]
|
||||
wire _T_205 = _T_200 | _T_204; // @[exu_div_ctl.scala 651:59]
|
||||
wire [35:0] _T_123 = {r_ff,a_ff[32:30]}; // @[Cat.scala 29:58]
|
||||
wire [35:0] _T_125 = {b_ff[34:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [35:0] _T_127 = _T_123 + _T_125; // @[exu_div_ctl.scala 640:49]
|
||||
wire [35:0] adder3_out = _T_127 + b_ff[35:0]; // @[exu_div_ctl.scala 640:71]
|
||||
wire _T_207 = ~adder3_out[35]; // @[exu_div_ctl.scala 649:23]
|
||||
wire _T_208 = _T_207 ^ control_ff[2]; // @[exu_div_ctl.scala 649:39]
|
||||
wire _T_211 = adder3_out == 36'h0; // @[exu_div_ctl.scala 649:97]
|
||||
wire _T_212 = _T_178 & _T_211; // @[exu_div_ctl.scala 649:83]
|
||||
wire _T_213 = _T_208 | _T_212; // @[exu_div_ctl.scala 649:59]
|
||||
wire [35:0] _T_127 = _T_123 + _T_125; // @[exu_div_ctl.scala 643:49]
|
||||
wire [35:0] adder3_out = _T_127 + b_ff[35:0]; // @[exu_div_ctl.scala 643:71]
|
||||
wire _T_207 = ~adder3_out[35]; // @[exu_div_ctl.scala 652:23]
|
||||
wire _T_208 = _T_207 ^ control_ff[2]; // @[exu_div_ctl.scala 652:39]
|
||||
wire _T_211 = adder3_out == 36'h0; // @[exu_div_ctl.scala 652:97]
|
||||
wire _T_212 = _T_178 & _T_211; // @[exu_div_ctl.scala 652:83]
|
||||
wire _T_213 = _T_208 | _T_212; // @[exu_div_ctl.scala 652:59]
|
||||
wire [34:0] _T_117 = {r_ff[31:0],a_ff[32:30]}; // @[Cat.scala 29:58]
|
||||
wire [34:0] _T_119 = {b_ff[33:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [34:0] adder2_out = _T_117 + _T_119; // @[exu_div_ctl.scala 639:49]
|
||||
wire _T_215 = ~adder2_out[34]; // @[exu_div_ctl.scala 650:23]
|
||||
wire _T_216 = _T_215 ^ control_ff[2]; // @[exu_div_ctl.scala 650:39]
|
||||
wire _T_219 = adder2_out == 35'h0; // @[exu_div_ctl.scala 650:97]
|
||||
wire _T_220 = _T_178 & _T_219; // @[exu_div_ctl.scala 650:83]
|
||||
wire _T_221 = _T_216 | _T_220; // @[exu_div_ctl.scala 650:59]
|
||||
wire [34:0] adder2_out = _T_117 + _T_119; // @[exu_div_ctl.scala 642:49]
|
||||
wire _T_215 = ~adder2_out[34]; // @[exu_div_ctl.scala 653:23]
|
||||
wire _T_216 = _T_215 ^ control_ff[2]; // @[exu_div_ctl.scala 653:39]
|
||||
wire _T_219 = adder2_out == 35'h0; // @[exu_div_ctl.scala 653:97]
|
||||
wire _T_220 = _T_178 & _T_219; // @[exu_div_ctl.scala 653:83]
|
||||
wire _T_221 = _T_216 | _T_220; // @[exu_div_ctl.scala 653:59]
|
||||
wire [33:0] _T_112 = {r_ff[30:0],a_ff[32:30]}; // @[Cat.scala 29:58]
|
||||
wire [33:0] adder1_out = _T_112 + b_ff[33:0]; // @[exu_div_ctl.scala 638:49]
|
||||
wire _T_223 = ~adder1_out[33]; // @[exu_div_ctl.scala 651:23]
|
||||
wire _T_224 = _T_223 ^ control_ff[2]; // @[exu_div_ctl.scala 651:39]
|
||||
wire _T_227 = adder1_out == 34'h0; // @[exu_div_ctl.scala 651:97]
|
||||
wire _T_228 = _T_178 & _T_227; // @[exu_div_ctl.scala 651:83]
|
||||
wire _T_229 = _T_224 | _T_228; // @[exu_div_ctl.scala 651:59]
|
||||
wire [33:0] adder1_out = _T_112 + b_ff[33:0]; // @[exu_div_ctl.scala 641:49]
|
||||
wire _T_223 = ~adder1_out[33]; // @[exu_div_ctl.scala 654:23]
|
||||
wire _T_224 = _T_223 ^ control_ff[2]; // @[exu_div_ctl.scala 654:39]
|
||||
wire _T_227 = adder1_out == 34'h0; // @[exu_div_ctl.scala 654:97]
|
||||
wire _T_228 = _T_178 & _T_227; // @[exu_div_ctl.scala 654:83]
|
||||
wire _T_229 = _T_224 | _T_228; // @[exu_div_ctl.scala 654:59]
|
||||
wire [7:0] quotient_raw = {_T_181,_T_189,_T_197,_T_205,_T_213,_T_221,_T_229,1'h0}; // @[Cat.scala 29:58]
|
||||
wire _T_239 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 652:43]
|
||||
wire _T_241 = _T_239 | quotient_raw[5]; // @[exu_div_ctl.scala 652:62]
|
||||
wire _T_243 = _T_241 | quotient_raw[4]; // @[exu_div_ctl.scala 652:80]
|
||||
wire _T_248 = ~quotient_raw[4]; // @[exu_div_ctl.scala 653:63]
|
||||
wire _T_250 = _T_248 & quotient_raw[3]; // @[exu_div_ctl.scala 653:80]
|
||||
wire _T_251 = _T_239 | _T_250; // @[exu_div_ctl.scala 653:61]
|
||||
wire _T_253 = ~quotient_raw[3]; // @[exu_div_ctl.scala 653:101]
|
||||
wire _T_255 = _T_253 & quotient_raw[2]; // @[exu_div_ctl.scala 653:118]
|
||||
wire _T_256 = _T_251 | _T_255; // @[exu_div_ctl.scala 653:99]
|
||||
wire _T_259 = ~quotient_raw[6]; // @[exu_div_ctl.scala 654:46]
|
||||
wire _T_261 = _T_259 & quotient_raw[5]; // @[exu_div_ctl.scala 654:63]
|
||||
wire _T_262 = quotient_raw[7] | _T_261; // @[exu_div_ctl.scala 654:42]
|
||||
wire _T_267 = _T_262 | _T_250; // @[exu_div_ctl.scala 654:82]
|
||||
wire _T_269 = ~quotient_raw[2]; // @[exu_div_ctl.scala 654:123]
|
||||
wire _T_271 = _T_269 & quotient_raw[1]; // @[exu_div_ctl.scala 654:140]
|
||||
wire _T_272 = _T_267 | _T_271; // @[exu_div_ctl.scala 654:121]
|
||||
wire _T_239 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 655:43]
|
||||
wire _T_241 = _T_239 | quotient_raw[5]; // @[exu_div_ctl.scala 655:62]
|
||||
wire _T_243 = _T_241 | quotient_raw[4]; // @[exu_div_ctl.scala 655:80]
|
||||
wire _T_248 = ~quotient_raw[4]; // @[exu_div_ctl.scala 656:63]
|
||||
wire _T_250 = _T_248 & quotient_raw[3]; // @[exu_div_ctl.scala 656:80]
|
||||
wire _T_251 = _T_239 | _T_250; // @[exu_div_ctl.scala 656:61]
|
||||
wire _T_253 = ~quotient_raw[3]; // @[exu_div_ctl.scala 656:101]
|
||||
wire _T_255 = _T_253 & quotient_raw[2]; // @[exu_div_ctl.scala 656:118]
|
||||
wire _T_256 = _T_251 | _T_255; // @[exu_div_ctl.scala 656:99]
|
||||
wire _T_259 = ~quotient_raw[6]; // @[exu_div_ctl.scala 657:46]
|
||||
wire _T_261 = _T_259 & quotient_raw[5]; // @[exu_div_ctl.scala 657:63]
|
||||
wire _T_262 = quotient_raw[7] | _T_261; // @[exu_div_ctl.scala 657:42]
|
||||
wire _T_267 = _T_262 | _T_250; // @[exu_div_ctl.scala 657:82]
|
||||
wire _T_269 = ~quotient_raw[2]; // @[exu_div_ctl.scala 657:123]
|
||||
wire _T_271 = _T_269 & quotient_raw[1]; // @[exu_div_ctl.scala 657:140]
|
||||
wire _T_272 = _T_267 | _T_271; // @[exu_div_ctl.scala 657:121]
|
||||
wire [2:0] quotient_new = {_T_243,_T_256,_T_272}; // @[Cat.scala 29:58]
|
||||
wire _T_86 = quotient_new == 3'h0; // @[exu_div_ctl.scala 629:61]
|
||||
wire _T_87 = running_state & _T_86; // @[exu_div_ctl.scala 629:45]
|
||||
wire r_restore_sel = _T_87 & _T_67; // @[exu_div_ctl.scala 629:70]
|
||||
wire _T_89 = quotient_new == 3'h1; // @[exu_div_ctl.scala 630:61]
|
||||
wire _T_90 = running_state & _T_89; // @[exu_div_ctl.scala 630:45]
|
||||
wire r_adder1_sel = _T_90 & _T_67; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_92 = quotient_new == 3'h2; // @[exu_div_ctl.scala 631:61]
|
||||
wire _T_93 = running_state & _T_92; // @[exu_div_ctl.scala 631:45]
|
||||
wire r_adder2_sel = _T_93 & _T_67; // @[exu_div_ctl.scala 631:70]
|
||||
wire _T_95 = quotient_new == 3'h3; // @[exu_div_ctl.scala 632:61]
|
||||
wire _T_96 = running_state & _T_95; // @[exu_div_ctl.scala 632:45]
|
||||
wire r_adder3_sel = _T_96 & _T_67; // @[exu_div_ctl.scala 632:70]
|
||||
wire _T_98 = quotient_new == 3'h4; // @[exu_div_ctl.scala 633:61]
|
||||
wire _T_99 = running_state & _T_98; // @[exu_div_ctl.scala 633:45]
|
||||
wire r_adder4_sel = _T_99 & _T_67; // @[exu_div_ctl.scala 633:70]
|
||||
wire _T_101 = quotient_new == 3'h5; // @[exu_div_ctl.scala 634:61]
|
||||
wire _T_102 = running_state & _T_101; // @[exu_div_ctl.scala 634:45]
|
||||
wire r_adder5_sel = _T_102 & _T_67; // @[exu_div_ctl.scala 634:70]
|
||||
wire _T_104 = quotient_new == 3'h6; // @[exu_div_ctl.scala 635:61]
|
||||
wire _T_105 = running_state & _T_104; // @[exu_div_ctl.scala 635:45]
|
||||
wire r_adder6_sel = _T_105 & _T_67; // @[exu_div_ctl.scala 635:70]
|
||||
wire _T_107 = quotient_new == 3'h7; // @[exu_div_ctl.scala 636:61]
|
||||
wire _T_108 = running_state & _T_107; // @[exu_div_ctl.scala 636:45]
|
||||
wire r_adder7_sel = _T_108 & _T_67; // @[exu_div_ctl.scala 636:70]
|
||||
wire _T_86 = quotient_new == 3'h0; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_87 = running_state & _T_86; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_0 = _T_87 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_89 = quotient_new == 3'h1; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_90 = running_state & _T_89; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_1 = _T_90 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_92 = quotient_new == 3'h2; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_93 = running_state & _T_92; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_2 = _T_93 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_95 = quotient_new == 3'h3; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_96 = running_state & _T_95; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_3 = _T_96 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_98 = quotient_new == 3'h4; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_99 = running_state & _T_98; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_4 = _T_99 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_101 = quotient_new == 3'h5; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_102 = running_state & _T_101; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_5 = _T_102 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_104 = quotient_new == 3'h6; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_105 = running_state & _T_104; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_6 = _T_105 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
wire _T_107 = quotient_new == 3'h7; // @[exu_div_ctl.scala 630:70]
|
||||
wire _T_108 = running_state & _T_107; // @[exu_div_ctl.scala 630:54]
|
||||
wire r_adder_sel_7 = _T_108 & _T_67; // @[exu_div_ctl.scala 630:84]
|
||||
reg [31:0] q_ff; // @[Reg.scala 27:20]
|
||||
wire [31:0] _T_276 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_277 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -554,9 +554,9 @@ module exu_div_new_3bit_fullshortq(
|
|||
wire [7:0] _T_486 = {_T_417,_T_411,_T_405,_T_399,_T_393,_T_387,_T_381,_T_375}; // @[lib.scala 430:14]
|
||||
wire [30:0] _T_495 = {_T_465,_T_459,_T_453,_T_447,_T_441,_T_435,_T_429,_T_423,_T_486,_T_479}; // @[lib.scala 430:14]
|
||||
wire [31:0] twos_comp_out = {_T_495,twos_comp_in[0]}; // @[Cat.scala 29:58]
|
||||
wire _T_497 = ~a_shift; // @[exu_div_ctl.scala 661:6]
|
||||
wire _T_499 = _T_497 & _T_67; // @[exu_div_ctl.scala 661:15]
|
||||
wire _T_502 = io_signed_in & io_dividend_in[31]; // @[exu_div_ctl.scala 661:63]
|
||||
wire _T_497 = ~a_shift; // @[exu_div_ctl.scala 664:6]
|
||||
wire _T_499 = _T_497 & _T_67; // @[exu_div_ctl.scala 664:15]
|
||||
wire _T_502 = io_signed_in & io_dividend_in[31]; // @[exu_div_ctl.scala 664:63]
|
||||
wire [32:0] _T_504 = {_T_502,io_dividend_in}; // @[Cat.scala 29:58]
|
||||
wire [32:0] _T_506 = {a_ff[29:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [65:0] ar_shifted = _T_72[65:0]; // @[exu_div_ctl.scala 622:28]
|
||||
|
|
@ -565,10 +565,10 @@ module exu_div_new_3bit_fullshortq(
|
|||
wire [32:0] _T_510 = shortq_enable_ff ? ar_shifted[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_511 = _T_508 | _T_509; // @[Mux.scala 27:72]
|
||||
wire [32:0] a_in = _T_511 | _T_510; // @[Mux.scala 27:72]
|
||||
wire _T_513 = ~b_twos_comp; // @[exu_div_ctl.scala 666:5]
|
||||
wire _T_515 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 666:63]
|
||||
wire _T_513 = ~b_twos_comp; // @[exu_div_ctl.scala 669:5]
|
||||
wire _T_515 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 669:63]
|
||||
wire [32:0] _T_517 = {_T_515,io_divisor_in}; // @[Cat.scala 29:58]
|
||||
wire _T_518 = ~control_ff[1]; // @[exu_div_ctl.scala 667:50]
|
||||
wire _T_518 = ~control_ff[1]; // @[exu_div_ctl.scala 670:50]
|
||||
wire [32:0] _T_520 = {_T_518,_T_495,twos_comp_in[0]}; // @[Cat.scala 29:58]
|
||||
wire [32:0] _T_521 = _T_513 ? _T_517 : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_522 = b_twos_comp ? _T_520 : 33'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -576,14 +576,14 @@ module exu_div_new_3bit_fullshortq(
|
|||
wire [32:0] _T_527 = {r_ff[29:0],a_ff[32:30]}; // @[Cat.scala 29:58]
|
||||
wire [32:0] _T_537 = {1'h0,a_ff[31:0]}; // @[Cat.scala 29:58]
|
||||
wire [32:0] _T_538 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_539 = r_restore_sel ? _T_527 : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_540 = r_adder1_sel ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_541 = r_adder2_sel ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_542 = r_adder3_sel ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_543 = r_adder4_sel ? _T_168[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_544 = r_adder5_sel ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_545 = r_adder6_sel ? _T_172[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_546 = r_adder7_sel ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_539 = r_adder_sel_0 ? _T_527 : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_540 = r_adder_sel_1 ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_541 = r_adder_sel_2 ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_542 = r_adder_sel_3 ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_543 = r_adder_sel_4 ? _T_168[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_544 = r_adder_sel_5 ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_545 = r_adder_sel_6 ? _T_172[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_546 = r_adder_sel_7 ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_547 = shortq_enable_ff ? ar_shifted[65:33] : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_548 = by_zero_case ? _T_537 : 33'h0; // @[Mux.scala 27:72]
|
||||
wire [32:0] _T_549 = _T_538 | _T_539; // @[Mux.scala 27:72]
|
||||
|
|
@ -597,175 +597,175 @@ module exu_div_new_3bit_fullshortq(
|
|||
wire [32:0] _T_557 = _T_556 | _T_547; // @[Mux.scala 27:72]
|
||||
wire [32:0] r_in = _T_557 | _T_548; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_561 = {q_ff[28:0],_T_243,_T_256,_T_272}; // @[Cat.scala 29:58]
|
||||
wire _T_584 = ~b_ff[3]; // @[exu_div_ctl.scala 695:70]
|
||||
wire _T_586 = ~b_ff[2]; // @[exu_div_ctl.scala 695:70]
|
||||
wire _T_589 = _T_584 & _T_586; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_588 = ~b_ff[1]; // @[exu_div_ctl.scala 695:70]
|
||||
wire _T_590 = _T_589 & _T_588; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_591 = a_ff[3] & _T_590; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_598 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_600 = ~b_ff[0]; // @[exu_div_ctl.scala 701:33]
|
||||
wire _T_601 = _T_598 & _T_600; // @[exu_div_ctl.scala 701:31]
|
||||
wire _T_611 = a_ff[2] & _T_590; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_612 = _T_601 | _T_611; // @[exu_div_ctl.scala 701:42]
|
||||
wire _T_615 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_621 = _T_615 & _T_589; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_622 = _T_612 | _T_621; // @[exu_div_ctl.scala 701:75]
|
||||
wire _T_629 = a_ff[2] & _T_589; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_632 = _T_629 & _T_600; // @[exu_div_ctl.scala 703:31]
|
||||
wire _T_642 = a_ff[1] & _T_590; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_643 = _T_632 | _T_642; // @[exu_div_ctl.scala 703:42]
|
||||
wire _T_649 = _T_584 & _T_588; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_650 = a_ff[3] & _T_649; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_653 = _T_650 & _T_600; // @[exu_div_ctl.scala 703:106]
|
||||
wire _T_654 = _T_643 | _T_653; // @[exu_div_ctl.scala 703:78]
|
||||
wire _T_657 = ~a_ff[2]; // @[exu_div_ctl.scala 694:70]
|
||||
wire _T_658 = a_ff[3] & _T_657; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_666 = _T_589 & b_ff[1]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_667 = _T_666 & b_ff[0]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_668 = _T_658 & _T_667; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_669 = _T_654 | _T_668; // @[exu_div_ctl.scala 703:117]
|
||||
wire _T_671 = ~a_ff[3]; // @[exu_div_ctl.scala 694:70]
|
||||
wire _T_674 = _T_671 & a_ff[2]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_675 = _T_674 & a_ff[1]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_681 = _T_675 & _T_589; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_682 = _T_669 | _T_681; // @[exu_div_ctl.scala 704:44]
|
||||
wire _T_688 = _T_615 & _T_584; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_691 = _T_688 & _T_600; // @[exu_div_ctl.scala 704:107]
|
||||
wire _T_692 = _T_682 | _T_691; // @[exu_div_ctl.scala 704:80]
|
||||
wire _T_701 = _T_584 & b_ff[2]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_702 = _T_701 & _T_588; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_703 = _T_615 & _T_702; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_704 = _T_692 | _T_703; // @[exu_div_ctl.scala 704:119]
|
||||
wire _T_707 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_713 = _T_707 & _T_649; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_714 = _T_704 | _T_713; // @[exu_div_ctl.scala 705:44]
|
||||
wire _T_719 = _T_615 & a_ff[1]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_724 = _T_719 & _T_701; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_725 = _T_714 | _T_724; // @[exu_div_ctl.scala 705:79]
|
||||
wire _T_729 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_730 = _T_729 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_736 = _T_730 & _T_649; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_742 = _T_658 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_747 = _T_584 & b_ff[1]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_748 = _T_747 & b_ff[0]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_749 = _T_742 & _T_748; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_750 = _T_736 | _T_749; // @[exu_div_ctl.scala 707:45]
|
||||
wire _T_757 = a_ff[2] & _T_649; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_760 = _T_757 & _T_600; // @[exu_div_ctl.scala 707:114]
|
||||
wire _T_761 = _T_750 | _T_760; // @[exu_div_ctl.scala 707:86]
|
||||
wire _T_768 = a_ff[1] & _T_589; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_771 = _T_768 & _T_600; // @[exu_div_ctl.scala 708:33]
|
||||
wire _T_772 = _T_761 | _T_771; // @[exu_div_ctl.scala 707:129]
|
||||
wire _T_782 = a_ff[0] & _T_590; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_783 = _T_772 | _T_782; // @[exu_div_ctl.scala 708:47]
|
||||
wire _T_788 = ~a_ff[1]; // @[exu_div_ctl.scala 694:70]
|
||||
wire _T_790 = _T_674 & _T_788; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_800 = _T_790 & _T_667; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_801 = _T_783 | _T_800; // @[exu_div_ctl.scala 708:88]
|
||||
wire _T_810 = _T_675 & _T_584; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_813 = _T_810 & _T_600; // @[exu_div_ctl.scala 709:36]
|
||||
wire _T_814 = _T_801 | _T_813; // @[exu_div_ctl.scala 708:131]
|
||||
wire _T_820 = _T_586 & _T_588; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_821 = a_ff[3] & _T_820; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_824 = _T_821 & _T_600; // @[exu_div_ctl.scala 709:76]
|
||||
wire _T_825 = _T_814 | _T_824; // @[exu_div_ctl.scala 709:47]
|
||||
wire _T_835 = _T_701 & b_ff[1]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_836 = _T_658 & _T_835; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_837 = _T_825 | _T_836; // @[exu_div_ctl.scala 709:88]
|
||||
wire _T_851 = _T_675 & _T_702; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_852 = _T_837 | _T_851; // @[exu_div_ctl.scala 709:131]
|
||||
wire _T_858 = _T_674 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_864 = _T_858 & _T_649; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_865 = _T_852 | _T_864; // @[exu_div_ctl.scala 710:47]
|
||||
wire _T_872 = _T_658 & _T_788; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_878 = _T_701 & b_ff[0]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_879 = _T_872 & _T_878; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_880 = _T_865 | _T_879; // @[exu_div_ctl.scala 710:88]
|
||||
wire _T_885 = _T_657 & a_ff[1]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_886 = _T_885 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_892 = _T_886 & _T_589; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_893 = _T_880 | _T_892; // @[exu_div_ctl.scala 710:131]
|
||||
wire _T_899 = _T_615 & _T_588; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_902 = _T_899 & _T_600; // @[exu_div_ctl.scala 711:75]
|
||||
wire _T_903 = _T_893 | _T_902; // @[exu_div_ctl.scala 711:47]
|
||||
wire _T_911 = _T_675 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_916 = _T_911 & _T_701; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_917 = _T_903 | _T_916; // @[exu_div_ctl.scala 711:88]
|
||||
wire _T_924 = b_ff[3] & _T_586; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_925 = _T_615 & _T_924; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_926 = _T_917 | _T_925; // @[exu_div_ctl.scala 711:131]
|
||||
wire _T_936 = _T_924 & _T_588; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_937 = _T_707 & _T_936; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_938 = _T_926 | _T_937; // @[exu_div_ctl.scala 712:47]
|
||||
wire _T_941 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_947 = _T_941 & _T_820; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_948 = _T_938 | _T_947; // @[exu_div_ctl.scala 712:88]
|
||||
wire _T_952 = a_ff[3] & _T_788; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_960 = _T_835 & b_ff[0]; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_961 = _T_952 & _T_960; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_962 = _T_948 | _T_961; // @[exu_div_ctl.scala 712:131]
|
||||
wire _T_969 = _T_719 & b_ff[3]; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_972 = _T_969 & _T_600; // @[exu_div_ctl.scala 713:77]
|
||||
wire _T_973 = _T_962 | _T_972; // @[exu_div_ctl.scala 713:47]
|
||||
wire _T_982 = b_ff[3] & _T_588; // @[exu_div_ctl.scala 695:95]
|
||||
wire _T_983 = _T_719 & _T_982; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_984 = _T_973 | _T_983; // @[exu_div_ctl.scala 713:88]
|
||||
wire _T_989 = _T_615 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_994 = _T_989 & _T_982; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_995 = _T_984 | _T_994; // @[exu_div_ctl.scala 713:131]
|
||||
wire _T_1001 = _T_658 & a_ff[1]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_1006 = _T_1001 & _T_747; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_1007 = _T_995 | _T_1006; // @[exu_div_ctl.scala 714:47]
|
||||
wire _T_1012 = _T_707 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_1015 = _T_1012 & _T_586; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_1016 = _T_1007 | _T_1015; // @[exu_div_ctl.scala 714:88]
|
||||
wire _T_1023 = _T_719 & a_ff[0]; // @[exu_div_ctl.scala 694:95]
|
||||
wire _T_1025 = _T_1023 & b_ff[3]; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_1026 = _T_1016 | _T_1025; // @[exu_div_ctl.scala 714:131]
|
||||
wire _T_1032 = _T_707 & _T_586; // @[exu_div_ctl.scala 696:11]
|
||||
wire _T_1035 = _T_1032 & _T_600; // @[exu_div_ctl.scala 715:74]
|
||||
wire _T_1036 = _T_1026 | _T_1035; // @[exu_div_ctl.scala 715:47]
|
||||
wire _T_584 = ~b_ff[3]; // @[exu_div_ctl.scala 698:70]
|
||||
wire _T_586 = ~b_ff[2]; // @[exu_div_ctl.scala 698:70]
|
||||
wire _T_589 = _T_584 & _T_586; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_588 = ~b_ff[1]; // @[exu_div_ctl.scala 698:70]
|
||||
wire _T_590 = _T_589 & _T_588; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_591 = a_ff[3] & _T_590; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_598 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_600 = ~b_ff[0]; // @[exu_div_ctl.scala 704:33]
|
||||
wire _T_601 = _T_598 & _T_600; // @[exu_div_ctl.scala 704:31]
|
||||
wire _T_611 = a_ff[2] & _T_590; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_612 = _T_601 | _T_611; // @[exu_div_ctl.scala 704:42]
|
||||
wire _T_615 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_621 = _T_615 & _T_589; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_622 = _T_612 | _T_621; // @[exu_div_ctl.scala 704:75]
|
||||
wire _T_629 = a_ff[2] & _T_589; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_632 = _T_629 & _T_600; // @[exu_div_ctl.scala 706:31]
|
||||
wire _T_642 = a_ff[1] & _T_590; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_643 = _T_632 | _T_642; // @[exu_div_ctl.scala 706:42]
|
||||
wire _T_649 = _T_584 & _T_588; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_650 = a_ff[3] & _T_649; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_653 = _T_650 & _T_600; // @[exu_div_ctl.scala 706:106]
|
||||
wire _T_654 = _T_643 | _T_653; // @[exu_div_ctl.scala 706:78]
|
||||
wire _T_657 = ~a_ff[2]; // @[exu_div_ctl.scala 697:70]
|
||||
wire _T_658 = a_ff[3] & _T_657; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_666 = _T_589 & b_ff[1]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_667 = _T_666 & b_ff[0]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_668 = _T_658 & _T_667; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_669 = _T_654 | _T_668; // @[exu_div_ctl.scala 706:117]
|
||||
wire _T_671 = ~a_ff[3]; // @[exu_div_ctl.scala 697:70]
|
||||
wire _T_674 = _T_671 & a_ff[2]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_675 = _T_674 & a_ff[1]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_681 = _T_675 & _T_589; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_682 = _T_669 | _T_681; // @[exu_div_ctl.scala 707:44]
|
||||
wire _T_688 = _T_615 & _T_584; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_691 = _T_688 & _T_600; // @[exu_div_ctl.scala 707:107]
|
||||
wire _T_692 = _T_682 | _T_691; // @[exu_div_ctl.scala 707:80]
|
||||
wire _T_701 = _T_584 & b_ff[2]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_702 = _T_701 & _T_588; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_703 = _T_615 & _T_702; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_704 = _T_692 | _T_703; // @[exu_div_ctl.scala 707:119]
|
||||
wire _T_707 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_713 = _T_707 & _T_649; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_714 = _T_704 | _T_713; // @[exu_div_ctl.scala 708:44]
|
||||
wire _T_719 = _T_615 & a_ff[1]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_724 = _T_719 & _T_701; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_725 = _T_714 | _T_724; // @[exu_div_ctl.scala 708:79]
|
||||
wire _T_729 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_730 = _T_729 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_736 = _T_730 & _T_649; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_742 = _T_658 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_747 = _T_584 & b_ff[1]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_748 = _T_747 & b_ff[0]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_749 = _T_742 & _T_748; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_750 = _T_736 | _T_749; // @[exu_div_ctl.scala 710:45]
|
||||
wire _T_757 = a_ff[2] & _T_649; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_760 = _T_757 & _T_600; // @[exu_div_ctl.scala 710:114]
|
||||
wire _T_761 = _T_750 | _T_760; // @[exu_div_ctl.scala 710:86]
|
||||
wire _T_768 = a_ff[1] & _T_589; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_771 = _T_768 & _T_600; // @[exu_div_ctl.scala 711:33]
|
||||
wire _T_772 = _T_761 | _T_771; // @[exu_div_ctl.scala 710:129]
|
||||
wire _T_782 = a_ff[0] & _T_590; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_783 = _T_772 | _T_782; // @[exu_div_ctl.scala 711:47]
|
||||
wire _T_788 = ~a_ff[1]; // @[exu_div_ctl.scala 697:70]
|
||||
wire _T_790 = _T_674 & _T_788; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_800 = _T_790 & _T_667; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_801 = _T_783 | _T_800; // @[exu_div_ctl.scala 711:88]
|
||||
wire _T_810 = _T_675 & _T_584; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_813 = _T_810 & _T_600; // @[exu_div_ctl.scala 712:36]
|
||||
wire _T_814 = _T_801 | _T_813; // @[exu_div_ctl.scala 711:131]
|
||||
wire _T_820 = _T_586 & _T_588; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_821 = a_ff[3] & _T_820; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_824 = _T_821 & _T_600; // @[exu_div_ctl.scala 712:76]
|
||||
wire _T_825 = _T_814 | _T_824; // @[exu_div_ctl.scala 712:47]
|
||||
wire _T_835 = _T_701 & b_ff[1]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_836 = _T_658 & _T_835; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_837 = _T_825 | _T_836; // @[exu_div_ctl.scala 712:88]
|
||||
wire _T_851 = _T_675 & _T_702; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_852 = _T_837 | _T_851; // @[exu_div_ctl.scala 712:131]
|
||||
wire _T_858 = _T_674 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_864 = _T_858 & _T_649; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_865 = _T_852 | _T_864; // @[exu_div_ctl.scala 713:47]
|
||||
wire _T_872 = _T_658 & _T_788; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_878 = _T_701 & b_ff[0]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_879 = _T_872 & _T_878; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_880 = _T_865 | _T_879; // @[exu_div_ctl.scala 713:88]
|
||||
wire _T_885 = _T_657 & a_ff[1]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_886 = _T_885 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_892 = _T_886 & _T_589; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_893 = _T_880 | _T_892; // @[exu_div_ctl.scala 713:131]
|
||||
wire _T_899 = _T_615 & _T_588; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_902 = _T_899 & _T_600; // @[exu_div_ctl.scala 714:75]
|
||||
wire _T_903 = _T_893 | _T_902; // @[exu_div_ctl.scala 714:47]
|
||||
wire _T_911 = _T_675 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_916 = _T_911 & _T_701; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_917 = _T_903 | _T_916; // @[exu_div_ctl.scala 714:88]
|
||||
wire _T_924 = b_ff[3] & _T_586; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_925 = _T_615 & _T_924; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_926 = _T_917 | _T_925; // @[exu_div_ctl.scala 714:131]
|
||||
wire _T_936 = _T_924 & _T_588; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_937 = _T_707 & _T_936; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_938 = _T_926 | _T_937; // @[exu_div_ctl.scala 715:47]
|
||||
wire _T_941 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_947 = _T_941 & _T_820; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_948 = _T_938 | _T_947; // @[exu_div_ctl.scala 715:88]
|
||||
wire _T_952 = a_ff[3] & _T_788; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_960 = _T_835 & b_ff[0]; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_961 = _T_952 & _T_960; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_962 = _T_948 | _T_961; // @[exu_div_ctl.scala 715:131]
|
||||
wire _T_969 = _T_719 & b_ff[3]; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_972 = _T_969 & _T_600; // @[exu_div_ctl.scala 716:77]
|
||||
wire _T_973 = _T_962 | _T_972; // @[exu_div_ctl.scala 716:47]
|
||||
wire _T_982 = b_ff[3] & _T_588; // @[exu_div_ctl.scala 698:95]
|
||||
wire _T_983 = _T_719 & _T_982; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_984 = _T_973 | _T_983; // @[exu_div_ctl.scala 716:88]
|
||||
wire _T_989 = _T_615 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_994 = _T_989 & _T_982; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_995 = _T_984 | _T_994; // @[exu_div_ctl.scala 716:131]
|
||||
wire _T_1001 = _T_658 & a_ff[1]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_1006 = _T_1001 & _T_747; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_1007 = _T_995 | _T_1006; // @[exu_div_ctl.scala 717:47]
|
||||
wire _T_1012 = _T_707 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_1015 = _T_1012 & _T_586; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_1016 = _T_1007 | _T_1015; // @[exu_div_ctl.scala 717:88]
|
||||
wire _T_1023 = _T_719 & a_ff[0]; // @[exu_div_ctl.scala 697:95]
|
||||
wire _T_1025 = _T_1023 & b_ff[3]; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_1026 = _T_1016 | _T_1025; // @[exu_div_ctl.scala 717:131]
|
||||
wire _T_1032 = _T_707 & _T_586; // @[exu_div_ctl.scala 699:11]
|
||||
wire _T_1035 = _T_1032 & _T_600; // @[exu_div_ctl.scala 718:74]
|
||||
wire _T_1036 = _T_1026 | _T_1035; // @[exu_div_ctl.scala 718:47]
|
||||
wire [31:0] _T_562 = {28'h0,_T_591,_T_622,_T_725,_T_1036}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_564 = _T_77 ? _T_561 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_565 = smallnum_case ? _T_562 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_566 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_567 = _T_564 | _T_565; // @[Mux.scala 27:72]
|
||||
wire [31:0] q_in = _T_567 | _T_566; // @[Mux.scala 27:72]
|
||||
wire _T_572 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 689:16]
|
||||
wire _T_573 = _T_30 & _T_572; // @[exu_div_ctl.scala 689:14]
|
||||
wire _T_572 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 692:16]
|
||||
wire _T_573 = _T_30 & _T_572; // @[exu_div_ctl.scala 692:14]
|
||||
wire [31:0] _T_576 = _T_573 ? q_ff : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_577 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_578 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_579 = _T_576 | _T_577; // @[Mux.scala 27:72]
|
||||
wire _T_1063 = shortq == 6'h1b; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1064 = shortq == 6'h1a; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1065 = shortq == 6'h19; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1066 = shortq == 6'h18; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1067 = shortq == 6'h17; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1068 = shortq == 6'h16; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1069 = shortq == 6'h15; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1070 = shortq == 6'h14; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1071 = shortq == 6'h13; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1072 = shortq == 6'h12; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1073 = shortq == 6'h11; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1074 = shortq == 6'h10; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1075 = shortq == 6'hf; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1076 = shortq == 6'he; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1077 = shortq == 6'hd; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1078 = shortq == 6'hc; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1079 = shortq == 6'hb; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1080 = shortq == 6'ha; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1081 = shortq == 6'h9; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1082 = shortq == 6'h8; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1083 = shortq == 6'h7; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1084 = shortq == 6'h6; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1085 = shortq == 6'h5; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1086 = shortq == 6'h4; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1087 = shortq == 6'h3; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1088 = shortq == 6'h2; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1089 = shortq == 6'h1; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1090 = shortq == 6'h0; // @[exu_div_ctl.scala 731:58]
|
||||
wire _T_1063 = shortq == 6'h1b; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1064 = shortq == 6'h1a; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1065 = shortq == 6'h19; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1066 = shortq == 6'h18; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1067 = shortq == 6'h17; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1068 = shortq == 6'h16; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1069 = shortq == 6'h15; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1070 = shortq == 6'h14; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1071 = shortq == 6'h13; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1072 = shortq == 6'h12; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1073 = shortq == 6'h11; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1074 = shortq == 6'h10; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1075 = shortq == 6'hf; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1076 = shortq == 6'he; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1077 = shortq == 6'hd; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1078 = shortq == 6'hc; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1079 = shortq == 6'hb; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1080 = shortq == 6'ha; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1081 = shortq == 6'h9; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1082 = shortq == 6'h8; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1083 = shortq == 6'h7; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1084 = shortq == 6'h6; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1085 = shortq == 6'h5; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1086 = shortq == 6'h4; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1087 = shortq == 6'h3; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1088 = shortq == 6'h2; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1089 = shortq == 6'h1; // @[exu_div_ctl.scala 734:58]
|
||||
wire _T_1090 = shortq == 6'h0; // @[exu_div_ctl.scala 734:58]
|
||||
wire [1:0] _T_1095 = _T_1063 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_1096 = _T_1064 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_1097 = _T_1065 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -824,11 +824,11 @@ module exu_div_new_3bit_fullshortq(
|
|||
wire [4:0] _T_1151 = _T_1150 | _T_1120; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1152 = _T_1151 | _T_1121; // @[Mux.scala 27:72]
|
||||
wire [4:0] shortq_decode = _T_1152 | _T_1122; // @[Mux.scala 27:72]
|
||||
exu_div_cls a_enc ( // @[exu_div_ctl.scala 718:21]
|
||||
exu_div_cls a_enc ( // @[exu_div_ctl.scala 721:21]
|
||||
.io_operand(a_enc_io_operand),
|
||||
.io_cls(a_enc_io_cls)
|
||||
);
|
||||
exu_div_cls b_enc ( // @[exu_div_ctl.scala 721:20]
|
||||
exu_div_cls b_enc ( // @[exu_div_ctl.scala 724:20]
|
||||
.io_operand(b_enc_io_operand),
|
||||
.io_cls(b_enc_io_cls)
|
||||
);
|
||||
|
|
@ -876,10 +876,10 @@ module exu_div_new_3bit_fullshortq(
|
|||
.io_clk(rvclkhdr_10_io_clk),
|
||||
.io_en(rvclkhdr_10_io_en)
|
||||
);
|
||||
assign io_data_out = _T_579 | _T_578; // @[exu_div_ctl.scala 688:15]
|
||||
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 687:15]
|
||||
assign a_enc_io_operand = {control_ff[2],a_ff[31:0]}; // @[exu_div_ctl.scala 719:20]
|
||||
assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 722:20]
|
||||
assign io_data_out = _T_579 | _T_578; // @[exu_div_ctl.scala 691:15]
|
||||
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 690:15]
|
||||
assign a_enc_io_operand = {control_ff[2],a_ff[31:0]}; // @[exu_div_ctl.scala 722:20]
|
||||
assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 725:20]
|
||||
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
|
||||
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
|
||||
|
|
|
|||
|
|
@ -626,14 +626,17 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
|
|||
val b_enable = io.valid_in | b_twos_comp
|
||||
val rq_enable = io.valid_in | valid_ff | running_state
|
||||
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
|
||||
val r_restore_sel = running_state & (quotient_new === 0.U) & !shortq_enable_ff
|
||||
val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff
|
||||
val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff
|
||||
val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff
|
||||
val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff
|
||||
val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff
|
||||
val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff
|
||||
val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff
|
||||
|
||||
val r_adder_sel = (0 to 7 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
|
||||
|
||||
// val r_restore_sel = running_state & (quotient_new === 0.U) & !shortq_enable_ff
|
||||
// val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff
|
||||
// val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff
|
||||
// val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff
|
||||
// val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff
|
||||
// val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff
|
||||
// val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff
|
||||
// val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff
|
||||
|
||||
val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
|
||||
val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
|
||||
|
|
@ -668,14 +671,14 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
|
|||
))
|
||||
val r_in = Mux1H (Seq(
|
||||
r_sign_sel -> Fill(33,1.U),
|
||||
r_restore_sel -> Cat(r_ff(29,0),a_ff(32,30)),
|
||||
r_adder1_sel -> adder1_out(32,0),
|
||||
r_adder2_sel -> adder2_out(32,0),
|
||||
r_adder3_sel -> adder3_out(32,0),
|
||||
r_adder4_sel -> adder4_out(32,0),
|
||||
r_adder5_sel -> adder5_out(32,0),
|
||||
r_adder6_sel -> adder6_out(32,0),
|
||||
r_adder7_sel -> adder7_out(32,0),
|
||||
r_adder_sel(0) -> Cat(r_ff(29,0),a_ff(32,30)),
|
||||
r_adder_sel(1) -> adder1_out(32,0),
|
||||
r_adder_sel(2) -> adder2_out(32,0),
|
||||
r_adder_sel(3) -> adder3_out(32,0),
|
||||
r_adder_sel(4) -> adder4_out(32,0),
|
||||
r_adder_sel(5) -> adder5_out(32,0),
|
||||
r_adder_sel(6) -> adder6_out(32,0),
|
||||
r_adder_sel(7) -> adder7_out(32,0),
|
||||
shortq_enable_ff -> ar_shifted(65,33),
|
||||
by_zero_case -> Cat(0.U,a_ff(31,0))
|
||||
))
|
||||
|
|
@ -746,24 +749,181 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
|
|||
|
||||
}
|
||||
|
||||
class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib {
|
||||
val io = IO(new Bundle {
|
||||
val scan_mode = Input(Bool())
|
||||
val cancel = Input(Bool())
|
||||
val valid_in = Input(Bool())
|
||||
val signed_in = Input(Bool())
|
||||
val rem_in = Input(Bool())
|
||||
val dividend_in = Input(UInt(32.W))
|
||||
val divisor_in = Input(UInt(32.W))
|
||||
val data_out = Output(UInt(32.W))
|
||||
val valid_out = Output(UInt(1.W))
|
||||
})
|
||||
io.data_out := 0.U
|
||||
io.valid_out :=0.U
|
||||
}
|
||||
// val valid_ff = WireInit(Bool(),init=false.B)
|
||||
// val finish_ff = WireInit(Bool(),init=false.B)
|
||||
// val control_ff = WireInit(0.U(3.W))
|
||||
// val count_ff = WireInit(0.U(7.W))
|
||||
// val smallnum = WireInit(0.U(4.W))
|
||||
// val a_ff = WireInit(0.U(32.W))
|
||||
// val b_ff1 = WireInit(0.U(33.W))
|
||||
// val b_ff = WireInit(0.U(38.W))
|
||||
// val q_ff = WireInit(0.U(32.W))
|
||||
// val r_ff = WireInit(0.U(33.W))
|
||||
// val quotient_raw = WireInit(0.U(16.W))
|
||||
// val quotient_new = WireInit(0.U(4.W))
|
||||
// val shortq_enable = WireInit(Bool(),init=false.B)
|
||||
// val shortq_enable_ff = WireInit(Bool(),init=false.B)
|
||||
// val by_zero_case_ff = WireInit(Bool(),init=false.B)
|
||||
// val ar_shifted = WireInit(0.U(65.W))
|
||||
// val shortq_shift = WireInit(0.U(5.W))
|
||||
// val shortq_decode = WireInit(0.U(5.W))
|
||||
// val shortq_shift_ff = WireInit(0.U(5.W))
|
||||
// val valid_ff_in = io.valid_in & !io.cancel
|
||||
// val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
|
||||
// val dividend_sign_ff = control_ff(2)
|
||||
// val divisor_sign_ff = control_ff(1)
|
||||
// val rem_ff = control_ff(0)
|
||||
// val by_zero_case = valid_ff & (b_ff(31,0) === 0.U)
|
||||
//
|
||||
// val smallnum_case = ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
|
||||
// ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
|
||||
// val running_state = count_ff.orR() | shortq_enable_ff
|
||||
// val misc_enable = io.valid_in | valid_ff | io.cancel | running_state | finish_ff
|
||||
// val finish_raw = smallnum_case | by_zero_case | (count_ff === 32.U)
|
||||
// val finish = finish_raw & !io.cancel
|
||||
// val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
|
||||
// val count_in = Fill(7,count_enable) & (count_ff + 4.U(7.W) + Cat(0.U(2.W),shortq_shift_ff))
|
||||
// val a_enable = io.valid_in | running_state
|
||||
// val a_shift = running_state & !shortq_enable_ff
|
||||
// ar_shifted := Cat (Fill(33,dividend_sign_ff),a_ff(31,0)) << shortq_shift_ff
|
||||
// val b_twos_comp = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
|
||||
// val twos_comp_b_sel = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
|
||||
// val twos_comp_q_sel = !valid_ff & !rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
|
||||
// val b_enable = io.valid_in | b_twos_comp
|
||||
// val rq_enable = io.valid_in | valid_ff | running_state
|
||||
// val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
|
||||
//
|
||||
// val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & ~shortq_enable_ff))
|
||||
//
|
||||
// val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
|
||||
// val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
|
||||
// val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
|
||||
// val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
|
||||
// val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
|
||||
// val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
|
||||
// val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
|
||||
// quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
|
||||
// (!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
|
||||
// (!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
|
||||
// (!adder4_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder4_out === 0.U)),
|
||||
// (!adder3_out(35) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)),
|
||||
// (!adder2_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)),
|
||||
// (!adder1_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)), 0.U)
|
||||
// quotient_new := Cat ((quotient_raw(7) | quotient_raw(6) | quotient_raw(5) | quotient_raw(4)),
|
||||
// (quotient_raw(7) | quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))),
|
||||
// (quotient_raw(7) | (!quotient_raw(6) & quotient_raw(5)) | (!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1))))
|
||||
// val twos_comp_in = Mux1H(Seq (
|
||||
// twos_comp_q_sel -> q_ff,
|
||||
// twos_comp_b_sel -> b_ff(31,0)
|
||||
// ))
|
||||
// val twos_comp_out = rvtwoscomp(twos_comp_in)
|
||||
// val a_in = Mux1H(Seq (
|
||||
// (!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)),
|
||||
// a_shift -> Cat(a_ff(29,0),0.U(3.W)),
|
||||
// shortq_enable_ff -> ar_shifted(32,0)
|
||||
// ))
|
||||
// val b_in = Mux1H(Seq (
|
||||
// !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
|
||||
// b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
|
||||
// ))
|
||||
// val r_in = Mux1H (Seq(
|
||||
// r_sign_sel -> Fill(33,1.U),
|
||||
// r_restore_sel -> Cat(r_ff(29,0),a_ff(32,30)),
|
||||
// r_adder1_sel -> adder1_out(32,0),
|
||||
// r_adder2_sel -> adder2_out(32,0),
|
||||
// r_adder3_sel -> adder3_out(32,0),
|
||||
// r_adder4_sel -> adder4_out(32,0),
|
||||
// r_adder5_sel -> adder5_out(32,0),
|
||||
// r_adder6_sel -> adder6_out(32,0),
|
||||
// r_adder7_sel -> adder7_out(32,0),
|
||||
// shortq_enable_ff -> ar_shifted(65,33),
|
||||
// by_zero_case -> Cat(0.U,a_ff(31,0))
|
||||
// ))
|
||||
// val q_in = Mux1H (Seq(
|
||||
// !valid_ff -> Cat(q_ff(28,0),quotient_new),
|
||||
// smallnum_case -> Cat(0.U(28.W),smallnum),
|
||||
// by_zero_case -> Fill(32,1.U)
|
||||
// ))
|
||||
// io.valid_out := finish_ff & !io.cancel
|
||||
// io.data_out := Mux1H(Seq(
|
||||
// (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
|
||||
// rem_ff -> r_ff(31,0),
|
||||
// twos_comp_q_sel -> twos_comp_out
|
||||
// ))
|
||||
// def pat1(x : List[Int], y : List[Int]) = {
|
||||
// val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
|
||||
// val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
|
||||
// pat_a & pat_b
|
||||
// }
|
||||
// smallnum := Cat(
|
||||
// pat1(List(3),List(-3, -2, -1)),
|
||||
//
|
||||
// pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
|
||||
//
|
||||
// pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1)) | pat1(List(3),List(-3, -1))& !b_ff(0) |
|
||||
// pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0) |
|
||||
// pat1(List(3, 2),List(-3, 2, -1)) | pat1(List(3, 1),List(-3,-1)) | pat1(List(3, 2, 1),List(-3, 2)),
|
||||
//
|
||||
// pat1(List(2, 1, 0),List(-3, -1)) | pat1(List(3, -2, 0),List(-3, 1, 0)) | pat1(List(2),List(-3, -1))& !b_ff(0) |
|
||||
// pat1(List(1),List(-3, -2))& !b_ff(0) | pat1(List(0),List(-3, -2, -1)) | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
|
||||
// pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0) | pat1(List(3, -2),List(-3, 2, 1)) |
|
||||
// pat1(List(-3, 2, 1),List(-3, 2, -1)) | pat1(List(-3, 2, 0),List(-3, -1)) | pat1(List(3, -2, -1),List(-3, 2, 0)) |
|
||||
// pat1(List(-2, 1, 0),List(-3, -2)) | pat1(List(3, 2),List(-1)) & !b_ff(0) | pat1(List(-3, 2, 1, 0),List(-3, 2)) |
|
||||
// pat1(List(3, 2),List(3, -2)) | pat1(List(3, 1),List(3,-2,-1)) | pat1(List(3, 0),List(-2, -1)) |
|
||||
// pat1(List(3, -1),List(-3, 2, 1, 0)) | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1)) |
|
||||
// pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) |
|
||||
// pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0))
|
||||
//
|
||||
// val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0))
|
||||
// val a_enc = Module(new exu_div_cls)
|
||||
// a_enc.io.operand := shortq_dividend
|
||||
// val dw_a_enc1 = a_enc.io.cls
|
||||
// val b_enc = Module(new exu_div_cls)
|
||||
// b_enc.io.operand := b_ff(32,0)
|
||||
// val dw_b_enc1 = b_enc.io.cls
|
||||
// val dw_a_enc = Cat (0.U, dw_a_enc1)
|
||||
// val dw_b_enc = Cat (0.U, dw_b_enc1)
|
||||
//
|
||||
// val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
|
||||
// val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
|
||||
// shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel
|
||||
// val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0)
|
||||
// shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
|
||||
// shortq_shift := Mux(!shortq_enable,0.U,shortq_decode)
|
||||
// b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
|
||||
// valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
|
||||
// control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode)
|
||||
// by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
|
||||
// shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
|
||||
// shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
|
||||
// finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
|
||||
// count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
|
||||
//
|
||||
// a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
|
||||
// b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
|
||||
// r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
|
||||
// q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
|
||||
//
|
||||
//}
|
||||
object div_main4 extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_3bit_fullshortq()))
|
||||
}
|
||||
class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib {
|
||||
val io = IO(new Bundle{
|
||||
val scan_mode = Input(Bool())
|
||||
val cancel = Input(Bool())
|
||||
val valid_in = Input(Bool())
|
||||
val signed_in = Input(Bool())
|
||||
val rem_in = Input(Bool())
|
||||
val dividend_in = Input(UInt(32.W))
|
||||
val divisor_in = Input(UInt(32.W))
|
||||
val data_out = Output(UInt(32.W))
|
||||
val valid_out = Output(UInt(1.W))
|
||||
})
|
||||
io.data_out :=5.U
|
||||
io.valid_out :=1.U
|
||||
}
|
||||
|
||||
class exu_div_cls extends Module{
|
||||
val io= IO(new Bundle{
|
||||
val operand = Input(UInt(33.W))
|
||||
|
|
|
|||
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Reference in New Issue