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dccm_ctl with dccm_dma_rdata corrected

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​Laraib Khan 2020-12-23 14:38:53 +05:00
parent 1b7a0b47e1
commit 6ce67de95c
4 changed files with 2972 additions and 2972 deletions
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4117
lsu_dccm_ctl.fir
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1825
lsu_dccm_ctl.v
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2
src/main/scala/lsu/lsu_dccm_ctl.scala
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@ -144,7 +144,7 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
else{ else{
io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma
io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc
io.dma_dccm_ctl.dccm_dma_rdata := Mux(io.ldst_dual_m,lsu_rdata_corr_m, Fill(2,lsu_rdata_corr_m)) io.dma_dccm_ctl.dccm_dma_rdata := Mux(io.ldst_dual_m,lsu_rdata_corr_m, Fill(2,lsu_rdata_corr_m(31,0)))
io.dma_dccm_ctl.dccm_dma_rtag := io.dma_mem_tag_m io.dma_dccm_ctl.dccm_dma_rtag := io.dma_mem_tag_m
io.dccm_rdata_lo_r := 0.U io.dccm_rdata_lo_r := 0.U
io.dccm_rdata_hi_r := 0.U io.dccm_rdata_hi_r := 0.U

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target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
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