Only 1 obj
This commit is contained in:
waleed-lm
parent
c6eb0bc37a
commit
7033394ff1
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@ -64248,7 +64248,7 @@ circuit quasar_wrapper :
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io.iccm_dma_rdata <= mem_ctl.io.iccm_dma_rdata @[ifu.scala 115:21]
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io.iccm_dma_rdata <= mem_ctl.io.iccm_dma_rdata @[ifu.scala 115:21]
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io.iccm_dma_rtag <= mem_ctl.io.iccm_dma_rtag @[ifu.scala 116:20]
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io.iccm_dma_rtag <= mem_ctl.io.iccm_dma_rtag @[ifu.scala 116:20]
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io.iccm_ready <= mem_ctl.io.iccm_ready @[ifu.scala 117:17]
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io.iccm_ready <= mem_ctl.io.iccm_ready @[ifu.scala 117:17]
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io.iccm_dma_sb_error <= mem_ctl.io.iccm_dma_sb_error @[ifu.scala 119:24]
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io.iccm_dma_sb_error <= mem_ctl.io.iccm_dma_sb_error @[ifu.scala 118:24]
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module dec_ib_ctl :
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module dec_ib_ctl :
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input clock : Clock
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input clock : Clock
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@ -114627,35 +114627,35 @@ circuit quasar_wrapper :
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io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 480:22]
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io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 480:22]
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io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 481:18]
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io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 481:18]
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skip @[quasar.scala 296:26]
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skip @[quasar.scala 296:26]
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else : @[quasar.scala 485:17]
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else : @[quasar.scala 483:17]
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io.haddr <= UInt<1>("h00") @[quasar.scala 487:18]
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io.haddr <= UInt<1>("h00") @[quasar.scala 485:18]
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io.hburst <= UInt<1>("h00") @[quasar.scala 488:19]
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io.hburst <= UInt<1>("h00") @[quasar.scala 486:19]
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io.hmastlock <= UInt<1>("h00") @[quasar.scala 489:22]
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io.hmastlock <= UInt<1>("h00") @[quasar.scala 487:22]
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io.hprot <= UInt<1>("h00") @[quasar.scala 490:18]
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io.hprot <= UInt<1>("h00") @[quasar.scala 488:18]
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io.hsize <= UInt<1>("h00") @[quasar.scala 491:18]
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io.hsize <= UInt<1>("h00") @[quasar.scala 489:18]
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io.htrans <= UInt<1>("h00") @[quasar.scala 492:19]
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io.htrans <= UInt<1>("h00") @[quasar.scala 490:19]
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io.hwrite <= UInt<1>("h00") @[quasar.scala 493:19]
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io.hwrite <= UInt<1>("h00") @[quasar.scala 491:19]
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io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 496:22]
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io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 494:22]
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io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 497:23]
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io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 495:23]
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io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 498:26]
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io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 496:26]
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io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 499:22]
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io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 497:22]
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io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 500:22]
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io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 498:22]
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io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 501:23]
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io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 499:23]
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io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 502:23]
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io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 500:23]
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io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 503:23]
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io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 501:23]
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io.sb_haddr <= UInt<1>("h00") @[quasar.scala 505:21]
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io.sb_haddr <= UInt<1>("h00") @[quasar.scala 503:21]
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io.sb_hburst <= UInt<1>("h00") @[quasar.scala 506:22]
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io.sb_hburst <= UInt<1>("h00") @[quasar.scala 504:22]
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io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 507:25]
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io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 505:25]
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io.sb_hprot <= UInt<1>("h00") @[quasar.scala 508:21]
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io.sb_hprot <= UInt<1>("h00") @[quasar.scala 506:21]
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io.sb_hsize <= UInt<1>("h00") @[quasar.scala 509:21]
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io.sb_hsize <= UInt<1>("h00") @[quasar.scala 507:21]
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io.sb_htrans <= UInt<1>("h00") @[quasar.scala 510:22]
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io.sb_htrans <= UInt<1>("h00") @[quasar.scala 508:22]
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io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 511:22]
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io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 509:22]
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io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 512:22]
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io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 510:22]
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io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 514:23]
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io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 512:23]
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io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 515:26]
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io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 513:26]
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io.dma_hresp <= UInt<1>("h00") @[quasar.scala 516:22]
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io.dma_hresp <= UInt<1>("h00") @[quasar.scala 514:22]
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skip @[quasar.scala 485:17]
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skip @[quasar.scala 483:17]
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io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 518:20]
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io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 516:20]
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module quasar_wrapper :
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module quasar_wrapper :
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input clock : Clock
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input clock : Clock
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@ -114688,282 +114688,282 @@ circuit quasar_wrapper :
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dmi_wrapper.tms is invalid
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dmi_wrapper.tms is invalid
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dmi_wrapper.tck is invalid
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dmi_wrapper.tck is invalid
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dmi_wrapper.trst_n is invalid
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dmi_wrapper.trst_n is invalid
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inst swerv of quasar @[quasar_wrapper.scala 80:21]
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inst core of quasar @[quasar_wrapper.scala 80:20]
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swerv.clock <= clock
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core.clock <= clock
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swerv.reset <= reset
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core.reset <= reset
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dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 81:25]
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dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 81:25]
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dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 82:22]
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dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 82:22]
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dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 83:22]
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dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 83:22]
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dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 84:22]
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dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 84:22]
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dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 85:27]
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dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 85:27]
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dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 86:26]
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dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 86:26]
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dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26]
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dmi_wrapper.rd_data <= core.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26]
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dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 90:29]
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dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 90:29]
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swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:26]
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core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:25]
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swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:25]
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core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:24]
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swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:23]
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core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:22]
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swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:26]
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core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:25]
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swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:27]
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core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:26]
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io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 96:15]
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io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 96:15]
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mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 99:28]
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mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 99:28]
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mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 100:27]
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mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 100:27]
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mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35]
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mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35]
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swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15]
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core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15]
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swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15]
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core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15]
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mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15]
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mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15]
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mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 102:15]
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mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 102:15]
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mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 102:15]
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mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 102:15]
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mem.rst_l <= reset @[quasar_wrapper.scala 103:16]
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mem.rst_l <= reset @[quasar_wrapper.scala 103:16]
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mem.clk <= clock @[quasar_wrapper.scala 104:14]
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mem.clk <= clock @[quasar_wrapper.scala 104:14]
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mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 105:20]
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mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 105:20]
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swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:22]
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core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:21]
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mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 108:15]
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mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 108:14]
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mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 108:15]
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mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 108:14]
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mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 108:15]
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mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 108:14]
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mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 108:15]
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mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 108:14]
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mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 108:15]
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mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 108:14]
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mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 108:15]
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mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 108:14]
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swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:15]
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core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:14]
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swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:15]
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core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:14]
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swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:15]
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core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:14]
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swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:15]
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core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:14]
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swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:15]
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core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:14]
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swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:15]
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core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:14]
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swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:15]
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core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:14]
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mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 108:15]
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mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 108:14]
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mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 108:15]
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mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 108:14]
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mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 108:15]
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mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 108:14]
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mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 108:15]
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mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 108:14]
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mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 108:15]
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mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 108:14]
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mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 108:15]
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mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 108:14]
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mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 108:15]
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mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 108:14]
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mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 108:15]
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mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 108:14]
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swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:17]
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core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:16]
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swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:17]
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core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:16]
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mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 109:17]
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mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 109:16]
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mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 109:17]
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mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 109:16]
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mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 109:17]
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mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 109:16]
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mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 109:17]
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mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 109:16]
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mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 109:17]
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mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 109:16]
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mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:17]
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mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:16]
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mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 109:17]
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mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 109:16]
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swerv.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:22]
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core.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:21]
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swerv.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:19]
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core.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:18]
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swerv.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:21]
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core.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:20]
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swerv.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:23]
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core.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:22]
|
||||||
swerv.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:22]
|
core.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:21]
|
||||||
swerv.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:23]
|
core.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:22]
|
||||||
swerv.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:19]
|
core.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:18]
|
||||||
swerv.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:18]
|
core.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:17]
|
||||||
swerv.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:22]
|
core.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:21]
|
||||||
swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:22]
|
core.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:21]
|
||||||
swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:22]
|
core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21]
|
||||||
swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:20]
|
core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19]
|
||||||
swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:20]
|
core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19]
|
||||||
swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:20]
|
core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:19]
|
||||||
swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:27]
|
core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:26]
|
||||||
swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:26]
|
core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:25]
|
||||||
swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 129:20]
|
core.io.core_id <= io.core_id @[quasar_wrapper.scala 129:19]
|
||||||
swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:31]
|
core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:30]
|
||||||
swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:30]
|
core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:29]
|
||||||
swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:30]
|
core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:29]
|
||||||
swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:19]
|
||||||
io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:20]
|
io.lsu_axi.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:20]
|
core.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:19]
|
||||||
swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:19]
|
||||||
io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:20]
|
io.ifu_axi.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:20]
|
core.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:19]
|
||||||
swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 144:19]
|
io.sb_axi.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:19]
|
io.sb_axi.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 144:19]
|
io.sb_axi.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:19]
|
io.sb_axi.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:19]
|
io.sb_axi.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:19]
|
io.sb_axi.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 144:19]
|
io.sb_axi.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:18]
|
||||||
io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:19]
|
io.sb_axi.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:18]
|
||||||
swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:19]
|
core.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:18]
|
||||||
io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:20]
|
io.dma_axi.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:20]
|
io.dma_axi.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:20]
|
io.dma_axi.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:20]
|
io.dma_axi.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 148:20]
|
io.dma_axi.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:20]
|
io.dma_axi.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:20]
|
io.dma_axi.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:20]
|
io.dma_axi.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 148:20]
|
io.dma_axi.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 148:20]
|
io.dma_axi.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:20]
|
core.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:19]
|
||||||
io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:20]
|
io.dma_axi.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:19]
|
||||||
swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:21]
|
core.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:20]
|
||||||
swerv.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:22]
|
core.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:21]
|
||||||
swerv.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:23]
|
core.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:22]
|
||||||
swerv.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:26]
|
core.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:25]
|
||||||
swerv.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:22]
|
core.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:21]
|
||||||
swerv.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:22]
|
core.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:21]
|
||||||
swerv.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:23]
|
core.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:22]
|
||||||
swerv.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:23]
|
core.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:22]
|
||||||
swerv.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:23]
|
core.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:22]
|
||||||
swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:25]
|
core.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:24]
|
||||||
swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 178:27]
|
core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 162:26]
|
||||||
swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 179:27]
|
core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 163:26]
|
||||||
swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 180:27]
|
core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 164:26]
|
||||||
swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 181:27]
|
core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 165:26]
|
||||||
swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 183:22]
|
core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 167:21]
|
||||||
swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 184:21]
|
core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 168:20]
|
||||||
swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 185:26]
|
core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 169:25]
|
||||||
io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 189:19]
|
io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 173:19]
|
||||||
io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 192:21]
|
io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 176:21]
|
||||||
io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 193:24]
|
io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 177:24]
|
||||||
io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 194:20]
|
io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 178:20]
|
||||||
io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 195:26]
|
io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 179:26]
|
||||||
io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 197:25]
|
io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 181:25]
|
||||||
io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 198:24]
|
io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 182:24]
|
||||||
io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 199:25]
|
io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 183:25]
|
||||||
io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 201:23]
|
io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 185:23]
|
||||||
io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 202:23]
|
io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 186:23]
|
||||||
io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 203:23]
|
io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 187:23]
|
||||||
io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 204:23]
|
io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 188:23]
|
||||||
io.dma_hrdata <= swerv.io.dma_hrdata @[quasar_wrapper.scala 211:17]
|
io.dma_hrdata <= core.io.dma_hrdata @[quasar_wrapper.scala 195:17]
|
||||||
io.dma_hreadyout <= swerv.io.dma_hreadyout @[quasar_wrapper.scala 212:20]
|
io.dma_hreadyout <= core.io.dma_hreadyout @[quasar_wrapper.scala 196:20]
|
||||||
io.dma_hresp <= swerv.io.dma_hresp @[quasar_wrapper.scala 213:16]
|
io.dma_hresp <= core.io.dma_hresp @[quasar_wrapper.scala 197:16]
|
||||||
|
|
||||||
|
|
|
||||||
974
quasar_wrapper.v
974
quasar_wrapper.v
File diff suppressed because it is too large
Load Diff
|
|
@ -303,7 +303,3 @@ class dec extends Module with param with RequireAsyncReset{
|
||||||
// debug command read data
|
// debug command read data
|
||||||
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
||||||
}
|
}
|
||||||
|
|
||||||
object dec_main extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
|
|
||||||
}
|
|
||||||
|
|
@ -115,10 +115,5 @@ class ifu extends Module with lib with RequireAsyncReset {
|
||||||
io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
|
io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
|
||||||
io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
|
io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
|
||||||
io.iccm_ready := mem_ctl.io.iccm_ready
|
io.iccm_ready := mem_ctl.io.iccm_ready
|
||||||
|
|
||||||
io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
||||||
|
|
||||||
}
|
|
||||||
object ifu extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -223,6 +223,3 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
||||||
|
|
||||||
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
||||||
}
|
}
|
||||||
object AHB_main extends App {
|
|
||||||
println("Generate Verilog")
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))}
|
|
||||||
|
|
|
||||||
|
|
@ -69,7 +69,3 @@ class blackbox_mem extends Module with lib {
|
||||||
val it = Module(new quasar.mem)
|
val it = Module(new quasar.mem)
|
||||||
io <> it.io
|
io <> it.io
|
||||||
}
|
}
|
||||||
|
|
||||||
object mem extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new blackbox_mem))
|
|
||||||
}
|
|
||||||
|
|
|
||||||
|
|
@ -405,8 +405,3 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
object pic_main extends App{
|
|
||||||
println("Generating Verilog...")
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
|
|
||||||
}
|
|
||||||
|
|
@ -479,8 +479,6 @@ class quasar extends Module with RequireAsyncReset with lib {
|
||||||
io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
|
io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
|
||||||
io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
|
io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
|
||||||
io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
|
io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
|
||||||
// io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata
|
|
||||||
// io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata
|
|
||||||
}
|
}
|
||||||
.otherwise{
|
.otherwise{
|
||||||
// AHB Signals
|
// AHB Signals
|
||||||
|
|
|
||||||
|
|
@ -77,140 +77,124 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
})
|
})
|
||||||
val mem = Module(new quasar.mem())
|
val mem = Module(new quasar.mem())
|
||||||
val dmi_wrapper = Module(new dmi_wrapper())
|
val dmi_wrapper = Module(new dmi_wrapper())
|
||||||
val swerv = Module(new quasar())
|
val core = Module(new quasar())
|
||||||
dmi_wrapper.io.trst_n := io.jtag_trst_n
|
dmi_wrapper.io.trst_n := io.jtag_trst_n
|
||||||
dmi_wrapper.io.tck := io.jtag_tck
|
dmi_wrapper.io.tck := io.jtag_tck
|
||||||
dmi_wrapper.io.tms := io.jtag_tms
|
dmi_wrapper.io.tms := io.jtag_tms
|
||||||
dmi_wrapper.io.tdi := io.jtag_tdi
|
dmi_wrapper.io.tdi := io.jtag_tdi
|
||||||
dmi_wrapper.io.core_clk := clock
|
dmi_wrapper.io.core_clk := clock
|
||||||
dmi_wrapper.io.jtag_id := io.jtag_id
|
dmi_wrapper.io.jtag_id := io.jtag_id
|
||||||
dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata
|
dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
|
||||||
|
|
||||||
|
|
||||||
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
|
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
|
||||||
swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
|
core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
|
||||||
swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
|
core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
|
||||||
swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en
|
core.io.dmi_reg_en := dmi_wrapper.io.reg_en
|
||||||
swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
|
core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
|
||||||
swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
|
core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
|
||||||
io.jtag_tdo := dmi_wrapper.io.tdo
|
io.jtag_tdo := dmi_wrapper.io.tdo
|
||||||
|
|
||||||
// Memory signals
|
// Memory signals
|
||||||
mem.io.dccm_clk_override := swerv.io.dccm_clk_override
|
mem.io.dccm_clk_override := core.io.dccm_clk_override
|
||||||
mem.io.icm_clk_override := swerv.io.icm_clk_override
|
mem.io.icm_clk_override := core.io.icm_clk_override
|
||||||
mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable
|
mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
|
||||||
mem.io.dccm <> swerv.io.dccm
|
mem.io.dccm <> core.io.dccm
|
||||||
mem.io.rst_l := reset
|
mem.io.rst_l := reset
|
||||||
mem.io.clk := clock
|
mem.io.clk := clock
|
||||||
mem.io.scan_mode := io.scan_mode
|
mem.io.scan_mode := io.scan_mode
|
||||||
// Memory outputs
|
// Memory outputs
|
||||||
swerv.io.dbg_rst_l := io.dbg_rst_l
|
core.io.dbg_rst_l := io.dbg_rst_l
|
||||||
swerv.io.ic <> mem.io.ic
|
core.io.ic <> mem.io.ic
|
||||||
swerv.io.iccm <> mem.io.iccm
|
core.io.iccm <> mem.io.iccm
|
||||||
swerv.io.sb_hready := 0.U
|
core.io.sb_hready := 0.U
|
||||||
swerv.io.hrdata := 0.U
|
core.io.hrdata := 0.U
|
||||||
swerv.io.sb_hresp := 0.U
|
core.io.sb_hresp := 0.U
|
||||||
swerv.io.lsu_hrdata := 0.U
|
core.io.lsu_hrdata := 0.U
|
||||||
swerv.io.lsu_hresp := 0.U
|
core.io.lsu_hresp := 0.U
|
||||||
swerv.io.lsu_hready := 0.U
|
core.io.lsu_hready := 0.U
|
||||||
swerv.io.hready := 0.U
|
core.io.hready := 0.U
|
||||||
swerv.io.hresp := 0.U
|
core.io.hresp := 0.U
|
||||||
swerv.io.sb_hrdata := 0.U
|
core.io.sb_hrdata := 0.U
|
||||||
swerv.io.scan_mode := io.scan_mode
|
core.io.scan_mode := io.scan_mode
|
||||||
// SweRV Inputs
|
// SweRV Inputs
|
||||||
swerv.io.dbg_rst_l := io.dbg_rst_l
|
core.io.dbg_rst_l := io.dbg_rst_l
|
||||||
swerv.io.rst_vec := io.rst_vec
|
core.io.rst_vec := io.rst_vec
|
||||||
swerv.io.nmi_int := io.nmi_int
|
core.io.nmi_int := io.nmi_int
|
||||||
swerv.io.nmi_vec := io.nmi_vec
|
core.io.nmi_vec := io.nmi_vec
|
||||||
|
|
||||||
// external halt/run interface
|
// external halt/run interface
|
||||||
swerv.io.i_cpu_halt_req := io.i_cpu_halt_req
|
core.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||||
swerv.io.i_cpu_run_req := io.i_cpu_run_req
|
core.io.i_cpu_run_req := io.i_cpu_run_req
|
||||||
swerv.io.core_id := io.core_id
|
core.io.core_id := io.core_id
|
||||||
|
|
||||||
// external MPC halt/run interface
|
// external MPC halt/run interface
|
||||||
swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||||
swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
|
core.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||||
swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
|
core.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||||
|
|
||||||
//-------------------------- LSU AXI signals--------------------------
|
//-------------------------- LSU AXI signals--------------------------
|
||||||
// AXI Write Channels
|
// AXI Write Channels
|
||||||
swerv.io.lsu_axi <> io.lsu_axi
|
core.io.lsu_axi <> io.lsu_axi
|
||||||
//-------------------------- IFU AXI signals--------------------------
|
//-------------------------- IFU AXI signals--------------------------
|
||||||
// AXI Write Channels
|
// AXI Write Channels
|
||||||
swerv.io.ifu_axi <> io.ifu_axi
|
core.io.ifu_axi <> io.ifu_axi
|
||||||
//-------------------------- SB AXI signals--------------------------
|
//-------------------------- SB AXI signals--------------------------
|
||||||
// AXI Write Channels
|
// AXI Write Channels
|
||||||
swerv.io.sb_axi <> io.sb_axi
|
core.io.sb_axi <> io.sb_axi
|
||||||
|
|
||||||
//-------------------------- DMA AXI signals--------------------------
|
//-------------------------- DMA AXI signals--------------------------
|
||||||
// AXI Write Channels
|
// AXI Write Channels
|
||||||
swerv.io.dma_axi <> io.dma_axi
|
core.io.dma_axi <> io.dma_axi
|
||||||
|
|
||||||
// DMA Slave
|
// DMA Slave
|
||||||
swerv.io.dma_hsel := io.dma_hsel
|
core.io.dma_hsel := io.dma_hsel
|
||||||
swerv.io.dma_haddr := io.dma_haddr
|
core.io.dma_haddr := io.dma_haddr
|
||||||
swerv.io.dma_hburst := io.dma_hburst
|
core.io.dma_hburst := io.dma_hburst
|
||||||
swerv.io.dma_hmastlock := io.dma_hmastlock
|
core.io.dma_hmastlock := io.dma_hmastlock
|
||||||
swerv.io.dma_hprot := io.dma_hprot
|
core.io.dma_hprot := io.dma_hprot
|
||||||
swerv.io.dma_hsize := io.dma_hsize
|
core.io.dma_hsize := io.dma_hsize
|
||||||
swerv.io.dma_htrans := io.dma_htrans
|
core.io.dma_htrans := io.dma_htrans
|
||||||
swerv.io.dma_hwrite := io.dma_hwrite
|
core.io.dma_hwrite := io.dma_hwrite
|
||||||
swerv.io.dma_hwdata := io.dma_hwdata
|
core.io.dma_hwdata := io.dma_hwdata
|
||||||
swerv.io.dma_hreadyin := io.dma_hreadyin
|
core.io.dma_hreadyin := io.dma_hreadyin
|
||||||
|
|
||||||
swerv.io.lsu_bus_clk_en
|
core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||||
swerv.io.ifu_bus_clk_en
|
core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||||
swerv.io.dbg_bus_clk_en
|
core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||||
swerv.io.dma_bus_clk_en
|
core.io.dma_bus_clk_en := io.dma_bus_clk_en
|
||||||
|
|
||||||
swerv.io.dmi_reg_en
|
core.io.timer_int := io.timer_int
|
||||||
swerv.io.dmi_reg_addr
|
core.io.soft_int := io.soft_int
|
||||||
swerv.io.dmi_reg_wr_en
|
core.io.extintsrc_req := io.extintsrc_req
|
||||||
swerv.io.dmi_reg_wdata
|
|
||||||
swerv.io.dmi_hard_reset
|
|
||||||
|
|
||||||
swerv.io.extintsrc_req
|
|
||||||
swerv.io.timer_int
|
|
||||||
swerv.io.soft_int
|
|
||||||
swerv.io.scan_mode
|
|
||||||
|
|
||||||
swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
|
||||||
swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
|
||||||
swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
|
||||||
swerv.io.dma_bus_clk_en := io.dma_bus_clk_en
|
|
||||||
|
|
||||||
swerv.io.timer_int := io.timer_int
|
|
||||||
swerv.io.soft_int := io.soft_int
|
|
||||||
swerv.io.extintsrc_req := io.extintsrc_req
|
|
||||||
|
|
||||||
// Outputs
|
// Outputs
|
||||||
val core_rst_l = swerv.io.core_rst_l
|
val core_rst_l = core.io.core_rst_l
|
||||||
io.rv_trace_pkt := swerv.io.rv_trace_pkt
|
io.rv_trace_pkt := core.io.rv_trace_pkt
|
||||||
|
|
||||||
// external halt/run interface
|
// external halt/run interface
|
||||||
io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack
|
io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
|
||||||
io.o_cpu_halt_status := swerv.io.o_cpu_halt_status
|
io.o_cpu_halt_status := core.io.o_cpu_halt_status
|
||||||
io.o_cpu_run_ack := swerv.io.o_cpu_run_ack
|
io.o_cpu_run_ack := core.io.o_cpu_run_ack
|
||||||
io.o_debug_mode_status := swerv.io.o_debug_mode_status
|
io.o_debug_mode_status := core.io.o_debug_mode_status
|
||||||
|
|
||||||
io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack
|
io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
|
||||||
io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack
|
io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
|
||||||
io.debug_brkpt_status := swerv.io.debug_brkpt_status
|
io.debug_brkpt_status := core.io.debug_brkpt_status
|
||||||
|
|
||||||
io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0
|
io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
|
||||||
io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1
|
io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
|
||||||
io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2
|
io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
|
||||||
io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3
|
io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
|
||||||
|
|
||||||
|
|
||||||
//-------------------------- LSU AXI signals--------------------------
|
//-------------------------- LSU AXI signals--------------------------
|
||||||
// AXI Write Channels
|
// AXI Write Channels
|
||||||
|
|
||||||
// DMA Slave
|
// DMA Slave
|
||||||
io.dma_hrdata := swerv.io.dma_hrdata
|
io.dma_hrdata := core.io.dma_hrdata
|
||||||
io.dma_hreadyout := swerv.io.dma_hreadyout
|
io.dma_hreadyout := core.io.dma_hreadyout
|
||||||
io.dma_hresp := swerv.io.dma_hresp
|
io.dma_hresp := core.io.dma_hresp
|
||||||
|
|
||||||
}
|
}
|
||||||
object QUASAR_Wrp extends App {
|
object QUASAR_Wrp extends App {
|
||||||
|
|
|
||||||
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Reference in New Issue