Num-Valid updated
This commit is contained in:
waleed-lm
parent
68d0cbcabe
commit
7127367363
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@ -1,90 +0,0 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2018 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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//
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// Copyright Western Digital, 2018
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// Owner : Anusha Narayanamoorthy
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// Description:
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// Wrapper module for JTAG_TAP and DMI synchronizer
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//
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//-------------------------------------------------------------------------------------
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module dmi_wrapper(
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// JTAG signals
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input trst_n, // JTAG reset
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input tck, // JTAG clock
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input tms, // Test mode select
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input tdi, // Test Data Input
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output tdo, // Test Data Output
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output tdoEnable, // Test Data Output enable
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// Processor Signals
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input core_rst_n, // Core reset
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input core_clk, // Core clock
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input [31:1] jtag_id, // JTAG ID
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input [31:0] rd_data, // 32 bit Read data from Processor
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output [31:0] reg_wr_data, // 32 bit Write data to Processor
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output [6:0] reg_wr_addr, // 7 bit reg address to Processor
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output reg_en, // 1 bit Read enable to Processor
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output reg_wr_en, // 1 bit Write enable to Processor
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output dmi_hard_reset
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);
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//Wire Declaration
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wire rd_en;
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wire wr_en;
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wire dmireset;
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//jtag_tap instantiation
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rvjtag_tap i_jtag_tap(
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.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
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.tck(tck), // dedicated JTAG TCK pad signal
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.tms(tms), // dedicated JTAG TMS pad signal
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.tdi(tdi), // dedicated JTAG TDI pad signal
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.tdo(tdo), // dedicated JTAG TDO pad signal
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.tdoEnable(tdoEnable), // enable for TDO pad
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.wr_data(reg_wr_data), // 32 bit Write data
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.wr_addr(reg_wr_addr), // 7 bit Write address
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.rd_en(rd_en), // 1 bit read enable
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.wr_en(wr_en), // 1 bit Write enable
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.rd_data(rd_data), // 32 bit Read data
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.rd_status(2'b0),
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.idle(3'h0), // no need to wait to sample data
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.dmi_stat(2'b0), // no need to wait or error possible
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.version(4'h1), // debug spec 0.13 compliant
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.jtag_id(jtag_id),
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.dmi_hard_reset(dmi_hard_reset),
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.dmi_reset(dmireset)
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);
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// dmi_jtag_to_core_sync instantiation
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dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
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.wr_en(wr_en), // 1 bit Write enable
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.rd_en(rd_en), // 1 bit Read enable
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.rst_n(core_rst_n),
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.clk(core_clk),
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.reg_en(reg_en), // 1 bit Write interface bit
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.reg_wr_en(reg_wr_en) // 1 bit Write enable
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);
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endmodule
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@ -1,3 +0,0 @@
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/home/waleedbinehsan/Desktop/Quasar/design/gated_latch.sv
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/home/waleedbinehsan/Desktop/Quasar/design/dmi_wrapper.sv
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/home/waleedbinehsan/Desktop/Quasar/design/mem.sv
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@ -1,14 +0,0 @@
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module gated_latch
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(
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input logic SE, EN, CK,
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output Q
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);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always @(CK, enable) begin
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if(!CK)
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en_ff = enable;
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end
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assign Q = CK & en_ff;
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endmodule
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173
design/mem.sv
173
design/mem.sv
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@ -1,173 +0,0 @@
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module mem #(
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parameter ICACHE_BEAT_BITS,
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parameter ICCM_BITS,
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parameter ICACHE_NUM_WAYS,
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parameter DCCM_BYTE_WIDTH,
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parameter ICCM_BANK_INDEX_LO,
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parameter ICACHE_BANK_BITS,
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parameter DCCM_BITS,
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parameter ICACHE_BEAT_ADDR_HI,
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parameter ICCM_INDEX_BITS,
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parameter ICCM_BANK_HI,
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parameter ICACHE_BANKS_WAY,
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parameter ICACHE_INDEX_HI,
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parameter DCCM_NUM_BANKS,
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parameter ICACHE_BANK_HI,
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parameter ICACHE_BANK_LO,
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parameter DCCM_ENABLE= 'b1,
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parameter ICACHE_TAG_LO,
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parameter ICACHE_DATA_INDEX_LO,
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parameter ICCM_NUM_BANKS,
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parameter ICACHE_ECC,
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parameter ICACHE_ENABLE= 'b1,
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parameter DCCM_BANK_BITS,
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parameter ICCM_ENABLE= 'b1,
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parameter ICCM_BANK_BITS,
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parameter ICACHE_TAG_DEPTH,
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parameter ICACHE_WAYPACK,
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parameter DCCM_SIZE,
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parameter DCCM_FDATA_WIDTH,
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parameter ICACHE_TAG_INDEX_LO,
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parameter ICACHE_DATA_DEPTH)
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(
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input logic clk,
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input logic rst_l,
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input logic dccm_clk_override,
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input logic icm_clk_override,
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input logic dec_tlu_core_ecc_disable,
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//DCCM ports
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input logic dccm_wren,
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input logic dccm_rden,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
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//`ifdef DCCM_ENABLE
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//`endif
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//ICCM ports
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input logic [ICCM_BITS-1:1] iccm_rw_addr,
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input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
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input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
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input logic iccm_wren,
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input logic iccm_rden,
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input logic [2:0] iccm_wr_size,
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input logic [77:0] iccm_wr_data,
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output logic [63:0] iccm_rd_data,
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output logic [77:0] iccm_rd_data_ecc,
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// Icache and Itag Ports
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input logic [31:1] ic_rw_addr,
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input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
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input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
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input logic ic_rd_en,
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input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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input logic ic_sel_premux_data, // Premux data sel
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input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
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input logic [70:0] ic_wr_data_1,
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input logic [70:0] ic_debug_wr_data, // Debug wr cache.
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output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
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input logic ic_debug_rd_en, // Icache debug rd
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input logic ic_debug_wr_en, // Icache debug wr
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input logic ic_debug_tag_array, // Debug tag array
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input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
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output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
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output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
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output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
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output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
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output logic ic_tag_perr, // Icache Tag parity error
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input logic scan_mode
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);
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logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
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assign ic_wr_data [0] = ic_wr_data_0;
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assign ic_wr_data [1] = ic_wr_data_1;
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// DCCM Instantiation
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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lsu_dccm_mem #(
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.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
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.DCCM_BITS(DCCM_BITS),
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.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
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.DCCM_BANK_BITS(DCCM_BANK_BITS),
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.DCCM_SIZE(DCCM_SIZE),
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.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
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.clk_override(dccm_clk_override),
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.*
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);
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end else begin: Gen_dccm_disable
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assign dccm_rd_data_lo = '0;
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assign dccm_rd_data_hi = '0;
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end
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if ( ICACHE_ENABLE ) begin: icache
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ifu_ic_mem #(
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.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
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.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
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.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
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.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
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.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
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.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
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.ICACHE_BANK_HI(ICACHE_BANK_HI),
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.ICACHE_BANK_LO(ICACHE_BANK_LO),
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.ICACHE_TAG_LO(ICACHE_TAG_LO),
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.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
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.ICACHE_ECC(ICACHE_ECC),
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.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
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.ICACHE_WAYPACK(ICACHE_WAYPACK),
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.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
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.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
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.clk_override(icm_clk_override),
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.*
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);
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end
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else begin
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assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
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assign ic_tag_perr = '0 ;
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assign ic_rd_data = '0 ;
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assign ic_tag_debug_rd_data = '0 ;
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end // else: !if( ICACHE_ENABLE )
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if (ICCM_ENABLE) begin : iccm
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ifu_iccm_mem #(
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.ICCM_BITS(ICCM_BITS),
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.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
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.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
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.ICCM_BANK_HI(ICCM_BANK_HI),
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.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
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.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
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.clk_override(icm_clk_override),
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.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
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.iccm_rd_data(iccm_rd_data[63:0])
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);
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end
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else begin
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assign iccm_rd_data = '0 ;
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assign iccm_rd_data_ecc = '0 ;
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end
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endmodule
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File diff suppressed because it is too large
Load Diff
110192
design/quasar_wrapper.fir
110192
design/quasar_wrapper.fir
File diff suppressed because one or more lines are too long
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@ -1,232 +0,0 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by waleedbinehsan on و 15:35:44 PKT ت 07 جنوری 2021
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//
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// cmd: quasar -target=default
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//
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`define RV_ROOT "/home/waleedbinehsan/Desktop/Quasar"
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`define RV_TIMER_LEGAL_EN 1
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`define RV_LSU_NUM_NBLOAD 4
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`define RV_DMA_BUF_DEPTH 5
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`define RV_ICCM_ONLY derived
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`define RV_NO_ICCM_NO_ICACHE derived
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`define RV_LSU2DMA 0
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`define RV_ICACHE_ONLY derived
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`define RV_LSU_NUM_NBLOAD_WIDTH 2
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`define RV_FAST_INTERRUPT_REDIRECT 1
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`define RV_ICCM_ICACHE 1
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`define RV_FPGA_OPTIMIZE 0
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`define RV_LSU_STBUF_DEPTH 4
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`define RV_ICACHE_TAG_LO 13
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`define RV_ICACHE_FDATA_WIDTH 71
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`define RV_ICACHE_DATA_INDEX_LO 4
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`define RV_ICACHE_TAG_INDEX_LO 6
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`define RV_ICACHE_SIZE 16
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`define RV_ICACHE_NUM_LINES 256
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`define RV_ICACHE_BANK_WIDTH 8
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`define RV_ICACHE_NUM_LINES_WAY 128
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`define RV_ICACHE_TAG_CELL ram_128x25
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`define RV_ICACHE_INDEX_HI 12
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`define RV_ICACHE_NUM_LINES_BANK 64
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`define RV_ICACHE_BEAT_ADDR_HI 5
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`define RV_ICACHE_ECC 1
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`define RV_ICACHE_LN_SZ 64
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`define RV_ICACHE_BANK_HI 3
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`define RV_ICACHE_BEAT_BITS 3
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`define RV_ICACHE_2BANKS 1
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`define RV_ICACHE_BANK_LO 3
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`define RV_ICACHE_BANK_BITS 1
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`define RV_ICACHE_SCND_LAST 6
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`define RV_ICACHE_TAG_DEPTH 128
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`define RV_ICACHE_DATA_CELL ram_512x71
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`define RV_ICACHE_NUM_BEATS 8
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`define RV_ICACHE_BANKS_WAY 2
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`define RV_ICACHE_DATA_DEPTH 512
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`define RV_ICACHE_ENABLE 1
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`define RV_ICACHE_STATUS_BITS 1
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`define RV_ICACHE_NUM_WAYS 2
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`define RV_ICACHE_DATA_WIDTH 64
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`define RV_XLEN 32
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`define RV_RET_STACK_SIZE 8
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`define RV_CONFIG_KEY 32'hdeadbeef
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`define RV_NUMIREGS 32
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`define RV_TARGET default
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`define REGWIDTH 32
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`define RV_BTB_INDEX2_HI 17
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`define RV_BTB_BTAG_FOLD 0
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`define RV_BTB_ARRAY_DEPTH 256
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`define RV_BTB_INDEX2_LO 10
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`define RV_BTB_FOLD2_INDEX_HASH 0
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`define RV_BTB_ADDR_HI 9
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`define RV_BTB_ADDR_LO 2
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`define RV_BTB_INDEX1_LO 2
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`define RV_BTB_INDEX3_LO 18
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`define RV_BTB_SIZE 512
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`define RV_BTB_INDEX3_HI 25
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`define RV_BTB_BTAG_SIZE 5
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`define RV_BTB_INDEX1_HI 9
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`define RV_NMI_VEC 'h11110000
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`define RV_PIC_MEIGWCLR_MASK 'h0
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`define RV_PIC_MEIE_COUNT 31
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`define RV_PIC_INT_WORDS 1
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`define RV_PIC_MEIPT_MASK 'h0
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`define RV_PIC_MEIP_OFFSET 'h1000
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`define RV_PIC_MEIPL_COUNT 31
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`define RV_PIC_MEIGWCTRL_COUNT 31
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`define RV_PIC_SIZE 32
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`define RV_PIC_MPICCFG_COUNT 1
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`define RV_PIC_MEIPT_OFFSET 'h3004
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`define RV_PIC_MEIGWCLR_COUNT 31
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`define RV_PIC_MEIE_OFFSET 'h2000
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`define RV_PIC_MEIP_COUNT 4
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`define RV_PIC_TOTAL_INT 31
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`define RV_PIC_MEIGWCTRL_MASK 'h3
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`define RV_PIC_BITS 15
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`define RV_PIC_REGION 4'hf
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`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
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`define RV_PIC_OFFSET 10'hc0000
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`define RV_PIC_MPICCFG_MASK 'h1
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`define RV_PIC_MEIPL_OFFSET 'h0000
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`define RV_PIC_MEIPL_MASK 'hf
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`define RV_PIC_MEIPT_COUNT 31
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`define RV_PIC_MEIGWCLR_OFFSET 'h5000
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`define RV_PIC_MEIE_MASK 'h1
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`define RV_PIC_MPICCFG_OFFSET 'h3000
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`define RV_PIC_TOTAL_INT_PLUS1 32
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`define RV_PIC_BASE_ADDR 32'hf00c0000
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`define RV_PIC_MEIP_MASK 'h0
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`define RV_EXTERNAL_PROG 'hb0000000
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`define RV_UNUSED_REGION1 'h10000000
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`define RV_UNUSED_REGION3 'h30000000
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`define RV_UNUSED_REGION7 'h70000000
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`define RV_UNUSED_REGION4 'h40000000
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`define RV_EXTERNAL_DATA_1 'h00000000
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`define RV_UNUSED_REGION0 'h00000000
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`define RV_EXTERNAL_DATA 'hc0580000
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`define RV_DEBUG_SB_MEM 'hb0580000
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`define RV_SERIALIO 'hd0580000
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`define RV_UNUSED_REGION5 'h50000000
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`define RV_EXTERNAL_MEM_HOLE 'h90000000
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`define RV_UNUSED_REGION6 'h60000000
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`define RV_UNUSED_REGION2 'h20000000
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`define RV_BHT_GHR_HASH_1
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`define RV_BHT_ARRAY_DEPTH 256
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`define RV_BHT_SIZE 512
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`define RV_BHT_ADDR_HI 9
|
||||
`define RV_BHT_ADDR_LO 2
|
||||
`define RV_BHT_HASH_STRING {hashin[8+1:2]^ghr[8-1:0]}// cf2
|
||||
`define RV_BHT_GHR_RANGE 7:0
|
||||
`define RV_BHT_GHR_SIZE 8
|
||||
`define RV_DATA_ACCESS_ENABLE5 1'h0
|
||||
`define RV_INST_ACCESS_ENABLE6 1'h0
|
||||
`define RV_INST_ACCESS_ENABLE0 1'h1
|
||||
`define RV_DATA_ACCESS_ENABLE0 1'h1
|
||||
`define RV_INST_ACCESS_ENABLE5 1'h0
|
||||
`define RV_DATA_ACCESS_ENABLE6 1'h0
|
||||
`define RV_INST_ACCESS_MASK0 'h7fffffff
|
||||
`define RV_INST_ACCESS_MASK4 'hffffffff
|
||||
`define RV_DATA_ACCESS_ADDR0 'h0
|
||||
`define RV_INST_ACCESS_ENABLE2 1'h1
|
||||
`define RV_DATA_ACCESS_ENABLE4 1'h0
|
||||
`define RV_DATA_ACCESS_ADDR4 'h00000000
|
||||
`define RV_DATA_ACCESS_ENABLE2 1'h1
|
||||
`define RV_INST_ACCESS_ADDR0 'h0
|
||||
`define RV_INST_ACCESS_ENABLE4 1'h0
|
||||
`define RV_INST_ACCESS_ADDR4 'h00000000
|
||||
`define RV_DATA_ACCESS_MASK0 'h7fffffff
|
||||
`define RV_DATA_ACCESS_MASK4 'hffffffff
|
||||
`define RV_DATA_ACCESS_ADDR1 'hc0000000
|
||||
`define RV_INST_ACCESS_ENABLE7 1'h0
|
||||
`define RV_INST_ACCESS_MASK1 'h3fffffff
|
||||
`define RV_INST_ACCESS_ENABLE1 1'h1
|
||||
`define RV_DATA_ACCESS_ENABLE3 1'h1
|
||||
`define RV_DATA_ACCESS_ENABLE7 1'h0
|
||||
`define RV_DATA_ACCESS_MASK1 'h3fffffff
|
||||
`define RV_DATA_ACCESS_ENABLE1 1'h1
|
||||
`define RV_INST_ACCESS_ENABLE3 1'h1
|
||||
`define RV_INST_ACCESS_ADDR1 'hc0000000
|
||||
`define RV_DATA_ACCESS_MASK5 'hffffffff
|
||||
`define RV_DATA_ACCESS_ADDR3 'h80000000
|
||||
`define RV_INST_ACCESS_ADDR6 'h00000000
|
||||
`define RV_DATA_ACCESS_ADDR2 'ha0000000
|
||||
`define RV_DATA_ACCESS_ADDR7 'h00000000
|
||||
`define RV_INST_ACCESS_MASK3 'h0fffffff
|
||||
`define RV_INST_ACCESS_ADDR5 'h00000000
|
||||
`define RV_INST_ACCESS_MASK7 'hffffffff
|
||||
`define RV_INST_ACCESS_MASK2 'h1fffffff
|
||||
`define RV_DATA_ACCESS_MASK6 'hffffffff
|
||||
`define RV_DATA_ACCESS_MASK3 'h0fffffff
|
||||
`define RV_DATA_ACCESS_ADDR5 'h00000000
|
||||
`define RV_DATA_ACCESS_MASK7 'hffffffff
|
||||
`define RV_DATA_ACCESS_MASK2 'h1fffffff
|
||||
`define RV_INST_ACCESS_MASK6 'hffffffff
|
||||
`define RV_INST_ACCESS_MASK5 'hffffffff
|
||||
`define RV_INST_ACCESS_ADDR3 'h80000000
|
||||
`define RV_DATA_ACCESS_ADDR6 'h00000000
|
||||
`define RV_INST_ACCESS_ADDR2 'ha0000000
|
||||
`define RV_INST_ACCESS_ADDR7 'h00000000
|
||||
`define RV_ICCM_NUM_BANKS_4
|
||||
`define RV_ICCM_SADR 32'hee000000
|
||||
`define RV_ICCM_OFFSET 10'he000000
|
||||
`define RV_ICCM_REGION 4'he
|
||||
`define RV_ICCM_INDEX_BITS 12
|
||||
`define RV_ICCM_ENABLE 1
|
||||
`define RV_ICCM_SIZE 64
|
||||
`define RV_ICCM_BANK_HI 3
|
||||
`define RV_ICCM_RESERVED 'h1000
|
||||
`define RV_ICCM_ROWS 4096
|
||||
`define RV_ICCM_BANK_INDEX_LO 4
|
||||
`define RV_ICCM_BANK_BITS 2
|
||||
`define RV_ICCM_DATA_CELL ram_4096x39
|
||||
`define RV_ICCM_BITS 16
|
||||
`define RV_ICCM_SIZE_64
|
||||
`define RV_ICCM_NUM_BANKS 4
|
||||
`define RV_ICCM_EADR 32'hee00ffff
|
||||
`define RV_RESET_VEC 'h80000000
|
||||
`define RV_BUS_PRTY_DEFAULT 2'h3
|
||||
`define RV_IFU_BUS_PRTY 2
|
||||
`define RV_IFU_BUS_ID 1
|
||||
`define RV_DMA_BUS_TAG 1
|
||||
`define RV_LSU_BUS_TAG 3
|
||||
`define RV_SB_BUS_TAG 1
|
||||
`define RV_IFU_BUS_TAG 3
|
||||
`define RV_LSU_BUS_ID 1
|
||||
`define RV_DMA_BUS_PRTY 2
|
||||
`define RV_LSU_BUS_PRTY 2
|
||||
`define RV_DMA_BUS_ID 1
|
||||
`define RV_SB_BUS_PRTY 2
|
||||
`define RV_SB_BUS_ID 1
|
||||
`define TEC_RV_ICG clockhdr
|
||||
`define RV_EXT_DATAWIDTH 64
|
||||
`define CPU_TOP `RV_TOP.quasar
|
||||
`define RV_LDERR_ROLLBACK 1
|
||||
`define RV_TOP `TOP.rvtop
|
||||
`define RV_EXT_ADDRWIDTH 32
|
||||
`define CLOCK_PERIOD 100
|
||||
`define RV_BUILD_AXI4 1
|
||||
`define SDVT_AHB 1
|
||||
`define RV_STERR_ROLLBACK 0
|
||||
`define ASSERT_ON
|
||||
`define TOP tb_top
|
||||
`define RV_BUILD_AXI_NATIVE 1
|
||||
`define RV_DCCM_WIDTH_BITS 2
|
||||
`define RV_DCCM_INDEX_BITS 12
|
||||
`define RV_DCCM_SADR 32'hf0040000
|
||||
`define RV_DCCM_NUM_BANKS_4
|
||||
`define RV_DCCM_OFFSET 28'h40000
|
||||
`define RV_DCCM_FDATA_WIDTH 39
|
||||
`define RV_DCCM_REGION 4'hf
|
||||
`define RV_DCCM_RESERVED 'h1400
|
||||
`define RV_DCCM_SIZE 64
|
||||
`define RV_DCCM_ENABLE 1
|
||||
`define RV_DCCM_DATA_WIDTH 32
|
||||
`define RV_DCCM_BITS 16
|
||||
`define RV_DCCM_ROWS 4096
|
||||
`define RV_DCCM_BYTE_WIDTH 4
|
||||
`define RV_DCCM_BANK_BITS 2
|
||||
`define RV_DCCM_DATA_CELL ram_4096x39
|
||||
`define RV_DCCM_ECC_WIDTH 7
|
||||
`define RV_DCCM_EADR 32'hf004ffff
|
||||
`define RV_DCCM_SIZE_64
|
||||
`define RV_DCCM_NUM_BANKS 4
|
||||
`define RV_LSU_SB_BITS 16
|
||||
`undef RV_ASSERT_ON
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
// This is an automatically generated file by waleedbinehsan on و 15:35:44 PKT ت 07 جنوری 2021
|
||||
//
|
||||
// cmd: quasar -target=default
|
||||
//
|
||||
#define RV_TIMER_LEGAL_EN 1
|
||||
#define RV_LSU_NUM_NBLOAD 4
|
||||
#define RV_DMA_BUF_DEPTH 5
|
||||
#define RV_ICCM_ONLY derived
|
||||
#define RV_NO_ICCM_NO_ICACHE derived
|
||||
#define RV_LSU2DMA 0
|
||||
#define RV_ICACHE_ONLY derived
|
||||
#define RV_LSU_NUM_NBLOAD_WIDTH 2
|
||||
#define RV_FAST_INTERRUPT_REDIRECT 1
|
||||
#define RV_ICCM_ICACHE 1
|
||||
#define RV_FPGA_OPTIMIZE 0
|
||||
#define RV_LSU_STBUF_DEPTH 4
|
||||
#define RV_XLEN 32
|
||||
#define RV_TARGET default
|
||||
#ifndef RV_NMI_VEC
|
||||
#define RV_NMI_VEC 0x11110000
|
||||
#endif
|
||||
#define RV_PIC_MEIGWCLR_MASK 0x0
|
||||
#define RV_PIC_MEIE_COUNT 31
|
||||
#define RV_PIC_INT_WORDS 1
|
||||
#define RV_PIC_MEIPT_MASK 0x0
|
||||
#define RV_PIC_MEIP_OFFSET 0x1000
|
||||
#define RV_PIC_MEIPL_COUNT 31
|
||||
#define RV_PIC_MEIGWCTRL_COUNT 31
|
||||
#define RV_PIC_SIZE 32
|
||||
#define RV_PIC_MPICCFG_COUNT 1
|
||||
#define RV_PIC_MEIPT_OFFSET 0x3004
|
||||
#define RV_PIC_MEIGWCLR_COUNT 31
|
||||
#define RV_PIC_MEIE_OFFSET 0x2000
|
||||
#define RV_PIC_MEIP_COUNT 4
|
||||
#define RV_PIC_TOTAL_INT 31
|
||||
#define RV_PIC_MEIGWCTRL_MASK 0x3
|
||||
#define RV_PIC_BITS 15
|
||||
#define RV_PIC_REGION 0xf
|
||||
#define RV_PIC_MEIGWCTRL_OFFSET 0x4000
|
||||
#define RV_PIC_OFFSET 0xc0000
|
||||
#define RV_PIC_MPICCFG_MASK 0x1
|
||||
#define RV_PIC_MEIPL_OFFSET 0x0000
|
||||
#define RV_PIC_MEIPL_MASK 0xf
|
||||
#define RV_PIC_MEIPT_COUNT 31
|
||||
#define RV_PIC_MEIGWCLR_OFFSET 0x5000
|
||||
#define RV_PIC_MEIE_MASK 0x1
|
||||
#define RV_PIC_MPICCFG_OFFSET 0x3000
|
||||
#define RV_PIC_TOTAL_INT_PLUS1 32
|
||||
#define RV_PIC_BASE_ADDR 0xf00c0000
|
||||
#define RV_PIC_MEIP_MASK 0x0
|
||||
#define RV_EXTERNAL_PROG 0xb0000000
|
||||
#define RV_UNUSED_REGION1 0x10000000
|
||||
#define RV_UNUSED_REGION3 0x30000000
|
||||
#define RV_UNUSED_REGION7 0x70000000
|
||||
#define RV_UNUSED_REGION4 0x40000000
|
||||
#define RV_EXTERNAL_DATA_1 0x00000000
|
||||
#define RV_UNUSED_REGION0 0x00000000
|
||||
#define RV_EXTERNAL_DATA 0xc0580000
|
||||
#define RV_DEBUG_SB_MEM 0xb0580000
|
||||
#define RV_SERIALIO 0xd0580000
|
||||
#define RV_UNUSED_REGION5 0x50000000
|
||||
#define RV_EXTERNAL_MEM_HOLE 0x90000000
|
||||
#define RV_UNUSED_REGION6 0x60000000
|
||||
#define RV_UNUSED_REGION2 0x20000000
|
||||
#define RV_DATA_ACCESS_ENABLE5 0x0
|
||||
#define RV_INST_ACCESS_ENABLE6 0x0
|
||||
#define RV_INST_ACCESS_ENABLE0 1
|
||||
#define RV_DATA_ACCESS_ENABLE0 1
|
||||
#define RV_INST_ACCESS_ENABLE5 0x0
|
||||
#define RV_DATA_ACCESS_ENABLE6 0x0
|
||||
#define RV_INST_ACCESS_MASK0 0x7fffffff
|
||||
#define RV_INST_ACCESS_MASK4 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR0 0x0
|
||||
#define RV_INST_ACCESS_ENABLE2 1
|
||||
#define RV_DATA_ACCESS_ENABLE4 0x0
|
||||
#define RV_DATA_ACCESS_ADDR4 0x00000000
|
||||
#define RV_DATA_ACCESS_ENABLE2 1
|
||||
#define RV_INST_ACCESS_ADDR0 0x0
|
||||
#define RV_INST_ACCESS_ENABLE4 0x0
|
||||
#define RV_INST_ACCESS_ADDR4 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK0 0x7fffffff
|
||||
#define RV_DATA_ACCESS_MASK4 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR1 0xc0000000
|
||||
#define RV_INST_ACCESS_ENABLE7 0x0
|
||||
#define RV_INST_ACCESS_MASK1 0x3fffffff
|
||||
#define RV_INST_ACCESS_ENABLE1 1
|
||||
#define RV_DATA_ACCESS_ENABLE3 1
|
||||
#define RV_DATA_ACCESS_ENABLE7 0x0
|
||||
#define RV_DATA_ACCESS_MASK1 0x3fffffff
|
||||
#define RV_DATA_ACCESS_ENABLE1 1
|
||||
#define RV_INST_ACCESS_ENABLE3 1
|
||||
#define RV_INST_ACCESS_ADDR1 0xc0000000
|
||||
#define RV_DATA_ACCESS_MASK5 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR3 0x80000000
|
||||
#define RV_INST_ACCESS_ADDR6 0x00000000
|
||||
#define RV_DATA_ACCESS_ADDR2 0xa0000000
|
||||
#define RV_DATA_ACCESS_ADDR7 0x00000000
|
||||
#define RV_INST_ACCESS_MASK3 0x0fffffff
|
||||
#define RV_INST_ACCESS_ADDR5 0x00000000
|
||||
#define RV_INST_ACCESS_MASK7 0xffffffff
|
||||
#define RV_INST_ACCESS_MASK2 0x1fffffff
|
||||
#define RV_DATA_ACCESS_MASK6 0xffffffff
|
||||
#define RV_DATA_ACCESS_MASK3 0x0fffffff
|
||||
#define RV_DATA_ACCESS_ADDR5 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK7 0xffffffff
|
||||
#define RV_DATA_ACCESS_MASK2 0x1fffffff
|
||||
#define RV_INST_ACCESS_MASK6 0xffffffff
|
||||
#define RV_INST_ACCESS_MASK5 0xffffffff
|
||||
#define RV_INST_ACCESS_ADDR3 0x80000000
|
||||
#define RV_DATA_ACCESS_ADDR6 0x00000000
|
||||
#define RV_INST_ACCESS_ADDR2 0xa0000000
|
||||
#define RV_INST_ACCESS_ADDR7 0x00000000
|
||||
#define RV_ICCM_NUM_BANKS_4
|
||||
#define RV_ICCM_SADR 0xee000000
|
||||
#define RV_ICCM_OFFSET 0xe000000
|
||||
#define RV_ICCM_REGION 0xe
|
||||
#define RV_ICCM_INDEX_BITS 12
|
||||
#define RV_ICCM_ENABLE 1
|
||||
#define RV_ICCM_SIZE 64
|
||||
#define RV_ICCM_BANK_HI 3
|
||||
#define RV_ICCM_RESERVED 0x1000
|
||||
#define RV_ICCM_ROWS 4096
|
||||
#define RV_ICCM_BANK_INDEX_LO 4
|
||||
#define RV_ICCM_BANK_BITS 2
|
||||
#define RV_ICCM_DATA_CELL ram_4096x39
|
||||
#define RV_ICCM_BITS 16
|
||||
#define RV_ICCM_SIZE_64
|
||||
#define RV_ICCM_NUM_BANKS 4
|
||||
#define RV_ICCM_EADR 0xee00ffff
|
||||
#ifndef RV_RESET_VEC
|
||||
#define RV_RESET_VEC 0x80000000
|
||||
#endif
|
||||
#define RV_BUS_PRTY_DEFAULT 3
|
||||
#define RV_IFU_BUS_PRTY 2
|
||||
#define RV_IFU_BUS_ID 1
|
||||
#define RV_DMA_BUS_TAG 1
|
||||
#define RV_LSU_BUS_TAG 3
|
||||
#define RV_SB_BUS_TAG 1
|
||||
#define RV_IFU_BUS_TAG 3
|
||||
#define RV_LSU_BUS_ID 1
|
||||
#define RV_DMA_BUS_PRTY 2
|
||||
#define RV_LSU_BUS_PRTY 2
|
||||
#define RV_DMA_BUS_ID 1
|
||||
#define RV_SB_BUS_PRTY 2
|
||||
#define RV_SB_BUS_ID 1
|
||||
#define RV_EXT_DATAWIDTH 64
|
||||
#define CPU_TOP `RV_TOP.quasar
|
||||
#define RV_LDERR_ROLLBACK 1
|
||||
#define RV_TOP `TOP.rvtop
|
||||
#define RV_EXT_ADDRWIDTH 32
|
||||
#define CLOCK_PERIOD 100
|
||||
#define RV_BUILD_AXI4 1
|
||||
#define SDVT_AHB 1
|
||||
#define RV_STERR_ROLLBACK 0
|
||||
#define ASSERT_ON
|
||||
#define TOP tb_top
|
||||
#define RV_BUILD_AXI_NATIVE 1
|
||||
#define RV_DCCM_WIDTH_BITS 2
|
||||
#define RV_DCCM_INDEX_BITS 12
|
||||
#define RV_DCCM_SADR 0xf0040000
|
||||
#define RV_DCCM_NUM_BANKS_4
|
||||
#define RV_DCCM_OFFSET 0x40000
|
||||
#define RV_DCCM_FDATA_WIDTH 39
|
||||
#define RV_DCCM_REGION 0xf
|
||||
#define RV_DCCM_RESERVED 0x1400
|
||||
#define RV_DCCM_SIZE 64
|
||||
#define RV_DCCM_ENABLE 1
|
||||
#define RV_DCCM_DATA_WIDTH 32
|
||||
#define RV_DCCM_BITS 16
|
||||
#define RV_DCCM_ROWS 4096
|
||||
#define RV_DCCM_BYTE_WIDTH 4
|
||||
#define RV_DCCM_BANK_BITS 2
|
||||
#define RV_DCCM_DATA_CELL ram_4096x39
|
||||
#define RV_DCCM_ECC_WIDTH 7
|
||||
#define RV_DCCM_EADR 0xf004ffff
|
||||
#define RV_DCCM_SIZE_64
|
||||
#define RV_DCCM_NUM_BANKS 4
|
||||
#define RV_LSU_SB_BITS 16
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
parameter param_t pt = '{
|
||||
BHT_ADDR_HI : 4'h9 ,
|
||||
BHT_ADDR_LO : 2'h2 ,
|
||||
BHT_ARRAY_DEPTH : 11'h100 ,
|
||||
BHT_GHR_HASH_1 : 1'h0 ,
|
||||
BHT_GHR_SIZE : 4'h8 ,
|
||||
BHT_SIZE : 12'h200 ,
|
||||
BTB_ADDR_HI : 5'h09 ,
|
||||
BTB_ADDR_LO : 2'h2 ,
|
||||
BTB_ARRAY_DEPTH : 9'h100 ,
|
||||
BTB_BTAG_FOLD : 1'h0 ,
|
||||
BTB_BTAG_SIZE : 4'h5 ,
|
||||
BTB_FOLD2_INDEX_HASH : 1'h0 ,
|
||||
BTB_INDEX1_HI : 5'h09 ,
|
||||
BTB_INDEX1_LO : 5'h02 ,
|
||||
BTB_INDEX2_HI : 5'h11 ,
|
||||
BTB_INDEX2_LO : 5'h0A ,
|
||||
BTB_INDEX3_HI : 5'h19 ,
|
||||
BTB_INDEX3_LO : 5'h12 ,
|
||||
BTB_SIZE : 10'h200 ,
|
||||
BUILD_AHB_LITE : 1'h0 ,
|
||||
BUILD_AXI4 : 1'h1 ,
|
||||
BUILD_AXI_NATIVE : 1'h1 ,
|
||||
BUS_PRTY_DEFAULT : 2'h3 ,
|
||||
DATA_ACCESS_ADDR0 : 32'h00000000 ,
|
||||
DATA_ACCESS_ADDR1 : 32'hC0000000 ,
|
||||
DATA_ACCESS_ADDR2 : 32'hA0000000 ,
|
||||
DATA_ACCESS_ADDR3 : 32'h80000000 ,
|
||||
DATA_ACCESS_ADDR4 : 32'h00000000 ,
|
||||
DATA_ACCESS_ADDR5 : 32'h00000000 ,
|
||||
DATA_ACCESS_ADDR6 : 32'h00000000 ,
|
||||
DATA_ACCESS_ADDR7 : 32'h00000000 ,
|
||||
DATA_ACCESS_ENABLE0 : 1'h1 ,
|
||||
DATA_ACCESS_ENABLE1 : 1'h1 ,
|
||||
DATA_ACCESS_ENABLE2 : 1'h1 ,
|
||||
DATA_ACCESS_ENABLE3 : 1'h1 ,
|
||||
DATA_ACCESS_ENABLE4 : 1'h0 ,
|
||||
DATA_ACCESS_ENABLE5 : 1'h0 ,
|
||||
DATA_ACCESS_ENABLE6 : 1'h0 ,
|
||||
DATA_ACCESS_ENABLE7 : 1'h0 ,
|
||||
DATA_ACCESS_MASK0 : 32'h7FFFFFFF ,
|
||||
DATA_ACCESS_MASK1 : 32'h3FFFFFFF ,
|
||||
DATA_ACCESS_MASK2 : 32'h1FFFFFFF ,
|
||||
DATA_ACCESS_MASK3 : 32'h0FFFFFFF ,
|
||||
DATA_ACCESS_MASK4 : 32'hFFFFFFFF ,
|
||||
DATA_ACCESS_MASK5 : 32'hFFFFFFFF ,
|
||||
DATA_ACCESS_MASK6 : 32'hFFFFFFFF ,
|
||||
DATA_ACCESS_MASK7 : 32'hFFFFFFFF ,
|
||||
DCCM_BANK_BITS : 3'h2 ,
|
||||
DCCM_BITS : 5'h10 ,
|
||||
DCCM_BYTE_WIDTH : 3'h4 ,
|
||||
DCCM_DATA_WIDTH : 6'h20 ,
|
||||
DCCM_ECC_WIDTH : 3'h7 ,
|
||||
DCCM_ENABLE : 1'h1 ,
|
||||
DCCM_FDATA_WIDTH : 6'h27 ,
|
||||
DCCM_INDEX_BITS : 4'hC ,
|
||||
DCCM_NUM_BANKS : 5'h04 ,
|
||||
DCCM_REGION : 4'hF ,
|
||||
DCCM_SADR : 32'hF0040000 ,
|
||||
DCCM_SIZE : 10'h040 ,
|
||||
DCCM_WIDTH_BITS : 2'h2 ,
|
||||
DMA_BUF_DEPTH : 3'h5 ,
|
||||
DMA_BUS_ID : 1'h1 ,
|
||||
DMA_BUS_PRTY : 2'h2 ,
|
||||
DMA_BUS_TAG : 4'h1 ,
|
||||
FAST_INTERRUPT_REDIRECT : 1'h1 ,
|
||||
ICACHE_2BANKS : 1'h1 ,
|
||||
ICACHE_BANK_BITS : 3'h1 ,
|
||||
ICACHE_BANK_HI : 3'h3 ,
|
||||
ICACHE_BANK_LO : 2'h3 ,
|
||||
ICACHE_BANK_WIDTH : 4'h8 ,
|
||||
ICACHE_BANKS_WAY : 3'h2 ,
|
||||
ICACHE_BEAT_ADDR_HI : 4'h5 ,
|
||||
ICACHE_BEAT_BITS : 4'h3 ,
|
||||
ICACHE_DATA_DEPTH : 14'h0200 ,
|
||||
ICACHE_DATA_INDEX_LO : 3'h4 ,
|
||||
ICACHE_DATA_WIDTH : 7'h40 ,
|
||||
ICACHE_ECC : 1'h1 ,
|
||||
ICACHE_ENABLE : 1'h1 ,
|
||||
ICACHE_FDATA_WIDTH : 7'h47 ,
|
||||
ICACHE_INDEX_HI : 5'h0C ,
|
||||
ICACHE_LN_SZ : 7'h40 ,
|
||||
ICACHE_NUM_BEATS : 4'h8 ,
|
||||
ICACHE_NUM_WAYS : 3'h2 ,
|
||||
ICACHE_ONLY : 1'h0 ,
|
||||
ICACHE_SCND_LAST : 4'h6 ,
|
||||
ICACHE_SIZE : 9'h010 ,
|
||||
ICACHE_STATUS_BITS : 3'h1 ,
|
||||
ICACHE_TAG_DEPTH : 13'h0080 ,
|
||||
ICACHE_TAG_INDEX_LO : 3'h6 ,
|
||||
ICACHE_TAG_LO : 5'h0D ,
|
||||
ICACHE_WAYPACK : 1'h0 ,
|
||||
ICCM_BANK_BITS : 3'h2 ,
|
||||
ICCM_BANK_HI : 5'h03 ,
|
||||
ICCM_BANK_INDEX_LO : 5'h04 ,
|
||||
ICCM_BITS : 5'h10 ,
|
||||
ICCM_ENABLE : 1'h1 ,
|
||||
ICCM_ICACHE : 1'h1 ,
|
||||
ICCM_INDEX_BITS : 4'hC ,
|
||||
ICCM_NUM_BANKS : 5'h04 ,
|
||||
ICCM_ONLY : 1'h0 ,
|
||||
ICCM_REGION : 4'hE ,
|
||||
ICCM_SADR : 32'hEE000000 ,
|
||||
ICCM_SIZE : 10'h040 ,
|
||||
IFU_BUS_ID : 1'h1 ,
|
||||
IFU_BUS_PRTY : 2'h2 ,
|
||||
IFU_BUS_TAG : 4'h3 ,
|
||||
INST_ACCESS_ADDR0 : 32'h00000000 ,
|
||||
INST_ACCESS_ADDR1 : 32'hC0000000 ,
|
||||
INST_ACCESS_ADDR2 : 32'hA0000000 ,
|
||||
INST_ACCESS_ADDR3 : 32'h80000000 ,
|
||||
INST_ACCESS_ADDR4 : 32'h00000000 ,
|
||||
INST_ACCESS_ADDR5 : 32'h00000000 ,
|
||||
INST_ACCESS_ADDR6 : 32'h00000000 ,
|
||||
INST_ACCESS_ADDR7 : 32'h00000000 ,
|
||||
INST_ACCESS_ENABLE0 : 1'h1 ,
|
||||
INST_ACCESS_ENABLE1 : 1'h1 ,
|
||||
INST_ACCESS_ENABLE2 : 1'h1 ,
|
||||
INST_ACCESS_ENABLE3 : 1'h1 ,
|
||||
INST_ACCESS_ENABLE4 : 1'h0 ,
|
||||
INST_ACCESS_ENABLE5 : 1'h0 ,
|
||||
INST_ACCESS_ENABLE6 : 1'h0 ,
|
||||
INST_ACCESS_ENABLE7 : 1'h0 ,
|
||||
INST_ACCESS_MASK0 : 32'h7FFFFFFF ,
|
||||
INST_ACCESS_MASK1 : 32'h3FFFFFFF ,
|
||||
INST_ACCESS_MASK2 : 32'h1FFFFFFF ,
|
||||
INST_ACCESS_MASK3 : 32'h0FFFFFFF ,
|
||||
INST_ACCESS_MASK4 : 32'hFFFFFFFF ,
|
||||
INST_ACCESS_MASK5 : 32'hFFFFFFFF ,
|
||||
INST_ACCESS_MASK6 : 32'hFFFFFFFF ,
|
||||
INST_ACCESS_MASK7 : 32'hFFFFFFFF ,
|
||||
LOAD_TO_USE_PLUS1 : 1'h0 ,
|
||||
LSU2DMA : 1'h0 ,
|
||||
LSU_BUS_ID : 1'h1 ,
|
||||
LSU_BUS_PRTY : 2'h2 ,
|
||||
LSU_BUS_TAG : 4'h3 ,
|
||||
LSU_NUM_NBLOAD : 5'h04 ,
|
||||
LSU_NUM_NBLOAD_WIDTH : 3'h2 ,
|
||||
LSU_SB_BITS : 5'h10 ,
|
||||
LSU_STBUF_DEPTH : 4'h4 ,
|
||||
NO_ICCM_NO_ICACHE : 1'h0 ,
|
||||
PIC_2CYCLE : 1'h0 ,
|
||||
PIC_BASE_ADDR : 32'hF00C0000 ,
|
||||
PIC_BITS : 5'h0F ,
|
||||
PIC_INT_WORDS : 4'h1 ,
|
||||
PIC_REGION : 4'hF ,
|
||||
PIC_SIZE : 9'h020 ,
|
||||
PIC_TOTAL_INT : 8'h1F ,
|
||||
PIC_TOTAL_INT_PLUS1 : 9'h020 ,
|
||||
RET_STACK_SIZE : 4'h8 ,
|
||||
SB_BUS_ID : 1'h1 ,
|
||||
SB_BUS_PRTY : 2'h2 ,
|
||||
SB_BUS_TAG : 4'h1 ,
|
||||
TIMER_LEGAL_EN : 1'h1
|
||||
}
|
||||
// parameter param_t pt = 1545'h1310041002680149145599400F00000000C0000000A00000008000000000000000000000000000000000000000F07FFFFFFF3FFFFFFF1FFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF50907CF84FF0040000102B872F84A6100481C76408460810406690C90F08EEE00000010318000000060000000500000004000000000000000000000000000000000000000783FFFFFFF9FFFFFFF8FFFFFFF87FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF98C8A08780600003C7C403E208C3
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
// This is an automatically generated file by waleedbinehsan on و 15:35:44 PKT ت 07 جنوری 2021
|
||||
//
|
||||
// cmd: quasar -target=default
|
||||
//
|
||||
|
||||
`include "common_defines.vh"
|
||||
`undef ASSERT_ON
|
||||
`undef TEC_RV_ICG
|
||||
`define TEC_RV_ICG HDBLVT16_CKGTPLT_V5_12
|
||||
`define PHYSICAL 1
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
typedef struct packed {
|
||||
bit [3:0] BHT_ADDR_HI;
|
||||
bit [1:0] BHT_ADDR_LO;
|
||||
bit [10:0] BHT_ARRAY_DEPTH;
|
||||
bit BHT_GHR_HASH_1;
|
||||
bit [3:0] BHT_GHR_SIZE;
|
||||
bit [11:0] BHT_SIZE;
|
||||
bit [4:0] BTB_ADDR_HI;
|
||||
bit [1:0] BTB_ADDR_LO;
|
||||
bit [8:0] BTB_ARRAY_DEPTH;
|
||||
bit BTB_BTAG_FOLD;
|
||||
bit [3:0] BTB_BTAG_SIZE;
|
||||
bit BTB_FOLD2_INDEX_HASH;
|
||||
bit [4:0] BTB_INDEX1_HI;
|
||||
bit [4:0] BTB_INDEX1_LO;
|
||||
bit [4:0] BTB_INDEX2_HI;
|
||||
bit [4:0] BTB_INDEX2_LO;
|
||||
bit [4:0] BTB_INDEX3_HI;
|
||||
bit [4:0] BTB_INDEX3_LO;
|
||||
bit [9:0] BTB_SIZE;
|
||||
bit BUILD_AHB_LITE;
|
||||
bit BUILD_AXI4;
|
||||
bit BUILD_AXI_NATIVE;
|
||||
bit [1:0] BUS_PRTY_DEFAULT;
|
||||
bit [31:0] DATA_ACCESS_ADDR0;
|
||||
bit [31:0] DATA_ACCESS_ADDR1;
|
||||
bit [31:0] DATA_ACCESS_ADDR2;
|
||||
bit [31:0] DATA_ACCESS_ADDR3;
|
||||
bit [31:0] DATA_ACCESS_ADDR4;
|
||||
bit [31:0] DATA_ACCESS_ADDR5;
|
||||
bit [31:0] DATA_ACCESS_ADDR6;
|
||||
bit [31:0] DATA_ACCESS_ADDR7;
|
||||
bit DATA_ACCESS_ENABLE0;
|
||||
bit DATA_ACCESS_ENABLE1;
|
||||
bit DATA_ACCESS_ENABLE2;
|
||||
bit DATA_ACCESS_ENABLE3;
|
||||
bit DATA_ACCESS_ENABLE4;
|
||||
bit DATA_ACCESS_ENABLE5;
|
||||
bit DATA_ACCESS_ENABLE6;
|
||||
bit DATA_ACCESS_ENABLE7;
|
||||
bit [31:0] DATA_ACCESS_MASK0;
|
||||
bit [31:0] DATA_ACCESS_MASK1;
|
||||
bit [31:0] DATA_ACCESS_MASK2;
|
||||
bit [31:0] DATA_ACCESS_MASK3;
|
||||
bit [31:0] DATA_ACCESS_MASK4;
|
||||
bit [31:0] DATA_ACCESS_MASK5;
|
||||
bit [31:0] DATA_ACCESS_MASK6;
|
||||
bit [31:0] DATA_ACCESS_MASK7;
|
||||
bit [2:0] DCCM_BANK_BITS;
|
||||
bit [4:0] DCCM_BITS;
|
||||
bit [2:0] DCCM_BYTE_WIDTH;
|
||||
bit [5:0] DCCM_DATA_WIDTH;
|
||||
bit [2:0] DCCM_ECC_WIDTH;
|
||||
bit DCCM_ENABLE;
|
||||
bit [5:0] DCCM_FDATA_WIDTH;
|
||||
bit [3:0] DCCM_INDEX_BITS;
|
||||
bit [4:0] DCCM_NUM_BANKS;
|
||||
bit [3:0] DCCM_REGION;
|
||||
bit [31:0] DCCM_SADR;
|
||||
bit [9:0] DCCM_SIZE;
|
||||
bit [1:0] DCCM_WIDTH_BITS;
|
||||
bit [2:0] DMA_BUF_DEPTH;
|
||||
bit DMA_BUS_ID;
|
||||
bit [1:0] DMA_BUS_PRTY;
|
||||
bit [3:0] DMA_BUS_TAG;
|
||||
bit FAST_INTERRUPT_REDIRECT;
|
||||
bit ICACHE_2BANKS;
|
||||
bit [2:0] ICACHE_BANK_BITS;
|
||||
bit [2:0] ICACHE_BANK_HI;
|
||||
bit [1:0] ICACHE_BANK_LO;
|
||||
bit [3:0] ICACHE_BANK_WIDTH;
|
||||
bit [2:0] ICACHE_BANKS_WAY;
|
||||
bit [3:0] ICACHE_BEAT_ADDR_HI;
|
||||
bit [3:0] ICACHE_BEAT_BITS;
|
||||
bit [13:0] ICACHE_DATA_DEPTH;
|
||||
bit [2:0] ICACHE_DATA_INDEX_LO;
|
||||
bit [6:0] ICACHE_DATA_WIDTH;
|
||||
bit ICACHE_ECC;
|
||||
bit ICACHE_ENABLE;
|
||||
bit [6:0] ICACHE_FDATA_WIDTH;
|
||||
bit [4:0] ICACHE_INDEX_HI;
|
||||
bit [6:0] ICACHE_LN_SZ;
|
||||
bit [3:0] ICACHE_NUM_BEATS;
|
||||
bit [2:0] ICACHE_NUM_WAYS;
|
||||
bit ICACHE_ONLY;
|
||||
bit [3:0] ICACHE_SCND_LAST;
|
||||
bit [8:0] ICACHE_SIZE;
|
||||
bit [2:0] ICACHE_STATUS_BITS;
|
||||
bit [12:0] ICACHE_TAG_DEPTH;
|
||||
bit [2:0] ICACHE_TAG_INDEX_LO;
|
||||
bit [4:0] ICACHE_TAG_LO;
|
||||
bit ICACHE_WAYPACK;
|
||||
bit [2:0] ICCM_BANK_BITS;
|
||||
bit [4:0] ICCM_BANK_HI;
|
||||
bit [4:0] ICCM_BANK_INDEX_LO;
|
||||
bit [4:0] ICCM_BITS;
|
||||
bit ICCM_ENABLE;
|
||||
bit ICCM_ICACHE;
|
||||
bit [3:0] ICCM_INDEX_BITS;
|
||||
bit [4:0] ICCM_NUM_BANKS;
|
||||
bit ICCM_ONLY;
|
||||
bit [3:0] ICCM_REGION;
|
||||
bit [31:0] ICCM_SADR;
|
||||
bit [9:0] ICCM_SIZE;
|
||||
bit IFU_BUS_ID;
|
||||
bit [1:0] IFU_BUS_PRTY;
|
||||
bit [3:0] IFU_BUS_TAG;
|
||||
bit [31:0] INST_ACCESS_ADDR0;
|
||||
bit [31:0] INST_ACCESS_ADDR1;
|
||||
bit [31:0] INST_ACCESS_ADDR2;
|
||||
bit [31:0] INST_ACCESS_ADDR3;
|
||||
bit [31:0] INST_ACCESS_ADDR4;
|
||||
bit [31:0] INST_ACCESS_ADDR5;
|
||||
bit [31:0] INST_ACCESS_ADDR6;
|
||||
bit [31:0] INST_ACCESS_ADDR7;
|
||||
bit INST_ACCESS_ENABLE0;
|
||||
bit INST_ACCESS_ENABLE1;
|
||||
bit INST_ACCESS_ENABLE2;
|
||||
bit INST_ACCESS_ENABLE3;
|
||||
bit INST_ACCESS_ENABLE4;
|
||||
bit INST_ACCESS_ENABLE5;
|
||||
bit INST_ACCESS_ENABLE6;
|
||||
bit INST_ACCESS_ENABLE7;
|
||||
bit [31:0] INST_ACCESS_MASK0;
|
||||
bit [31:0] INST_ACCESS_MASK1;
|
||||
bit [31:0] INST_ACCESS_MASK2;
|
||||
bit [31:0] INST_ACCESS_MASK3;
|
||||
bit [31:0] INST_ACCESS_MASK4;
|
||||
bit [31:0] INST_ACCESS_MASK5;
|
||||
bit [31:0] INST_ACCESS_MASK6;
|
||||
bit [31:0] INST_ACCESS_MASK7;
|
||||
bit LOAD_TO_USE_PLUS1;
|
||||
bit LSU2DMA;
|
||||
bit LSU_BUS_ID;
|
||||
bit [1:0] LSU_BUS_PRTY;
|
||||
bit [3:0] LSU_BUS_TAG;
|
||||
bit [4:0] LSU_NUM_NBLOAD;
|
||||
bit [2:0] LSU_NUM_NBLOAD_WIDTH;
|
||||
bit [4:0] LSU_SB_BITS;
|
||||
bit [3:0] LSU_STBUF_DEPTH;
|
||||
bit NO_ICCM_NO_ICACHE;
|
||||
bit PIC_2CYCLE;
|
||||
bit [31:0] PIC_BASE_ADDR;
|
||||
bit [4:0] PIC_BITS;
|
||||
bit [3:0] PIC_INT_WORDS;
|
||||
bit [3:0] PIC_REGION;
|
||||
bit [8:0] PIC_SIZE;
|
||||
bit [7:0] PIC_TOTAL_INT;
|
||||
bit [8:0] PIC_TOTAL_INT_PLUS1;
|
||||
bit [3:0] RET_STACK_SIZE;
|
||||
bit SB_BUS_ID;
|
||||
bit [1:0] SB_BUS_PRTY;
|
||||
bit [3:0] SB_BUS_TAG;
|
||||
bit TIMER_LEGAL_EN;
|
||||
} param_t;
|
||||
|
||||
|
|
@ -1,683 +0,0 @@
|
|||
# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
# This is an automatically generated file by waleedbinehsan on و 15:35:44 PKT ت 07 جنوری 2021
|
||||
#
|
||||
# cmd: quasar -target=default
|
||||
#
|
||||
# To use this in a perf script, use 'require $RV_ROOT/configs/config.pl'
|
||||
# Reference the hash via $config{name}..
|
||||
|
||||
|
||||
%config = (
|
||||
'max_mmode_perf_event' => '516',
|
||||
'core' => {
|
||||
'timer_legal_en' => '1',
|
||||
'lsu_num_nbload' => '4',
|
||||
'dma_buf_depth' => '5',
|
||||
'iccm_only' => 'derived',
|
||||
'no_iccm_no_icache' => 'derived',
|
||||
'lsu2dma' => 0,
|
||||
'icache_only' => 'derived',
|
||||
'lsu_num_nbload_width' => '2',
|
||||
'fast_interrupt_redirect' => '1',
|
||||
'iccm_icache' => 1,
|
||||
'fpga_optimize' => '0',
|
||||
'lsu_stbuf_depth' => '4'
|
||||
},
|
||||
'icache' => {
|
||||
'icache_tag_lo' => 13,
|
||||
'icache_fdata_width' => 71,
|
||||
'icache_data_index_lo' => 4,
|
||||
'icache_tag_index_lo' => '6',
|
||||
'icache_size' => 16,
|
||||
'icache_num_lines' => 256,
|
||||
'icache_bank_width' => 8,
|
||||
'icache_num_lines_way' => '128',
|
||||
'icache_tag_cell' => 'ram_128x25',
|
||||
'icache_index_hi' => 12,
|
||||
'icache_num_lines_bank' => '64',
|
||||
'icache_beat_addr_hi' => 5,
|
||||
'icache_ecc' => '1',
|
||||
'icache_ln_sz' => 64,
|
||||
'icache_bank_hi' => 3,
|
||||
'icache_beat_bits' => 3,
|
||||
'icache_2banks' => '1',
|
||||
'icache_bank_lo' => 3,
|
||||
'icache_bank_bits' => 1,
|
||||
'icache_scnd_last' => 6,
|
||||
'icache_tag_depth' => 128,
|
||||
'icache_data_cell' => 'ram_512x71',
|
||||
'icache_num_beats' => 8,
|
||||
'icache_banks_way' => 2,
|
||||
'icache_data_depth' => '512',
|
||||
'icache_enable' => 1,
|
||||
'icache_status_bits' => 1,
|
||||
'icache_num_ways' => 2,
|
||||
'icache_data_width' => 64
|
||||
},
|
||||
'xlen' => 32,
|
||||
'retstack' => {
|
||||
'ret_stack_size' => '8'
|
||||
},
|
||||
'triggers' => [
|
||||
{
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
]
|
||||
}
|
||||
],
|
||||
'config_key' => '32\'hdeadbeef',
|
||||
'numiregs' => '32',
|
||||
'physical' => '1',
|
||||
'target' => 'default',
|
||||
'num_mmode_perf_regs' => '4',
|
||||
'regwidth' => '32',
|
||||
'btb' => {
|
||||
'btb_index2_hi' => 17,
|
||||
'btb_btag_fold' => 0,
|
||||
'btb_array_depth' => 256,
|
||||
'btb_index2_lo' => 10,
|
||||
'btb_fold2_index_hash' => 0,
|
||||
'btb_addr_hi' => 9,
|
||||
'btb_addr_lo' => '2',
|
||||
'btb_index1_lo' => '2',
|
||||
'btb_index3_lo' => 18,
|
||||
'btb_size' => 512,
|
||||
'btb_index3_hi' => 25,
|
||||
'btb_btag_size' => 5,
|
||||
'btb_index1_hi' => 9
|
||||
},
|
||||
'csr' => {
|
||||
'instret' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'tselect' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0x3'
|
||||
},
|
||||
'pmpcfg1' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr13' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'misa' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x40001104',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'pmpaddr15' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicad1' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7ca',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'mask' => '0x3',
|
||||
'debug' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mcgc' => {
|
||||
'poke_mask' => '0x000001ff',
|
||||
'mask' => '0x000001ff',
|
||||
'number' => '0x7f8',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpaddr4' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter6' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr8' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'time' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicago' => {
|
||||
'exists' => 'true',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'number' => '0x7cb',
|
||||
'debug' => 'true',
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mhpmcounter3h' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mhpmevent6' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mimpid' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x2',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'mitctl0' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d4',
|
||||
'reset' => '0x1',
|
||||
'mask' => '0x00000007'
|
||||
},
|
||||
'mitcnt1' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7d5',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr9' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr1' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter5' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mitcnt0' => {
|
||||
'mask' => '0xffffffff',
|
||||
'number' => '0x7d2',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mvendorid' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x45',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'mitctl1' => {
|
||||
'mask' => '0x0000000f',
|
||||
'number' => '0x7d7',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x1'
|
||||
},
|
||||
'dcsr' => {
|
||||
'debug' => 'true',
|
||||
'mask' => '0x00008c04',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x40000003',
|
||||
'poke_mask' => '0x00008dcc'
|
||||
},
|
||||
'pmpaddr0' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicad0' => {
|
||||
'reset' => '0x0',
|
||||
'debug' => 'true',
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c9',
|
||||
'comment' => 'Cache diagnostics.'
|
||||
},
|
||||
'mhpmcounter6h' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpaddr11' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr5' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr7' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mdccmect' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7f2',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mhpmcounter5h' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mpmc' => {
|
||||
'number' => '0x7c6',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x2',
|
||||
'mask' => '0x2'
|
||||
},
|
||||
'miccmect' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7f1',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mhpmcounter3' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpcfg0' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mstatus' => {
|
||||
'mask' => '0x88',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x1800'
|
||||
},
|
||||
'micect' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7f0'
|
||||
},
|
||||
'mhpmevent4' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr6' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr2' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter4h' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mhpmevent3' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpcfg2' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'meicidpl' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'External interrupt claim id priority level.',
|
||||
'number' => '0xbcb',
|
||||
'mask' => '0xf'
|
||||
},
|
||||
'mitbnd0' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d3'
|
||||
},
|
||||
'mhpmevent5' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'dicawics' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c8',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'debug' => 'true',
|
||||
'mask' => '0x0130fffc',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpaddr3' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mcpc' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7c2',
|
||||
'comment' => 'Core pause',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'pmpcfg3' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'marchid' => {
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x00000010',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mcountinhibit' => {
|
||||
'poke_mask' => '0x7d',
|
||||
'mask' => '0x7d',
|
||||
'exists' => 'true',
|
||||
'commnet' => 'Performance counter inhibit. One bit per counter.',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mie' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x70000888'
|
||||
},
|
||||
'cycle' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mfdc' => {
|
||||
'number' => '0x7f9',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x00070040',
|
||||
'mask' => '0x00070fff'
|
||||
},
|
||||
'mhpmcounter4' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr12' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mscause' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7ff',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0x0000000f'
|
||||
},
|
||||
'pmpaddr14' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'meipt' => {
|
||||
'mask' => '0xf',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'number' => '0xbc9',
|
||||
'comment' => 'External interrupt priority threshold.'
|
||||
},
|
||||
'mrac' => {
|
||||
'mask' => '0xffffffff',
|
||||
'shared' => 'true',
|
||||
'exists' => 'true',
|
||||
'comment' => 'Memory region io and cache control.',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7c0'
|
||||
},
|
||||
'dmst' => {
|
||||
'exists' => 'true',
|
||||
'comment' => 'Memory synch trigger: Flush caches in debug mode.',
|
||||
'number' => '0x7c4',
|
||||
'mask' => '0x0',
|
||||
'debug' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'meicurpl' => {
|
||||
'mask' => '0xf',
|
||||
'comment' => 'External interrupt current priority level.',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0xbcc'
|
||||
},
|
||||
'pmpaddr10' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mip' => {
|
||||
'poke_mask' => '0x70000888',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'mhartid' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0',
|
||||
'poke_mask' => '0xfffffff0'
|
||||
},
|
||||
'mitbnd1' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d6'
|
||||
}
|
||||
},
|
||||
'nmi_vec' => '0x11110000',
|
||||
'pic' => {
|
||||
'pic_meigwclr_mask' => '0x0',
|
||||
'pic_meie_count' => 31,
|
||||
'pic_int_words' => 1,
|
||||
'pic_meipt_mask' => '0x0',
|
||||
'pic_meip_offset' => '0x1000',
|
||||
'pic_meipl_count' => 31,
|
||||
'pic_meigwctrl_count' => 31,
|
||||
'pic_size' => 32,
|
||||
'pic_mpiccfg_count' => 1,
|
||||
'pic_meipt_offset' => '0x3004',
|
||||
'pic_meigwclr_count' => 31,
|
||||
'pic_meie_offset' => '0x2000',
|
||||
'pic_meip_count' => 4,
|
||||
'pic_total_int' => 31,
|
||||
'pic_meigwctrl_mask' => '0x3',
|
||||
'pic_bits' => 15,
|
||||
'pic_region' => '0xf',
|
||||
'pic_meigwctrl_offset' => '0x4000',
|
||||
'pic_offset' => '0xc0000',
|
||||
'pic_mpiccfg_mask' => '0x1',
|
||||
'pic_meipl_offset' => '0x0000',
|
||||
'pic_meipl_mask' => '0xf',
|
||||
'pic_meipt_count' => 31,
|
||||
'pic_meigwclr_offset' => '0x5000',
|
||||
'pic_meie_mask' => '0x1',
|
||||
'pic_mpiccfg_offset' => '0x3000',
|
||||
'pic_total_int_plus1' => 32,
|
||||
'pic_base_addr' => '0xf00c0000',
|
||||
'pic_meip_mask' => '0x0'
|
||||
},
|
||||
'memmap' => {
|
||||
'external_prog' => '0xb0000000',
|
||||
'unused_region1' => '0x10000000',
|
||||
'unused_region3' => '0x30000000',
|
||||
'unused_region7' => '0x70000000',
|
||||
'unused_region4' => '0x40000000',
|
||||
'external_data_1' => '0x00000000',
|
||||
'unused_region0' => '0x00000000',
|
||||
'external_data' => '0xc0580000',
|
||||
'debug_sb_mem' => '0xb0580000',
|
||||
'serialio' => '0xd0580000',
|
||||
'unused_region5' => '0x50000000',
|
||||
'external_mem_hole' => '0x90000000',
|
||||
'unused_region6' => '0x60000000',
|
||||
'unused_region2' => '0x20000000'
|
||||
},
|
||||
'bht' => {
|
||||
'bht_ghr_hash_1' => '',
|
||||
'bht_array_depth' => 256,
|
||||
'bht_size' => 512,
|
||||
'bht_addr_hi' => 9,
|
||||
'bht_addr_lo' => '2',
|
||||
'bht_hash_string' => '{hashin[8+1:2]^ghr[8-1:0]}// cf2',
|
||||
'bht_ghr_range' => '7:0',
|
||||
'bht_ghr_size' => 8
|
||||
},
|
||||
'protection' => {
|
||||
'data_access_enable5' => '0x0',
|
||||
'inst_access_enable6' => '0x0',
|
||||
'inst_access_enable0' => '1',
|
||||
'data_access_enable0' => '1',
|
||||
'inst_access_enable5' => '0x0',
|
||||
'data_access_enable6' => '0x0',
|
||||
'inst_access_mask0' => '0x7fffffff',
|
||||
'inst_access_mask4' => '0xffffffff',
|
||||
'data_access_addr0' => '0x0',
|
||||
'inst_access_enable2' => '1',
|
||||
'data_access_enable4' => '0x0',
|
||||
'data_access_addr4' => '0x00000000',
|
||||
'data_access_enable2' => '1',
|
||||
'inst_access_addr0' => '0x0',
|
||||
'inst_access_enable4' => '0x0',
|
||||
'inst_access_addr4' => '0x00000000',
|
||||
'data_access_mask0' => '0x7fffffff',
|
||||
'data_access_mask4' => '0xffffffff',
|
||||
'data_access_addr1' => '0xc0000000',
|
||||
'inst_access_enable7' => '0x0',
|
||||
'inst_access_mask1' => '0x3fffffff',
|
||||
'inst_access_enable1' => '1',
|
||||
'data_access_enable3' => '1',
|
||||
'data_access_enable7' => '0x0',
|
||||
'data_access_mask1' => '0x3fffffff',
|
||||
'data_access_enable1' => '1',
|
||||
'inst_access_enable3' => '1',
|
||||
'inst_access_addr1' => '0xc0000000',
|
||||
'data_access_mask5' => '0xffffffff',
|
||||
'data_access_addr3' => '0x80000000',
|
||||
'inst_access_addr6' => '0x00000000',
|
||||
'data_access_addr2' => '0xa0000000',
|
||||
'data_access_addr7' => '0x00000000',
|
||||
'inst_access_mask3' => '0x0fffffff',
|
||||
'inst_access_addr5' => '0x00000000',
|
||||
'inst_access_mask7' => '0xffffffff',
|
||||
'inst_access_mask2' => '0x1fffffff',
|
||||
'data_access_mask6' => '0xffffffff',
|
||||
'data_access_mask3' => '0x0fffffff',
|
||||
'data_access_addr5' => '0x00000000',
|
||||
'data_access_mask7' => '0xffffffff',
|
||||
'data_access_mask2' => '0x1fffffff',
|
||||
'inst_access_mask6' => '0xffffffff',
|
||||
'inst_access_mask5' => '0xffffffff',
|
||||
'inst_access_addr3' => '0x80000000',
|
||||
'data_access_addr6' => '0x00000000',
|
||||
'inst_access_addr2' => '0xa0000000',
|
||||
'inst_access_addr7' => '0x00000000'
|
||||
},
|
||||
'iccm' => {
|
||||
'iccm_num_banks_4' => '',
|
||||
'iccm_sadr' => '0xee000000',
|
||||
'iccm_offset' => '0xe000000',
|
||||
'iccm_region' => '0xe',
|
||||
'iccm_index_bits' => 12,
|
||||
'iccm_enable' => 1,
|
||||
'iccm_size' => 64,
|
||||
'iccm_bank_hi' => 3,
|
||||
'iccm_reserved' => '0x1000',
|
||||
'iccm_rows' => '4096',
|
||||
'iccm_bank_index_lo' => 4,
|
||||
'iccm_bank_bits' => 2,
|
||||
'iccm_data_cell' => 'ram_4096x39',
|
||||
'iccm_bits' => 16,
|
||||
'iccm_size_64' => '',
|
||||
'iccm_num_banks' => '4',
|
||||
'iccm_eadr' => '0xee00ffff'
|
||||
},
|
||||
'harts' => 1,
|
||||
'reset_vec' => '0x80000000',
|
||||
'bus' => {
|
||||
'bus_prty_default' => '3',
|
||||
'ifu_bus_prty' => '2',
|
||||
'ifu_bus_id' => '1',
|
||||
'dma_bus_tag' => 1,
|
||||
'lsu_bus_tag' => 3,
|
||||
'sb_bus_tag' => 1,
|
||||
'ifu_bus_tag' => '3',
|
||||
'lsu_bus_id' => '1',
|
||||
'dma_bus_prty' => '2',
|
||||
'lsu_bus_prty' => '2',
|
||||
'dma_bus_id' => '1',
|
||||
'sb_bus_prty' => '2',
|
||||
'sb_bus_id' => '1'
|
||||
},
|
||||
'tec_rv_icg' => 'clockhdr',
|
||||
'testbench' => {
|
||||
'ext_datawidth' => '64',
|
||||
'CPU_TOP' => '`RV_TOP.quasar',
|
||||
'lderr_rollback' => '1',
|
||||
'RV_TOP' => '`TOP.rvtop',
|
||||
'ext_addrwidth' => '32',
|
||||
'clock_period' => '100',
|
||||
'build_axi4' => 1,
|
||||
'SDVT_AHB' => '1',
|
||||
'sterr_rollback' => '0',
|
||||
'assert_on' => '',
|
||||
'TOP' => 'tb_top',
|
||||
'build_axi_native' => 1
|
||||
},
|
||||
'even_odd_trigger_chains' => 'true',
|
||||
'dccm' => {
|
||||
'dccm_width_bits' => 2,
|
||||
'dccm_index_bits' => 12,
|
||||
'dccm_sadr' => '0xf0040000',
|
||||
'dccm_num_banks_4' => '',
|
||||
'dccm_offset' => '0x40000',
|
||||
'dccm_fdata_width' => 39,
|
||||
'dccm_region' => '0xf',
|
||||
'dccm_reserved' => '0x1400',
|
||||
'dccm_size' => 64,
|
||||
'dccm_enable' => '1',
|
||||
'dccm_data_width' => 32,
|
||||
'dccm_bits' => 16,
|
||||
'dccm_rows' => '4096',
|
||||
'dccm_byte_width' => '4',
|
||||
'dccm_bank_bits' => 2,
|
||||
'dccm_data_cell' => 'ram_4096x39',
|
||||
'dccm_ecc_width' => 7,
|
||||
'dccm_eadr' => '0xf004ffff',
|
||||
'dccm_size_64' => '',
|
||||
'dccm_num_banks' => '4',
|
||||
'lsu_sb_bits' => 16
|
||||
}
|
||||
);
|
||||
1;
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }
|
||||
always_comb begin
|
||||
case (address[14:0])
|
||||
15'b011000000000000 : mask[3:0] = 4'b0100;
|
||||
15'b100000000000100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000001000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000001100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000010000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000010100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000011000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000011100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000100000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000100100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000101000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000101100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000110000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000110100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000111000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000111100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001000000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001000100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001001000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001001100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001010000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001010100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001011000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001011100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001100000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001100100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001101000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001101100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001110000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001110100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001111000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001111100 : mask[3:0] = 4'b1000;
|
||||
15'b010000000000100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000001000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000001100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000010000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000010100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000011000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000011100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000100000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000100100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000101000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000101100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000110000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000110100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000111000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000111100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001000000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001000100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001001000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001001100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001010000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001010100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001011000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001011100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001100000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001100100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001101000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001101100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001110000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001110100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001111000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001111100 : mask[3:0] = 4'b0100;
|
||||
15'b000000000000100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000001000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000001100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000010000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000010100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000011000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000011100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000100000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000100100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000101000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000101100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000110000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000110100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000111000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000111100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001000000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001000100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001001000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001001100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001010000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001010100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001011000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001011100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001100000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001100100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001101000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001101100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001110000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001110100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001111000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001111100 : mask[3:0] = 4'b0010;
|
||||
default : mask[3:0] = 4'b0001;
|
||||
endcase
|
||||
end
|
||||
|
|
@ -1,546 +0,0 @@
|
|||
{
|
||||
"amo_illegal_outside_dccm" : "true",
|
||||
"num_mmode_perf_regs" : "4",
|
||||
"fast_interrupt_redirect" : "1",
|
||||
"even_odd_trigger_chains" : "true",
|
||||
"dccm" : {
|
||||
"size" : "0x10000",
|
||||
"offset" : "0x40000",
|
||||
"region" : "0xf"
|
||||
},
|
||||
"harts" : 1,
|
||||
"load_error_rollback" : "1",
|
||||
"reset_vec" : "0x80000000",
|
||||
"effective_address_compatible_with_base" : "true",
|
||||
"iccm" : {
|
||||
"size" : "0x10000",
|
||||
"region" : "0xe",
|
||||
"offset" : "0xe000000"
|
||||
},
|
||||
"xlen" : 32,
|
||||
"triggers" : [
|
||||
{
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
]
|
||||
}
|
||||
],
|
||||
"csr" : {
|
||||
"instret" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"tselect" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0x3"
|
||||
},
|
||||
"pmpcfg1" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr13" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"misa" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x40001104",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"pmpaddr15" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicad1" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7ca",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"mask" : "0x3",
|
||||
"debug" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mcgc" : {
|
||||
"poke_mask" : "0x000001ff",
|
||||
"mask" : "0x000001ff",
|
||||
"number" : "0x7f8",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpaddr4" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter6" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr8" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"time" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicago" : {
|
||||
"exists" : "true",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"number" : "0x7cb",
|
||||
"debug" : "true",
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mhpmcounter3h" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mhpmevent6" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mimpid" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x2",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"mitctl0" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7d4",
|
||||
"reset" : "0x1",
|
||||
"mask" : "0x00000007"
|
||||
},
|
||||
"mitcnt1" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7d5",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr9" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr1" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter5" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mitcnt0" : {
|
||||
"mask" : "0xffffffff",
|
||||
"number" : "0x7d2",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mvendorid" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x45",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"mitctl1" : {
|
||||
"mask" : "0x0000000f",
|
||||
"number" : "0x7d7",
|
||||
"exists" : "true",
|
||||
"reset" : "0x1"
|
||||
},
|
||||
"dcsr" : {
|
||||
"debug" : "true",
|
||||
"mask" : "0x00008c04",
|
||||
"exists" : "true",
|
||||
"reset" : "0x40000003",
|
||||
"poke_mask" : "0x00008dcc"
|
||||
},
|
||||
"pmpaddr0" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicad0" : {
|
||||
"reset" : "0x0",
|
||||
"debug" : "true",
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"number" : "0x7c9",
|
||||
"comment" : "Cache diagnostics."
|
||||
},
|
||||
"mhpmcounter6h" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpaddr11" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr5" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr7" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mdccmect" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7f2",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mhpmcounter5h" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mpmc" : {
|
||||
"number" : "0x7c6",
|
||||
"exists" : "true",
|
||||
"reset" : "0x2",
|
||||
"mask" : "0x2"
|
||||
},
|
||||
"miccmect" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7f1",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mhpmcounter3" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpcfg0" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mstatus" : {
|
||||
"mask" : "0x88",
|
||||
"exists" : "true",
|
||||
"reset" : "0x1800"
|
||||
},
|
||||
"micect" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"number" : "0x7f0"
|
||||
},
|
||||
"mhpmevent4" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr6" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr2" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter4h" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mhpmevent3" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpcfg2" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"meicidpl" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "External interrupt claim id priority level.",
|
||||
"number" : "0xbcb",
|
||||
"mask" : "0xf"
|
||||
},
|
||||
"mitbnd0" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d3"
|
||||
},
|
||||
"mhpmevent5" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"dicawics" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7c8",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"debug" : "true",
|
||||
"mask" : "0x0130fffc",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpaddr3" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mcpc" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7c2",
|
||||
"comment" : "Core pause",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"pmpcfg3" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"marchid" : {
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x00000010",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mcountinhibit" : {
|
||||
"poke_mask" : "0x7d",
|
||||
"mask" : "0x7d",
|
||||
"exists" : "true",
|
||||
"commnet" : "Performance counter inhibit. One bit per counter.",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mie" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0x70000888"
|
||||
},
|
||||
"cycle" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mfdc" : {
|
||||
"number" : "0x7f9",
|
||||
"exists" : "true",
|
||||
"reset" : "0x00070040",
|
||||
"mask" : "0x00070fff"
|
||||
},
|
||||
"mhpmcounter4" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr12" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mscause" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7ff",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0x0000000f"
|
||||
},
|
||||
"pmpaddr14" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"meipt" : {
|
||||
"mask" : "0xf",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"number" : "0xbc9",
|
||||
"comment" : "External interrupt priority threshold."
|
||||
},
|
||||
"mrac" : {
|
||||
"mask" : "0xffffffff",
|
||||
"shared" : "true",
|
||||
"exists" : "true",
|
||||
"comment" : "Memory region io and cache control.",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7c0"
|
||||
},
|
||||
"dmst" : {
|
||||
"exists" : "true",
|
||||
"comment" : "Memory synch trigger: Flush caches in debug mode.",
|
||||
"number" : "0x7c4",
|
||||
"mask" : "0x0",
|
||||
"debug" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"meicurpl" : {
|
||||
"mask" : "0xf",
|
||||
"comment" : "External interrupt current priority level.",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0xbcc"
|
||||
},
|
||||
"pmpaddr10" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mip" : {
|
||||
"poke_mask" : "0x70000888",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"mhartid" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0x0",
|
||||
"poke_mask" : "0xfffffff0"
|
||||
},
|
||||
"mitbnd1" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d6"
|
||||
}
|
||||
},
|
||||
"nmi_vec" : "0x11110000",
|
||||
"pic" : {
|
||||
"offset" : "0xc0000",
|
||||
"meipl_count" : 31,
|
||||
"meipt_count" : 31,
|
||||
"meigwclr_offset" : "0x5000",
|
||||
"meie_offset" : "0x2000",
|
||||
"meigwctrl_mask" : "0x3",
|
||||
"meigwctrl_offset" : "0x4000",
|
||||
"meipl_offset" : "0x0000",
|
||||
"size" : "0x8000",
|
||||
"meipt_offset" : "0x3004",
|
||||
"total_int" : 31,
|
||||
"meip_count" : 4,
|
||||
"meip_mask" : "0x0",
|
||||
"meipl_mask" : "0xf",
|
||||
"meipt_mask" : "0x0",
|
||||
"meigwclr_count" : 31,
|
||||
"meie_mask" : "0x1",
|
||||
"meie_count" : 31,
|
||||
"total_int_plus1" : 32,
|
||||
"meip_offset" : "0x1000",
|
||||
"meigwctrl_count" : 31,
|
||||
"mpiccfg_offset" : "0x3000",
|
||||
"int_words" : 1,
|
||||
"region" : "0xf",
|
||||
"mpiccfg_count" : 1,
|
||||
"mpiccfg_mask" : "0x1",
|
||||
"meigwclr_mask" : "0x0",
|
||||
"bits" : 15
|
||||
},
|
||||
"max_mmode_perf_event" : "516",
|
||||
"memmap" : {
|
||||
"inst" : [
|
||||
[
|
||||
"0x00000000",
|
||||
"0x7fffffff"
|
||||
],
|
||||
[
|
||||
"0xa0000000",
|
||||
"0xbfffffff"
|
||||
],
|
||||
[
|
||||
"0xc0000000",
|
||||
"0xffffffff"
|
||||
],
|
||||
[
|
||||
"0x80000000",
|
||||
"0x8fffffff"
|
||||
]
|
||||
],
|
||||
"data" : [
|
||||
[
|
||||
"0x00000000",
|
||||
"0x7fffffff"
|
||||
],
|
||||
[
|
||||
"0xa0000000",
|
||||
"0xbfffffff"
|
||||
],
|
||||
[
|
||||
"0x80000000",
|
||||
"0x8fffffff"
|
||||
],
|
||||
[
|
||||
"0xc0000000",
|
||||
"0xffffffff"
|
||||
]
|
||||
]
|
||||
},
|
||||
"memory_mapped_registers" : {
|
||||
"default_mask" : 0,
|
||||
"size" : "0x8000",
|
||||
"address" : "0xf00c0000",
|
||||
"registers" : {
|
||||
"meigwclr" : {
|
||||
"mask" : "0x0",
|
||||
"address" : "0xf00c5004",
|
||||
"count" : "31"
|
||||
},
|
||||
"meipl" : {
|
||||
"mask" : "0xf",
|
||||
"address" : "0xf00c0004",
|
||||
"count" : "31"
|
||||
},
|
||||
"meigwctrl" : {
|
||||
"mask" : "0x3",
|
||||
"address" : "0xf00c4004",
|
||||
"count" : "31"
|
||||
},
|
||||
"meie" : {
|
||||
"address" : "0xf00c2004",
|
||||
"mask" : "0x1",
|
||||
"count" : "31"
|
||||
},
|
||||
"meip" : {
|
||||
"address" : "0xf00c1000",
|
||||
"mask" : "0x0",
|
||||
"count" : 4
|
||||
},
|
||||
"mpiccfg" : {
|
||||
"count" : 1,
|
||||
"mask" : "0x1",
|
||||
"address" : "0xf00c3000"
|
||||
}
|
||||
}
|
||||
},
|
||||
"store_error_rollback" : "0"
|
||||
}
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
//THIS IS A SELF WRITTEN PARAMETER FILE FOR CHISEL
|
||||
|
||||
package lib
|
||||
import chisel3._
|
||||
trait param {
|
||||
val BHT_ADDR_HI = 0x9
|
||||
val BHT_ADDR_LO = 0x2
|
||||
val BHT_ARRAY_DEPTH = 0x100
|
||||
val BHT_GHR_HASH_1 = 0x0
|
||||
val BHT_GHR_SIZE = 0x8
|
||||
val BHT_SIZE = 0x200
|
||||
val BTB_ADDR_HI = 0x09
|
||||
val BTB_ADDR_LO = 0x2
|
||||
val BTB_ARRAY_DEPTH = 0x100
|
||||
val BTB_BTAG_FOLD = 0x0
|
||||
val BTB_BTAG_SIZE = 0x5
|
||||
val BTB_FOLD2_INDEX_HASH = 0x0
|
||||
val BTB_INDEX1_HI = 0x09
|
||||
val BTB_INDEX1_LO = 0x02
|
||||
val BTB_INDEX2_HI = 0x11
|
||||
val BTB_INDEX2_LO = 0x0A
|
||||
val BTB_INDEX3_HI = 0x19
|
||||
val BTB_INDEX3_LO = 0x12
|
||||
val BTB_SIZE = 0x200
|
||||
val BUILD_AHB_LITE = 0x0
|
||||
val BUILD_AXI4 = 0x1
|
||||
val BUILD_AXI_NATIVE = 0x1
|
||||
val BUS_PRTY_DEFAULT = 0x3
|
||||
val DATA_ACCESS_ADDR0 = 0x00000000
|
||||
val DATA_ACCESS_ADDR1 = 0xC0000000
|
||||
val DATA_ACCESS_ADDR2 = 0xA0000000
|
||||
val DATA_ACCESS_ADDR3 = 0x80000000
|
||||
val DATA_ACCESS_ADDR4 = 0x00000000
|
||||
val DATA_ACCESS_ADDR5 = 0x00000000
|
||||
val DATA_ACCESS_ADDR6 = 0x00000000
|
||||
val DATA_ACCESS_ADDR7 = 0x00000000
|
||||
val DATA_ACCESS_ENABLE0 = 0x1
|
||||
val DATA_ACCESS_ENABLE1 = 0x1
|
||||
val DATA_ACCESS_ENABLE2 = 0x1
|
||||
val DATA_ACCESS_ENABLE3 = 0x1
|
||||
val DATA_ACCESS_ENABLE4 = 0x0
|
||||
val DATA_ACCESS_ENABLE5 = 0x0
|
||||
val DATA_ACCESS_ENABLE6 = 0x0
|
||||
val DATA_ACCESS_ENABLE7 = 0x0
|
||||
val DATA_ACCESS_MASK0 = 0x7FFFFFFF
|
||||
val DATA_ACCESS_MASK1 = 0x3FFFFFFF
|
||||
val DATA_ACCESS_MASK2 = 0x1FFFFFFF
|
||||
val DATA_ACCESS_MASK3 = 0x0FFFFFFF
|
||||
val DATA_ACCESS_MASK4 = 0xFFFFFFFF
|
||||
val DATA_ACCESS_MASK5 = 0xFFFFFFFF
|
||||
val DATA_ACCESS_MASK6 = 0xFFFFFFFF
|
||||
val DATA_ACCESS_MASK7 = 0xFFFFFFFF
|
||||
val DCCM_BANK_BITS = 0x2
|
||||
val DCCM_BITS = 0x10
|
||||
val DCCM_BYTE_WIDTH = 0x4
|
||||
val DCCM_DATA_WIDTH = 0x20
|
||||
val DCCM_ECC_WIDTH = 0x7
|
||||
val DCCM_ENABLE = 0x1
|
||||
val DCCM_FDATA_WIDTH = 0x27
|
||||
val DCCM_INDEX_BITS = 0xC
|
||||
val DCCM_NUM_BANKS = 0x04
|
||||
val DCCM_REGION = 0xF
|
||||
val DCCM_SADR = 0xF0040000
|
||||
val DCCM_SIZE = 0x040
|
||||
val DCCM_WIDTH_BITS = 0x2
|
||||
val DMA_BUF_DEPTH = 0x5
|
||||
val DMA_BUS_ID = 0x1
|
||||
val DMA_BUS_PRTY = 0x2
|
||||
val DMA_BUS_TAG = 0x1
|
||||
val FAST_INTERRUPT_REDIRECT = 0x1
|
||||
val ICACHE_2BANKS = 0x1
|
||||
val ICACHE_BANK_BITS = 0x1
|
||||
val ICACHE_BANK_HI = 0x3
|
||||
val ICACHE_BANK_LO = 0x3
|
||||
val ICACHE_BANK_WIDTH = 0x8
|
||||
val ICACHE_BANKS_WAY = 0x2
|
||||
val ICACHE_BEAT_ADDR_HI = 0x5
|
||||
val ICACHE_BEAT_BITS = 0x3
|
||||
val ICACHE_DATA_DEPTH = 0x0200
|
||||
val ICACHE_DATA_INDEX_LO = 0x4
|
||||
val ICACHE_DATA_WIDTH = 0x40
|
||||
val ICACHE_ECC = 0x1
|
||||
val ICACHE_ENABLE = 0x1
|
||||
val ICACHE_FDATA_WIDTH = 0x47
|
||||
val ICACHE_INDEX_HI = 0x0C
|
||||
val ICACHE_LN_SZ = 0x40
|
||||
val ICACHE_NUM_BEATS = 0x8
|
||||
val ICACHE_NUM_WAYS = 0x2
|
||||
val ICACHE_ONLY = 0x0
|
||||
val ICACHE_SCND_LAST = 0x6
|
||||
val ICACHE_SIZE = 0x010
|
||||
val ICACHE_STATUS_BITS = 0x1
|
||||
val ICACHE_TAG_DEPTH = 0x0080
|
||||
val ICACHE_TAG_INDEX_LO = 0x6
|
||||
val ICACHE_TAG_LO = 0x0D
|
||||
val ICACHE_WAYPACK = 0x0
|
||||
val ICCM_BANK_BITS = 0x2
|
||||
val ICCM_BANK_HI = 0x03
|
||||
val ICCM_BANK_INDEX_LO = 0x04
|
||||
val ICCM_BITS = 0x10
|
||||
val ICCM_ENABLE = 0x1
|
||||
val ICCM_ICACHE = 0x1
|
||||
val ICCM_INDEX_BITS = 0xC
|
||||
val ICCM_NUM_BANKS = 0x04
|
||||
val ICCM_ONLY = 0x0
|
||||
val ICCM_REGION = 0xE
|
||||
val ICCM_SADR = 0xEE000000
|
||||
val ICCM_SIZE = 0x040
|
||||
val IFU_BUS_ID = 0x1
|
||||
val IFU_BUS_PRTY = 0x2
|
||||
val IFU_BUS_TAG = 0x3
|
||||
val INST_ACCESS_ADDR0 = 0x00000000
|
||||
val INST_ACCESS_ADDR1 = 0xC0000000
|
||||
val INST_ACCESS_ADDR2 = 0xA0000000
|
||||
val INST_ACCESS_ADDR3 = 0x80000000
|
||||
val INST_ACCESS_ADDR4 = 0x00000000
|
||||
val INST_ACCESS_ADDR5 = 0x00000000
|
||||
val INST_ACCESS_ADDR6 = 0x00000000
|
||||
val INST_ACCESS_ADDR7 = 0x00000000
|
||||
val INST_ACCESS_ENABLE0 = 0x1
|
||||
val INST_ACCESS_ENABLE1 = 0x1
|
||||
val INST_ACCESS_ENABLE2 = 0x1
|
||||
val INST_ACCESS_ENABLE3 = 0x1
|
||||
val INST_ACCESS_ENABLE4 = 0x0
|
||||
val INST_ACCESS_ENABLE5 = 0x0
|
||||
val INST_ACCESS_ENABLE6 = 0x0
|
||||
val INST_ACCESS_ENABLE7 = 0x0
|
||||
val INST_ACCESS_MASK0 = 0x7FFFFFFF
|
||||
val INST_ACCESS_MASK1 = 0x3FFFFFFF
|
||||
val INST_ACCESS_MASK2 = 0x1FFFFFFF
|
||||
val INST_ACCESS_MASK3 = 0x0FFFFFFF
|
||||
val INST_ACCESS_MASK4 = 0xFFFFFFFF
|
||||
val INST_ACCESS_MASK5 = 0xFFFFFFFF
|
||||
val INST_ACCESS_MASK6 = 0xFFFFFFFF
|
||||
val INST_ACCESS_MASK7 = 0xFFFFFFFF
|
||||
val LOAD_TO_USE_PLUS1 = 0x0
|
||||
val LSU2DMA = 0x0
|
||||
val LSU_BUS_ID = 0x1
|
||||
val LSU_BUS_PRTY = 0x2
|
||||
val LSU_BUS_TAG = 0x3
|
||||
val LSU_NUM_NBLOAD = 0x04
|
||||
val LSU_NUM_NBLOAD_WIDTH = 0x2
|
||||
val LSU_SB_BITS = 0x10
|
||||
val LSU_STBUF_DEPTH = 0x4
|
||||
val NO_ICCM_NO_ICACHE = 0x0
|
||||
val PIC_2CYCLE = 0x0
|
||||
val PIC_BASE_ADDR = 0xF00C0000
|
||||
val PIC_BITS = 0x0F
|
||||
val PIC_INT_WORDS = 0x1
|
||||
val PIC_REGION = 0xF
|
||||
val PIC_SIZE = 0x020
|
||||
val PIC_TOTAL_INT = 0x1F
|
||||
val PIC_TOTAL_INT_PLUS1 = 0x020
|
||||
val RET_STACK_SIZE = 0x8
|
||||
val SB_BUS_ID = 0x1
|
||||
val SB_BUS_PRTY = 0x2
|
||||
val SB_BUS_TAG = 0x1
|
||||
val TIMER_LEGAL_EN = 0x1
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,3 +0,0 @@
|
|||
----------------------------------
|
||||
Hello World from Quasar @LM !!
|
||||
----------------------------------
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
# 1 "/home/waleedbinehsan/Desktop/Quasar/testbench/asm/hello_world.s"
|
||||
# 1 "<built-in>"
|
||||
# 1 "<command-line>"
|
||||
# 1 "/home/waleedbinehsan/Desktop/Quasar/testbench/asm/hello_world.s"
|
||||
# 20 "/home/waleedbinehsan/Desktop/Quasar/testbench/asm/hello_world.s"
|
||||
# 1 "/home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/defines.h" 1
|
||||
# 21 "/home/waleedbinehsan/Desktop/Quasar/testbench/asm/hello_world.s" 2
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
.section .text
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
|
||||
csrw minstret, zero
|
||||
csrw minstreth, zero
|
||||
|
||||
|
||||
li x1, 0xee000000
|
||||
csrw mtvec, x1
|
||||
|
||||
|
||||
|
||||
li x1, 0x5f555555
|
||||
csrw 0x7c0, x1
|
||||
|
||||
|
||||
|
||||
|
||||
li x3, 0xd0580000
|
||||
la x4, hw_data
|
||||
|
||||
loop:
|
||||
lb x5, 0(x4)
|
||||
sb x5, 0(x3)
|
||||
addi x4, x4, 1
|
||||
bnez x5, loop
|
||||
|
||||
|
||||
_finish:
|
||||
li x3, 0xd0580000
|
||||
addi x5, x0, 0xff
|
||||
sb x5, 0(x3)
|
||||
beq x0, x0, _finish
|
||||
.rept 100
|
||||
nop
|
||||
.endr
|
||||
|
||||
.data
|
||||
hw_data:
|
||||
.ascii "----------------------------------\n"
|
||||
.ascii "Hello World from Quasar @LM !!\n"
|
||||
.ascii "----------------------------------\n"
|
||||
.byte 0
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
|
||||
/home/waleedbinehsan/Desktop/Quasar/verif/sim/hello_world.exe: file format elf32-littleriscv
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <_start>:
|
||||
0: b0201073 csrw minstret,zero
|
||||
4: b8201073 csrw minstreth,zero
|
||||
8: ee0000b7 lui ra,0xee000
|
||||
c: 30509073 csrw mtvec,ra
|
||||
10: 5f5550b7 lui ra,0x5f555
|
||||
14: 55508093 addi ra,ra,1365 # 5f555555 <STACK+0x5f53d4e5>
|
||||
18: 7c009073 csrw 0x7c0,ra
|
||||
1c: d05801b7 lui gp,0xd0580
|
||||
20: 00010217 auipc tp,0x10
|
||||
24: fe020213 addi tp,tp,-32 # 10000 <hw_data>
|
||||
|
||||
00000028 <loop>:
|
||||
28: 00020283 lb t0,0(tp) # 0 <_start>
|
||||
2c: 00518023 sb t0,0(gp) # d0580000 <STACK+0xd0567f90>
|
||||
30: 0205 addi tp,tp,1
|
||||
32: fe029be3 bnez t0,28 <loop>
|
||||
|
||||
00000036 <_finish>:
|
||||
36: d05801b7 lui gp,0xd0580
|
||||
3a: 0ff00293 li t0,255
|
||||
3e: 00518023 sb t0,0(gp) # d0580000 <STACK+0xd0567f90>
|
||||
42: fe000ae3 beqz zero,36 <_finish>
|
||||
46: 0001 nop
|
||||
48: 0001 nop
|
||||
4a: 0001 nop
|
||||
4c: 0001 nop
|
||||
4e: 0001 nop
|
||||
50: 0001 nop
|
||||
52: 0001 nop
|
||||
54: 0001 nop
|
||||
56: 0001 nop
|
||||
58: 0001 nop
|
||||
5a: 0001 nop
|
||||
5c: 0001 nop
|
||||
5e: 0001 nop
|
||||
60: 0001 nop
|
||||
62: 0001 nop
|
||||
64: 0001 nop
|
||||
66: 0001 nop
|
||||
68: 0001 nop
|
||||
6a: 0001 nop
|
||||
6c: 0001 nop
|
||||
6e: 0001 nop
|
||||
70: 0001 nop
|
||||
72: 0001 nop
|
||||
74: 0001 nop
|
||||
76: 0001 nop
|
||||
78: 0001 nop
|
||||
7a: 0001 nop
|
||||
7c: 0001 nop
|
||||
7e: 0001 nop
|
||||
80: 0001 nop
|
||||
82: 0001 nop
|
||||
84: 0001 nop
|
||||
86: 0001 nop
|
||||
88: 0001 nop
|
||||
8a: 0001 nop
|
||||
8c: 0001 nop
|
||||
8e: 0001 nop
|
||||
90: 0001 nop
|
||||
92: 0001 nop
|
||||
94: 0001 nop
|
||||
96: 0001 nop
|
||||
98: 0001 nop
|
||||
9a: 0001 nop
|
||||
9c: 0001 nop
|
||||
9e: 0001 nop
|
||||
a0: 0001 nop
|
||||
a2: 0001 nop
|
||||
a4: 0001 nop
|
||||
a6: 0001 nop
|
||||
a8: 0001 nop
|
||||
aa: 0001 nop
|
||||
ac: 0001 nop
|
||||
ae: 0001 nop
|
||||
b0: 0001 nop
|
||||
b2: 0001 nop
|
||||
b4: 0001 nop
|
||||
b6: 0001 nop
|
||||
b8: 0001 nop
|
||||
ba: 0001 nop
|
||||
bc: 0001 nop
|
||||
be: 0001 nop
|
||||
c0: 0001 nop
|
||||
c2: 0001 nop
|
||||
c4: 0001 nop
|
||||
c6: 0001 nop
|
||||
c8: 0001 nop
|
||||
ca: 0001 nop
|
||||
cc: 0001 nop
|
||||
ce: 0001 nop
|
||||
d0: 0001 nop
|
||||
d2: 0001 nop
|
||||
d4: 0001 nop
|
||||
d6: 0001 nop
|
||||
d8: 0001 nop
|
||||
da: 0001 nop
|
||||
dc: 0001 nop
|
||||
de: 0001 nop
|
||||
e0: 0001 nop
|
||||
e2: 0001 nop
|
||||
e4: 0001 nop
|
||||
e6: 0001 nop
|
||||
e8: 0001 nop
|
||||
ea: 0001 nop
|
||||
ec: 0001 nop
|
||||
ee: 0001 nop
|
||||
f0: 0001 nop
|
||||
f2: 0001 nop
|
||||
f4: 0001 nop
|
||||
f6: 0001 nop
|
||||
f8: 0001 nop
|
||||
fa: 0001 nop
|
||||
fc: 0001 nop
|
||||
fe: 0001 nop
|
||||
100: 0001 nop
|
||||
102: 0001 nop
|
||||
104: 0001 nop
|
||||
106: 0001 nop
|
||||
108: 0001 nop
|
||||
10a: 0001 nop
|
||||
10c: 0001 nop
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,7 +0,0 @@
|
|||
_end T 0000010e
|
||||
_finish t 00000036
|
||||
hw_data d 00010000
|
||||
.L0 t 00000020
|
||||
loop t 00000028
|
||||
STACK D 00018070
|
||||
_start T 00000000
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,67 +0,0 @@
|
|||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
|
||||
#
|
||||
# Execute this makefile from the object directory:
|
||||
# make -f Vtb_top.mk
|
||||
|
||||
default: Vtb_top
|
||||
|
||||
### Constants...
|
||||
# Perl executable (from $PERL)
|
||||
PERL = perl
|
||||
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||
VERILATOR_ROOT = /usr/local/share/verilator
|
||||
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||
SYSTEMC_INCLUDE ?=
|
||||
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||
SYSTEMC_LIBDIR ?=
|
||||
|
||||
### Switches...
|
||||
# SystemC output mode? 0/1 (from --sc)
|
||||
VM_SC = 0
|
||||
# Legacy or SystemC output mode? 0/1 (from --sc)
|
||||
VM_SP_OR_SC = $(VM_SC)
|
||||
# Deprecated
|
||||
VM_PCLI = 1
|
||||
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
|
||||
VM_SC_TARGET_ARCH = linux
|
||||
|
||||
### Vars...
|
||||
# Design prefix (from --prefix)
|
||||
VM_PREFIX = Vtb_top
|
||||
# Module prefix (from --prefix)
|
||||
VM_MODPREFIX = Vtb_top
|
||||
# User CFLAGS (from -CFLAGS on Verilator command line)
|
||||
VM_USER_CFLAGS = \
|
||||
-std=c++11 \
|
||||
|
||||
# User LDLIBS (from -LDFLAGS on Verilator command line)
|
||||
VM_USER_LDLIBS = \
|
||||
|
||||
# User .cpp files (from .cpp's on Verilator command line)
|
||||
VM_USER_CLASSES = \
|
||||
test_tb_top \
|
||||
|
||||
# User .cpp directories (from .cpp's on Verilator command line)
|
||||
VM_USER_DIR = \
|
||||
. \
|
||||
|
||||
|
||||
### Default rules...
|
||||
# Include list of all generated classes
|
||||
include Vtb_top_classes.mk
|
||||
# Include global rules
|
||||
include $(VERILATOR_ROOT)/include/verilated.mk
|
||||
|
||||
### Executable rules... (from --exe)
|
||||
VPATH += $(VM_USER_DIR)
|
||||
|
||||
test_tb_top.o: test_tb_top.cpp
|
||||
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
|
||||
|
||||
### Link rules... (from --exe)
|
||||
Vtb_top: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
|
||||
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
Binary file not shown.
|
|
@ -1,4 +0,0 @@
|
|||
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||
#define VL_INCLUDE_OPT include
|
||||
#include "Vtb_top.cpp"
|
||||
#include "Vtb_top___024unit.cpp"
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
Vtb_top__ALLfast.o: Vtb_top__ALLfast.cpp Vtb_top.cpp Vtb_top.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h Vtb_top__Syms.h \
|
||||
Vtb_top___024unit.h Vtb_top___024unit.cpp
|
||||
Binary file not shown.
|
|
@ -1,3 +0,0 @@
|
|||
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||
#define VL_INCLUDE_OPT include
|
||||
#include "Vtb_top__Syms.cpp"
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
Vtb_top__ALLslow.o: Vtb_top__ALLslow.cpp Vtb_top__Syms.cpp \
|
||||
Vtb_top__Syms.h /usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h Vtb_top.h \
|
||||
Vtb_top___024unit.h
|
||||
Binary file not shown.
|
|
@ -1,22 +0,0 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table implementation internals
|
||||
|
||||
#include "Vtb_top__Syms.h"
|
||||
#include "Vtb_top.h"
|
||||
#include "Vtb_top___024unit.h"
|
||||
|
||||
|
||||
|
||||
// FUNCTIONS
|
||||
Vtb_top__Syms::Vtb_top__Syms(Vtb_top* topp, const char* namep)
|
||||
// Setup locals
|
||||
: __Vm_namep(namep)
|
||||
, __Vm_didInit(false)
|
||||
// Setup submodule names
|
||||
{
|
||||
// Pointer to top level
|
||||
TOPp = topp;
|
||||
// Setup each module's pointers to their submodules
|
||||
// Setup each module's pointer back to symbol table (for public functions)
|
||||
TOPp->__Vconfigure(this, true);
|
||||
}
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||
//
|
||||
// Internal details; most calling programs do not need this header,
|
||||
// unless using verilator public meta comments.
|
||||
|
||||
#ifndef _VTB_TOP__SYMS_H_
|
||||
#define _VTB_TOP__SYMS_H_ // guard
|
||||
|
||||
#include "verilated_heavy.h"
|
||||
|
||||
// INCLUDE MODULE CLASSES
|
||||
#include "Vtb_top.h"
|
||||
#include "Vtb_top___024unit.h"
|
||||
|
||||
// SYMS CLASS
|
||||
class Vtb_top__Syms : public VerilatedSyms {
|
||||
public:
|
||||
|
||||
// LOCAL STATE
|
||||
const char* __Vm_namep;
|
||||
bool __Vm_didInit;
|
||||
|
||||
// SUBCELL STATE
|
||||
Vtb_top* TOPp;
|
||||
|
||||
// CREATORS
|
||||
Vtb_top__Syms(Vtb_top* topp, const char* namep);
|
||||
~Vtb_top__Syms() {}
|
||||
|
||||
// METHODS
|
||||
inline const char* name() { return __Vm_namep; }
|
||||
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
#endif // guard
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vtb_top.h for the primary calling header
|
||||
|
||||
#include "Vtb_top___024unit.h"
|
||||
#include "Vtb_top__Syms.h"
|
||||
|
||||
//==========
|
||||
|
||||
VL_CTOR_IMP(Vtb_top___024unit) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void Vtb_top___024unit::__Vconfigure(Vtb_top__Syms* vlSymsp, bool first) {
|
||||
if (false && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
if (false && this->__VlSymsp) {} // Prevent unused
|
||||
}
|
||||
|
||||
Vtb_top___024unit::~Vtb_top___024unit() {
|
||||
}
|
||||
|
||||
void Vtb_top___024unit::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb_top___024unit::_ctor_var_reset\n"); );
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See Vtb_top.h for the primary calling header
|
||||
|
||||
#ifndef _VTB_TOP___024UNIT_H_
|
||||
#define _VTB_TOP___024UNIT_H_ // guard
|
||||
|
||||
#include "verilated_heavy.h"
|
||||
|
||||
//==========
|
||||
|
||||
class Vtb_top__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(Vtb_top___024unit) {
|
||||
public:
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
Vtb_top__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(Vtb_top___024unit); ///< Copying not allowed
|
||||
public:
|
||||
Vtb_top___024unit(const char* name = "TOP");
|
||||
~Vtb_top___024unit();
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(Vtb_top__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
//----------
|
||||
|
||||
|
||||
#endif // guard
|
||||
|
|
@ -1 +0,0 @@
|
|||
obj_dir/Vtb_top.cpp obj_dir/Vtb_top.h obj_dir/Vtb_top.mk obj_dir/Vtb_top__Syms.cpp obj_dir/Vtb_top__Syms.h obj_dir/Vtb_top___024unit.cpp obj_dir/Vtb_top___024unit.h obj_dir/Vtb_top__ver.d obj_dir/Vtb_top_classes.mk : /usr/local/bin/verilator_bin /home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/common_defines.vh /home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/pdef.vh /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv /home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv /home/waleedbinehsan/Desktop/Quasar/generated_rtl/quasar_wrapper.sv /home/waleedbinehsan/Desktop/Quasar/testbench/ahb_sif.sv /home/waleedbinehsan/Desktop/Quasar/testbench/axi_lsu_dma_bridge.sv /home/waleedbinehsan/Desktop/Quasar/testbench/flist /home/waleedbinehsan/Desktop/Quasar/testbench/tb_top.sv /usr/local/bin/verilator_bin
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "--cc -CFLAGS -std=c++11 /home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/common_defines.vh /home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/pdef.vh -I/home/waleedbinehsan/Desktop/Quasar/design/snapshots/default -I/home/waleedbinehsan/Desktop/Quasar/testbench -f /home/waleedbinehsan/Desktop/Quasar/testbench/flist -Wno-WIDTH -Wno-UNOPTFLAT /home/waleedbinehsan/Desktop/Quasar/testbench/tb_top.sv --top-module tb_top -exe test_tb_top.cpp --autoflush"
|
||||
S 7412 56361993 1610015888 384359670 1610015888 384359670 "/home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/common_defines.vh"
|
||||
S 5027 56361991 1610015744 710171881 1610015744 710171881 "/home/waleedbinehsan/Desktop/Quasar/design/snapshots/default/pdef.vh"
|
||||
S 17754 55838324 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv"
|
||||
S 1967 55838325 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"
|
||||
S 4005 55838326 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv"
|
||||
S 246 55838327 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv"
|
||||
S 105910 55838328 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv"
|
||||
S 17538 55838329 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv"
|
||||
S 11999 55838330 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv"
|
||||
S 5965 55838331 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv"
|
||||
S 5591 55838332 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv"
|
||||
S 7042 55838334 1610015510 81195353 1610015510 81195353 "/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv"
|
||||
S 4272705 55838562 1610015887 52376390 1610015887 28376691 "/home/waleedbinehsan/Desktop/Quasar/generated_rtl/quasar_wrapper.sv"
|
||||
S 5400 56361915 1610015510 205193722 1610015510 205193722 "/home/waleedbinehsan/Desktop/Quasar/testbench/ahb_sif.sv"
|
||||
S 5540 56361928 1610015510 209193669 1610015510 209193669 "/home/waleedbinehsan/Desktop/Quasar/testbench/axi_lsu_dma_bridge.sv"
|
||||
S 719 56361929 1610015510 209193669 1610015510 209193669 "/home/waleedbinehsan/Desktop/Quasar/testbench/flist"
|
||||
S 50639 56361948 1610015510 217193563 1610015510 217193563 "/home/waleedbinehsan/Desktop/Quasar/testbench/tb_top.sv"
|
||||
S 8412896 41291989 1594797538 958726862 1594797538 958726862 "/usr/local/bin/verilator_bin"
|
||||
T 12882045 56362057 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top.cpp"
|
||||
T 944064 56362056 1610015898 828228612 1610015898 828228612 "obj_dir/Vtb_top.h"
|
||||
T 1794 56362061 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top.mk"
|
||||
T 575 56362054 1610015898 784229164 1610015898 784229164 "obj_dir/Vtb_top__Syms.cpp"
|
||||
T 825 56362055 1610015898 784229164 1610015898 784229164 "obj_dir/Vtb_top__Syms.h"
|
||||
T 714 56362059 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top___024unit.cpp"
|
||||
T 818 56362058 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top___024unit.h"
|
||||
T 1540 56362062 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top__ver.d"
|
||||
T 0 0 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top__verFiles.dat"
|
||||
T 1554 56362060 1610015899 224223644 1610015899 224223644 "obj_dir/Vtb_top_classes.mk"
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Make include file with class lists
|
||||
#
|
||||
# This file lists generated Verilated files, for including in higher level makefiles.
|
||||
# See Vtb_top.mk for the caller.
|
||||
|
||||
### Switches...
|
||||
# C11 constructs required? 0/1 (from --threads, --trace-threads or use of classes)
|
||||
VM_C11 = 0
|
||||
# Coverage output mode? 0/1 (from --coverage)
|
||||
VM_COVERAGE = 0
|
||||
# Parallel builds? 0/1 (from --output-split)
|
||||
VM_PARALLEL_BUILDS = 0
|
||||
# Threaded output mode? 0/1/N threads (from --threads)
|
||||
VM_THREADS = 0
|
||||
# Tracing output mode? 0/1 (from --trace/--trace-fst)
|
||||
VM_TRACE = 0
|
||||
# Tracing threaded output mode? 0/1/N threads (from --trace-thread)
|
||||
VM_TRACE_THREADS = 0
|
||||
# Separate FST writer thread? 0/1 (from --trace-fst with --trace-thread > 0)
|
||||
VM_TRACE_FST_WRITER_THREAD = 0
|
||||
|
||||
### Object file lists...
|
||||
# Generated module classes, fast-path, compile with highest optimization
|
||||
VM_CLASSES_FAST += \
|
||||
Vtb_top \
|
||||
Vtb_top___024unit \
|
||||
|
||||
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||
VM_CLASSES_SLOW += \
|
||||
|
||||
# Generated support classes, fast-path, compile with highest optimization
|
||||
VM_SUPPORT_FAST += \
|
||||
|
||||
# Generated support classes, non-fast-path, compile with low/medium optimization
|
||||
VM_SUPPORT_SLOW += \
|
||||
Vtb_top__Syms \
|
||||
|
||||
# Global classes, need linked once per executable, fast-path, compile with highest optimization
|
||||
VM_GLOBAL_FAST += \
|
||||
verilated \
|
||||
|
||||
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
|
||||
VM_GLOBAL_SLOW += \
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2019 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
#include <stdlib.h>
|
||||
#include <iostream>
|
||||
#include <utility>
|
||||
#include <string>
|
||||
#include "Vtb_top.h"
|
||||
#include "verilated.h"
|
||||
#include "verilated_vcd_c.h"
|
||||
|
||||
|
||||
vluint64_t main_time = 0;
|
||||
|
||||
double sc_time_stamp () {
|
||||
return main_time;
|
||||
}
|
||||
|
||||
|
||||
int main(int argc, char** argv) {
|
||||
std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
|
||||
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
Vtb_top* tb = new Vtb_top;
|
||||
|
||||
// init trace dump
|
||||
VerilatedVcdC* tfp = NULL;
|
||||
|
||||
#if VM_TRACE
|
||||
Verilated::traceEverOn(true);
|
||||
tfp = new VerilatedVcdC;
|
||||
tb->trace (tfp, 24);
|
||||
tfp->open ("sim.vcd");
|
||||
#endif
|
||||
// Simulate
|
||||
while(!Verilated::gotFinish()){
|
||||
#if VM_TRACE
|
||||
tfp->dump (main_time);
|
||||
#endif
|
||||
main_time += 5;
|
||||
tb->core_clk = !tb->core_clk;
|
||||
tb->eval();
|
||||
}
|
||||
|
||||
#if VM_TRACE
|
||||
tfp->close();
|
||||
#endif
|
||||
|
||||
std::cout << "\nVerilatorTB: End of sim" << std::endl;
|
||||
exit(EXIT_SUCCESS);
|
||||
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
test_tb_top.o: test_tb_top.cpp Vtb_top.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilated_vcd_c.h \
|
||||
/usr/local/share/verilator/include/verilated_trace.h
|
||||
Binary file not shown.
|
|
@ -1,8 +0,0 @@
|
|||
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
/usr/local/share/verilator/include/verilated_imp.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated_syms.h \
|
||||
/usr/local/share/verilator/include/verilated_sym_props.h \
|
||||
/usr/local/share/verilator/include/verilated_config.h
|
||||
Binary file not shown.
|
|
@ -1,421 +0,0 @@
|
|||
01,00000000,00000000,0,b0201073,3,00,00,00000000,00
|
||||
01,00000000,00000004,0,b8201073,3,00,00,00000000,00
|
||||
01,00000000,00000008,0,ee0000b7,3,00,00,00000000,00
|
||||
01,00000000,0000000c,0,30509073,3,00,00,00000000,00
|
||||
01,00000000,00000010,0,5f5550b7,3,00,00,00000000,00
|
||||
01,00000000,00000014,0,55508093,3,00,00,00000000,00
|
||||
01,00000000,00000018,0,7c009073,3,00,00,00000000,00
|
||||
01,00000000,0000001c,0,d05801b7,3,00,00,00000000,00
|
||||
01,00000000,00000020,0,10217,3,00,00,00000000,00
|
||||
01,00000000,00000024,0,fe020213,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000028,0,20283,3,00,00,00000000,00
|
||||
01,00000000,0000002c,0,518023,3,00,00,00000000,00
|
||||
01,00000000,00000030,0,205,3,00,00,00000000,00
|
||||
01,00000000,00000032,0,fe029be3,3,00,00,00000000,00
|
||||
01,00000000,00000036,0,d05801b7,3,00,00,00000000,00
|
||||
01,00000000,0000003a,0,ff00293,3,00,00,00000000,00
|
||||
01,00000000,0000003e,0,518023,3,00,00,00000000,00
|
||||
|
Loading…
Reference in New Issue