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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-03 11:39:11 +05:00
parent 5e4f49b6b2
commit 7a1457b2e2
6 changed files with 748 additions and 733 deletions
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axi4_to_ahb.fir
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axi4_to_ahb.v
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@ -132,25 +132,25 @@ module axi4_to_ahb(
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 391:12]
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 410:12]
reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:45]
wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 89:21 axi4_to_ahb.scala 201:11]
reg wrbuf_vld; // @[axi4_to_ahb.scala 359:51]
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 360:51]
reg wrbuf_vld; // @[axi4_to_ahb.scala 378:51]
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 379:51]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 178:27]
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 179:30]
wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hready_q; // @[axi4_to_ahb.scala 379:52]
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 380:52]
reg ahb_hready_q; // @[axi4_to_ahb.scala 398:52]
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 399:52]
wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 241:58]
wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 241:36]
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 392:17]
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 381:57]
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 411:17]
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 400:57]
wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 241:72]
wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 241:70]
wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hresp_q; // @[axi4_to_ahb.scala 382:52]
reg ahb_hresp_q; // @[axi4_to_ahb.scala 401:52]
wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 255:37]
wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
@ -165,12 +165,12 @@ module axi4_to_ahb(
wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
reg cmd_doneQ; // @[axi4_to_ahb.scala 377:52]
reg cmd_doneQ; // @[axi4_to_ahb.scala 396:52]
wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 297:34]
wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 297:50]
wire _T_443 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 196:32]
wire _GEN_1 = _T_443 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67]
@ -199,9 +199,9 @@ module axi4_to_ahb(
wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 252:70]
wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 252:55]
wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 252:53]
wire _T_287 = _T_283 & _T_137; // @[axi4_to_ahb.scala 298:66]
wire _T_288 = _T_287 & slave_ready; // @[axi4_to_ahb.scala 298:81]
wire _GEN_4 = _T_281 & _T_288; // @[Conditional.scala 39:67]
wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 298:36]
wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 298:51]
wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
@ -212,12 +212,12 @@ module axi4_to_ahb(
wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 254:97]
wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:67]
wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 254:26]
wire _T_289 = ~slave_ready; // @[axi4_to_ahb.scala 299:42]
wire _T_290 = ahb_hresp_q | _T_289; // @[axi4_to_ahb.scala 299:40]
wire [2:0] _T_296 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:119]
wire [2:0] _T_297 = _T_149 ? _T_296 : 3'h0; // @[axi4_to_ahb.scala 299:75]
wire [2:0] _T_298 = _T_290 ? 3'h5 : _T_297; // @[axi4_to_ahb.scala 299:26]
wire [2:0] _GEN_5 = _T_281 ? _T_298 : 3'h0; // @[Conditional.scala 39:67]
wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 299:42]
wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 299:40]
wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:99]
wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 299:65]
wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 299:26]
wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67]
wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67]
wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67]
wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67]
@ -231,56 +231,55 @@ module axi4_to_ahb(
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 183:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
wire _T_158 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 259:39]
wire _T_361 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 308:55]
wire _T_362 = buf_state_en & _T_361; // @[axi4_to_ahb.scala 308:39]
wire _GEN_14 = _T_281 ? _T_362 : _T_443; // @[Conditional.scala 39:67]
wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 309:55]
wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 309:39]
wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67]
wire _GEN_73 = _T_136 ? _T_158 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 188:32]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 390:12]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 409:12]
reg slvbuf_write; // @[Reg.scala 27:20]
wire [1:0] _T_599 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 343:23]
wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 362:23]
reg slvbuf_error; // @[Reg.scala 27:20]
wire [1:0] _T_601 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_602 = _T_601 & 2'h2; // @[axi4_to_ahb.scala 343:88]
wire [3:0] slave_opc = {_T_599,_T_602}; // @[Cat.scala 29:58]
wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 362:88]
wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58]
wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 189:49]
reg slvbuf_tag; // @[Reg.scala 27:20]
wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 192:65]
reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
wire [63:0] _T_606 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_607 = buf_state == 3'h5; // @[axi4_to_ahb.scala 344:91]
wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 363:91]
reg [63:0] buf_data; // @[el2_lib.scala 514:16]
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 393:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 383:57]
wire [63:0] _T_610 = _T_607 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 344:79]
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 412:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 402:57]
wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 363:79]
wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 199:56]
wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 199:91]
wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74]
wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38]
wire [3:0] _T_86 = wrbuf_byteen[7] ? 4'h7 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_87 = wrbuf_byteen[6] ? 4'h6 : _T_86; // @[Mux.scala 98:16]
wire [3:0] _T_88 = wrbuf_byteen[5] ? 4'h5 : _T_87; // @[Mux.scala 98:16]
wire [3:0] _T_89 = wrbuf_byteen[4] ? 4'h4 : _T_88; // @[Mux.scala 98:16]
wire [3:0] _T_90 = wrbuf_byteen[3] ? 4'h3 : _T_89; // @[Mux.scala 98:16]
wire [3:0] _T_91 = wrbuf_byteen[2] ? 4'h2 : _T_90; // @[Mux.scala 98:16]
wire [3:0] _T_92 = wrbuf_byteen[1] ? 4'h1 : _T_91; // @[Mux.scala 98:16]
wire [3:0] _T_93 = wrbuf_byteen[0] ? 4'h0 : _T_92; // @[Mux.scala 98:16]
wire [3:0] _T_86 = wrbuf_byteen[0] ? 4'h0 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_87 = wrbuf_byteen[1] ? 4'h1 : _T_86; // @[Mux.scala 98:16]
wire [3:0] _T_88 = wrbuf_byteen[2] ? 4'h2 : _T_87; // @[Mux.scala 98:16]
wire [3:0] _T_89 = wrbuf_byteen[3] ? 4'h3 : _T_88; // @[Mux.scala 98:16]
wire [3:0] _T_90 = wrbuf_byteen[4] ? 4'h4 : _T_89; // @[Mux.scala 98:16]
wire [3:0] _T_91 = wrbuf_byteen[5] ? 4'h5 : _T_90; // @[Mux.scala 98:16]
wire [3:0] _T_92 = wrbuf_byteen[6] ? 4'h6 : _T_91; // @[Mux.scala 98:16]
wire [3:0] _T_93 = wrbuf_byteen[7] ? 4'h7 : _T_92; // @[Mux.scala 98:16]
wire [3:0] _T_95 = buf_write_in ? _T_93 : {{1'd0}, master_addr[2:0]}; // @[axi4_to_ahb.scala 233:30]
wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51]
wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33]
wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 261:64]
wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 261:48]
wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 261:79]
wire _T_352 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 306:33]
wire _T_354 = _T_352 & _T_55; // @[axi4_to_ahb.scala 306:48]
wire _GEN_12 = _T_281 & _T_354; // @[Conditional.scala 39:67]
wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 307:33]
wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 307:48]
wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
@ -321,14 +320,14 @@ module axi4_to_ahb(
wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 175:48]
wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 175:62]
wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 175:48]
wire [3:0] _T_223 = buf_byteen[7] ? 4'h7 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_224 = _T_219 ? 4'h6 : _T_223; // @[Mux.scala 98:16]
wire [3:0] _T_225 = _T_216 ? 4'h5 : _T_224; // @[Mux.scala 98:16]
wire [3:0] _T_226 = _T_213 ? 4'h4 : _T_225; // @[Mux.scala 98:16]
wire [3:0] _T_227 = _T_210 ? 4'h3 : _T_226; // @[Mux.scala 98:16]
wire [3:0] _T_228 = _T_207 ? 4'h2 : _T_227; // @[Mux.scala 98:16]
wire [3:0] _T_229 = _T_204 ? 4'h1 : _T_228; // @[Mux.scala 98:16]
wire [3:0] _T_230 = _T_201 ? 4'h0 : _T_229; // @[Mux.scala 98:16]
wire [3:0] _T_223 = _T_201 ? 4'h0 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_224 = _T_204 ? 4'h1 : _T_223; // @[Mux.scala 98:16]
wire [3:0] _T_225 = _T_207 ? 4'h2 : _T_224; // @[Mux.scala 98:16]
wire [3:0] _T_226 = _T_210 ? 4'h3 : _T_225; // @[Mux.scala 98:16]
wire [3:0] _T_227 = _T_213 ? 4'h4 : _T_226; // @[Mux.scala 98:16]
wire [3:0] _T_228 = _T_216 ? 4'h5 : _T_227; // @[Mux.scala 98:16]
wire [3:0] _T_229 = _T_219 ? 4'h6 : _T_228; // @[Mux.scala 98:16]
wire [3:0] _T_230 = buf_byteen[7] ? 4'h7 : _T_229; // @[Mux.scala 98:16]
wire [3:0] _T_231 = trxn_done ? _T_230 : {{1'd0}, buf_cmd_byte_ptrQ}; // @[axi4_to_ahb.scala 291:30]
wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65]
reg buf_aligned; // @[Reg.scala 27:20]
@ -337,10 +336,10 @@ module axi4_to_ahb(
wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 292:163]
wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 292:79]
wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 292:29]
wire _T_349 = _T_232 | _T_273; // @[axi4_to_ahb.scala 305:123]
wire _T_350 = _T_109 & _T_349; // @[axi4_to_ahb.scala 305:87]
wire _T_351 = ahb_hresp_q | _T_350; // @[axi4_to_ahb.scala 305:32]
wire _GEN_11 = _T_281 & _T_351; // @[Conditional.scala 39:67]
wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 306:38]
wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 305:80]
wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 305:34]
wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67]
wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67]
wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67]
@ -351,16 +350,16 @@ module axi4_to_ahb(
wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 293:32]
wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 293:57]
wire _T_303 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62]
wire _T_304 = buf_state_en & _T_303; // @[axi4_to_ahb.scala 303:33]
wire _T_357 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 307:57]
wire [1:0] _T_359 = _T_357 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_360 = _T_359 & 2'h2; // @[axi4_to_ahb.scala 307:71]
wire _T_367 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 310:40]
wire [3:0] _T_442 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 311:30]
wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62]
wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 303:33]
wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 308:57]
wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 308:71]
wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 311:40]
wire [3:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 312:30]
wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_281 ? buf_state_en : _T_443; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_281 & _T_304; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67]
wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
@ -368,9 +367,9 @@ module axi4_to_ahb(
wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67]
wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58]
wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67]
wire [1:0] _GEN_13 = _T_281 ? _T_360 : 2'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_281 & _T_367; // @[Conditional.scala 39:67]
wire [3:0] _GEN_17 = _T_281 ? _T_442 : 4'h0; // @[Conditional.scala 39:67]
wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67]
wire [3:0] _GEN_17 = _T_281 ? _T_439 : 4'h0; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67]
wire [3:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67]
@ -406,93 +405,93 @@ module axi4_to_ahb(
wire [3:0] _GEN_105 = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_538 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 329:24]
wire _T_539 = _T_103 | _T_538; // @[axi4_to_ahb.scala 328:48]
wire _T_541 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 329:54]
wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 329:33]
wire _T_544 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 329:93]
wire _T_545 = _T_542 | _T_544; // @[axi4_to_ahb.scala 329:72]
wire _T_547 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 330:25]
wire _T_549 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 330:62]
wire _T_551 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 330:97]
wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 330:74]
wire _T_554 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 330:132]
wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 330:109]
wire _T_557 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 330:168]
wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 330:145]
wire _T_560 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 331:28]
wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 330:181]
wire _T_563 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 331:63]
wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 331:40]
wire _T_566 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 331:99]
wire _T_567 = _T_564 | _T_566; // @[axi4_to_ahb.scala 331:76]
wire _T_568 = _T_547 & _T_567; // @[axi4_to_ahb.scala 330:38]
wire buf_aligned_in = _T_545 | _T_568; // @[axi4_to_ahb.scala 329:106]
wire _T_447 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 323:60]
wire [2:0] _T_464 = _T_551 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_465 = 3'h2 & _T_464; // @[axi4_to_ahb.scala 167:15]
wire _T_471 = _T_563 | _T_549; // @[axi4_to_ahb.scala 168:56]
wire [2:0] _T_473 = _T_471 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_474 = 3'h4 & _T_473; // @[axi4_to_ahb.scala 168:15]
wire [2:0] _T_475 = _T_465 | _T_474; // @[axi4_to_ahb.scala 167:63]
wire [2:0] _T_479 = _T_557 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_480 = 3'h6 & _T_479; // @[axi4_to_ahb.scala 169:17]
wire [2:0] _T_481 = _T_475 | _T_480; // @[axi4_to_ahb.scala 168:96]
wire [2:0] _T_488 = _T_447 ? _T_481 : master_addr[2:0]; // @[axi4_to_ahb.scala 323:43]
wire _T_492 = buf_state == 3'h3; // @[axi4_to_ahb.scala 326:33]
wire _T_498 = buf_aligned_in & _T_547; // @[axi4_to_ahb.scala 327:38]
wire _T_501 = _T_498 & _T_51; // @[axi4_to_ahb.scala 327:71]
wire [1:0] _T_507 = _T_566 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_513 = _T_563 | _T_560; // @[axi4_to_ahb.scala 161:55]
wire [1:0] _T_515 = _T_513 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_516 = 2'h2 & _T_515; // @[axi4_to_ahb.scala 161:16]
wire [1:0] _T_517 = _T_507 | _T_516; // @[axi4_to_ahb.scala 160:62]
wire _T_522 = _T_557 | _T_554; // @[axi4_to_ahb.scala 162:60]
wire _T_525 = _T_522 | _T_551; // @[axi4_to_ahb.scala 162:89]
wire _T_528 = _T_525 | _T_549; // @[axi4_to_ahb.scala 162:123]
wire [1:0] _T_530 = _T_528 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_531 = 2'h1 & _T_530; // @[axi4_to_ahb.scala 162:21]
wire [1:0] _T_532 = _T_517 | _T_531; // @[axi4_to_ahb.scala 161:93]
wire [1:0] _T_534 = _T_501 ? _T_532 : master_size[1:0]; // @[axi4_to_ahb.scala 327:21]
wire [2:0] buf_cmd_byte_ptr = _GEN_105[2:0]; // @[axi4_to_ahb.scala 217:20 axi4_to_ahb.scala 233:24 axi4_to_ahb.scala 247:24 axi4_to_ahb.scala 262:24 axi4_to_ahb.scala 272:24 axi4_to_ahb.scala 291:24 axi4_to_ahb.scala 311:24]
wire [31:0] _T_573 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_576 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_580 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_534}; // @[axi4_to_ahb.scala 327:15]
wire [1:0] _T_582 = _T_580 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 334:77]
wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58]
wire [1:0] _T_585 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 348:24]
wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 347:48]
wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 348:54]
wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 348:33]
wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 348:93]
wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 348:72]
wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 349:25]
wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 349:62]
wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 349:97]
wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 349:74]
wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 349:132]
wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 349:109]
wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 349:168]
wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 349:145]
wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 350:28]
wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 349:181]
wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 350:63]
wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 350:40]
wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 350:99]
wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 350:76]
wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 349:38]
wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 348:106]
wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 342:60]
wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 167:15]
wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 168:56]
wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 168:15]
wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 167:63]
wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 169:17]
wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 168:96]
wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 342:43]
wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 345:33]
wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 346:38]
wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 346:71]
wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 161:55]
wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 161:16]
wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 160:62]
wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 162:60]
wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 162:89]
wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 162:123]
wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 162:21]
wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 161:93]
wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 346:21]
wire [2:0] buf_cmd_byte_ptr = _GEN_105[2:0]; // @[axi4_to_ahb.scala 217:20 axi4_to_ahb.scala 233:24 axi4_to_ahb.scala 247:24 axi4_to_ahb.scala 262:24 axi4_to_ahb.scala 272:24 axi4_to_ahb.scala 291:24 axi4_to_ahb.scala 312:24]
wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 346:15]
wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 353:77]
wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58]
wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
reg [1:0] buf_size; // @[Reg.scala 27:20]
wire [1:0] _T_587 = _T_585 & buf_size; // @[axi4_to_ahb.scala 334:134]
wire [2:0] _T_588 = {1'h0,_T_587}; // @[Cat.scala 29:58]
wire _T_591 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 338:33]
wire [1:0] _T_592 = {1'h1,_T_591}; // @[Cat.scala 29:58]
wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 353:134]
wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
wire _T_588 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 357:33]
wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20]
wire _T_614 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 347:40]
wire _T_615 = _T_614 & io_ahb_hready; // @[axi4_to_ahb.scala 347:52]
wire last_addr_en = _T_615 & io_ahb_hwrite; // @[axi4_to_ahb.scala 347:68]
wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 349:47]
wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 350:50]
wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 351:49]
wire _T_625 = ~wrbuf_en; // @[axi4_to_ahb.scala 352:33]
wire wrbuf_rst = wrbuf_cmd_sent & _T_625; // @[axi4_to_ahb.scala 352:31]
wire _T_627 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 354:35]
wire _T_628 = wrbuf_vld & _T_627; // @[axi4_to_ahb.scala 354:33]
wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 354:21]
wire _T_632 = wrbuf_data_vld & _T_627; // @[axi4_to_ahb.scala 355:37]
wire _T_633 = ~_T_632; // @[axi4_to_ahb.scala 355:20]
wire _T_636 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 356:21]
wire _T_639 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 359:55]
wire _T_640 = ~wrbuf_rst; // @[axi4_to_ahb.scala 359:91]
wire _T_644 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 360:55]
wire _T_611 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 366:40]
wire _T_612 = _T_611 & io_ahb_hready; // @[axi4_to_ahb.scala 366:52]
wire last_addr_en = _T_612 & io_ahb_hwrite; // @[axi4_to_ahb.scala 366:68]
wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 368:47]
wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 369:50]
wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 370:49]
wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 371:33]
wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 371:31]
wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 373:35]
wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 373:33]
wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 373:21]
wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 374:37]
wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 374:20]
wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 375:21]
wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 378:55]
wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 378:91]
wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 379:55]
reg buf_tag; // @[Reg.scala 27:20]
wire _T_694 = ~slave_valid_pre; // @[axi4_to_ahb.scala 377:92]
wire _T_707 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 385:43]
wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 385:58]
wire _T_711 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 386:54]
wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 386:74]
wire _T_714 = buf_state != 3'h0; // @[axi4_to_ahb.scala 387:50]
wire _T_715 = _T_714 | io_clk_override; // @[axi4_to_ahb.scala 387:60]
wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 396:92]
wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 404:43]
wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 404:58]
wire _T_708 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 405:54]
wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 405:74]
wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 406:50]
wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 406:60]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
@ -553,25 +552,25 @@ module axi4_to_ahb(
.io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode)
);
assign io_axi_awready = _T_629 & master_ready; // @[axi4_to_ahb.scala 354:18]
assign io_axi_wready = _T_633 & master_ready; // @[axi4_to_ahb.scala 355:17]
assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 373:18]
assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 374:17]
assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 188:17]
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 189:16]
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 190:14]
assign io_axi_arready = _T_636 & master_ready; // @[axi4_to_ahb.scala 356:18]
assign io_axi_arready = _T_633 & master_ready; // @[axi4_to_ahb.scala 375:18]
assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 192:17]
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 194:14]
assign io_axi_rdata = slvbuf_error ? _T_606 : _T_610; // @[axi4_to_ahb.scala 195:16]
assign io_axi_rdata = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 195:16]
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 193:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 357:16]
assign io_ahb_haddr = bypass_en ? _T_573 : _T_576; // @[axi4_to_ahb.scala 333:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 336:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 337:20]
assign io_ahb_hprot = {{2'd0}, _T_592}; // @[axi4_to_ahb.scala 338:16]
assign io_ahb_hsize = bypass_en ? _T_583 : _T_588; // @[axi4_to_ahb.scala 334:16]
assign io_ahb_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 205:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 339:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 340:17]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 376:16]
assign io_ahb_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 352:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 355:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 356:20]
assign io_ahb_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 357:16]
assign io_ahb_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 353:16]
assign io_ahb_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 205:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 308:21]
assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 358:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 359:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
@ -591,16 +590,16 @@ module axi4_to_ahb(
assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_6_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16]
assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[el2_lib.scala 485:16]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_8_io_en = io_bus_clk_en & _T_712; // @[el2_lib.scala 485:16]
assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[el2_lib.scala 485:16]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_9_io_en = io_bus_clk_en & _T_715; // @[el2_lib.scala 485:16]
assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[el2_lib.scala 485:16]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
@ -805,9 +804,9 @@ end // initial
end else if (_T_188) begin
buf_state <= 3'h4;
end else if (_T_281) begin
if (_T_290) begin
if (_T_288) begin
buf_state <= 3'h5;
end else if (_T_149) begin
end else if (master_valid) begin
if (_T_51) begin
buf_state <= 3'h2;
end else begin
@ -825,14 +824,14 @@ end // initial
if (reset) begin
wrbuf_vld <= 1'h0;
end else begin
wrbuf_vld <= _T_639 & _T_640;
wrbuf_vld <= _T_636 & _T_637;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_data_vld <= 1'h0;
end else begin
wrbuf_data_vld <= _T_644 & _T_640;
wrbuf_data_vld <= _T_641 & _T_637;
end
end
always @(posedge ahbm_clk or posedge reset) begin
@ -867,7 +866,7 @@ end // initial
if (reset) begin
cmd_doneQ <= 1'h0;
end else begin
cmd_doneQ <= _T_276 & _T_694;
cmd_doneQ <= _T_276 & _T_691;
end
end
always @(posedge bus_clk or posedge reset) begin
@ -950,7 +949,7 @@ end // initial
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
if (reset) begin
buf_data <= 64'h0;
end else if (_T_492) begin
end else if (_T_489) begin
buf_data <= ahb_hrdata_q;
end else begin
buf_data <= wrbuf_data;
@ -967,7 +966,7 @@ end // initial
if (reset) begin
buf_addr <= 32'h0;
end else begin
buf_addr <= {master_addr[31:3],_T_488};
buf_addr <= {master_addr[31:3],_T_485};
end
end
always @(posedge ahbm_clk or posedge reset) begin

39
src/main/scala/lib/axi4_to_ahb.scala
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@ -172,7 +172,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
}
def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U).reverse
MuxCase(8.U, temp)
}
wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
@ -249,7 +249,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
}
is(stream_rd) {
master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
master_ready := (ahb_hready_q & !ahb_hresp_q) & ~(master_valid & master_opc(2, 1) === "b01".U)
buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
buf_state_en := (ahb_hready_q | ahb_hresp_q)
@ -295,20 +295,39 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
is(data_wr) {
buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready
buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U(2.W)), cmd_wr, cmd_rd), idle))
master_ready := buf_state_en & !ahb_hresp_q & slave_ready
buf_nxtstate := Mux((ahb_hresp_q | !slave_ready),done ,Mux((master_valid & master_valid),Mux((master_opc(2,1) === 1.U).asBool(),cmd_wr,cmd_rd),idle))
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
buf_write_in := (master_opc(2, 1) === "b01".U)
buf_write_in := master_opc(2,1) === 1.U
buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd))
buf_data_wr_en := buf_wr_en
cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === "b0".U))))
bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being
io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U
cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1,0) =/= 0.U) &
((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)) === 0.U))))
bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr)
io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U
slave_valid_pre := buf_state_en & (buf_nxtstate =/= done)
trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W))
trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1,0) =/= 0.U)
buf_cmd_byte_ptr_en := trxn_done | bypass_en
buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
buf_cmd_byte_ptr := Mux(bypass_en,get_nxtbyte_ptr(0.U(3.W),buf_byteen_in(7,0),false.B),Mux(trxn_done,get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B),buf_cmd_byte_ptrQ))
//
// buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
// master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready
// buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U(2.W)), cmd_wr, cmd_rd), idle))
// slvbuf_error_in := ahb_hresp_q
// slvbuf_error_en := buf_state_en
// buf_write_in := (master_opc(2, 1) === "b01".U)
// buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd))
// buf_data_wr_en := buf_wr_en
// cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === "b0".U))))
// bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being
// io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U
// slave_valid_pre := buf_state_en & (buf_nxtstate =/= done)
// trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W))
// buf_cmd_byte_ptr_en := trxn_done | bypass_en
// buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
}
is(done) {

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target/scala-2.12/classes/lib/AXImain$.class
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