ifu added
This commit is contained in:
Laraib Khan
parent
33a4c11f1c
commit
7ae7c4687f
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@ -0,0 +1,393 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_premux_data",
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"sources":[
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"~ifu|ifu>io_iccm_rd_data",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_iccm_wr_size",
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"sources":[
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_sz",
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_iccm_rw_addr",
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"sources":[
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_addr",
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
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"~ifu|ifu>io_iccm_rd_data_ecc",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_exu_flush_path_final",
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"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
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"~ifu|ifu>io_dec_i0_decode_d",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
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"~ifu|ifu>io_ic_rd_data",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_sel_premux_data",
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"sources":[
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_iccm_wr_data",
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"sources":[
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_wdata",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
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"~ifu|ifu>io_iccm_rd_data_ecc",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu|ifu>io_exu_flush_path_final",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
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"~ifu|ifu>io_dec_i0_decode_d",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
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"~ifu|ifu>io_ic_rd_data",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ifu_dec_dec_aln_ifu_pmu_instr_aligned",
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"sources":[
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"~ifu|ifu>io_dec_i0_decode_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_debug_wr_data",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_debug_rd_en",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_debug_wr_en",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_debug_addr",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_iccm_ready",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
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"~ifu|ifu>io_iccm_rd_data_ecc",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu|ifu>io_exu_flush_path_final",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
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"~ifu|ifu>io_dec_i0_decode_d",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
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"~ifu|ifu>io_ic_rd_data",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_debug_tag_array",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err",
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"sources":[
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
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"~ifu|ifu>io_iccm_rd_data_ecc",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start",
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"sources":[
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"~ifu|ifu>io_ic_eccerr",
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"~ifu|ifu>io_ic_tag_perr",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_iccm_rden",
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"sources":[
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
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"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
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"~ifu|ifu>io_iccm_rd_data_ecc",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_exu_flush_path_final",
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"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
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"~ifu|ifu>io_ic_rd_data",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en",
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"~ifu|ifu>io_dec_i0_decode_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_debug_way",
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"sources":[
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_rw_addr",
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"sources":[
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"~ifu|ifu>io_exu_flush_path_final",
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
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"~ifu|ifu>io_ic_rd_hit"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_ic_rd_en",
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"sources":[
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"~ifu|ifu>io_exu_flush_final",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt",
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"~ifu|ifu>io_ic_rd_hit",
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"~ifu|ifu>io_exu_flush_path_final",
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"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_mrac_ff",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu|ifu>io_dec_tlu_flush_lower_wb",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
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"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
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"~ifu|ifu>io_ic_rd_data",
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"~ifu|ifu>io_ifu_r_bits_id",
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"~ifu|ifu>io_ifu_r_valid",
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"~ifu|ifu>io_ifu_bus_clk_en",
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"~ifu|ifu>io_dec_i0_decode_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu|ifu>io_iccm_wren",
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"sources":[
|
||||
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
|
||||
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
|
||||
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||
"~ifu|ifu>io_exu_flush_final",
|
||||
"~ifu|ifu>io_ic_rd_hit",
|
||||
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||
"~ifu|ifu>io_exu_flush_path_final",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu|ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||
"~ifu|ifu>io_dec_i0_decode_d",
|
||||
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||
"~ifu|ifu>io_ic_rd_data",
|
||||
"~ifu|ifu>io_ifu_r_bits_id",
|
||||
"~ifu|ifu>io_ifu_r_valid",
|
||||
"~ifu|ifu>io_ifu_bus_clk_en"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu|ifu>io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall",
|
||||
"sources":[
|
||||
"~ifu|ifu>io_exu_flush_final",
|
||||
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||
"~ifu|ifu>io_ic_rd_data",
|
||||
"~ifu|ifu>io_ifu_r_bits_id",
|
||||
"~ifu|ifu>io_ic_rd_hit",
|
||||
"~ifu|ifu>io_ifu_r_valid",
|
||||
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||
"~ifu|ifu>io_dec_i0_decode_d",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu|ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu|ifu>io_iccm_dma_sb_error",
|
||||
"sources":[
|
||||
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||
"~ifu|ifu>io_exu_flush_final",
|
||||
"~ifu|ifu>io_ic_rd_hit",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu|ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"ifu.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way1_p1_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way0_p1_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way1_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way0_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu|ifu_mem_ctl>ifc_region_acc_okay"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"ifu"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist0_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_way_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_index",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_btag",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_pkt_bits_misp",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
|
||||
"sources":[
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"ifu_bp_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way1_p1_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way0_p1_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way1_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way0_f"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"ifu_bp_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,499 +1,499 @@
|
|||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import dbg._
|
||||
import scala.collection._
|
||||
import lib._
|
||||
|
||||
class dma_ctrl extends Module with lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle {
|
||||
val free_clk = Input(Clock())
|
||||
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
|
||||
val clk_override = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
|
||||
val dma_dbg_rddata = Output(UInt(32.W))
|
||||
val dma_dbg_cmd_done = Output(Bool())
|
||||
val dma_dbg_cmd_fail = Output(Bool())
|
||||
val dbg_dma = new dec_dbg()
|
||||
val dbg_dma_io = new dbg_dma()
|
||||
val dec_dma = Flipped(new dec_dma())
|
||||
val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
|
||||
val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
|
||||
val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
|
||||
val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
|
||||
val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
|
||||
// AXI Write Channels
|
||||
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||
val lsu_dma = Flipped(new lsu_dma)
|
||||
val ifu_dma = Flipped(new ifu_dma)
|
||||
})
|
||||
|
||||
|
||||
val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH)
|
||||
|
||||
val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
|
||||
val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W)))
|
||||
|
||||
val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W)))
|
||||
|
||||
val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W)))
|
||||
|
||||
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
|
||||
|
||||
val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W)))
|
||||
|
||||
val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W)))
|
||||
|
||||
val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W)))
|
||||
|
||||
val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
|
||||
|
||||
val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
|
||||
val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
|
||||
|
||||
val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
|
||||
val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
|
||||
val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
|
||||
val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
|
||||
val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
|
||||
val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
|
||||
val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
|
||||
|
||||
val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val fifo_empty = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val dma_address_error = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val dma_alignment_error = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val num_fifo_vld = WireInit(UInt(4.W),0.U)
|
||||
|
||||
val dma_mem_req = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val dma_mem_addr_int = WireInit(UInt(32.W), 0.U)
|
||||
|
||||
val dma_mem_sz_int = WireInit(UInt(3.W), 0.U)
|
||||
|
||||
val dma_mem_byteen = WireInit(UInt(8.W), 0.U)
|
||||
|
||||
val dma_nack_count = WireInit(UInt(3.W), 0.U)
|
||||
|
||||
val dma_nack_count_csr = WireInit(UInt(3.W), 0.U)
|
||||
|
||||
val bus_rsp_valid = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val bus_cmd_valid = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val bus_cmd_sent = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val bus_cmd_write = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
|
||||
|
||||
val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
|
||||
|
||||
val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
|
||||
|
||||
val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
|
||||
|
||||
val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U)
|
||||
|
||||
val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U)
|
||||
|
||||
val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U)
|
||||
|
||||
val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val axi_mstr_priority = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val axi_mstr_sel = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val axi_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val wrbuf_vld = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val wrbuf_data_vld = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val rdbuf_vld = WireInit(UInt(1.W), 0.U)
|
||||
|
||||
val dma_free_clk = Wire(Clock())
|
||||
|
||||
val dma_bus_clk = Wire(Clock())
|
||||
|
||||
val dma_buffer_c1_clk = Wire(Clock())
|
||||
|
||||
val fifo_byteen_in = WireInit(UInt(8.W), 0.U)
|
||||
|
||||
//------------------------LOGIC STARTS HERE---------------------------------
|
||||
|
||||
|
||||
// DCCM Address check
|
||||
|
||||
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)
|
||||
|
||||
// PIC memory address check
|
||||
|
||||
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)
|
||||
|
||||
// ICCM Address check
|
||||
|
||||
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE) else (0.U,0.U)
|
||||
|
||||
// FIFO inputs
|
||||
|
||||
val fifo_addr_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
|
||||
|
||||
fifo_byteen_in := Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_dma.dbg_ib.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
|
||||
|
||||
val fifo_sz_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
|
||||
|
||||
val fifo_write_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_write, bus_cmd_write)
|
||||
|
||||
val fifo_posted_write_in = !io.dbg_dma.dbg_ib.dbg_cmd_valid & bus_cmd_posted_write
|
||||
|
||||
val fifo_dbg_in = io.dbg_dma.dbg_ib.dbg_cmd_valid
|
||||
|
||||
|
||||
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1) & io.dbg_dma.dbg_ib.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write)) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), Cat(0.U, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, Fill(2, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
|
||||
|
||||
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
|
||||
|
||||
fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
|
||||
|
||||
fifo_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_dbg := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
|
||||
|
||||
// Pointer logic
|
||||
|
||||
NxtWrPtr := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U)
|
||||
|
||||
NxtRdPtr := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U)
|
||||
|
||||
NxtRspPtr := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U)
|
||||
|
||||
val WrPtrEn = fifo_cmd_en.orR
|
||||
|
||||
val RdPtrEn = (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
|
||||
|
||||
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
|
||||
|
||||
WrPtr := withClock(dma_free_clk) {
|
||||
RegEnable(NxtWrPtr, 0.U, WrPtrEn)
|
||||
}
|
||||
|
||||
RdPtr := withClock(dma_free_clk) {
|
||||
RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool)
|
||||
}
|
||||
|
||||
RspPtr := withClock(dma_free_clk) {
|
||||
RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool)
|
||||
}
|
||||
|
||||
// Miscellaneous signal
|
||||
|
||||
val fifo_full = fifo_full_spec_bus;
|
||||
|
||||
val num_fifo_vld_tmp = WireInit(UInt(4.W),0.U)
|
||||
val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U)
|
||||
|
||||
num_fifo_vld_tmp := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent))
|
||||
|
||||
num_fifo_vld_tmp2 := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_)
|
||||
|
||||
num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2
|
||||
|
||||
val fifo_full_spec = (num_fifo_vld >= DMA_BUF_DEPTH.asUInt())
|
||||
|
||||
val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
|
||||
|
||||
// Error logic
|
||||
|
||||
dma_address_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt // request not for ICCM or DCCM
|
||||
dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error &
|
||||
(((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned
|
||||
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
|
||||
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
|
||||
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
|
||||
(dma_mem_addr_in_dccm & io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
|
||||
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
|
||||
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
|
||||
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
|
||||
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)),
|
||||
(dma_mem_addr_int(2,0) === 4.U) -> (dma_mem_byteen(7,4)),
|
||||
(dma_mem_addr_int(2,0) === 5.U) -> (dma_mem_byteen(7,5)),
|
||||
(dma_mem_addr_int(2,0) === 6.U) -> (dma_mem_byteen(7,6)),
|
||||
(dma_mem_addr_int(2,0) === 7.U) -> (dma_mem_byteen(7)))) =/= "hf".U)) | // Write byte enables not aligned for word store
|
||||
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
|
||||
|
||||
|
||||
//Dbg outputs
|
||||
|
||||
io.dbg_dma_io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
|
||||
io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
|
||||
io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
|
||||
io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
|
||||
|
||||
dma_dbg_cmd_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U)) // Only word accesses allowed
|
||||
|
||||
// Block the decode if fifo full
|
||||
|
||||
io.dec_dma.tlu_dma.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
|
||||
io.ifu_dma.dma_ifc.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
|
||||
io.dec_dma.tlu_dma.dma_iccm_stall_any := io.ifu_dma.dma_ifc.dma_iccm_stall_any
|
||||
io.dec_dma.dctl_dma.dma_dccm_stall_any := io.dec_dma.tlu_dma.dma_dccm_stall_any
|
||||
// Used to indicate ready to debug
|
||||
|
||||
fifo_empty := ~(fifo_valid.orR)
|
||||
|
||||
// Nack counter, stall the lsu pipe if 7 nacks
|
||||
|
||||
dma_nack_count_csr := io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty
|
||||
val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
|
||||
|
||||
dma_nack_count := withClock(dma_free_clk) {
|
||||
RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
|
||||
}
|
||||
|
||||
// Core outputs
|
||||
|
||||
dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.lsu_dma.dccm_ready
|
||||
io.ifu_dma.dma_mem_ctl.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
|
||||
io.lsu_dma.dma_mem_tag := RdPtr
|
||||
dma_mem_addr_int := fifo_addr(RdPtr)
|
||||
dma_mem_sz_int := fifo_sz(RdPtr)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_addr := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_sz := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
|
||||
dma_mem_byteen := fifo_byteen(RdPtr)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_write := fifo_write(RdPtr)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_wdata := fifo_data(RdPtr)
|
||||
|
||||
// PMU outputs
|
||||
|
||||
io.dec_dma.tlu_dma.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.dec_dma.tlu_dma.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.dec_dma.tlu_dma.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.dec_dma.tlu_dma.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
|
||||
// Inputs
|
||||
|
||||
fifo_full_spec_bus := withClock(dma_bus_clk) {
|
||||
RegNext(fifo_full_spec, 0.U)
|
||||
}
|
||||
|
||||
dbg_dma_bubble_bus := withClock(dma_bus_clk) {
|
||||
RegNext(io.dbg_dma_io.dbg_dma_bubble, 0.U)
|
||||
}
|
||||
|
||||
dma_dbg_cmd_done_q := withClock(io.free_clk) {
|
||||
RegNext(io.dma_dbg_cmd_done, 0.U)
|
||||
}
|
||||
|
||||
// Clock Gating logic
|
||||
|
||||
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.clk_override
|
||||
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
||||
|
||||
dma_buffer_c1_clk := rvclkhdr(clock,dma_buffer_c1_clken.asBool,io.scan_mode)
|
||||
dma_free_clk := rvclkhdr(clock,dma_free_clken.asBool(),io.scan_mode)
|
||||
dma_bus_clk := rvclkhdr(clock,io.dma_bus_clk_en,io.scan_mode)
|
||||
|
||||
|
||||
// Write channel buffer
|
||||
|
||||
val wrbuf_en = io.dma_axi.aw.valid & io.dma_axi.aw.ready
|
||||
val wrbuf_data_en = io.dma_axi.w.valid & io.dma_axi.w.ready
|
||||
val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
|
||||
val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
|
||||
val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
|
||||
|
||||
wrbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)}
|
||||
|
||||
wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
|
||||
|
||||
val wrbuf_tag = withClock(dma_bus_clk) {
|
||||
RegEnable(io.dma_axi.aw.bits.id, 0.U, wrbuf_en)
|
||||
}
|
||||
|
||||
val wrbuf_sz = withClock(dma_bus_clk) {
|
||||
RegEnable(io.dma_axi.aw.bits.size, 0.U, wrbuf_en)
|
||||
}
|
||||
|
||||
val wrbuf_addr = rvdffe(io.dma_axi.aw.bits.addr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
|
||||
val wrbuf_data = rvdffe(io.dma_axi.w.bits.data, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
|
||||
val wrbuf_byteen = withClock(dma_bus_clk) {
|
||||
RegEnable(io.dma_axi.w.bits.strb, 0.U, wrbuf_data_en)
|
||||
}
|
||||
|
||||
// Read channel buffer
|
||||
|
||||
val rdbuf_en = io.dma_axi.ar.valid & io.dma_axi.ar.ready
|
||||
val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
|
||||
val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
|
||||
|
||||
rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
|
||||
|
||||
val rdbuf_tag = withClock(dma_bus_clk) {
|
||||
RegEnable(io.dma_axi.ar.bits.id, 0.U, rdbuf_en)
|
||||
}
|
||||
|
||||
val rdbuf_sz = withClock(dma_bus_clk) {
|
||||
RegEnable(io.dma_axi.ar.bits.size, 0.U, rdbuf_en)
|
||||
}
|
||||
|
||||
val rdbuf_addr = rvdffe(io.dma_axi.ar.bits.addr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
|
||||
io.dma_axi.aw.ready := ~(wrbuf_vld & !wrbuf_cmd_sent)
|
||||
io.dma_axi.w.ready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
|
||||
io.dma_axi.ar.ready := ~(rdbuf_vld & !rdbuf_cmd_sent)
|
||||
|
||||
//Generate a single request from read/write channel
|
||||
|
||||
bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
|
||||
bus_cmd_sent := bus_cmd_valid & dma_fifo_ready.asUInt
|
||||
bus_cmd_write := axi_mstr_sel
|
||||
bus_cmd_posted_write := 0.U;
|
||||
bus_cmd_addr := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr)
|
||||
bus_cmd_sz := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz)
|
||||
bus_cmd_wdata := wrbuf_data
|
||||
bus_cmd_byteen := wrbuf_byteen
|
||||
bus_cmd_tag := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag)
|
||||
bus_cmd_mid := 0.U
|
||||
bus_cmd_prty := 0.U
|
||||
|
||||
// Sel=1 -> write has higher priority
|
||||
|
||||
axi_mstr_sel := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld)
|
||||
val axi_mstr_prty_in = ~axi_mstr_priority
|
||||
val axi_mstr_prty_en = bus_cmd_sent
|
||||
|
||||
axi_mstr_priority := withClock(dma_bus_clk) {
|
||||
RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool)
|
||||
}
|
||||
|
||||
val axi_rsp_valid = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
|
||||
val axi_rsp_rdata = fifo_data(RspPtr)
|
||||
val axi_rsp_write = fifo_write(RspPtr)
|
||||
val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U));
|
||||
|
||||
val axi_rsp_tag = fifo_tag(RspPtr)
|
||||
|
||||
// AXI response channel signals
|
||||
|
||||
io.dma_axi.b.valid := axi_rsp_valid & axi_rsp_write
|
||||
io.dma_axi.b.bits.resp := axi_rsp_error(1,0)
|
||||
io.dma_axi.b.bits.id := axi_rsp_tag
|
||||
|
||||
io.dma_axi.r.valid := axi_rsp_valid & !axi_rsp_write
|
||||
io.dma_axi.r.bits.resp := axi_rsp_error
|
||||
io.dma_axi.r.bits.data := axi_rsp_rdata(63,0)
|
||||
io.dma_axi.r.bits.last := 1.U
|
||||
io.dma_axi.r.bits.id := axi_rsp_tag
|
||||
|
||||
bus_posted_write_done := 0.U
|
||||
bus_rsp_valid := (io.dma_axi.b.valid | io.dma_axi.r.valid)
|
||||
bus_rsp_sent := ((io.dma_axi.b.valid & io.dma_axi.b.ready) | (io.dma_axi.r.valid & io.dma_axi.r.ready))
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_sz := io.lsu_dma.dma_lsc_ctl.dma_mem_sz
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import include._
|
||||
//import dbg._
|
||||
//import scala.collection._
|
||||
//import lib._
|
||||
//
|
||||
//class dma_ctrl extends Module with lib with RequireAsyncReset {
|
||||
// val io = IO(new Bundle {
|
||||
// val free_clk = Input(Clock())
|
||||
// val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
|
||||
// val clk_override = Input(Bool())
|
||||
// val scan_mode = Input(Bool())
|
||||
// val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
|
||||
// val dma_dbg_rddata = Output(UInt(32.W))
|
||||
// val dma_dbg_cmd_done = Output(Bool())
|
||||
// val dma_dbg_cmd_fail = Output(Bool())
|
||||
// val dbg_dma = new dec_dbg()
|
||||
// val dbg_dma_io = new dbg_dma()
|
||||
// val dec_dma = Flipped(new dec_dma())
|
||||
// val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
|
||||
// val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
|
||||
// val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
|
||||
// val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
|
||||
// val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
|
||||
// // AXI Write Channels
|
||||
// val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||
// val lsu_dma = Flipped(new lsu_dma)
|
||||
// val ifu_dma = Flipped(new ifu_dma)
|
||||
// })
|
||||
//
|
||||
//
|
||||
// val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH)
|
||||
//
|
||||
// val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
//
|
||||
// val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W)))
|
||||
//
|
||||
// val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W)))
|
||||
//
|
||||
// val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W)))
|
||||
//
|
||||
// val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
|
||||
//
|
||||
// val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W)))
|
||||
//
|
||||
// val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W)))
|
||||
//
|
||||
// val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W)))
|
||||
//
|
||||
// val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
|
||||
//
|
||||
// val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
//
|
||||
// val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
|
||||
//
|
||||
// val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
|
||||
//
|
||||
// val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val fifo_empty = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_address_error = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_alignment_error = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val num_fifo_vld = WireInit(UInt(4.W),0.U)
|
||||
//
|
||||
// val dma_mem_req = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_mem_addr_int = WireInit(UInt(32.W), 0.U)
|
||||
//
|
||||
// val dma_mem_sz_int = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val dma_mem_byteen = WireInit(UInt(8.W), 0.U)
|
||||
//
|
||||
// val dma_nack_count = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val dma_nack_count_csr = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val bus_rsp_valid = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_valid = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_sent = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_write = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U)
|
||||
//
|
||||
// val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U)
|
||||
//
|
||||
// val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val axi_mstr_priority = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val axi_mstr_sel = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val axi_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val wrbuf_vld = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val wrbuf_data_vld = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val rdbuf_vld = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_free_clk = Wire(Clock())
|
||||
//
|
||||
// val dma_bus_clk = Wire(Clock())
|
||||
//
|
||||
// val dma_buffer_c1_clk = Wire(Clock())
|
||||
//
|
||||
// val fifo_byteen_in = WireInit(UInt(8.W), 0.U)
|
||||
//
|
||||
// //------------------------LOGIC STARTS HERE---------------------------------
|
||||
//
|
||||
//
|
||||
// // DCCM Address check
|
||||
//
|
||||
// val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)
|
||||
//
|
||||
// // PIC memory address check
|
||||
//
|
||||
// val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)
|
||||
//
|
||||
// // ICCM Address check
|
||||
//
|
||||
// val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE) else (0.U,0.U)
|
||||
//
|
||||
// // FIFO inputs
|
||||
//
|
||||
// val fifo_addr_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
|
||||
//
|
||||
// fifo_byteen_in := Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_dma.dbg_ib.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
|
||||
//
|
||||
// val fifo_sz_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
|
||||
//
|
||||
// val fifo_write_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_write, bus_cmd_write)
|
||||
//
|
||||
// val fifo_posted_write_in = !io.dbg_dma.dbg_ib.dbg_cmd_valid & bus_cmd_posted_write
|
||||
//
|
||||
// val fifo_dbg_in = io.dbg_dma.dbg_ib.dbg_cmd_valid
|
||||
//
|
||||
//
|
||||
// fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1) & io.dbg_dma.dbg_ib.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write)) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), Cat(0.U, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, Fill(2, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
|
||||
//
|
||||
// fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
|
||||
//
|
||||
// fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
|
||||
//
|
||||
// fifo_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_dbg := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// // Pointer logic
|
||||
//
|
||||
// NxtWrPtr := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U)
|
||||
//
|
||||
// NxtRdPtr := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U)
|
||||
//
|
||||
// NxtRspPtr := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U)
|
||||
//
|
||||
// val WrPtrEn = fifo_cmd_en.orR
|
||||
//
|
||||
// val RdPtrEn = (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
|
||||
//
|
||||
// val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
|
||||
//
|
||||
// WrPtr := withClock(dma_free_clk) {
|
||||
// RegEnable(NxtWrPtr, 0.U, WrPtrEn)
|
||||
// }
|
||||
//
|
||||
// RdPtr := withClock(dma_free_clk) {
|
||||
// RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool)
|
||||
// }
|
||||
//
|
||||
// RspPtr := withClock(dma_free_clk) {
|
||||
// RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool)
|
||||
// }
|
||||
//
|
||||
// // Miscellaneous signal
|
||||
//
|
||||
// val fifo_full = fifo_full_spec_bus;
|
||||
//
|
||||
// val num_fifo_vld_tmp = WireInit(UInt(4.W),0.U)
|
||||
// val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U)
|
||||
//
|
||||
// num_fifo_vld_tmp := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent))
|
||||
//
|
||||
// num_fifo_vld_tmp2 := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_)
|
||||
//
|
||||
// num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2
|
||||
//
|
||||
// val fifo_full_spec = (num_fifo_vld >= DMA_BUF_DEPTH.asUInt())
|
||||
//
|
||||
// val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
|
||||
//
|
||||
// // Error logic
|
||||
//
|
||||
// dma_address_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt // request not for ICCM or DCCM
|
||||
// dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error &
|
||||
// (((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned
|
||||
// ((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
|
||||
// ((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
|
||||
// (dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
|
||||
// (dma_mem_addr_in_dccm & io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
|
||||
// (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
|
||||
// (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
|
||||
// (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
|
||||
// (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)),
|
||||
// (dma_mem_addr_int(2,0) === 4.U) -> (dma_mem_byteen(7,4)),
|
||||
// (dma_mem_addr_int(2,0) === 5.U) -> (dma_mem_byteen(7,5)),
|
||||
// (dma_mem_addr_int(2,0) === 6.U) -> (dma_mem_byteen(7,6)),
|
||||
// (dma_mem_addr_int(2,0) === 7.U) -> (dma_mem_byteen(7)))) =/= "hf".U)) | // Write byte enables not aligned for word store
|
||||
// (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
|
||||
//
|
||||
//
|
||||
// //Dbg outputs
|
||||
//
|
||||
// io.dbg_dma_io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
|
||||
// io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
|
||||
// io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
|
||||
// io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
|
||||
//
|
||||
// dma_dbg_cmd_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U)) // Only word accesses allowed
|
||||
//
|
||||
// // Block the decode if fifo full
|
||||
//
|
||||
// io.dec_dma.tlu_dma.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
|
||||
// io.ifu_dma.dma_ifc.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
|
||||
// io.dec_dma.tlu_dma.dma_iccm_stall_any := io.ifu_dma.dma_ifc.dma_iccm_stall_any
|
||||
// io.dec_dma.dctl_dma.dma_dccm_stall_any := io.dec_dma.tlu_dma.dma_dccm_stall_any
|
||||
// // Used to indicate ready to debug
|
||||
//
|
||||
// fifo_empty := ~(fifo_valid.orR)
|
||||
//
|
||||
// // Nack counter, stall the lsu pipe if 7 nacks
|
||||
//
|
||||
// dma_nack_count_csr := io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty
|
||||
// val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
|
||||
//
|
||||
// dma_nack_count := withClock(dma_free_clk) {
|
||||
// RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
|
||||
// }
|
||||
//
|
||||
// // Core outputs
|
||||
//
|
||||
// dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.lsu_dma.dccm_ready
|
||||
// io.ifu_dma.dma_mem_ctl.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
|
||||
// io.lsu_dma.dma_mem_tag := RdPtr
|
||||
// dma_mem_addr_int := fifo_addr(RdPtr)
|
||||
// dma_mem_sz_int := fifo_sz(RdPtr)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_addr := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_sz := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
|
||||
// dma_mem_byteen := fifo_byteen(RdPtr)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_write := fifo_write(RdPtr)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_wdata := fifo_data(RdPtr)
|
||||
//
|
||||
// // PMU outputs
|
||||
//
|
||||
// io.dec_dma.tlu_dma.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.dec_dma.tlu_dma.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.dec_dma.tlu_dma.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.dec_dma.tlu_dma.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
//
|
||||
// // Inputs
|
||||
//
|
||||
// fifo_full_spec_bus := withClock(dma_bus_clk) {
|
||||
// RegNext(fifo_full_spec, 0.U)
|
||||
// }
|
||||
//
|
||||
// dbg_dma_bubble_bus := withClock(dma_bus_clk) {
|
||||
// RegNext(io.dbg_dma_io.dbg_dma_bubble, 0.U)
|
||||
// }
|
||||
//
|
||||
// dma_dbg_cmd_done_q := withClock(io.free_clk) {
|
||||
// RegNext(io.dma_dbg_cmd_done, 0.U)
|
||||
// }
|
||||
//
|
||||
// // Clock Gating logic
|
||||
//
|
||||
// val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.clk_override
|
||||
// val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
||||
//
|
||||
// dma_buffer_c1_clk := rvclkhdr(clock,dma_buffer_c1_clken.asBool,io.scan_mode)
|
||||
// dma_free_clk := rvclkhdr(clock,dma_free_clken.asBool(),io.scan_mode)
|
||||
// dma_bus_clk := rvclkhdr(clock,io.dma_bus_clk_en,io.scan_mode)
|
||||
//
|
||||
//
|
||||
// // Write channel buffer
|
||||
//
|
||||
// val wrbuf_en = io.dma_axi.aw.valid & io.dma_axi.aw.ready
|
||||
// val wrbuf_data_en = io.dma_axi.w.valid & io.dma_axi.w.ready
|
||||
// val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
|
||||
// val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
|
||||
// val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
|
||||
//
|
||||
// wrbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)}
|
||||
//
|
||||
// wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
|
||||
//
|
||||
// val wrbuf_tag = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.aw.bits.id, 0.U, wrbuf_en)
|
||||
// }
|
||||
//
|
||||
// val wrbuf_sz = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.aw.bits.size, 0.U, wrbuf_en)
|
||||
// }
|
||||
//
|
||||
// val wrbuf_addr = rvdffe(io.dma_axi.aw.bits.addr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
//
|
||||
// val wrbuf_data = rvdffe(io.dma_axi.w.bits.data, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
//
|
||||
// val wrbuf_byteen = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.w.bits.strb, 0.U, wrbuf_data_en)
|
||||
// }
|
||||
//
|
||||
// // Read channel buffer
|
||||
//
|
||||
// val rdbuf_en = io.dma_axi.ar.valid & io.dma_axi.ar.ready
|
||||
// val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
|
||||
// val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
|
||||
//
|
||||
// rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
|
||||
//
|
||||
// val rdbuf_tag = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.ar.bits.id, 0.U, rdbuf_en)
|
||||
// }
|
||||
//
|
||||
// val rdbuf_sz = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.ar.bits.size, 0.U, rdbuf_en)
|
||||
// }
|
||||
//
|
||||
// val rdbuf_addr = rvdffe(io.dma_axi.ar.bits.addr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
//
|
||||
// io.dma_axi.aw.ready := ~(wrbuf_vld & !wrbuf_cmd_sent)
|
||||
// io.dma_axi.w.ready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
|
||||
// io.dma_axi.ar.ready := ~(rdbuf_vld & !rdbuf_cmd_sent)
|
||||
//
|
||||
// //Generate a single request from read/write channel
|
||||
//
|
||||
// bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
|
||||
// bus_cmd_sent := bus_cmd_valid & dma_fifo_ready.asUInt
|
||||
// bus_cmd_write := axi_mstr_sel
|
||||
// bus_cmd_posted_write := 0.U;
|
||||
// bus_cmd_addr := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr)
|
||||
// bus_cmd_sz := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz)
|
||||
// bus_cmd_wdata := wrbuf_data
|
||||
// bus_cmd_byteen := wrbuf_byteen
|
||||
// bus_cmd_tag := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag)
|
||||
// bus_cmd_mid := 0.U
|
||||
// bus_cmd_prty := 0.U
|
||||
//
|
||||
// // Sel=1 -> write has higher priority
|
||||
//
|
||||
// axi_mstr_sel := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld)
|
||||
// val axi_mstr_prty_in = ~axi_mstr_priority
|
||||
// val axi_mstr_prty_en = bus_cmd_sent
|
||||
//
|
||||
// axi_mstr_priority := withClock(dma_bus_clk) {
|
||||
// RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool)
|
||||
// }
|
||||
//
|
||||
// val axi_rsp_valid = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
|
||||
// val axi_rsp_rdata = fifo_data(RspPtr)
|
||||
// val axi_rsp_write = fifo_write(RspPtr)
|
||||
// val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U));
|
||||
//
|
||||
// val axi_rsp_tag = fifo_tag(RspPtr)
|
||||
//
|
||||
// // AXI response channel signals
|
||||
//
|
||||
// io.dma_axi.b.valid := axi_rsp_valid & axi_rsp_write
|
||||
// io.dma_axi.b.bits.resp := axi_rsp_error(1,0)
|
||||
// io.dma_axi.b.bits.id := axi_rsp_tag
|
||||
//
|
||||
// io.dma_axi.r.valid := axi_rsp_valid & !axi_rsp_write
|
||||
// io.dma_axi.r.bits.resp := axi_rsp_error
|
||||
// io.dma_axi.r.bits.data := axi_rsp_rdata(63,0)
|
||||
// io.dma_axi.r.bits.last := 1.U
|
||||
// io.dma_axi.r.bits.id := axi_rsp_tag
|
||||
//
|
||||
// bus_posted_write_done := 0.U
|
||||
// bus_rsp_valid := (io.dma_axi.b.valid | io.dma_axi.r.valid)
|
||||
// bus_rsp_sent := ((io.dma_axi.b.valid & io.dma_axi.b.ready) | (io.dma_axi.r.valid & io.dma_axi.r.ready))
|
||||
// io.lsu_dma.dma_dccm_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||
// io.lsu_dma.dma_dccm_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_sz := io.lsu_dma.dma_lsc_ctl.dma_mem_sz
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||
//}
|
||||
//
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,121 +1,148 @@
|
|||
//package ifu
|
||||
//import chisel3._
|
||||
//import chisel3.internal.naming.chiselName
|
||||
//import chisel3.util._
|
||||
//import exu._
|
||||
//import lib._
|
||||
//import include._
|
||||
//
|
||||
//@chiselName
|
||||
//class ifu extends Module with lib with RequireAsyncReset {
|
||||
// val io = IO(new Bundle{
|
||||
// val exu_flush_final = Input(Bool())
|
||||
// val exu_flush_path_final = Input(UInt(31.W))
|
||||
// val free_clk = Input(Clock())
|
||||
// val active_clk = Input(Clock())
|
||||
// val ifu_dec = new ifu_dec() // IFU and DEC interconnects
|
||||
// val exu_ifu = new exu_ifu() // IFU and EXU interconnects
|
||||
// val iccm = new iccm_mem() // ICCM memory signals
|
||||
// val ic = new ic_mem() // I$ memory signals
|
||||
// val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel
|
||||
// val ifu_bus_clk_en = Input(Bool())
|
||||
// val ifu_dma = new ifu_dma() // DMA signals
|
||||
// // ICCM DMA signals
|
||||
// val iccm_dma_ecc_error = Output(Bool())
|
||||
// val iccm_dma_rvalid = Output(Bool())
|
||||
// val iccm_dma_rdata = Output(UInt(64.W))
|
||||
// val iccm_dma_rtag = Output(UInt(3.W))
|
||||
// val iccm_ready = Output(Bool())
|
||||
// // Performance counter
|
||||
// val iccm_dma_sb_error = Output(Bool())
|
||||
// val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
// val scan_mode = Input(Bool())
|
||||
// })
|
||||
// val mem_ctl = Module(new ifu_mem_ctl)
|
||||
// val bp_ctl = Module(new ifu_bp_ctl)
|
||||
// val aln_ctl = Module(new ifu_aln_ctl)
|
||||
// val ifc_ctl = Module(new ifu_ifc_ctl)
|
||||
//
|
||||
// // IFC wiring Inputs
|
||||
// ifc_ctl.io.active_clk := io.active_clk
|
||||
// ifc_ctl.io.free_clk := io.free_clk
|
||||
// ifc_ctl.io.scan_mode := io.scan_mode
|
||||
// ifc_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
// ifc_ctl.io.ifu_fb_consume1 := aln_ctl.io.ifu_fb_consume1
|
||||
// ifc_ctl.io.ifu_fb_consume2 := aln_ctl.io.ifu_fb_consume2
|
||||
// ifc_ctl.io.dec_ifc <> io.ifu_dec.dec_ifc
|
||||
// ifc_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// ifc_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
// ifc_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
// ifc_ctl.io.ic_dma_active := mem_ctl.io.ic_dma_active
|
||||
// ifc_ctl.io.ic_write_stall := mem_ctl.io.ic_write_stall
|
||||
// ifc_ctl.io.dma_ifc <> io.ifu_dma.dma_ifc
|
||||
// ifc_ctl.io.ifu_ic_mb_empty := mem_ctl.io.ifu_ic_mb_empty
|
||||
// ifc_ctl.io.exu_flush_path_final := io.exu_flush_path_final
|
||||
//
|
||||
// // ALN wiring Inputs
|
||||
// aln_ctl.io.scan_mode := io.scan_mode
|
||||
// aln_ctl.io.active_clk := io.active_clk
|
||||
// aln_ctl.io.ifu_async_error_start := mem_ctl.io.ifu_async_error_start
|
||||
// aln_ctl.io.iccm_rd_ecc_double_err := mem_ctl.io.iccm_rd_ecc_double_err
|
||||
// aln_ctl.io.ic_access_fault_f := mem_ctl.io.ic_access_fault_f
|
||||
// aln_ctl.io.ic_access_fault_type_f := mem_ctl.io.ic_access_fault_type_f
|
||||
// aln_ctl.io.ifu_bp_fghr_f := bp_ctl.io.ifu_bp_fghr_f
|
||||
// aln_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
// aln_ctl.io.ifu_bp_poffset_f := bp_ctl.io.ifu_bp_poffset_f
|
||||
// aln_ctl.io.ifu_bp_hist0_f := bp_ctl.io.ifu_bp_hist0_f
|
||||
// aln_ctl.io.ifu_bp_hist1_f := bp_ctl.io.ifu_bp_hist1_f
|
||||
// aln_ctl.io.ifu_bp_pc4_f := bp_ctl.io.ifu_bp_pc4_f
|
||||
// aln_ctl.io.ifu_bp_way_f := bp_ctl.io.ifu_bp_way_f
|
||||
// aln_ctl.io.ifu_bp_valid_f := bp_ctl.io.ifu_bp_valid_f
|
||||
// aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
|
||||
// aln_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
|
||||
// aln_ctl.io.ifu_fetch_data_f := mem_ctl.io.ic_data_f
|
||||
// aln_ctl.io.ifu_fetch_val := mem_ctl.io.ifu_fetch_val
|
||||
// aln_ctl.io.ifu_fetch_pc := ifc_ctl.io.ifc_fetch_addr_f
|
||||
//
|
||||
// // BP wiring Inputs
|
||||
// bp_ctl.io.scan_mode := io.scan_mode
|
||||
// bp_ctl.io.active_clk := io.active_clk
|
||||
// bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
// bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
|
||||
// bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f
|
||||
// bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp
|
||||
// bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
|
||||
// bp_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
//
|
||||
// // mem-ctl Inputs
|
||||
// mem_ctl.io.free_clk := io.free_clk
|
||||
// mem_ctl.io.active_clk := io.active_clk
|
||||
// mem_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// mem_ctl.io.dec_mem_ctrl <> io.ifu_dec.dec_mem_ctrl
|
||||
// mem_ctl.io.ifc_fetch_addr_bf := ifc_ctl.io.ifc_fetch_addr_bf
|
||||
// mem_ctl.io.ifc_fetch_uncacheable_bf := ifc_ctl.io.ifc_fetch_uncacheable_bf
|
||||
// mem_ctl.io.ifc_fetch_req_bf := ifc_ctl.io.ifc_fetch_req_bf
|
||||
// mem_ctl.io.ifc_fetch_req_bf_raw := ifc_ctl.io.ifc_fetch_req_bf_raw
|
||||
// mem_ctl.io.ifc_iccm_access_bf := ifc_ctl.io.ifc_iccm_access_bf
|
||||
// mem_ctl.io.ifc_region_acc_fault_bf := ifc_ctl.io.ifc_region_acc_fault_bf
|
||||
// mem_ctl.io.ifc_dma_access_ok := ifc_ctl.io.ifc_dma_access_ok
|
||||
// mem_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
// mem_ctl.io.ifu_bp_inst_mask_f := bp_ctl.io.ifu_bp_inst_mask_f
|
||||
// mem_ctl.io.ifu_axi <> io.ifu
|
||||
// mem_ctl.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
// mem_ctl.io.dma_mem_ctl <> io.ifu_dma.dma_mem_ctl
|
||||
// mem_ctl.io.ic <> io.ic
|
||||
// mem_ctl.io.iccm <> io.iccm
|
||||
// mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f
|
||||
// mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
// mem_ctl.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// // DMA to the ICCM
|
||||
// io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error
|
||||
// io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid
|
||||
// io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
|
||||
// io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
|
||||
// io.iccm_ready := mem_ctl.io.iccm_ready
|
||||
// io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
||||
//}
|
||||
//
|
||||
//
|
||||
package ifu
|
||||
import chisel3._
|
||||
import chisel3.internal.naming.chiselName
|
||||
import chisel3.util._
|
||||
import exu._
|
||||
import lib._
|
||||
import include._
|
||||
|
||||
@chiselName
|
||||
class ifu extends Module with lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
|
||||
val dec_i0_decode_d = Input(Bool()) // Dec
|
||||
val dec_fa_error_index = Input(UInt(log2Ceil(BTB_SIZE).W))// Fully associative btb error index
|
||||
|
||||
|
||||
val exu_flush_final = Input(Bool())
|
||||
val exu_flush_path_final = Input(UInt(31.W))
|
||||
val free_l2clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
val ifu_dec = new ifu_dec() // IFU and DEC interconnects
|
||||
val exu_ifu = new exu_ifu() // IFU and EXU interconnects
|
||||
val iccm = new iccm_mem() // ICCM memory signals
|
||||
val ic = new ic_mem() // I$ memory signals
|
||||
val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel
|
||||
val ifu_bus_clk_en = Input(Bool())
|
||||
val ifu_dma = new ifu_dma() // DMA signals
|
||||
// ICCM DMA signals
|
||||
val iccm_dma_ecc_error = Output(Bool())
|
||||
val iccm_dma_rvalid = Output(Bool())
|
||||
val iccm_dma_rdata = Output(UInt(64.W))
|
||||
val iccm_dma_rtag = Output(UInt(3.W))
|
||||
val iccm_ready = Output(Bool())
|
||||
// Performance counter
|
||||
val iccm_dma_sb_error = Output(Bool())
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
val mem_ctl = Module(new ifu_mem_ctl)
|
||||
val bp_ctl = Module(new ifu_bp_ctl)
|
||||
val aln_ctl = Module(new ifu_aln_ctl)
|
||||
val ifc_ctl = Module(new ifu_ifc_ctl)
|
||||
|
||||
// IFC wiring Inputs
|
||||
//ifc_ctl.io.active_clk := io.active_clk
|
||||
ifc_ctl.io.free_l2clk := io.free_l2clk
|
||||
ifc_ctl.io.scan_mode := io.scan_mode
|
||||
ifc_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
ifc_ctl.io.ifu_fb_consume1 := aln_ctl.io.ifu_fb_consume1
|
||||
ifc_ctl.io.ifu_fb_consume2 := aln_ctl.io.ifu_fb_consume2
|
||||
ifc_ctl.io.dec_ifc <> io.ifu_dec.dec_ifc
|
||||
ifc_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
ifc_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
ifc_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
ifc_ctl.io.ic_dma_active := mem_ctl.io.ic_dma_active
|
||||
ifc_ctl.io.ic_write_stall := mem_ctl.io.ic_write_stall
|
||||
ifc_ctl.io.dma_ifc <> io.ifu_dma.dma_ifc
|
||||
ifc_ctl.io.ifu_ic_mb_empty := mem_ctl.io.ifu_ic_mb_empty
|
||||
ifc_ctl.io.exu_flush_path_final := io.exu_flush_path_final
|
||||
|
||||
// ALN wiring Inputs
|
||||
aln_ctl.io.scan_mode := io.scan_mode
|
||||
aln_ctl.io.active_clk := io.active_clk
|
||||
aln_ctl.io.ifu_async_error_start := mem_ctl.io.ifu_async_error_start
|
||||
aln_ctl.io.iccm_rd_ecc_double_err := mem_ctl.io.iccm_rd_ecc_double_err
|
||||
aln_ctl.io.ic_access_fault_f := mem_ctl.io.ic_access_fault_f
|
||||
aln_ctl.io.ic_access_fault_type_f := mem_ctl.io.ic_access_fault_type_f
|
||||
aln_ctl.io.ifu_bp_fghr_f := bp_ctl.io.ifu_bp_fghr_f
|
||||
aln_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
aln_ctl.io.ifu_bp_poffset_f := bp_ctl.io.ifu_bp_poffset_f
|
||||
aln_ctl.io.ifu_bp_hist0_f := bp_ctl.io.ifu_bp_hist0_f
|
||||
aln_ctl.io.ifu_bp_hist1_f := bp_ctl.io.ifu_bp_hist1_f
|
||||
aln_ctl.io.ifu_bp_pc4_f := bp_ctl.io.ifu_bp_pc4_f
|
||||
aln_ctl.io.ifu_bp_way_f := bp_ctl.io.ifu_bp_way_f
|
||||
aln_ctl.io.ifu_bp_valid_f := bp_ctl.io.ifu_bp_valid_f
|
||||
aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
|
||||
aln_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
|
||||
// io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst := aln_ctl.io.ifu_i0_cinst
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf := aln_ctl.io.ifu_i0_icaf
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type := aln_ctl.io.ifu_i0_icaf_type
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second := aln_ctl.io.ifu_i0_icaf_second
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc := aln_ctl.io.ifu_i0_dbecc
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index := aln_ctl.io.ifu_i0_bp_index
|
||||
io.ifu_i0_fa_index := aln_ctl.io.ifu_i0_fa_index
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr := aln_ctl.io.ifu_i0_bp_fghr
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag := aln_ctl.io.ifu_i0_bp_btag
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid := aln_ctl.io.ifu_i0_valid
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr := aln_ctl.io.ifu_i0_instr
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc := aln_ctl.io.ifu_i0_pc
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 := aln_ctl.io.ifu_i0_pc4
|
||||
// io.ifu_dec.dec_aln.ifu_pmu_instr_aligned := aln_ctl.io.ifu_pmu_instr_aligned
|
||||
// aln_ctl.io.i0_brp <> io.ifu_dec.dec_aln.aln_ib.i0_brp
|
||||
aln_ctl.io.dec_i0_decode_d := io.dec_i0_decode_d
|
||||
aln_ctl.io.ifu_bp_fa_index_f := bp_ctl.io.ifu_bp_fa_index_f
|
||||
|
||||
aln_ctl.io.ifu_fetch_data_f := mem_ctl.io.ic_data_f
|
||||
aln_ctl.io.ifu_fetch_val := mem_ctl.io.ifu_fetch_val
|
||||
aln_ctl.io.ifu_fetch_pc := ifc_ctl.io.ifc_fetch_addr_f
|
||||
|
||||
// BP wiring Inputs
|
||||
bp_ctl.io.scan_mode := io.scan_mode
|
||||
bp_ctl.io.active_clk := io.active_clk
|
||||
bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
|
||||
bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f
|
||||
bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp
|
||||
bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
|
||||
bp_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
bp_ctl.io.dec_fa_error_index := io.dec_fa_error_index
|
||||
|
||||
// mem-ctl Inputs
|
||||
mem_ctl.io.free_l2clk := io.free_l2clk
|
||||
mem_ctl.io.active_clk := io.active_clk
|
||||
mem_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
mem_ctl.io.dec_mem_ctrl <> io.ifu_dec.dec_mem_ctrl
|
||||
mem_ctl.io.ifc_fetch_addr_bf := ifc_ctl.io.ifc_fetch_addr_bf
|
||||
mem_ctl.io.ifc_fetch_uncacheable_bf := ifc_ctl.io.ifc_fetch_uncacheable_bf
|
||||
mem_ctl.io.ifc_fetch_req_bf := ifc_ctl.io.ifc_fetch_req_bf
|
||||
mem_ctl.io.ifc_fetch_req_bf_raw := ifc_ctl.io.ifc_fetch_req_bf_raw
|
||||
mem_ctl.io.ifc_iccm_access_bf := ifc_ctl.io.ifc_iccm_access_bf
|
||||
mem_ctl.io.ifc_region_acc_fault_bf := ifc_ctl.io.ifc_region_acc_fault_bf
|
||||
mem_ctl.io.ifc_dma_access_ok := ifc_ctl.io.ifc_dma_access_ok
|
||||
mem_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
mem_ctl.io.ifu_bp_inst_mask_f := bp_ctl.io.ifu_bp_inst_mask_f
|
||||
mem_ctl.io.ifu_axi <> io.ifu
|
||||
mem_ctl.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
mem_ctl.io.dma_mem_ctl <> io.ifu_dma.dma_mem_ctl
|
||||
mem_ctl.io.ic <> io.ic
|
||||
mem_ctl.io.iccm <> io.iccm
|
||||
mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f
|
||||
mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
mem_ctl.io.scan_mode := io.scan_mode
|
||||
|
||||
// DMA to the ICCM
|
||||
io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error
|
||||
io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid
|
||||
io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
|
||||
io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
|
||||
io.iccm_ready := mem_ctl.io.iccm_ready
|
||||
io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
||||
}
|
||||
|
||||
|
||||
object ifu_top extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
|
||||
}
|
||||
|
|
@ -9,9 +9,27 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
val scan_mode = Input(Bool())
|
||||
val active_clk = Input(Clock())
|
||||
val ifu_async_error_start = Input(Bool()) // Error coming from mem-ctl
|
||||
val iccm_rd_ecc_double_err = Input(Bool()) // ICCM double error coming from mem-ctl
|
||||
val ic_access_fault_f = Input(Bool()) // Access fault in I$
|
||||
val iccm_rd_ecc_double_err = Input(UInt(2.W)) // ICCM double error coming from mem-ctl
|
||||
val ic_access_fault_f = Input(UInt(2.W)) // Access fault in I$
|
||||
val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
|
||||
val dec_i0_decode_d = Input(Bool())
|
||||
val dec_aln = new dec_aln()
|
||||
// val ifu_i0_valid = Output(Bool())
|
||||
// val ifu_i0_icaf = Output(Bool())
|
||||
// val ifu_i0_icaf_type = Output(UInt(2.W))
|
||||
// val ifu_i0_icaf_second = Output(Bool())
|
||||
// val ifu_i0_dbecc = Output(Bool())
|
||||
// val ifu_i0_instr = Output(UInt(32.W))
|
||||
// val ifu_i0_pc = Output(UInt(31.W))
|
||||
// val ifu_i0_pc4 = Output(Bool())
|
||||
val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W)))
|
||||
// val i0_brp = Output(Valid(new br_pkt_t()))
|
||||
// val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
|
||||
// val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
|
||||
// val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
|
||||
val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
|
||||
// val ifu_pmu_instr_aligned = Output(Bool())
|
||||
// val ifu_i0_cinst = Output(UInt(16.W))
|
||||
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
|
||||
val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
|
||||
val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch
|
||||
|
|
@ -22,8 +40,6 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
val ifu_bp_valid_f = Input(UInt(2.W)) // Valid Branch prediction
|
||||
val ifu_bp_ret_f = Input(UInt(2.W)) // BP ret
|
||||
val exu_flush_final = Input(Bool()) // Miss prediction
|
||||
val dec_i0_decode_d = Input(Bool())
|
||||
val dec_aln = new dec_aln() // Data going to the dec from the ALN
|
||||
val ifu_fetch_data_f = Input(UInt(32.W)) // PC of the current instruction in the FP
|
||||
val ifu_fetch_val = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
|
||||
val ifu_fetch_pc = Input(UInt(31.W)) // Current PC
|
||||
|
|
@ -32,10 +48,11 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
val ifu_fb_consume2 = Output(Bool()) // FP used 2
|
||||
|
||||
})
|
||||
val MHI = 46+BHT_GHR_SIZE // 54
|
||||
val MSIZE = 47+BHT_GHR_SIZE // 55
|
||||
val BRDATA_SIZE = 12
|
||||
val error_stall_in = WireInit(Bool(),0.U)
|
||||
val MHI = 1 + (BTB_ENABLE * (43+BHT_GHR_SIZE))
|
||||
val MSIZE = 2 + (BTB_ENABLE * (43+BHT_GHR_SIZE))
|
||||
val BRDATA_SIZE = if(BTB_ENABLE) 16+log2Ceil(BTB_SIZE) * 2 * BTB_FULLYA else 2
|
||||
val BRDATA_WIDTH = if(BTB_ENABLE) 8+log2Ceil(BTB_SIZE)*BTB_FULLYA else 1
|
||||
|
||||
val alignval = WireInit(UInt(2.W), 0.U)
|
||||
val q0final = WireInit(UInt(32.W), 0.U)
|
||||
val q1final = WireInit(UInt(16.W), 0.U)
|
||||
|
|
@ -59,8 +76,8 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
val shift_f2_f0 = WireInit(Bool(), init = 0.U)
|
||||
val shift_f1_f0 = WireInit(Bool(), init = 0.U)
|
||||
|
||||
val f0icaf = WireInit(Bool(), init = 0.U)
|
||||
val f1icaf = WireInit(Bool(), init = 0.U)
|
||||
val f0icaf = WireInit(UInt(2.W), init = 0.U)
|
||||
val f1icaf = WireInit(UInt(2.W), init = 0.U)
|
||||
|
||||
val sf0val = WireInit(UInt(2.W), 0.U)
|
||||
val sf1val = WireInit(UInt(2.W), 0.U)
|
||||
|
|
@ -69,9 +86,9 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
val misc1 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
val misc2 = WireInit(UInt((MHI+1).W), 0.U)
|
||||
|
||||
val brdata1 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata0 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata2 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata1 = WireInit(UInt(BRDATA_SIZE.W), init = 0.U)
|
||||
val brdata0 = WireInit(UInt(BRDATA_SIZE.W), init = 0.U)
|
||||
val brdata2 = WireInit(UInt(BRDATA_SIZE.W), init = 0.U)
|
||||
|
||||
val q0 = WireInit(UInt(32.W), init = 0.U)
|
||||
val q1 = WireInit(UInt(32.W), init = 0.U)
|
||||
|
|
@ -95,52 +112,55 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
val first4B = WireInit(Bool(), 0.U)
|
||||
val shift_2B = WireInit(Bool(), 0.U)
|
||||
val f0_shift_2B = WireInit(Bool(), 0.U)
|
||||
|
||||
implicit val clk = clock
|
||||
implicit val rst = reset.asAsyncReset()
|
||||
implicit val scan_mode = io.scan_mode
|
||||
// Stall if there is an error in the instrucion
|
||||
error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
|
||||
|
||||
// Flop the stall until flush
|
||||
error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
|
||||
// Write Ptr of the FP
|
||||
val error_stall_in = (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
|
||||
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
// Read Ptr of the FP
|
||||
val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
|
||||
// Fetch Instruction boundary
|
||||
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
|
||||
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
|
||||
val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
|
||||
|
||||
val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
|
||||
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
|
||||
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
|
||||
// Instrution PC to the FP
|
||||
val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
|
||||
val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
|
||||
val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
|
||||
|
||||
// Flop the stall until flush
|
||||
error_stall := rvdffie(error_stall_in,clock,reset.asAsyncReset(),io.scan_mode)
|
||||
val f2val = rvdffie(f2val_in,clock,reset.asAsyncReset(),io.scan_mode)
|
||||
val f1val = rvdffie(f1val_in,clock,reset.asAsyncReset(),io.scan_mode)
|
||||
val f0val = rvdffie(f0val_in,clock,reset.asAsyncReset(),io.scan_mode)
|
||||
// Branch data to the FP
|
||||
brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
|
||||
brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
|
||||
brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
|
||||
if(BTB_ENABLE){
|
||||
brdata2 := rvdffe(brdata_in, qwen(2),clock,io.scan_mode)
|
||||
brdata1 := rvdffe(brdata_in, qwen(1),clock,io.scan_mode)
|
||||
brdata0 := rvdffe(brdata_in, qwen(0),clock,io.scan_mode)
|
||||
// Miscalanious data to the FP including error's
|
||||
misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
|
||||
misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
|
||||
misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
|
||||
misc2 := rvdffe(misc_data_in, qwen(2),clock,io.scan_mode)
|
||||
misc1 := rvdffe(misc_data_in, qwen(1),clock,io.scan_mode)
|
||||
misc0 := rvdffe(misc_data_in, qwen(0),clock,io.scan_mode)
|
||||
}
|
||||
else{
|
||||
brdata2 := rvdffie(Mux(qwen(2),brdata_in, brdata2),clock,reset.asAsyncReset(),io.scan_mode)
|
||||
brdata1 := rvdffie(Mux(qwen(1),brdata_in, brdata1),clock,reset.asAsyncReset(),io.scan_mode)
|
||||
brdata0 := rvdffie(Mux(qwen(0),brdata_in, brdata0),clock,reset.asAsyncReset(),io.scan_mode)
|
||||
// Miscalanious data to the FP including error's
|
||||
misc2 := rvdffie(Mux(qwen(2),misc_data_in, misc2),clock,reset.asAsyncReset(),io.scan_mode)
|
||||
misc1 := rvdffie(Mux(qwen(1),misc_data_in, misc1),clock,reset.asAsyncReset(),io.scan_mode)
|
||||
misc0 := rvdffie(Mux(qwen(0),misc_data_in, misc0),clock,reset.asAsyncReset(),io.scan_mode)
|
||||
}
|
||||
|
||||
// Instruction in the FP
|
||||
q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
|
||||
q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
|
||||
q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
|
||||
q2 := rvdffe(io.ifu_fetch_data_f, qwen(2),clock,io.scan_mode)
|
||||
q1 := rvdffe(io.ifu_fetch_data_f, qwen(1),clock,io.scan_mode)
|
||||
q0 := rvdffe(io.ifu_fetch_data_f, qwen(0),clock,io.scan_mode)
|
||||
|
||||
val q2pc = rvdffe(io.ifu_fetch_pc, qwen(2),clock,io.scan_mode)
|
||||
val q1pc = rvdffe(io.ifu_fetch_pc, qwen(1),clock,io.scan_mode)
|
||||
val q0pc = rvdffe(io.ifu_fetch_pc, qwen(0),clock,io.scan_mode)
|
||||
|
||||
// Shift FP logic
|
||||
f2_wr_en := fetch_to_f2
|
||||
f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
|
||||
f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
|
||||
// FP read enable .. 3-bit for Implemenation of 1HMux
|
||||
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
|
||||
// FP write enable .. 3-bit for Implemenation of 1HMux
|
||||
qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
|
||||
|
||||
// Read Pointer calculation
|
||||
// Next rdptr = # of consume + current ptr location (Rounding it from 2)
|
||||
qwen := Cat((wrptr === 2.U) & ifvalid, (wrptr === 1.U) & ifvalid, (wrptr === 0.U) & ifvalid)
|
||||
|
||||
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
|
||||
(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
|
||||
(qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
|
||||
|
|
@ -149,27 +169,29 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
(qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
|
||||
(!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
|
||||
|
||||
// As there is only 1 enqueue so each time move by 1
|
||||
|
||||
wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
|
||||
(qwen(1) & !io.exu_flush_final).asBool -> 2.U,
|
||||
(qwen(2) & !io.exu_flush_final).asBool -> 0.U,
|
||||
(!ifvalid & !io.exu_flush_final).asBool->wrptr))
|
||||
(!ifvalid & !io.exu_flush_final).asBool-> wrptr))
|
||||
|
||||
q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
|
||||
(!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
|
||||
(!qwen(2) & (rdptr===0.U)).asBool->q2off))
|
||||
q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool -> (q2off.asUInt | f0_shift_2B),
|
||||
(!qwen(2) & (rdptr===1.U)).asBool -> (q2off.asUInt | f1_shift_2B),
|
||||
(!qwen(2) & (rdptr===0.U)).asBool -> q2off))
|
||||
|
||||
q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
|
||||
(!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
|
||||
(!qwen(1) & (rdptr===2.U)).asBool->q1off))
|
||||
q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool -> (q1off.asUInt | f0_shift_2B),
|
||||
(!qwen(1) & (rdptr===0.U)).asBool -> (q1off.asUInt | f1_shift_2B),
|
||||
(!qwen(1) & (rdptr===2.U)).asBool -> q1off))
|
||||
|
||||
q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
|
||||
(!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
|
||||
(!qwen(0) & (rdptr===1.U)).asBool -> q0off))
|
||||
|
||||
val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
|
||||
(rdptr===1.U)->q1off,
|
||||
(rdptr===2.U)->q2off))
|
||||
// Shift FP logic
|
||||
|
||||
val q0ptr = Mux1H(Seq((rdptr===0.U) -> q0off,
|
||||
(rdptr===1.U) -> q1off,
|
||||
(rdptr===2.U) -> q2off))
|
||||
|
||||
val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
|
||||
|
||||
|
|
@ -177,58 +199,126 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
|
||||
val q1sel = Cat(q1ptr, !q1ptr)
|
||||
// Misc data error, access-fault, type of fault, target, offset and ghr value
|
||||
misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
|
||||
io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
|
||||
|
||||
if(BTB_ENABLE){
|
||||
misc_data_in := Cat(io.ic_access_fault_type_f, io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
|
||||
|
||||
}else{
|
||||
misc_data_in := io.ic_access_fault_type_f
|
||||
}
|
||||
|
||||
val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
|
||||
qren(1).asBool()->Cat(misc2, misc1),
|
||||
qren(2).asBool()->Cat(misc0, misc2)))
|
||||
qren(1).asBool() -> Cat(misc2, misc1),
|
||||
qren(2).asBool() -> Cat(misc0, misc2)))
|
||||
|
||||
val misc1eff = misceff(misceff.getWidth-1,MHI+1)
|
||||
val misc0eff = misceff(MHI, 0)
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
val f1ictype = if(BTB_ENABLE) misc1eff(misc1eff.getWidth-1, misc1eff.getWidth-2) else misc1eff
|
||||
val f1prett = if(BTB_ENABLE) misc1eff(misc1eff.getWidth-3, misc1eff.getWidth-33) else 0.U
|
||||
val f1poffset = if(BTB_ENABLE) misc1eff(misc1eff.getWidth-34, misc1eff.getWidth-45) else 0.U
|
||||
val f1fghr = if(BTB_ENABLE) misc1eff(BHT_GHR_SIZE-1, 0) else 0.U
|
||||
|
||||
val f1dbecc = misc1eff(misc1eff.getWidth-1)
|
||||
f1icaf := misc1eff(misc1eff.getWidth-2)
|
||||
val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
|
||||
val f0ictype = if(BTB_ENABLE) misc0eff(misc0eff.getWidth-1, misc0eff.getWidth-2) else misc0eff
|
||||
val f0prett = if(BTB_ENABLE) misc0eff(misc0eff.getWidth-3, misc0eff.getWidth-33) else 0.U
|
||||
val f0poffset = if(BTB_ENABLE) misc0eff(misc0eff.getWidth-34, misc0eff.getWidth-45) else 0.U
|
||||
val f0fghr = if(BTB_ENABLE) misc0eff(BHT_GHR_SIZE-1, 0) else 0.U
|
||||
|
||||
val f0dbecc = misc0eff(misc1eff.getWidth-1)
|
||||
f0icaf := misc0eff(misc1eff.getWidth-2)
|
||||
val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
|
||||
val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
|
||||
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
|
||||
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
|
||||
val f0ret = WireInit(UInt(2.W), 0.U)
|
||||
val f0brend = WireInit(UInt(2.W), 0.U)
|
||||
val f0way = WireInit(UInt(2.W), 0.U)
|
||||
val f0pc4 = WireInit(UInt(2.W), 0.U)
|
||||
val f0hist0 = WireInit(UInt(2.W), 0.U)
|
||||
val f0hist1 = WireInit(UInt(2.W), 0.U)
|
||||
val f1ret = WireInit(UInt(2.W), 0.U)
|
||||
val f1brend = WireInit(UInt(2.W), 0.U)
|
||||
val f1way = WireInit(UInt(2.W), 0.U)
|
||||
val f1pc4 = WireInit(UInt(2.W), 0.U)
|
||||
val f1hist0 = WireInit(UInt(2.W), 0.U)
|
||||
val f1hist1 = WireInit(UInt(2.W), 0.U)
|
||||
|
||||
// Branch information
|
||||
brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
|
||||
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
|
||||
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
|
||||
// Effective branch information
|
||||
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
|
||||
qren(1).asBool->Cat(brdata2,brdata1),
|
||||
qren(2).asBool->Cat(brdata0,brdata2)))
|
||||
|
||||
val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
|
||||
val f0dbecc = WireInit(UInt(2.W), 0.U)
|
||||
val f1dbecc = WireInit(UInt(2.W), 0.U)
|
||||
val f0index = Wire(Vec(2,UInt(log2Ceil(BTB_SIZE).W)))
|
||||
val f1index = Wire(Vec(2,UInt(log2Ceil(BTB_SIZE).W)))
|
||||
f0index := (0 until 2).map(i => 0.U)
|
||||
f1index := (0 until 2).map(i => 0.U)
|
||||
val brdataeff = WireInit(UInt(((2*BRDATA_SIZE)).W),0.U)
|
||||
brdataeff := Mux1H(Seq(qren(0).asBool -> Cat(brdata1,brdata0),
|
||||
qren(1).asBool -> Cat(brdata2,brdata1),
|
||||
qren(2).asBool -> Cat(brdata0,brdata2)))
|
||||
val brdata1eff = WireInit(UInt(BRDATA_SIZE.W),0.U)
|
||||
val brdata0eff = WireInit(UInt(BRDATA_SIZE.W),0.U)
|
||||
brdata1eff := brdataeff(brdataeff.getWidth - 1,brdataeff.getWidth/2)
|
||||
brdata0eff := brdataeff(brdataeff.getWidth/2 - 1,0)
|
||||
val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff(2*BRDATA_WIDTH-1,0),
|
||||
q0sel(1).asBool -> brdata0eff(BRDATA_SIZE-1,BRDATA_WIDTH)))
|
||||
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff(2*BRDATA_WIDTH-1,0),
|
||||
q1sel(1).asBool -> brdata1eff(BRDATA_SIZE-1,BRDATA_WIDTH)))
|
||||
if(BTB_ENABLE){
|
||||
if(BTB_FULLYA){
|
||||
brdata_in := Cat(io.ifu_bp_fa_index_f(1), io.iccm_rd_ecc_double_err(1), io.ic_access_fault_f(1), io.ifu_bp_hist1_f(1), io.ifu_bp_hist0_f(1), io.ifu_bp_pc4_f(1), io.ifu_bp_way_f(1), io.ifu_bp_valid_f(1), io.ifu_bp_ret_f(1),
|
||||
io.ifu_bp_fa_index_f(0), io.iccm_rd_ecc_double_err(0), io.ic_access_fault_f(0), io.ifu_bp_hist1_f(0), io.ifu_bp_hist0_f(0), io.ifu_bp_pc4_f(0), io.ifu_bp_way_f(0), io.ifu_bp_valid_f(0), io.ifu_bp_ret_f(0))
|
||||
|
||||
val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
|
||||
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
|
||||
f0ret := Cat(brdata0final(17) , brdata0final(0))
|
||||
f0brend := Cat(brdata0final(18), brdata0final(1))
|
||||
f0way := Cat(brdata0final(19), brdata0final(2))
|
||||
f0pc4 := Cat(brdata0final(20), brdata0final(3))
|
||||
f0hist0 := Cat(brdata0final(21), brdata0final(4))
|
||||
f0hist1 := Cat(brdata0final(22), brdata0final(5))
|
||||
f0icaf := Cat(brdata0final(23), brdata0final(6))
|
||||
f0dbecc := Cat(brdata0final(24), brdata0final(7))
|
||||
f0index(1) := Cat(brdata0final(33), brdata0final(32), brdata0final(31), brdata0final(30), brdata0final(29), brdata0final(28), brdata0final(27), brdata0final(26), brdata0final(25))
|
||||
f0index(0) := Cat(brdata0final(16), brdata0final(15), brdata0final(14), brdata0final(13), brdata0final(12), brdata0final(11), brdata0final(10), brdata0final(9), brdata0final(8))
|
||||
|
||||
val f0ret = Cat(brdata0final(6),brdata0final(0))
|
||||
val f0brend = Cat(brdata0final(7),brdata0final(1))
|
||||
val f0way = Cat(brdata0final(8),brdata0final(2))
|
||||
val f0pc4 = Cat(brdata0final(9),brdata0final(3))
|
||||
val f0hist0 = Cat(brdata0final(10),brdata0final(4))
|
||||
val f0hist1 = Cat(brdata0final(11),brdata0final(5))
|
||||
f1ret := Cat(brdata1final(17) , brdata1final(0))
|
||||
f1brend := Cat(brdata1final(18), brdata1final(1))
|
||||
f1way := Cat(brdata1final(19), brdata1final(2))
|
||||
f1pc4 := Cat(brdata1final(20), brdata1final(3))
|
||||
f1hist0 := Cat(brdata1final(21), brdata1final(4))
|
||||
f1hist1 := Cat(brdata1final(22), brdata1final(5))
|
||||
f1icaf := Cat(brdata1final(23), brdata1final(6))
|
||||
f1dbecc := Cat(brdata1final(24), brdata1final(7))
|
||||
f1index(1) := Cat(brdata1final(33), brdata1final(32), brdata1final(31), brdata1final(30), brdata1final(29), brdata1final(28), brdata1final(27), brdata1final(26), brdata1final(25))
|
||||
f1index(0) := Cat(brdata1final(16), brdata1final(15), brdata1final(14), brdata1final(13), brdata1final(12), brdata1final(11), brdata1final(10), brdata1final(9), brdata1final(8))
|
||||
|
||||
val f1ret = Cat(brdata1final(6),brdata1final(0))
|
||||
val f1brend = Cat(brdata1final(7),brdata1final(1))
|
||||
val f1way = Cat(brdata1final(8),brdata1final(2))
|
||||
val f1pc4 = Cat(brdata1final(9),brdata1final(3))
|
||||
val f1hist0 = Cat(brdata1final(10),brdata1final(4))
|
||||
val f1hist1 = Cat(brdata1final(11),brdata1final(5))
|
||||
}else{
|
||||
brdata_in := Cat(io.iccm_rd_ecc_double_err(1), io.ic_access_fault_f(1), io.ifu_bp_hist1_f(1), io.ifu_bp_hist0_f(1), io.ifu_bp_pc4_f(1), io.ifu_bp_way_f(1), io.ifu_bp_valid_f(1), io.ifu_bp_ret_f(1),
|
||||
io.iccm_rd_ecc_double_err(0), io.ic_access_fault_f(0), io.ifu_bp_hist1_f(0), io.ifu_bp_hist0_f(0), io.ifu_bp_pc4_f(0), io.ifu_bp_way_f(0), io.ifu_bp_valid_f(0), io.ifu_bp_ret_f(0))
|
||||
f0ret := Cat(brdata0final(8) , brdata0final(0))
|
||||
f0brend := Cat(brdata0final(9) , brdata0final(1))
|
||||
f0way := Cat(brdata0final(10), brdata0final(2))
|
||||
f0pc4 := Cat(brdata0final(11), brdata0final(3))
|
||||
f0hist0 := Cat(brdata0final(12), brdata0final(4))
|
||||
f0hist1 := Cat(brdata0final(13), brdata0final(5))
|
||||
f0icaf := Cat(brdata0final(14), brdata0final(6))
|
||||
f0dbecc := Cat(brdata0final(15), brdata0final(7))
|
||||
|
||||
f1ret := Cat(brdata1final(8) , brdata1final(0))
|
||||
f1brend := Cat(brdata1final(9) , brdata1final(1))
|
||||
f1way := Cat(brdata1final(10), brdata1final(2))
|
||||
f1pc4 := Cat(brdata1final(11), brdata1final(3))
|
||||
f1hist0 := Cat(brdata1final(12), brdata1final(4))
|
||||
f1hist1 := Cat(brdata1final(13), brdata1final(5))
|
||||
f1icaf := Cat(brdata1final(14), brdata1final(6))
|
||||
f1dbecc := Cat(brdata1final(15), brdata1final(7))
|
||||
|
||||
}
|
||||
}else{
|
||||
brdata_in := Cat(io.iccm_rd_ecc_double_err(1),io.ic_access_fault_f(1),
|
||||
io.iccm_rd_ecc_double_err(0),io.ic_access_fault_f(0))
|
||||
|
||||
|
||||
f0dbecc := Cat(brdata0final(3),brdata0final(1))
|
||||
f0icaf := Cat(brdata0final(2),brdata0final(0))
|
||||
|
||||
f1dbecc := Cat(brdata1final(3),brdata1final(1))
|
||||
f1icaf := Cat(brdata1final(2),brdata1final(0))
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
f2_valid := f2val(0)
|
||||
|
|
@ -257,21 +347,6 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
fetch_to_f2 := (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
|
||||
( sf0_valid & sf1_valid & !f2_valid & ifvalid)
|
||||
|
||||
val f0pc_plus1 = f0pc + 1.U
|
||||
|
||||
val f1pc_plus1 = f1pc + 1.U
|
||||
|
||||
val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
|
||||
|
||||
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f1.asBool->f2pc,
|
||||
(!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
|
||||
|
||||
f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f0.asBool->f2pc,
|
||||
shift_f1_f0.asBool->sf1pc,
|
||||
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
|
||||
|
||||
f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
|
||||
(!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
|
||||
|
||||
|
|
@ -289,43 +364,59 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
( shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
|
||||
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
|
||||
|
||||
val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
|
||||
qren(1).asBool->Cat(q2,q1),
|
||||
qren(2).asBool->Cat(q0,q2)))
|
||||
val qeff = Mux1H(Seq(qren(0).asBool -> Cat(q1,q0),
|
||||
qren(1).asBool -> Cat(q2,q1),
|
||||
qren(2).asBool -> Cat(q0,q2)))
|
||||
val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
|
||||
|
||||
q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
|
||||
q0final := Mux1H(Seq(q0sel(0).asBool->q0eff,
|
||||
q0sel(1).asBool->q0eff(31,16)))
|
||||
|
||||
q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
|
||||
|
||||
val qpceff = Mux1H(Seq(qren(0).asBool -> Cat(q1pc, q0pc),
|
||||
qren(1).asBool -> Cat(q2pc, q1pc),
|
||||
qren(2).asBool -> Cat(q0pc, q2pc)))
|
||||
val q1pceff = qpceff(61, 31)
|
||||
val q0pceff = qpceff(30, 0)
|
||||
val q0pcfinal = Mux1H(Seq(q0sel(0) -> q0pceff, q0sel(1) -> (q0pceff+1.U)))
|
||||
// Alinging the data according to the boundary of PC
|
||||
val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
|
||||
val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (!f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
|
||||
|
||||
alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
|
||||
|
||||
val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
|
||||
val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf(0),f0icaf(0))))
|
||||
|
||||
val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
|
||||
val aligndbecc = Mux1H(Seq(f0val(1).asBool -> f0dbecc, (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc(0),f0dbecc(0))))
|
||||
|
||||
val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
|
||||
/////////////////////////////////////////////////////////
|
||||
val alignbrend = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0)))) else 0.U
|
||||
|
||||
val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
|
||||
val alignpc4 = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0)))) else 0.U
|
||||
|
||||
val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
|
||||
val alignret = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0)))) else 0.U
|
||||
|
||||
val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
|
||||
val alignway = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0)))) else 0.U
|
||||
|
||||
val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
|
||||
val alignhist1 = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0)))) else 0.U
|
||||
|
||||
val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
|
||||
val alignhist0 = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0)))) else 0.U
|
||||
|
||||
val secondpc = if(BTB_ENABLE) Mux1H(Seq(f0val(1).asBool() -> (q0pceff + 1.U), (!f0val(1) & f0val(0)).asBool -> q1pceff)) else 0.U
|
||||
|
||||
val firstpc = if(BTB_ENABLE) q0pcfinal else 0.U
|
||||
|
||||
val alignindex = Wire(Vec(2,UInt(log2Ceil(BTB_SIZE).W)))
|
||||
alignindex := (0 until 2).map(i => 0.U)
|
||||
if(BTB_ENABLE){if(BTB_FULLYA) {
|
||||
alignindex(0):= f0index(0)
|
||||
alignindex(1):= Mux(f0val(1).asBool, f0index(1), f1index(0))
|
||||
} }
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
val alignfromf1 = !f0val(1) & f0val(0)
|
||||
|
||||
val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_pc := f0pc
|
||||
|
||||
val firstpc = f0pc
|
||||
io.dec_aln.aln_ib.ifu_i0_pc := q0pcfinal
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
|
||||
|
||||
|
|
@ -334,7 +425,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
// Instruction is compressed or not
|
||||
first4B := aligndata(1,0) === 3.U
|
||||
|
||||
val first2B = ~first4B
|
||||
val first2B = !first4B
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
|
||||
|
||||
|
|
@ -342,9 +433,9 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
|
||||
|
||||
val icaf_eff = alignicaf(1) | aligndbecc(1)
|
||||
val icaf_eff = alignicaf | aligndbecc
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & !icaf_eff(0) & icaf_eff(1)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
|
||||
|
||||
|
|
@ -352,23 +443,28 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
// Expander from 16-bit to 32-bit
|
||||
val decompressed = Module(new ifu_compress_ctl())
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
|
||||
io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq((first4B & alignval(1)).asBool -> ifirst,
|
||||
(first2B & alignval(0)).asBool -> decompressed.io.dout))
|
||||
|
||||
// Hashing the PC
|
||||
val firstpc_hash = btb_addr_hash(f0pc)
|
||||
////////////////////////////////////////////////////////////////////////////////////////////
|
||||
val firstpc_hash = btb_addr_hash(firstpc)
|
||||
|
||||
val secondpc_hash = btb_addr_hash(secondpc)
|
||||
|
||||
val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
|
||||
val firstbrtag_hash = WireInit(UInt(BTB_BTAG_SIZE.W),0.U)
|
||||
val secondbrtag_hash = WireInit(UInt(BTB_BTAG_SIZE.W),0.U)
|
||||
if(BTB_ENABLE){if(BTB_FULLYA)
|
||||
firstbrtag_hash := firstpc else {if(BTB_BTAG_FOLD) firstbrtag_hash := btb_tag_hash_fold(firstpc) else firstbrtag_hash := btb_tag_hash(firstpc)} }
|
||||
if(BTB_ENABLE){if(BTB_FULLYA)
|
||||
secondbrtag_hash := secondpc else {if(BTB_BTAG_FOLD) secondbrtag_hash := btb_tag_hash_fold(secondpc) else secondbrtag_hash := btb_tag_hash(secondpc)} }
|
||||
|
||||
val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
if(BTB_ENABLE){
|
||||
io.dec_aln.aln_ib.i0_brp.valid := (first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
|
||||
io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
|
|
@ -386,21 +482,35 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid & i0_brp_pc4 & first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
|
||||
|
||||
decompressed.io.din := aligndata
|
||||
if(BTB_FULLYA){
|
||||
io.ifu_i0_fa_index := Mux((first2B | alignbrend(0)).asBool, alignindex(0), alignindex(1))
|
||||
}else{
|
||||
io.ifu_i0_fa_index := 0.U
|
||||
}
|
||||
}else{
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_index := 0.U
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_fghr := 0.U
|
||||
io.dec_aln.aln_ib.ifu_i0_bp_btag := 0.U
|
||||
io.dec_aln.aln_ib.i0_brp := 0.U.asTypeOf(io.dec_aln.aln_ib.i0_brp)
|
||||
}
|
||||
|
||||
val i0_shift = io.dec_i0_decode_d & ~error_stall
|
||||
|
||||
|
||||
decompressed.io.din := Mux(first2B.asBool(),aligndata,0.U)
|
||||
|
||||
val i0_shift = io.dec_i0_decode_d & !error_stall
|
||||
|
||||
io.dec_aln.ifu_pmu_instr_aligned := i0_shift
|
||||
|
||||
shift_2B := i0_shift & first2B
|
||||
shift_4B := i0_shift & first4B
|
||||
|
||||
////
|
||||
f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
|
||||
f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
|
||||
|
||||
}
|
||||
//object Aligner extends App {
|
||||
// (new chisel3.stage.ChiselStage).emitVerilog(new ifu_aln_ctl())
|
||||
//}
|
||||
|
|
@ -433,11 +433,16 @@ if(!BTB_FULLYA) {
|
|||
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
|
||||
|
||||
btb_bank0_rd_data_way0_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
|
||||
btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
|
||||
dontTouch(btb_bank0_rd_data_way0_f)
|
||||
|
||||
btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
|
||||
dontTouch(btb_bank0_rd_data_way1_f)
|
||||
// BTB read muxing
|
||||
btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
|
||||
dontTouch(btb_bank0_rd_data_way0_p1_f)
|
||||
|
||||
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
|
||||
dontTouch(btb_bank0_rd_data_way1_p1_f)
|
||||
}
|
||||
// if(BTB_FULLYA){
|
||||
// val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
|
||||
|
|
@ -500,6 +505,7 @@ if(!BTB_FULLYA) {
|
|||
if(RV_FPGA_OPTIMIZE) {
|
||||
for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)) bht_bank_clk(i)(k) := rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode)
|
||||
// (0 until 2).map(i=>(0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)).map(k=>rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode)))
|
||||
|
||||
}
|
||||
for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){
|
||||
// Checking if there is a write enable with address for the BHT
|
||||
|
|
|
|||
|
|
@ -1,14 +1,11 @@
|
|||
package ifu
|
||||
import chisel3._
|
||||
import chisel3.internal.naming.chiselName
|
||||
import chisel3.util._
|
||||
import lib._
|
||||
import include._
|
||||
|
||||
import scala.math.pow
|
||||
|
||||
class mem_ctl_io extends Bundle with lib{
|
||||
val free_clk = Input(Clock())
|
||||
val free_l2clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
val exu_flush_final = Input(Bool())
|
||||
val dec_mem_ctrl = new dec_mem_ctrl
|
||||
|
|
@ -40,11 +37,11 @@ class mem_ctl_io extends Bundle with lib{
|
|||
val iccm_ready = Output(Bool())
|
||||
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
val iccm_rd_ecc_double_err = Output(Bool())
|
||||
val iccm_rd_ecc_double_err = Output(UInt(2.W))
|
||||
val iccm_dma_sb_error = Output(Bool())
|
||||
|
||||
val ic_hit_f = Output(Bool())
|
||||
val ic_access_fault_f = Output(Bool())
|
||||
val ic_access_fault_f = Output(UInt(2.W))
|
||||
val ic_access_fault_type_f = Output(UInt(2.W))
|
||||
val ifu_async_error_start = Output(Bool())
|
||||
val ic_fetch_val_f = Output(UInt(2.W))
|
||||
|
|
@ -60,43 +57,42 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5)
|
||||
|
||||
val iccm_single_ecc_error = WireInit(UInt(2.W), 0.U)
|
||||
val ifc_fetch_req_f = WireInit(Bool(), false.B)
|
||||
val miss_pending = WireInit(Bool(), false.B)
|
||||
val scnd_miss_req = WireInit(Bool(), false.B)
|
||||
val dma_iccm_req_f = WireInit(Bool(), false.B)
|
||||
val iccm_correct_ecc = WireInit(Bool(), false.B)
|
||||
val ifc_fetch_req_f = WireInit(Bool(), 0.B)
|
||||
val miss_pending = WireInit(Bool(), 0.B)
|
||||
val scnd_miss_req = WireInit(Bool(), 0.B)
|
||||
val dma_iccm_req_f = WireInit(Bool(), 0.B)
|
||||
val iccm_correct_ecc = WireInit(Bool(), 0.B)
|
||||
val perr_state = WireInit(UInt(3.W), 0.U)
|
||||
val err_stop_state = WireInit(UInt(2.W), 0.U)
|
||||
val err_stop_fetch = WireInit(Bool(), false.B)
|
||||
val err_stop_fetch = WireInit(Bool(), 0.B)
|
||||
val miss_state = WireInit(UInt(3.W), 0.U)
|
||||
val miss_nxtstate = WireInit(UInt(3.W), 0.U)
|
||||
val miss_state_en = WireInit(Bool(), false.B)
|
||||
val ifu_bus_rsp_valid = WireInit(Bool(), false.B)
|
||||
val bus_ifu_bus_clk_en = WireInit(Bool(), false.B)
|
||||
val ifu_bus_rsp_ready = WireInit(Bool(), false.B)
|
||||
val uncacheable_miss_ff = WireInit(Bool(), false.B)
|
||||
val ic_act_miss_f = WireInit(Bool(), false.B)
|
||||
val ic_byp_hit_f = WireInit(Bool(), false.B)
|
||||
val miss_state_en = WireInit(Bool(), 0.B)
|
||||
val bus_ifu_bus_clk_en = WireInit(Bool(), 0.B)
|
||||
val uncacheable_miss_ff = WireInit(Bool(), 0.B)
|
||||
val ic_act_miss_f = WireInit(Bool(), 0.B)
|
||||
val ic_byp_hit_f = WireInit(Bool(), 0.B)
|
||||
val bus_new_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
|
||||
val bus_ifu_wr_en_ff = WireInit(Bool(), false.B)
|
||||
val last_beat = WireInit(Bool(), false.B)
|
||||
val last_data_recieved_ff = WireInit(Bool(), false.B)
|
||||
val stream_eol_f = WireInit(Bool(), false.B)
|
||||
val ic_miss_under_miss_f = WireInit(Bool(), false.B)
|
||||
val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B)
|
||||
val ic_debug_rd_en_ff = WireInit(Bool(), false.B)
|
||||
val bus_ifu_wr_en_ff = WireInit(Bool(), 0.B)
|
||||
val last_beat = WireInit(Bool(), 0.B)
|
||||
val last_data_recieved_ff = WireInit(Bool(), 0.B)
|
||||
val stream_eol_f = WireInit(Bool(), 0.B)
|
||||
val ic_miss_under_miss_f = WireInit(Bool(), 0.B)
|
||||
val ic_ignore_2nd_miss_f = WireInit(Bool(), 0.B)
|
||||
val ic_debug_rd_en_ff = WireInit(Bool(), 0.B)
|
||||
|
||||
val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode)
|
||||
val flush_final_f = withClock(io.free_clk){RegNext(io.exu_flush_final, 0.U)}
|
||||
val flush_final_f = rvdffie(io.exu_flush_final,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_l2clk){RegNext(io.exu_flush_final, 0.U)}
|
||||
val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
|
||||
val debug_c1_clken = io.ic.debug_rd_en | io.ic.debug_wr_en
|
||||
val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
|
||||
val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode)
|
||||
val fetch_bf_f_c1_clk = if(RV_FPGA_OPTIMIZE) 0.B.asClock() else rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode)
|
||||
val debug_c1_clk = if(RV_FPGA_OPTIMIZE) 0.B.asClock() else rvclkhdr(clock, debug_c1_clken, io.scan_mode)
|
||||
|
||||
io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool()
|
||||
io.ifu_async_error_start := io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err | io.dec_mem_ctrl.ifu_ic_error_start
|
||||
io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_mem_ctrl.dec_tlu_flush_err_wb
|
||||
|
||||
val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & (bus_new_data_beat_count.andR) &
|
||||
val scnd_miss_req_in = io.ifu_axi.r.valid & bus_ifu_bus_clk_en & io.ifu_axi.r.ready & (bus_new_data_beat_count.andR) &
|
||||
!uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
|
||||
|
||||
val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
|
|
@ -145,7 +141,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
}
|
||||
}
|
||||
miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)}
|
||||
miss_state := withClock(io.active_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)}
|
||||
// Calculation all the relevant signals for the miss FSM
|
||||
val crit_byp_hit_f = WireInit(Bool(), 0.U)
|
||||
val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
|
|
@ -165,13 +161,13 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
|
||||
val way_status_mb_scnd_in = Mux(miss_state === scnd_miss_C, way_status_mb_scnd_ff, way_status)
|
||||
|
||||
val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags) & io.ic.tag_valid)
|
||||
val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags & !io.exu_flush_final) & io.ic.tag_valid)
|
||||
val uncacheable_miss_scnd_in = Mux(sel_hold_imb_scnd.asBool, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf)
|
||||
uncacheable_miss_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_scnd_in, 0.U)}
|
||||
uncacheable_miss_scnd_ff := rvdff_fpga(uncacheable_miss_scnd_in,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_scnd_in, 0.U)}
|
||||
val imb_scnd_in = Mux(sel_hold_imb_scnd.asBool, imb_scnd_ff, io.ifc_fetch_addr_bf)
|
||||
imb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_scnd_in, 0.U)}
|
||||
way_status_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_scnd_in, 0.U)}
|
||||
tagv_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_scnd_in, 0.U)}
|
||||
imb_scnd_ff := rvdffpcie(imb_scnd_in,fetch_bf_f_c1_clken,reset.asAsyncReset(),clock,io.scan_mode)//withClock(fetch_bf_f_c1_clk){RegNext(imb_scnd_in, 0.U)}
|
||||
way_status_mb_scnd_ff := rvdff_fpga(way_status_mb_scnd_in,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_scnd_in, 0.U)}
|
||||
tagv_mb_scnd_ff := rvdff_fpga(tagv_mb_scnd_in,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_scnd_in, 0.U)}
|
||||
|
||||
val ic_req_addr_bits_hi_3 = bus_rd_addr_count
|
||||
val ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & Fill(ICACHE_BEAT_BITS, bus_ifu_wr_en_ff)
|
||||
|
|
@ -205,45 +201,45 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
|
||||
val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))),
|
||||
Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
|
||||
val scnd_miss_req_q = WireInit(Bool(), false.B)
|
||||
val reset_ic_ff = WireInit(Bool(), false.B)
|
||||
Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags & !io.exu_flush_final)))
|
||||
val scnd_miss_req_q = WireInit(Bool(), 0.B)
|
||||
val reset_ic_ff = WireInit(Bool(), 0.B)
|
||||
val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
|
||||
reset_ic_ff := withClock(io.free_clk){RegNext(reset_ic_in, false.B)}
|
||||
val fetch_uncacheable_ff = withClock(io.active_clk){RegNext(io.ifc_fetch_uncacheable_bf, 0.U)}
|
||||
ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)}
|
||||
reset_ic_ff := rvdffie(reset_ic_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(reset_ic_in, false.B)}
|
||||
val fetch_uncacheable_ff = rvdffie(io.ifc_fetch_uncacheable_bf,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(io.ifc_fetch_uncacheable_bf, 0.U)}
|
||||
ifu_fetch_addr_int_f := rvdffpcie(io.ifc_fetch_addr_bf,fetch_bf_f_c1_clken,reset.asAsyncReset(),clock,io.scan_mode) // withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)}
|
||||
val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0)
|
||||
uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)}
|
||||
imb_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_in, 0.U)}
|
||||
uncacheable_miss_ff := rvdff_fpga(uncacheable_miss_in,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)}
|
||||
imb_ff := rvdffpcie(imb_in,fetch_bf_f_c1_clken,reset.asAsyncReset(),clock,io.scan_mode)//withClock(fetch_bf_f_c1_clk){RegNext(imb_in, 0.U)}
|
||||
val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
|
||||
val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI),
|
||||
Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr))
|
||||
val busclk_reset = rvclkhdr(clock, bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt, io.scan_mode)
|
||||
miss_addr := withClock(busclk_reset) {RegNext(miss_addr_in, 0.U)}
|
||||
way_status_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)}
|
||||
tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)}
|
||||
val busclk_reset = if(RV_FPGA_OPTIMIZE) 0.B.asClock() else rvclkhdr(clock, bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt, io.scan_mode)
|
||||
|
||||
miss_addr := rvdfflie_UInt(miss_addr_in,clock,reset.asAsyncReset(),bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt,io.scan_mode)//withClock(busclk_reset) {RegNext(miss_addr_in, 0.U)}
|
||||
way_status_mb_ff := rvdff_fpga(way_status_mb_in,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)}
|
||||
tagv_mb_ff := rvdff_fpga(tagv_mb_in,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)}
|
||||
val stream_miss_f = WireInit(Bool(), 0.U)
|
||||
val ifc_fetch_req_qual_bf = io.ifc_fetch_req_bf & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f
|
||||
val ifc_fetch_req_f_raw = withClock(io.active_clk){RegNext(ifc_fetch_req_qual_bf, 0.U)}
|
||||
val ifc_fetch_req_f_raw = rvdffie(ifc_fetch_req_qual_bf,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ifc_fetch_req_qual_bf, 0.U)}
|
||||
ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final
|
||||
ifc_iccm_access_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)}
|
||||
ifc_iccm_access_f := rvdff_fpga(io.ifc_iccm_access_bf,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)}
|
||||
val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U)
|
||||
ifc_region_acc_fault_final_f := withClock(fetch_bf_f_c1_clk){RegNext(ifc_region_acc_fault_final_bf, 0.U)}
|
||||
val ifc_region_acc_fault_f = withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)}
|
||||
ifc_region_acc_fault_final_f := rvdff_fpga(ifc_region_acc_fault_final_bf,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)// withClock(fetch_bf_f_c1_clk){RegNext(ifc_region_acc_fault_final_bf, 0.U)}
|
||||
val ifc_region_acc_fault_f = rvdff_fpga(io.ifc_region_acc_fault_bf,fetch_bf_f_c1_clk,fetch_bf_f_c1_clken,clock)//withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)}
|
||||
val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3)
|
||||
io.ifu_ic_mb_empty := (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending
|
||||
io.dec_mem_ctrl.ifu_miss_state_idle := miss_state === idle_C
|
||||
val write_ic_16_bytes = WireInit(Bool(), false.B)
|
||||
val reset_tag_valid_for_miss = WireInit(Bool(), false.B)
|
||||
val write_ic_16_bytes = WireInit(Bool(), 0.B)
|
||||
val reset_tag_valid_for_miss = WireInit(Bool(), 0.B)
|
||||
val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
|
||||
val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
|
||||
io.ic.rw_addr := Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
|
||||
!sel_mb_addr -> io.ifc_fetch_addr_bf))
|
||||
val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B)
|
||||
val bus_ifu_wr_en_ff_q = WireInit(Bool(), 0.B)
|
||||
val sel_mb_status_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss
|
||||
val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f)
|
||||
io.ic.rw_addr := ifu_ic_rw_int_addr
|
||||
sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
|
||||
val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
|
||||
sel_mb_addr_ff := rvdffie(sel_mb_addr,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(sel_mb_addr, 0.U)}
|
||||
val ifu_bus_rdata_ff = rvdffe(io.ifu_axi.r.bits.data,io.ifu_bus_clk_en & io.ifu_axi.r.valid,clock,io.scan_mode)
|
||||
val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
|
||||
|
||||
// Ecc of the read data from the AXI
|
||||
|
|
@ -260,7 +256,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ic.tag_debug_rd_data(25,21),0.U(32.W),io.ic.tag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
|
||||
else Cat(0.U(6.W),io.ic.tag_debug_rd_data(21),0.U(32.W),io.ic.tag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
|
||||
io.ic.debug_rd_data)
|
||||
io.dec_mem_ctrl.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)}
|
||||
|
||||
io.dec_mem_ctrl.ifu_ic_debug_rd_data := rvdffe(ifu_ic_debug_rd_data_in,ic_debug_rd_en_ff,clock,io.scan_mode)//withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)}
|
||||
val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
|
||||
val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
|
||||
|
||||
|
|
@ -270,59 +267,52 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
|
||||
val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
|
||||
val reset_beat_cnt = WireInit(Bool(), 0.U)
|
||||
val ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff
|
||||
val ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & !reset_beat_cnt
|
||||
ifu_wr_cumulative_err_data := ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff
|
||||
ifu_wr_data_comb_err_ff := withClock(io.free_clk) {RegNext(ifu_wr_cumulative_err, 0.U)}
|
||||
val ifu_wr_cumulative_err = (bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff) & !reset_beat_cnt
|
||||
ifu_wr_cumulative_err_data := bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff
|
||||
ifu_wr_data_comb_err_ff := rvdffie(ifu_wr_cumulative_err,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk) {RegNext(ifu_wr_cumulative_err, 0.U)}
|
||||
val ic_crit_wd_rdy = WireInit(Bool(), 0.U)
|
||||
val ifu_byp_data_err_new = WireInit(Bool(), 0.U)
|
||||
val sel_byp_data = (ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !ifu_byp_data_err_new
|
||||
val sel_ic_data = !(ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !fetch_req_iccm_f
|
||||
val sel_iccm_data = fetch_req_iccm_f
|
||||
val ifu_byp_data_err_f = WireInit(UInt(2.W), 0.U)
|
||||
val sel_byp_data = (ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C))
|
||||
val sel_ic_data = !(ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C) | (miss_state === miss_wait_C)) & !fetch_req_iccm_f & !ifc_region_acc_fault_final_f
|
||||
|
||||
val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U)
|
||||
val final_data_sel1 = VecInit(sel_byp_data | sel_iccm_data | sel_ic_data, sel_byp_data, sel_byp_data | sel_ic_data, sel_byp_data)
|
||||
val final_data_sel2 = VecInit(true.B, sel_iccm_data, true.B, true.B)
|
||||
val final_data_out1 = VecInit(io.ic.rd_data, ic_byp_data_only_new, io.ic.rd_data, ic_byp_data_only_new)
|
||||
val final_data_out2 = VecInit(1.U, io.iccm.rd_data, 1.U, 1.U)
|
||||
val ic_final_data = if(ICCM_ICACHE) Fill(64, sel_byp_data | sel_iccm_data | sel_ic_data) & io.ic.rd_data else
|
||||
if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else
|
||||
|
||||
val ic_final_data = if(ICCM_ICACHE) Fill(64, sel_byp_data | fetch_req_iccm_f | sel_ic_data) & io.ic.rd_data else
|
||||
if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, fetch_req_iccm_f) & io.iccm.rd_data) else
|
||||
if (ICACHE_ONLY) Fill(64, sel_byp_data | sel_ic_data) & io.ic.rd_data else
|
||||
if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
|
||||
val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm.rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
|
||||
val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,fetch_req_iccm_f) & io.iccm.rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
|
||||
else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
|
||||
val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
|
||||
val ic_sel_premux_data_temp = if(ICCM_ICACHE) fetch_req_iccm_f | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
|
||||
io.ic.premux_data := ic_premux_data_temp
|
||||
io.ic.sel_premux_data := ic_sel_premux_data_temp
|
||||
val ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new
|
||||
val ifc_bus_acc_fault_f = Fill(2,ic_byp_hit_f) & ifu_byp_data_err_f
|
||||
io.ic_data_f := ic_final_data
|
||||
val fetch_req_f_qual = io.ic_hit_f & !io.exu_flush_final
|
||||
val ifc_region_acc_fault_memory_f = WireInit(Bool(), 0.U)
|
||||
io.ic_access_fault_f := (ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) & !io.exu_flush_final
|
||||
io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.asBool, 1.U,
|
||||
Mux(ifc_region_acc_fault_f.asBool, 2.U,
|
||||
Mux(ifc_region_acc_fault_memory_f.asBool(), 3.U, 0.U)))
|
||||
io.ic_access_fault_f := (Fill(2,ifc_region_acc_fault_final_f) | ifc_bus_acc_fault_f) & Fill(2,!io.exu_flush_final)
|
||||
io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.orR, 1.U, Mux(ifc_region_acc_fault_f, 2.U, Mux(ifc_region_acc_fault_memory_f, 3.U, 0.U)))
|
||||
|
||||
io.ic_fetch_val_f := Cat(fetch_req_f_qual & io.ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual)
|
||||
val two_byte_instr = io.ic_data_f(1,0) =/= 3.U
|
||||
//// Creating full buffer
|
||||
val ifu_bus_rsp_rdata = WireInit(UInt(64.W), 0.U)
|
||||
val ic_miss_buff_data_in = ifu_bus_rsp_rdata
|
||||
val ifu_bus_rsp_tag = WireInit(UInt(IFU_BUS_TAG.W), 0.U)
|
||||
val bus_ifu_wr_en = WireInit(Bool(), false.B)
|
||||
val write_fill_data = (0 until ICACHE_NUM_BEATS).map(i=>bus_ifu_wr_en & (ifu_bus_rsp_tag===i.U))
|
||||
val ic_miss_buff_data_in = io.ifu_axi.r.bits.data
|
||||
val bus_ifu_wr_en = WireInit(Bool(), 0.B)
|
||||
val write_fill_data = (0 until ICACHE_NUM_BEATS).map(i=>bus_ifu_wr_en & (io.ifu_axi.r.bits.id===i.U))
|
||||
val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W)))
|
||||
for(i<- 0 until ICACHE_NUM_BEATS){
|
||||
val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
|
||||
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
|
||||
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
|
||||
for(i<- 0 until ICACHE_NUM_BEATS) {
|
||||
//val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
|
||||
ic_miss_buff_data(2 * i) := rvdffe(ic_miss_buff_data_in(31, 0), write_fill_data(i), clock, io.scan_mode) //withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
|
||||
ic_miss_buff_data(2 * i + 1) := rvdffe(ic_miss_buff_data_in(63, 32), write_fill_data(i), clock, io.scan_mode) //withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
|
||||
}
|
||||
val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
|
||||
val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f)))
|
||||
ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
|
||||
ic_miss_buff_data_valid := withClock(io.active_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
|
||||
val bus_ifu_wr_data_error = WireInit(Bool(), 0.U)
|
||||
val ic_miss_buff_data_error = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
|
||||
val ic_miss_buff_data_error_in =(0 until ICACHE_NUM_BEATS).map(i=>Mux(write_fill_data(i).asBool,bus_ifu_wr_data_error,
|
||||
ic_miss_buff_data_error(i) & !ic_act_miss_f))
|
||||
ic_miss_buff_data_error := withClock(io.free_clk){RegNext(ic_miss_buff_data_error_in.reverse.reduce(Cat(_,_)), 0.U)}
|
||||
ic_miss_buff_data_error := withClock(io.active_clk){RegNext(ic_miss_buff_data_error_in.reverse.reduce(Cat(_,_)), 0.U)}
|
||||
|
||||
// New Bypass ready
|
||||
val bypass_index = imb_ff(ICACHE_BEAT_ADDR_HI-1, 0)
|
||||
|
|
@ -339,7 +329,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
|
||||
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
|
||||
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
|
||||
ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
|
||||
ic_crit_wd_rdy_new_ff := rvdffie(ic_crit_wd_rdy_new_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
|
||||
val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0)
|
||||
val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U)
|
||||
val byp_fetch_index_1 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 1.U)
|
||||
|
|
@ -348,19 +338,18 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U)
|
||||
val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i)))
|
||||
val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i)))
|
||||
ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) |
|
||||
ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0))))
|
||||
val miss_wrap_f = WireInit(Bool(),0.B)
|
||||
ifu_byp_data_err_f := Mux(ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2) ) , 3.U,
|
||||
Mux((ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ~(ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) &
|
||||
(~miss_wrap_f & ic_miss_buff_data_error(byp_fetch_index_inc))), 2.U, 0.U))
|
||||
|
||||
val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool,
|
||||
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))),
|
||||
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0)))))
|
||||
|
||||
ic_byp_data_only_new := Mux(!ifu_fetch_addr_int_f(0).asBool(),ic_byp_data_only_pre_new,Cat(0.U(16.W),ic_byp_data_only_pre_new(79,16)))
|
||||
|
||||
val miss_wrap_f = imb_ff(ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(ICACHE_TAG_INDEX_LO-1)
|
||||
miss_wrap_f := imb_ff(ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(ICACHE_TAG_INDEX_LO-1)
|
||||
val ic_miss_buff_data_valid_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_valid(i)))
|
||||
val ic_miss_buff_data_valid_inc_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_valid(i)))
|
||||
val miss_buff_hit_unq_f = (ic_miss_buff_data_valid_bypass_index & !byp_fetch_index(1) & !byp_fetch_index(0)) |
|
||||
|
|
@ -382,23 +371,23 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i))))
|
||||
|
||||
// Parity check for the I$ logic
|
||||
ic_rd_parity_final_err := io.ic.tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f)
|
||||
ic_rd_parity_final_err := io.ic.tag_perr & !io.exu_flush_final & sel_ic_data & !(ifc_region_acc_fault_final_f | (ifc_bus_acc_fault_f.orR)) &
|
||||
(fetch_req_icache_f & !reset_all_tags & (!miss_pending | (miss_state===hit_u_miss_C)) & !sel_mb_addr_ff);
|
||||
|
||||
val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U)
|
||||
|
||||
val perr_sb_write_status = WireInit(Bool(), false.B)
|
||||
val perr_ic_index_ff = withClock(io.active_clk){RegEnable(ifu_ic_rw_int_addr_ff, 0.U, perr_sb_write_status)}
|
||||
val perr_sel_invalidate = WireInit(Bool(), false.B)
|
||||
val perr_sb_write_status = WireInit(Bool(), 0.B)
|
||||
val perr_ic_index_ff = rvdffe(ifu_ic_rw_int_addr_ff,perr_sb_write_status,clock,io.scan_mode)//withClock(io.active_clk){RegEnable(ifu_ic_rw_int_addr_ff, 0.U, perr_sb_write_status)}
|
||||
val perr_sel_invalidate = WireInit(Bool(), 0.B)
|
||||
val perr_err_inv_way = Fill(ICACHE_NUM_WAYS, perr_sel_invalidate)
|
||||
iccm_correct_ecc := perr_state === ecc_cor_C
|
||||
val dma_sb_err_state = perr_state === dma_sb_err_C
|
||||
val dma_sb_err_state_ff = Wire(Bool())
|
||||
val dma_sb_err_state_ff = rvdffie(perr_state === dma_sb_err_C,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
io.iccm.buf_correct_ecc := iccm_correct_ecc & !dma_sb_err_state_ff
|
||||
dma_sb_err_state_ff := withClock(io.active_clk){RegNext(dma_sb_err_state, false.B)}
|
||||
|
||||
///////////////////////////////// PARITY ERROR FSM /////////////////////////////////
|
||||
val perr_nxtstate = WireInit(UInt(3.W), 0.U)
|
||||
val perr_state_en = WireInit(Bool(), false.B)
|
||||
val iccm_error_start = WireInit(Bool(), false.B)
|
||||
val perr_state_en = WireInit(Bool(), 0.B)
|
||||
val iccm_error_start = if(ICCM_ENABLE) io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err else 0.U
|
||||
switch(perr_state){
|
||||
is(err_idle_C){
|
||||
perr_nxtstate := Mux(io.iccm_dma_sb_error, dma_sb_err_C, Mux((io.dec_mem_ctrl.ifu_ic_error_start & !io.exu_flush_final).asBool, ic_wff_C, ecc_wff_C))
|
||||
|
|
@ -416,18 +405,18 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
}
|
||||
is(dma_sb_err_C){
|
||||
perr_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, err_idle_C, ecc_cor_C)
|
||||
perr_state_en := true.B
|
||||
perr_state_en := 1.B
|
||||
}
|
||||
is(ecc_cor_C){
|
||||
perr_nxtstate := err_idle_C
|
||||
perr_state_en := true.B
|
||||
perr_state_en := 1.B
|
||||
}
|
||||
}
|
||||
perr_state := withClock(io.free_clk){RegEnable(perr_nxtstate, 0.U, perr_state_en)}
|
||||
perr_state := withClock(io.active_clk){RegEnable(perr_nxtstate, 0.U, perr_state_en)}
|
||||
///////////////////////////////// STOP FETCH FSM /////////////////////////////////
|
||||
val err_stop_nxtstate = WireInit(UInt(2.W), 0.U)
|
||||
val err_stop_state_en = WireInit(Bool(), false.B)
|
||||
io.iccm.correction_state := false.B
|
||||
val err_stop_state_en = WireInit(Bool(), 0.B)
|
||||
io.iccm.correction_state := 0.B
|
||||
switch(err_stop_state){
|
||||
is(err_stop_idle_C){
|
||||
err_stop_nxtstate := err_fetch1_C
|
||||
|
|
@ -439,190 +428,167 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C)))
|
||||
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr)) & !(io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt)
|
||||
io.iccm.correction_state := true.B
|
||||
io.iccm.correction_state := 1.B
|
||||
}
|
||||
is(err_fetch2_C){
|
||||
err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
|
||||
err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C))
|
||||
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_mem_ctrl.dec_tlu_i0_commit_cmt
|
||||
io.iccm.correction_state := true.B
|
||||
io.iccm.correction_state := 1.B
|
||||
}
|
||||
is(err_stop_fetch_C){
|
||||
err_stop_nxtstate := Mux(((io.dec_tlu_flush_lower_wb & !io.dec_mem_ctrl.dec_tlu_flush_err_wb) | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
|
||||
err_stop_idle_C, Mux(io.dec_mem_ctrl.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C))
|
||||
err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
err_stop_fetch := true.B
|
||||
io.iccm.correction_state := true.B
|
||||
err_stop_fetch := 1.B
|
||||
io.iccm.correction_state := 1.B
|
||||
}
|
||||
}
|
||||
err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
|
||||
err_stop_state := withClock(io.active_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
|
||||
bus_ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
|
||||
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
|
||||
val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
|
||||
scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
|
||||
val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)}
|
||||
|
||||
val busclk = if(RV_FPGA_OPTIMIZE) 0.B.asClock() else rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
|
||||
val busclk_force = if(RV_FPGA_OPTIMIZE) 0.B.asClock() else rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
|
||||
|
||||
|
||||
|
||||
val bus_ifu_bus_clk_en_ff = rvdffie(bus_ifu_bus_clk_en,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
|
||||
scnd_miss_req_q := rvdffie(scnd_miss_req_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
|
||||
scnd_miss_req := scnd_miss_req_q & (!io.exu_flush_final)
|
||||
val bus_cmd_req_hold = WireInit(Bool(), false.B)
|
||||
val ifu_bus_cmd_valid = WireInit(Bool(), false.B)
|
||||
val bus_cmd_req_hold = WireInit(Bool(), 0.B)
|
||||
val ifu_bus_cmd_valid = WireInit(Bool(), 0.B)
|
||||
val bus_cmd_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
|
||||
val ifu_bus_cmd_ready = WireInit(Bool(), false.B)
|
||||
val ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & !io.dec_mem_ctrl.dec_tlu_force_halt & !((bus_cmd_beat_count===Fill(ICACHE_BEAT_BITS,1.U)) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending)
|
||||
ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)}
|
||||
val bus_cmd_sent = WireInit(Bool(), false.B)
|
||||
val ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & !io.dec_mem_ctrl.dec_tlu_force_halt & !((bus_cmd_beat_count===Fill(ICACHE_BEAT_BITS,1.U)) & ifu_bus_cmd_valid & io.ifu_axi.ar.ready & miss_pending)
|
||||
ifu_bus_cmd_valid := rvdff_fpga(ifc_bus_ic_req_ff_in,busclk_force,bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt,clock)//withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)}
|
||||
val bus_cmd_sent = WireInit(Bool(), 0.B)
|
||||
val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
|
||||
bus_cmd_req_hold := rvdffie(bus_cmd_req_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
|
||||
// AXI Read-Channel
|
||||
io.ifu_axi.w.valid := 0.U
|
||||
io.ifu_axi.w.bits.data := 0.U
|
||||
io.ifu_axi.aw.bits.qos := 0.U
|
||||
io.ifu_axi.aw.bits.addr := 0.U
|
||||
io.ifu_axi.aw.bits.prot := 0.U
|
||||
io.ifu_axi.aw.bits.len := 0.U
|
||||
io.ifu_axi.ar.bits.lock := 0.U
|
||||
io.ifu_axi.aw.bits.region := 0.U
|
||||
io.ifu_axi.aw.bits.id := 0.U
|
||||
io.ifu_axi.aw.valid := 0.U
|
||||
io.ifu_axi.w.bits.strb := 0.U
|
||||
io.ifu_axi.aw.bits.cache := 0.U
|
||||
io.ifu_axi.ar.bits.qos := 0.U
|
||||
io.ifu_axi.aw.bits.lock := 0.U
|
||||
io.ifu_axi.b.ready := 0.U
|
||||
io.ifu_axi.ar.bits.len := 0.U
|
||||
io.ifu_axi.aw.bits.size := 0.U
|
||||
io.ifu_axi.ar.bits.prot := 0.U
|
||||
io.ifu_axi.aw.bits.burst := 0.U
|
||||
io.ifu_axi.w.bits.last := 0.U
|
||||
io.ifu_axi <> 0.U.asTypeOf(io.ifu_axi)
|
||||
io.ifu_axi.ar.bits.prot := 5.U
|
||||
io.ifu_axi.ar.valid := ifu_bus_cmd_valid
|
||||
io.ifu_axi.ar.bits.id := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid)
|
||||
io.ifu_axi.ar.bits.addr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid)
|
||||
io.ifu_axi.ar.bits.size := 3.U(3.W)
|
||||
io.ifu_axi.ar.bits.size := 3.U
|
||||
io.ifu_axi.ar.bits.cache := 15.U
|
||||
io.ifu_axi.ar.bits.region := ifu_ic_req_addr_f(28,25)
|
||||
io.ifu_axi.ar.bits.burst := 1.U
|
||||
io.ifu_axi.r.ready := true.B
|
||||
io.ifu_axi.r.ready := 1.B
|
||||
|
||||
val ifu_bus_arready_unq = io.ifu_axi.ar.ready
|
||||
val ifu_bus_rvalid_unq = io.ifu_axi.r.valid
|
||||
val ifu_bus_arvalid = io.ifu_axi.ar.valid
|
||||
val ifu_bus_arready_unq_ff = withClock(busclk){RegNext(ifu_bus_arready_unq, false.B)}
|
||||
val ifu_bus_rvalid_unq_ff = withClock(busclk){RegNext(ifu_bus_rvalid_unq, false.B)}
|
||||
val ifu_bus_arvalid_ff = withClock(busclk){RegNext(ifu_bus_arvalid, false.B)}
|
||||
val ifu_bus_rresp_ff = withClock(busclk){RegNext(io.ifu_axi.r.bits.resp, 0.U)}
|
||||
ifu_bus_rdata_ff := withClock(busclk){RegNext(io.ifu_axi.r.bits.data, 0.U)}
|
||||
ifu_bus_rid_ff := withClock(busclk){RegNext(io.ifu_axi.r.bits.id, 0.U)}
|
||||
ifu_bus_cmd_ready := io.ifu_axi.ar.ready
|
||||
ifu_bus_rsp_valid := io.ifu_axi.r.valid
|
||||
ifu_bus_rsp_ready := io.ifu_axi.r.ready
|
||||
ifu_bus_rsp_tag := io.ifu_axi.r.bits.id
|
||||
ifu_bus_rsp_rdata := io.ifu_axi.r.bits.data
|
||||
val ifu_bus_rsp_opc = io.ifu_axi.r.bits.resp
|
||||
val ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en
|
||||
val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en
|
||||
val ifu_bus_arready_unq_ff = rvdff_fpga(io.ifu_axi.ar.ready,busclk,bus_ifu_bus_clk_en,clock)//withClock(busclk){RegNext(io.ifu_axi.ar.ready, false.B)}
|
||||
val ifu_bus_rvalid_unq_ff = rvdff_fpga(io.ifu_axi.r.valid,busclk,bus_ifu_bus_clk_en,clock)//withClock(busclk){RegNext(io.ifu_axi.r.valid, false.B)}
|
||||
val ifu_bus_arvalid_ff = rvdff_fpga(io.ifu_axi.ar.valid,busclk,bus_ifu_bus_clk_en,clock)//withClock(busclk){RegNext(io.ifu_axi.ar.valid, false.B)}
|
||||
val ifu_bus_rresp_ff = rvdff_fpga(io.ifu_axi.r.bits.resp,busclk,bus_ifu_bus_clk_en,clock)//withClock(busclk){RegNext(io.ifu_axi.r.bits.resp, 0.U)}
|
||||
//withClock(busclk){RegNext(io.ifu_axi.r.bits.data, 0.U)}
|
||||
ifu_bus_rid_ff := rvdff_fpga(io.ifu_axi.r.bits.id,busclk,bus_ifu_bus_clk_en,clock)//withClock(busclk){RegNext(io.ifu_axi.r.bits.id, 0.U)}
|
||||
val ifu_bus_rvalid = io.ifu_axi.r.valid & bus_ifu_bus_clk_en
|
||||
val ifu_bus_arready = io.ifu_axi.ar.ready & bus_ifu_bus_clk_en
|
||||
val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff
|
||||
val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff
|
||||
// Write signals to write to the bus
|
||||
bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_last_data_beat = WireInit(Bool(), false.B)
|
||||
bus_cmd_sent := io.ifu_axi.ar.valid & ifu_bus_arready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_last_data_beat = WireInit(Bool(), 0.B)
|
||||
val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_reset_data_beat_cnt = ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat) | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_hold_data_beat_cnt = !bus_inc_data_beat_cnt & !bus_reset_data_beat_cnt
|
||||
val bus_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
|
||||
bus_new_data_beat_count := Mux1H(Seq(bus_reset_data_beat_cnt->0.U, bus_inc_data_beat_cnt-> (bus_data_beat_count + 1.U), bus_hold_data_beat_cnt->bus_data_beat_count))
|
||||
bus_data_beat_count := withClock(io.free_clk){RegNext(bus_new_data_beat_count, 0.U)}
|
||||
bus_data_beat_count := rvdffie(bus_new_data_beat_count,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(bus_new_data_beat_count, 0.U)}
|
||||
val last_data_recieved_in = (bus_ifu_wr_en_ff & bus_last_data_beat & !scnd_miss_req) | (last_data_recieved_ff & !ic_act_miss_f)
|
||||
last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
|
||||
last_data_recieved_ff := rvdffie(last_data_recieved_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
|
||||
// Request Address Count
|
||||
val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2),
|
||||
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
|
||||
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
|
||||
bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
|
||||
bus_rd_addr_count := rvdff_fpga(bus_new_rd_addr_count,busclk_reset,bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt,clock)//withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
|
||||
// Command beat Count
|
||||
val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & io.ifu_axi.ar.ready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & !uncacheable_miss_in) | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in
|
||||
val bus_hold_cmd_beat_cnt = !bus_inc_cmd_beat_cnt & !(ic_act_miss_f | scnd_miss_req | io.dec_mem_ctrl.dec_tlu_force_halt)
|
||||
val bus_cmd_beat_en = bus_inc_cmd_beat_cnt | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
val bus_new_cmd_beat_count = Mux1H(Seq(bus_reset_cmd_beat_cnt_0->0.U, bus_reset_cmd_beat_cnt_secondlast.asBool->ICACHE_SCND_LAST.U,
|
||||
bus_inc_cmd_beat_cnt->(bus_cmd_beat_count+1.U), bus_hold_cmd_beat_cnt->bus_cmd_beat_count))
|
||||
bus_cmd_beat_count := withClock(busclk_reset){RegEnable(bus_new_cmd_beat_count, 0.U, bus_cmd_beat_en)}
|
||||
bus_cmd_beat_count := rvdffs_fpga(bus_new_cmd_beat_count,bus_cmd_beat_en,busclk_reset,bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt,clock)//withClock(busclk_reset){RegEnable(bus_new_cmd_beat_count, 0.U, bus_cmd_beat_en)}
|
||||
bus_last_data_beat := Mux(uncacheable_miss_ff, bus_data_beat_count===1.U, bus_data_beat_count.andR())
|
||||
bus_ifu_wr_en := ifu_bus_rvalid & miss_pending
|
||||
bus_ifu_wr_en_ff := ifu_bus_rvalid_ff & miss_pending
|
||||
bus_ifu_wr_en_ff_q := ifu_bus_rvalid_ff & miss_pending & !uncacheable_miss_ff & !(ifu_bus_rresp_ff.orR) & write_ic_16_bytes
|
||||
val bus_ifu_wr_en_ff_wo_err = ifu_bus_rvalid_ff & miss_pending & !uncacheable_miss_ff
|
||||
val ic_act_miss_f_delayed = withClock(io.free_clk){RegNext(ic_act_miss_f, false.B)}
|
||||
val ic_act_miss_f_delayed = rvdffie(ic_act_miss_f,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(ic_act_miss_f, false.B)}
|
||||
reset_tag_valid_for_miss := ic_act_miss_f_delayed & (miss_state===crit_byp_ok_C) & !uncacheable_miss_ff
|
||||
bus_ifu_wr_data_error := ifu_bus_rsp_opc.orR() & ifu_bus_rvalid & miss_pending
|
||||
bus_ifu_wr_data_error := io.ifu_axi.r.bits.resp.orR() & ifu_bus_rvalid & miss_pending
|
||||
bus_ifu_wr_data_error_ff := ifu_bus_rresp_ff.orR & ifu_bus_rvalid_ff & miss_pending
|
||||
val ifc_dma_access_ok_d = WireInit(Bool(), false.B)
|
||||
val ifc_dma_access_ok_prev = withClock(io.free_clk){RegNext(ifc_dma_access_ok_d, false.B)}
|
||||
val ifc_dma_access_ok_d = io.ifc_dma_access_ok & !iccm_correct_ecc & !io.iccm_dma_sb_error
|
||||
val ifc_dma_access_ok_prev = rvdffie(ifc_dma_access_ok_d,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(ifc_dma_access_ok_d, false.B)}
|
||||
ic_crit_wd_rdy := ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff
|
||||
last_beat := bus_last_data_beat & bus_ifu_wr_en_ff
|
||||
reset_beat_cnt := bus_reset_data_beat_cnt
|
||||
// DMA
|
||||
ifc_dma_access_ok_d := io.ifc_dma_access_ok & !iccm_correct_ecc & !io.iccm_dma_sb_error
|
||||
val ifc_dma_access_q_ok = io.ifc_dma_access_ok & !iccm_correct_ecc & ifc_dma_access_ok_prev & (perr_state===err_idle_C) & !io.iccm_dma_sb_error
|
||||
io.iccm_ready := ifc_dma_access_q_ok
|
||||
dma_iccm_req_f := withClock(io.free_clk){RegNext(io.dma_mem_ctl.dma_iccm_req, false.B)}
|
||||
io.iccm.wren := (ifc_dma_access_q_ok & io.dma_mem_ctl.dma_iccm_req & io.dma_mem_ctl.dma_mem_write) | iccm_correct_ecc
|
||||
io.iccm.rden := (ifc_dma_access_q_ok & io.dma_mem_ctl.dma_iccm_req & !io.dma_mem_ctl.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
|
||||
val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_mem_ctl.dma_iccm_req & !io.dma_mem_ctl.dma_mem_write
|
||||
|
||||
io.iccm_ready := io.ifc_dma_access_ok & !iccm_correct_ecc & ifc_dma_access_ok_prev & (perr_state===err_idle_C) & !io.iccm_dma_sb_error
|
||||
dma_iccm_req_f := rvdffie(io.dma_mem_ctl.dma_iccm_req,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.dma_mem_ctl.dma_iccm_req, false.B)}
|
||||
io.iccm.wren := (io.iccm_ready & io.dma_mem_ctl.dma_iccm_req & io.dma_mem_ctl.dma_mem_write) | iccm_correct_ecc
|
||||
io.iccm.rden := (io.iccm_ready & io.dma_mem_ctl.dma_iccm_req & !io.dma_mem_ctl.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
|
||||
val iccm_dma_rden = io.iccm_ready & io.dma_mem_ctl.dma_iccm_req & !io.dma_mem_ctl.dma_mem_write
|
||||
io.iccm.wr_size := Fill(3, io.dma_mem_ctl.dma_iccm_req) & io.dma_mem_ctl.dma_mem_sz
|
||||
|
||||
val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_ctl.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_ctl.dma_mem_wdata(31,0)))
|
||||
val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
|
||||
io.iccm.wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_mem_ctl.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
|
||||
io.iccm.wr_data := Mux(iccm_correct_ecc & !(io.iccm_ready & io.dma_mem_ctl.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
|
||||
Cat(dma_mem_ecc(13,7),io.dma_mem_ctl.dma_mem_wdata(63,32), dma_mem_ecc(6,0), io.dma_mem_ctl.dma_mem_wdata(31,0)))
|
||||
val iccm_corrected_data = Wire(Vec(2, UInt(32.W)))
|
||||
iccm_corrected_data(0) := 0.U
|
||||
iccm_corrected_data(1) := 0.U
|
||||
val dma_mem_addr_ff = WireInit(UInt(2.W), 0.U)
|
||||
val iccm_dma_rdata_1_muxed = Mux(dma_mem_addr_ff(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1))
|
||||
val iccm_double_ecc_error = WireInit(UInt(2.W), 0.U)
|
||||
val iccm_dma_ecc_error_in = iccm_double_ecc_error.orR
|
||||
val iccm_dma_rdata_in = Mux(iccm_dma_ecc_error_in, Fill(2, io.dma_mem_ctl.dma_mem_addr), Cat(iccm_dma_rdata_1_muxed, iccm_corrected_data(0)))
|
||||
val dma_mem_tag_ff = withClock(io.free_clk){RegNext(io.dma_mem_ctl.dma_mem_tag, 0.U)}
|
||||
val iccm_dma_rtag_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(dma_mem_tag_ff, 0.U)} else 0.U
|
||||
val iccm_dma_rdata_in = Mux(iccm_double_ecc_error.orR, Fill(2, io.dma_mem_ctl.dma_mem_addr), Cat(iccm_dma_rdata_1_muxed, iccm_corrected_data(0)))
|
||||
val dma_mem_tag_ff = rvdffie(io.dma_mem_ctl.dma_mem_tag,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.dma_mem_ctl.dma_mem_tag, 0.U)}
|
||||
val iccm_dma_rtag_temp = if(ICCM_ENABLE) rvdffie(dma_mem_tag_ff,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) else 0.U
|
||||
io.iccm_dma_rtag := iccm_dma_rtag_temp
|
||||
|
||||
dma_mem_addr_ff := withClock(io.free_clk) {RegNext(io.dma_mem_ctl.dma_mem_addr(3,2), 0.U)}
|
||||
val iccm_dma_rvalid_in = withClock(io.free_clk) {RegNext(iccm_dma_rden, false.B)}
|
||||
val iccm_dma_rvalid_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rvalid_in, false.B)} else 0.U
|
||||
dma_mem_addr_ff := rvdffie(io.dma_mem_ctl.dma_mem_addr(3,2),io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk) {RegNext(io.dma_mem_ctl.dma_mem_addr(3,2), 0.U)}
|
||||
val iccm_dma_rvalid_in = rvdffie(iccm_dma_rden,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk) {RegNext(iccm_dma_rden, false.B)}
|
||||
val iccm_dma_rvalid_temp = if(ICCM_ENABLE) rvdffie(iccm_dma_rvalid_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) else 0.U
|
||||
io.iccm_dma_rvalid := iccm_dma_rvalid_temp
|
||||
val iccm_dma_ecc_error = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_ecc_error_in, false.B)} else 0.U
|
||||
val iccm_dma_ecc_error = if(ICCM_ENABLE) rvdffie(iccm_double_ecc_error.orR,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) else 0.U
|
||||
io.iccm_dma_ecc_error := iccm_dma_ecc_error
|
||||
val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U
|
||||
val iccm_dma_rdata_temp = if(ICCM_ENABLE) rvdffe(iccm_dma_rdata_in,iccm_dma_rvalid_in,clock,io.scan_mode) else 0.U
|
||||
io.iccm_dma_rdata := iccm_dma_rdata_temp
|
||||
val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
|
||||
io.iccm.rw_addr := Mux(ifc_dma_access_q_ok & io.dma_mem_ctl.dma_iccm_req & !iccm_correct_ecc, io.dma_mem_ctl.dma_mem_addr(ICCM_BITS-1,1),
|
||||
Mux(!(ifc_dma_access_q_ok & io.dma_mem_ctl.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
|
||||
io.iccm.rw_addr := Mux(io.iccm_ready & io.dma_mem_ctl.dma_iccm_req & !iccm_correct_ecc, io.dma_mem_ctl.dma_mem_addr(ICCM_BITS-1,1),
|
||||
Mux(!(io.iccm_ready & io.dma_mem_ctl.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
|
||||
val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
|
||||
val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
|
||||
val iccm_rdmux_data = io.iccm.rd_data_ecc
|
||||
// ICCM ECC Check logic
|
||||
val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)).orR & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_mem_ctrl.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_))
|
||||
val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U))
|
||||
val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)).orR & !io.exu_flush_final & fetch_req_iccm_f) | iccm_dma_rvalid_in) & !io.dec_mem_ctrl.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_))
|
||||
val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), io.iccm.rd_data_ecc((39*i+31),(39*i)), io.iccm.rd_data_ecc((39*i+38),(39*i+32)), 0.U))
|
||||
val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W)))
|
||||
iccm_corrected_ecc := VecInit(ecc_decoded(0)._1,ecc_decoded(1)._1)
|
||||
iccm_corrected_data := VecInit(ecc_decoded(0)._2,ecc_decoded(1)._2)
|
||||
iccm_single_ecc_error := Cat(ecc_decoded(1)._3,ecc_decoded(0)._3)
|
||||
iccm_double_ecc_error := Cat(ecc_decoded(1)._4,ecc_decoded(0)._4)
|
||||
if(ICCM_ENABLE){
|
||||
io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err := iccm_single_ecc_error.orR & ifc_iccm_access_f & ifc_fetch_req_f
|
||||
io.iccm_rd_ecc_double_err := iccm_double_ecc_error.orR & ifc_iccm_access_f
|
||||
io.iccm_rd_ecc_double_err := Mux(!ifu_fetch_addr_int_f(0), (Cat(iccm_double_ecc_error(0), iccm_double_ecc_error(0)) ) & Fill(2,ifc_iccm_access_f),
|
||||
(Cat(iccm_double_ecc_error(1), iccm_double_ecc_error(0)) ) & Fill(2,ifc_iccm_access_f))
|
||||
}
|
||||
else {
|
||||
io.iccm_rd_ecc_double_err := 0.U
|
||||
io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err := 0.U
|
||||
}
|
||||
|
||||
val iccm_corrected_data_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1))
|
||||
val iccm_corrected_ecc_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_ecc(0), iccm_corrected_ecc(1))
|
||||
val iccm_rd_ecc_single_err_ff = WireInit(Bool(), false.B)
|
||||
val iccm_rd_ecc_single_err_hold_in = WireInit(Bool(),0.B)
|
||||
val iccm_rd_ecc_single_err_ff = if(ICCM_ENABLE) rvdffie(iccm_rd_ecc_single_err_hold_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) else 0.U
|
||||
val iccm_ecc_write_status = if(ICCM_ENABLE)((io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error else 0.U
|
||||
val iccm_rd_ecc_single_err_hold_in = (io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final
|
||||
iccm_error_start := io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err
|
||||
iccm_rd_ecc_single_err_hold_in := (io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final
|
||||
|
||||
val iccm_rw_addr_f = WireInit(UInt((ICCM_BITS-2).W), 0.U)
|
||||
val iccm_ecc_corr_index_in = Mux(iccm_single_ecc_error(0).asBool(), iccm_rw_addr_f, iccm_rw_addr_f + 1.U)
|
||||
iccm_rw_addr_f := withClock(io.free_clk){RegNext(io.iccm.rw_addr(ICCM_BITS-2,1), 0.U)}
|
||||
iccm_rd_ecc_single_err_ff := withClock(io.free_clk){RegNext(iccm_rd_ecc_single_err_hold_in, false.B)}
|
||||
iccm_ecc_corr_data_ff := withClock(io.free_clk){RegEnable(Cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux), 0.U, iccm_ecc_write_status.asBool())}
|
||||
iccm_ecc_corr_index_ff := withClock(io.free_clk){RegEnable(iccm_ecc_corr_index_in, 0.U, iccm_ecc_write_status.asBool())}
|
||||
iccm_rw_addr_f := rvdffie(io.iccm.rw_addr(ICCM_BITS-2,1),io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
iccm_ecc_corr_data_ff := rvdffe(Cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux),iccm_ecc_write_status,clock,io.scan_mode)//withClock(io.free_clk){RegEnable(Cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux), 0.U, iccm_ecc_write_status.asBool())}
|
||||
if(ICCM_ENABLE) iccm_ecc_corr_index_ff := rvdffe(iccm_ecc_corr_index_in,iccm_ecc_write_status,clock,io.scan_mode) else iccm_ecc_corr_index_ff := 0.U//withClock(io.free_clk){RegEnable(iccm_ecc_corr_index_in, 0.U, iccm_ecc_write_status.asBool())}
|
||||
io.ic.rd_en := (io.ifc_fetch_req_bf & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf &
|
||||
!(((miss_state===stream_C) & !miss_state_en) |
|
||||
((miss_state===crit_byp_ok_C) & !miss_state_en) |
|
||||
|
|
@ -634,66 +600,60 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
|
||||
io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
|
||||
reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)}
|
||||
reset_all_tags := rvdffie(io.dec_mem_ctrl.dec_tlu_fence_i_wb,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)}
|
||||
// I$ status and P-LRU
|
||||
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
|
||||
val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
|
||||
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_status_wr_addr_w_debug, 0.U)
|
||||
}
|
||||
val way_status_wr_en = WireInit(Bool(), false.B)
|
||||
val ifu_status_wr_addr_ff = rvdffie(ifu_status_wr_addr_w_debug,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
val way_status_wr_en = WireInit(Bool(), 0.B)
|
||||
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array)
|
||||
val way_status_wr_en_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_wr_en_w_debug, false.B)
|
||||
}
|
||||
val way_status_wr_en_ff = rvdffie(way_status_wr_en_w_debug,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array,
|
||||
if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new)
|
||||
val way_status_new_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_new_w_debug, 0.U)
|
||||
}
|
||||
val way_status_new_ff = rvdffie(way_status_new_w_debug,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
|
||||
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
|
||||
val way_status_clk = if(RV_FPGA_OPTIMIZE) way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) else (0 until ICACHE_TAG_DEPTH/8).map(i=>0.B.asClock())
|
||||
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
|
||||
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
|
||||
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
|
||||
way_status_out((8 * i) + j) := rvdffs_fpga(way_status_new_ff,(ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff,way_status_clk(i),way_status_clken(i),clock)//withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
|
||||
val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
|
||||
// io.test_way_status_out := test_way_status_out
|
||||
val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
|
||||
//io.test_way_status_clken := test_way_status_clken
|
||||
way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
|
||||
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array,
|
||||
io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
|
||||
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
|
||||
}
|
||||
io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), io.ic.rw_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
ifu_ic_rw_int_addr_ff := rvdffie(ifu_ic_rw_int_addr_w_debug,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
// withClock(io.free_clk) {
|
||||
// RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
|
||||
// }
|
||||
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
|
||||
val ifu_tag_wren_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_tag_wren_w_debug, 0.U)
|
||||
}
|
||||
val ifu_tag_wren_ff = rvdffie(ifu_tag_wren_w_debug,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid)
|
||||
val ic_valid_ff = withClock(io.free_clk) {
|
||||
RegNext(ic_valid_w_debug, false.B)
|
||||
}
|
||||
val ic_valid_ff =rvdffie(ic_valid_w_debug,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
|
||||
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
|
||||
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
|
||||
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
|
||||
reset_all_tags).reverse.reduce(Cat(_, _)))
|
||||
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
|
||||
val tag_valid_clk = if(RV_FPGA_OPTIMIZE) (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) else (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => 0.B.asClock()))
|
||||
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
|
||||
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
|
||||
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
|
||||
|
||||
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
|
||||
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
|
||||
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
|
||||
|
||||
ic_tag_valid_out(j)((32 * i) + k) := rvdffs_fpga(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate,(((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags),tag_valid_clk(i)(j),tag_valid_clken(i)(j),clock)
|
||||
val ic_tag_valid_unq = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
|
||||
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
|
||||
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), 0.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
|
||||
else 0.U(ICACHE_NUM_WAYS.W)
|
||||
// Making sudo LRU
|
||||
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
|
|
@ -706,10 +666,10 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
(!tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
|
||||
|
||||
way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
|
||||
way_status_hit_new := Mux1H(Seq((!io.exu_flush_final & io.ic.rd_hit(0)) -> Cat(way_status(2), 3.U),
|
||||
(!io.exu_flush_final & io.ic.rd_hit(1)) -> Cat(way_status(2), 1.U(2.W)),
|
||||
(!io.exu_flush_final & io.ic.rd_hit(2)) -> Cat(1.U, way_status(1), 0.U),
|
||||
(!io.exu_flush_final & io.ic.rd_hit(3)) -> Cat(0.U, way_status(1), 0.U)))
|
||||
|
||||
way_status_rep_new := Mux1H(Seq(replace_way_mb_any(0).asBool -> Cat(way_status_mb_ff(2), 3.U),
|
||||
replace_way_mb_any(1).asBool -> Cat(way_status_mb_ff(2), 1.U(2.W)),
|
||||
|
|
@ -739,16 +699,16 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
way_status_new := 0.U
|
||||
way_status_wr_en := 0.U
|
||||
}
|
||||
io.ic.tag_valid := ic_tag_valid_unq & Fill(ICACHE_NUM_WAYS, !fetch_uncacheable_ff & ifc_fetch_req_f)
|
||||
io.ic.tag_valid := ic_tag_valid_unq & Fill(ICACHE_NUM_WAYS, !fetch_uncacheable_ff & ifc_fetch_req_f_raw)
|
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|
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val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR()
|
||||
|
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io.dec_mem_ctrl.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)}
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||||
io.dec_mem_ctrl.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)}
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io.dec_mem_ctrl.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)}
|
||||
io.dec_mem_ctrl.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)}
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io.dec_mem_ctrl.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)}
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io.dec_mem_ctrl.ifu_pmu_ic_miss := rvdffie(ic_act_miss_f,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)}
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io.dec_mem_ctrl.ifu_pmu_ic_hit := rvdffie(ic_act_hit_f,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)}
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io.dec_mem_ctrl.ifu_pmu_bus_error := rvdffie(ifc_bus_acc_fault_f.orR,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f.orR, false.B)}
|
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io.dec_mem_ctrl.ifu_pmu_bus_busy := rvdffie(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)}
|
||||
io.dec_mem_ctrl.ifu_pmu_bus_trxn := rvdffie(bus_cmd_sent,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)}
|
||||
|
||||
|
||||
io.ic.debug_addr := io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics
|
||||
|
|
@ -759,10 +719,10 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===1.U, io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===0.U)
|
||||
ic_debug_tag_wr_en := Fill(ICACHE_NUM_WAYS, io.ic.debug_wr_en & io.ic.debug_tag_array) & io.ic.debug_way
|
||||
val ic_debug_ict_array_sel_in = io.ic.debug_rd_en & io.ic.debug_tag_array
|
||||
ic_debug_way_ff := withClock(debug_c1_clk){RegNext(io.ic.debug_way, 0.U)}
|
||||
ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
|
||||
ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic.debug_rd_en, false.B)}
|
||||
io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)}
|
||||
ic_debug_way_ff := rvdff_fpga(io.ic.debug_way,debug_c1_clk,debug_c1_clken,clock)//withClock(debug_c1_clk){RegNext(io.ic.debug_way, 0.U)}
|
||||
ic_debug_ict_array_sel_ff := rvdff_fpga(ic_debug_ict_array_sel_in,debug_c1_clk,debug_c1_clken,clock)//withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
|
||||
ic_debug_rd_en_ff := rvdffie(io.ic.debug_rd_en,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.ic.debug_rd_en, false.B)}
|
||||
io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := rvdffie(ic_debug_rd_en_ff,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ic_debug_rd_en_ff, 0.U)}
|
||||
// Memory protection each access enable with its Mask
|
||||
val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) |
|
||||
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
|
||||
|
|
@ -773,9 +733,13 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
|
||||
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
|
||||
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
|
||||
dontTouch(ifc_region_acc_okay)
|
||||
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
|
||||
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
|
||||
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
|
||||
ifc_region_acc_fault_memory_f := rvdffie(ifc_region_acc_fault_memory_bf,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.active_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
|
||||
|
||||
}
|
||||
|
||||
//object ifumem_ctl extends App {
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_mem_ctl()))
|
||||
//}
|
||||
|
|
|
|||
|
|
@ -381,6 +381,11 @@ trait lib extends param{
|
|||
withClock(rawclk) {RegEnable (din, 0.U, clken)}
|
||||
else withClock(clk) {RegNext (din, 0.U)}
|
||||
}
|
||||
def apply(din: Bool, clk: Clock, clken: Bool,rawclk:Clock) = {
|
||||
if (RV_FPGA_OPTIMIZE)
|
||||
withClock(rawclk) {RegEnable (din, 0.B, clken)}
|
||||
else withClock(clk) {RegNext (din, 0.B)}
|
||||
}
|
||||
}
|
||||
object rvdffs_fpga {
|
||||
def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock) = {
|
||||
|
|
|
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Reference in New Issue