obuf_timer corrected
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parent
3de7adb50f
commit
33a4c11f1c
2
lsu.fir
2
lsu.fir
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@ -10798,7 +10798,7 @@ circuit lsu :
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obuf_data <= obuf_data_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when obuf_wr_en : @[Reg.scala 28:19]
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when io.lsu_busm_clken : @[Reg.scala 28:19]
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_T_1791 <= obuf_wr_timer_in @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 367:17]
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2
lsu.v
2
lsu.v
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@ -8929,7 +8929,7 @@ end // initial
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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obuf_wr_timer <= 3'h0;
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end else if (obuf_wr_en) begin
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end else if (io_lsu_busm_clken) begin
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if (obuf_wr_en) begin
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obuf_wr_timer <= 3'h0;
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end else if (_T_1058) begin
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@ -364,7 +364,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
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val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
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obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode)
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val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode)
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obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,obuf_wr_en,clock)
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obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
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val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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