LSU Paramtere problem
This commit is contained in:
waleed-lm
parent
95f191bcb9
commit
7d4de00f76
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@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
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<module external.linked.project.id="quasar-master [file:/home/waleedbinehsan/Desktop/Quasar-master/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
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<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
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<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
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<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
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@ -1,34 +0,0 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hready",
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"sources":[
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"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hresp",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_aw_valid",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_aw_ready",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_ar_valid",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_ar_ready"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"ahb_to_axi4.gated_latch",
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"resourceId":"/vsrc/gated_latch.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"ahb_to_axi4"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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615
ahb_to_axi4.fir
615
ahb_to_axi4.fir
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@ -1,615 +0,0 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit ahb_to_axi4 :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_5 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module ahb_to_axi4 :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}}
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wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25]
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_T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10]
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_T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10]
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_T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10]
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_T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10]
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_T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10]
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io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10]
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io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10]
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_T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10]
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_T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10]
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_T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10]
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_T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10]
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io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10]
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io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10]
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_T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10]
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io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10]
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_T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10]
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wire master_wstrb : UInt<8>
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master_wstrb <= UInt<8>("h00")
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wire buf_state_en : UInt<1>
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buf_state_en <= UInt<1>("h00")
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wire buf_read_error_in : UInt<1>
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buf_read_error_in <= UInt<1>("h00")
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wire buf_read_error : UInt<1>
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buf_read_error <= UInt<1>("h00")
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wire buf_rdata : UInt<64>
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||||
buf_rdata <= UInt<64>("h00")
|
||||
wire ahb_hready : UInt<1>
|
||||
ahb_hready <= UInt<1>("h00")
|
||||
wire ahb_hready_q : UInt<1>
|
||||
ahb_hready_q <= UInt<1>("h00")
|
||||
wire ahb_htrans_in : UInt<2>
|
||||
ahb_htrans_in <= UInt<2>("h00")
|
||||
wire ahb_htrans_q : UInt<2>
|
||||
ahb_htrans_q <= UInt<2>("h00")
|
||||
wire ahb_hsize_q : UInt<3>
|
||||
ahb_hsize_q <= UInt<3>("h00")
|
||||
wire ahb_hwrite_q : UInt<1>
|
||||
ahb_hwrite_q <= UInt<1>("h00")
|
||||
wire ahb_haddr_q : UInt<32>
|
||||
ahb_haddr_q <= UInt<32>("h00")
|
||||
wire ahb_hwdata_q : UInt<64>
|
||||
ahb_hwdata_q <= UInt<64>("h00")
|
||||
wire ahb_hresp_q : UInt<1>
|
||||
ahb_hresp_q <= UInt<1>("h00")
|
||||
wire buf_rdata_en : UInt<1>
|
||||
buf_rdata_en <= UInt<1>("h00")
|
||||
wire ahb_bus_addr_clk_en : UInt<1>
|
||||
ahb_bus_addr_clk_en <= UInt<1>("h00")
|
||||
wire buf_rdata_clk_en : UInt<1>
|
||||
buf_rdata_clk_en <= UInt<1>("h00")
|
||||
wire ahb_clk : Clock @[ahb_to_axi4.scala 44:33]
|
||||
wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 45:33]
|
||||
wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 46:33]
|
||||
wire cmdbuf_wr_en : UInt<1>
|
||||
cmdbuf_wr_en <= UInt<1>("h00")
|
||||
wire cmdbuf_rst : UInt<1>
|
||||
cmdbuf_rst <= UInt<1>("h00")
|
||||
wire cmdbuf_full : UInt<1>
|
||||
cmdbuf_full <= UInt<1>("h00")
|
||||
wire cmdbuf_vld : UInt<1>
|
||||
cmdbuf_vld <= UInt<1>("h00")
|
||||
wire cmdbuf_write : UInt<1>
|
||||
cmdbuf_write <= UInt<1>("h00")
|
||||
wire cmdbuf_size : UInt<2>
|
||||
cmdbuf_size <= UInt<2>("h00")
|
||||
wire cmdbuf_wstrb : UInt<8>
|
||||
cmdbuf_wstrb <= UInt<8>("h00")
|
||||
wire cmdbuf_addr : UInt<32>
|
||||
cmdbuf_addr <= UInt<32>("h00")
|
||||
wire cmdbuf_wdata : UInt<64>
|
||||
cmdbuf_wdata <= UInt<64>("h00")
|
||||
wire bus_clk : Clock @[ahb_to_axi4.scala 58:33]
|
||||
node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
|
||||
node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47]
|
||||
node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
|
||||
node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29]
|
||||
node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
|
||||
node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47]
|
||||
node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
|
||||
node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29]
|
||||
node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
|
||||
node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47]
|
||||
node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14]
|
||||
node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29]
|
||||
wire buf_state : UInt<2>
|
||||
buf_state <= UInt<2>("h00")
|
||||
wire buf_nxtstate : UInt<2>
|
||||
buf_nxtstate <= UInt<2>("h00")
|
||||
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 68:31]
|
||||
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31]
|
||||
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31]
|
||||
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31]
|
||||
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31]
|
||||
node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_7 : @[Conditional.scala 40:58]
|
||||
node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 76:26]
|
||||
buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 76:20]
|
||||
node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 77:57]
|
||||
node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 77:34]
|
||||
node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 77:61]
|
||||
buf_state_en <= _T_11 @[ahb_to_axi4.scala 77:20]
|
||||
skip @[Conditional.scala 40:58]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_12 : @[Conditional.scala 39:67]
|
||||
node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:72]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 80:79]
|
||||
node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 80:48]
|
||||
node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 80:93]
|
||||
node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 80:91]
|
||||
node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 80:107]
|
||||
node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 80:124]
|
||||
node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 80:26]
|
||||
buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 80:20]
|
||||
node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:24]
|
||||
node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 81:37]
|
||||
buf_state_en <= _T_22 @[ahb_to_axi4.scala 81:20]
|
||||
node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:23]
|
||||
node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 82:85]
|
||||
node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 82:92]
|
||||
node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 82:110]
|
||||
node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 82:60]
|
||||
node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 82:38]
|
||||
node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 82:36]
|
||||
cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 82:20]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_30 : @[Conditional.scala 39:67]
|
||||
node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 85:26]
|
||||
buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 85:20]
|
||||
node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:24]
|
||||
node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 86:37]
|
||||
buf_state_en <= _T_33 @[ahb_to_axi4.scala 86:20]
|
||||
node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 87:23]
|
||||
node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:46]
|
||||
node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 87:44]
|
||||
cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 87:20]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_37 : @[Conditional.scala 39:67]
|
||||
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 90:20]
|
||||
node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 91:40]
|
||||
node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 91:38]
|
||||
buf_state_en <= _T_39 @[ahb_to_axi4.scala 91:20]
|
||||
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 92:20]
|
||||
node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 93:61]
|
||||
node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 93:68]
|
||||
node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 93:41]
|
||||
buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 93:25]
|
||||
skip @[Conditional.scala 39:67]
|
||||
node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 96:99]
|
||||
reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_43 : @[Reg.scala 28:19]
|
||||
_T_44 <= buf_nxtstate @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
buf_state <= _T_44 @[ahb_to_axi4.scala 96:31]
|
||||
node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:54]
|
||||
node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 98:60]
|
||||
node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:92]
|
||||
node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 98:78]
|
||||
node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 98:70]
|
||||
node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24]
|
||||
node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 99:30]
|
||||
node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62]
|
||||
node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 99:48]
|
||||
node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 99:40]
|
||||
node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 98:109]
|
||||
node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24]
|
||||
node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 100:30]
|
||||
node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62]
|
||||
node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 100:48]
|
||||
node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 100:40]
|
||||
node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 99:79]
|
||||
node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24]
|
||||
node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 101:30]
|
||||
node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 101:40]
|
||||
node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 100:79]
|
||||
master_wstrb <= _T_73 @[ahb_to_axi4.scala 98:31]
|
||||
node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 104:80]
|
||||
node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 104:78]
|
||||
node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 104:98]
|
||||
node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 104:124]
|
||||
node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 104:111]
|
||||
node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 104:149]
|
||||
node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 104:168]
|
||||
node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 104:156]
|
||||
node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 104:137]
|
||||
node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 104:135]
|
||||
node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 104:181]
|
||||
node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 104:179]
|
||||
node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 104:44]
|
||||
io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 104:38]
|
||||
node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 105:55]
|
||||
ahb_hready <= _T_87 @[ahb_to_axi4.scala 105:31]
|
||||
node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 106:77]
|
||||
node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 106:54]
|
||||
ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 106:31]
|
||||
node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 107:50]
|
||||
io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 107:38]
|
||||
node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 108:55]
|
||||
node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 108:61]
|
||||
node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 108:83]
|
||||
node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 108:70]
|
||||
node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 109:26]
|
||||
node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 109:7]
|
||||
node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 110:46]
|
||||
node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 110:26]
|
||||
node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:80]
|
||||
node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 110:86]
|
||||
node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:109]
|
||||
node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 110:115]
|
||||
node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 110:95]
|
||||
node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 110:66]
|
||||
node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 110:64]
|
||||
node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 109:47]
|
||||
node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20]
|
||||
node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 111:26]
|
||||
node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 111:48]
|
||||
node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 111:35]
|
||||
node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 110:126]
|
||||
node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20]
|
||||
node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 112:26]
|
||||
node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 112:49]
|
||||
node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 112:56]
|
||||
node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 112:35]
|
||||
node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 111:55]
|
||||
node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20]
|
||||
node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 113:26]
|
||||
node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 113:49]
|
||||
node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 113:56]
|
||||
node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 113:35]
|
||||
node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 112:61]
|
||||
node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 108:94]
|
||||
node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 113:63]
|
||||
node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 115:20]
|
||||
node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 115:18]
|
||||
node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 114:20]
|
||||
io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 108:38]
|
||||
reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:66]
|
||||
_T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 118:66]
|
||||
buf_rdata <= _T_131 @[ahb_to_axi4.scala 118:31]
|
||||
reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:60]
|
||||
_T_132 <= buf_read_error_in @[ahb_to_axi4.scala 119:60]
|
||||
buf_read_error <= _T_132 @[ahb_to_axi4.scala 119:31]
|
||||
reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60]
|
||||
_T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 122:60]
|
||||
ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 122:31]
|
||||
reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60]
|
||||
_T_134 <= ahb_hready @[ahb_to_axi4.scala 123:60]
|
||||
ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 123:31]
|
||||
reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60]
|
||||
_T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 124:60]
|
||||
ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 124:31]
|
||||
reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65]
|
||||
_T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 125:65]
|
||||
ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 125:31]
|
||||
reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65]
|
||||
_T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 126:65]
|
||||
ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 126:31]
|
||||
reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65]
|
||||
_T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 127:65]
|
||||
ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 127:31]
|
||||
node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 130:85]
|
||||
node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 130:62]
|
||||
node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 130:48]
|
||||
ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 130:31]
|
||||
node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 131:48]
|
||||
buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 131:31]
|
||||
inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
|
||||
rvclkhdr.clock <= clock
|
||||
rvclkhdr.reset <= reset
|
||||
rvclkhdr.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16]
|
||||
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 133:31]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16]
|
||||
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 134:31]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22]
|
||||
rvclkhdr_2.clock <= clock
|
||||
rvclkhdr_2.reset <= reset
|
||||
rvclkhdr_2.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16]
|
||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 135:31]
|
||||
node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:53]
|
||||
node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:91]
|
||||
node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 137:72]
|
||||
node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 137:113]
|
||||
node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 137:111]
|
||||
node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 137:153]
|
||||
node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 137:151]
|
||||
node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 137:128]
|
||||
cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 137:31]
|
||||
node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:67]
|
||||
node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:105]
|
||||
node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 138:86]
|
||||
node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 138:48]
|
||||
node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 138:46]
|
||||
cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 138:31]
|
||||
node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 140:86]
|
||||
node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 140:66]
|
||||
node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 140:110]
|
||||
node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 140:108]
|
||||
reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 140:61]
|
||||
_T_160 <= _T_159 @[ahb_to_axi4.scala 140:61]
|
||||
cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 140:31]
|
||||
node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:53]
|
||||
reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_161 : @[Reg.scala 28:19]
|
||||
_T_162 <= ahb_hwrite_q @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 143:31]
|
||||
node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:52]
|
||||
reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_163 : @[Reg.scala 28:19]
|
||||
_T_164 <= ahb_hsize_q @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 146:31]
|
||||
node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:53]
|
||||
reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_165 : @[Reg.scala 28:19]
|
||||
_T_166 <= master_wstrb @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 149:31]
|
||||
node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:57]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
|
||||
rvclkhdr_3.clock <= clock
|
||||
rvclkhdr_3.reset <= reset
|
||||
rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18]
|
||||
rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17]
|
||||
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
_T_168 <= ahb_haddr_q @[lib.scala 374:16]
|
||||
cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 153:15]
|
||||
node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:68]
|
||||
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23]
|
||||
rvclkhdr_4.clock <= clock
|
||||
rvclkhdr_4.reset <= reset
|
||||
rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18]
|
||||
rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17]
|
||||
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
_T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16]
|
||||
cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 154:16]
|
||||
node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 157:42]
|
||||
io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 157:28]
|
||||
io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 158:33]
|
||||
io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 159:33]
|
||||
node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 160:59]
|
||||
node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58]
|
||||
io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 160:33]
|
||||
node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 161:33]
|
||||
node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 162:33]
|
||||
io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 163:33]
|
||||
node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 165:42]
|
||||
io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 165:28]
|
||||
io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 166:33]
|
||||
io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 167:33]
|
||||
io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 168:33]
|
||||
io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 170:28]
|
||||
node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 172:44]
|
||||
node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 172:42]
|
||||
io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 172:28]
|
||||
io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 173:33]
|
||||
io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 174:33]
|
||||
node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 175:59]
|
||||
node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58]
|
||||
io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 175:33]
|
||||
node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 176:33]
|
||||
node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 177:33]
|
||||
io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 178:33]
|
||||
io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 180:28]
|
||||
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22]
|
||||
rvclkhdr_5.clock <= clock
|
||||
rvclkhdr_5.reset <= reset
|
||||
rvclkhdr_5.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16]
|
||||
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 181:27]
|
||||
|
||||
584
ahb_to_axi4.v
584
ahb_to_axi4.v
|
|
@ -1,584 +0,0 @@
|
|||
module rvclkhdr(
|
||||
output io_l1clk,
|
||||
input io_clk,
|
||||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[lib.scala 334:26]
|
||||
wire clkhdr_CK; // @[lib.scala 334:26]
|
||||
wire clkhdr_EN; // @[lib.scala 334:26]
|
||||
wire clkhdr_SE; // @[lib.scala 334:26]
|
||||
gated_latch clkhdr ( // @[lib.scala 334:26]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
|
||||
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
|
||||
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
|
||||
assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
|
||||
endmodule
|
||||
module ahb_to_axi4(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_scan_mode,
|
||||
input io_bus_clk_en,
|
||||
input io_clk_override,
|
||||
input io_axi_aw_ready,
|
||||
output io_axi_aw_valid,
|
||||
output io_axi_aw_bits_id,
|
||||
output [31:0] io_axi_aw_bits_addr,
|
||||
output [3:0] io_axi_aw_bits_region,
|
||||
output [7:0] io_axi_aw_bits_len,
|
||||
output [2:0] io_axi_aw_bits_size,
|
||||
output [1:0] io_axi_aw_bits_burst,
|
||||
output io_axi_aw_bits_lock,
|
||||
output [3:0] io_axi_aw_bits_cache,
|
||||
output [2:0] io_axi_aw_bits_prot,
|
||||
output [3:0] io_axi_aw_bits_qos,
|
||||
input io_axi_w_ready,
|
||||
output io_axi_w_valid,
|
||||
output [63:0] io_axi_w_bits_data,
|
||||
output [7:0] io_axi_w_bits_strb,
|
||||
output io_axi_w_bits_last,
|
||||
output io_axi_b_ready,
|
||||
input io_axi_b_valid,
|
||||
input [1:0] io_axi_b_bits_resp,
|
||||
input io_axi_b_bits_id,
|
||||
input io_axi_ar_ready,
|
||||
output io_axi_ar_valid,
|
||||
output io_axi_ar_bits_id,
|
||||
output [31:0] io_axi_ar_bits_addr,
|
||||
output [3:0] io_axi_ar_bits_region,
|
||||
output [7:0] io_axi_ar_bits_len,
|
||||
output [2:0] io_axi_ar_bits_size,
|
||||
output [1:0] io_axi_ar_bits_burst,
|
||||
output io_axi_ar_bits_lock,
|
||||
output [3:0] io_axi_ar_bits_cache,
|
||||
output [2:0] io_axi_ar_bits_prot,
|
||||
output [3:0] io_axi_ar_bits_qos,
|
||||
output io_axi_r_ready,
|
||||
input io_axi_r_valid,
|
||||
input io_axi_r_bits_id,
|
||||
input [63:0] io_axi_r_bits_data,
|
||||
input [1:0] io_axi_r_bits_resp,
|
||||
input io_axi_r_bits_last,
|
||||
output [63:0] io_ahb_sig_in_hrdata,
|
||||
output io_ahb_sig_in_hready,
|
||||
output io_ahb_sig_in_hresp,
|
||||
input [31:0] io_ahb_sig_out_haddr,
|
||||
input [2:0] io_ahb_sig_out_hburst,
|
||||
input io_ahb_sig_out_hmastlock,
|
||||
input [3:0] io_ahb_sig_out_hprot,
|
||||
input [2:0] io_ahb_sig_out_hsize,
|
||||
input [1:0] io_ahb_sig_out_htrans,
|
||||
input io_ahb_sig_out_hwrite,
|
||||
input [63:0] io_ahb_sig_out_hwdata,
|
||||
input io_ahb_hsel,
|
||||
input io_ahb_hreadyin
|
||||
);
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [31:0] _RAND_6;
|
||||
reg [31:0] _RAND_7;
|
||||
reg [63:0] _RAND_8;
|
||||
reg [31:0] _RAND_9;
|
||||
reg [31:0] _RAND_10;
|
||||
reg [31:0] _RAND_11;
|
||||
reg [31:0] _RAND_12;
|
||||
reg [31:0] _RAND_13;
|
||||
reg [63:0] _RAND_14;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire rvclkhdr_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_1_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_1_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_2_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_2_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_3_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_3_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_4_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_4_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_5_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_5_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31]
|
||||
reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 127:65]
|
||||
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29]
|
||||
wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29]
|
||||
wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31]
|
||||
reg [1:0] buf_state; // @[Reg.scala 27:20]
|
||||
wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
|
||||
wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 105:55]
|
||||
wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 77:34]
|
||||
wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 77:61]
|
||||
wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
|
||||
wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 80:79]
|
||||
wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 80:48]
|
||||
wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 80:93]
|
||||
wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 80:91]
|
||||
wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27]
|
||||
reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61]
|
||||
wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67]
|
||||
wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105]
|
||||
wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86]
|
||||
wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48]
|
||||
wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46]
|
||||
wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24]
|
||||
wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 81:37]
|
||||
wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 82:92]
|
||||
wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 82:110]
|
||||
wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 82:60]
|
||||
wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 82:38]
|
||||
wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 82:36]
|
||||
wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
|
||||
wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 87:23]
|
||||
wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 87:44]
|
||||
wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
|
||||
reg cmdbuf_write; // @[Reg.scala 27:20]
|
||||
wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 91:40]
|
||||
wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 91:38]
|
||||
wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 93:68]
|
||||
wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67]
|
||||
wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67]
|
||||
wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67]
|
||||
wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58]
|
||||
wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 93:41]
|
||||
wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67]
|
||||
wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67]
|
||||
wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67]
|
||||
wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67]
|
||||
wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67]
|
||||
wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
|
||||
wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
|
||||
wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
|
||||
reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 125:65]
|
||||
wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 98:60]
|
||||
wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:78]
|
||||
wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 98:70]
|
||||
wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 99:30]
|
||||
wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48]
|
||||
wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 99:40]
|
||||
wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 99:40]
|
||||
wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 98:109]
|
||||
wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 98:109]
|
||||
wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 100:30]
|
||||
wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 100:48]
|
||||
wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 100:40]
|
||||
wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 100:40]
|
||||
wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 99:79]
|
||||
wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 99:79]
|
||||
wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 101:30]
|
||||
wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 100:79]
|
||||
wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 100:79]
|
||||
reg ahb_hready_q; // @[ahb_to_axi4.scala 123:60]
|
||||
wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 104:80]
|
||||
reg ahb_hresp_q; // @[ahb_to_axi4.scala 122:60]
|
||||
wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 104:78]
|
||||
wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 104:124]
|
||||
wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 104:111]
|
||||
wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 104:149]
|
||||
wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 104:168]
|
||||
wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 104:156]
|
||||
wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 104:137]
|
||||
wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 104:135]
|
||||
reg buf_read_error; // @[ahb_to_axi4.scala 119:60]
|
||||
wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 104:181]
|
||||
wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 104:179]
|
||||
wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 46:33 ahb_to_axi4.scala 135:31]
|
||||
reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 118:66]
|
||||
reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 124:60]
|
||||
wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 108:61]
|
||||
wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 108:83]
|
||||
wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 108:70]
|
||||
wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 109:26]
|
||||
wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 109:7]
|
||||
reg ahb_hwrite_q; // @[ahb_to_axi4.scala 126:65]
|
||||
wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 110:46]
|
||||
wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 110:26]
|
||||
wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 110:86]
|
||||
wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 110:115]
|
||||
wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 110:95]
|
||||
wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 110:66]
|
||||
wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 110:64]
|
||||
wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 109:47]
|
||||
wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 111:35]
|
||||
wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 110:126]
|
||||
wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 112:56]
|
||||
wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 112:35]
|
||||
wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 111:55]
|
||||
wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 113:56]
|
||||
wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 113:35]
|
||||
wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 112:61]
|
||||
wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 108:94]
|
||||
wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 113:63]
|
||||
wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 137:113]
|
||||
wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 137:111]
|
||||
wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 137:151]
|
||||
wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 137:128]
|
||||
wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66]
|
||||
wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110]
|
||||
reg [2:0] _T_164; // @[Reg.scala 27:20]
|
||||
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
|
||||
wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 98:31]
|
||||
reg [31:0] cmdbuf_addr; // @[lib.scala 374:16]
|
||||
reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16]
|
||||
wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 146:31]
|
||||
rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||
.io_clk(rvclkhdr_2_io_clk),
|
||||
.io_en(rvclkhdr_2_io_en),
|
||||
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
|
||||
.io_l1clk(rvclkhdr_3_io_l1clk),
|
||||
.io_clk(rvclkhdr_3_io_clk),
|
||||
.io_en(rvclkhdr_3_io_en),
|
||||
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23]
|
||||
.io_l1clk(rvclkhdr_4_io_l1clk),
|
||||
.io_clk(rvclkhdr_4_io_clk),
|
||||
.io_en(rvclkhdr_4_io_en),
|
||||
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_5_io_l1clk),
|
||||
.io_clk(rvclkhdr_5_io_clk),
|
||||
.io_en(rvclkhdr_5_io_en),
|
||||
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
||||
);
|
||||
assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28]
|
||||
assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33]
|
||||
assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33]
|
||||
assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 162:33]
|
||||
assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33]
|
||||
assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 163:33]
|
||||
assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 161:33]
|
||||
assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:28]
|
||||
assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33]
|
||||
assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:33]
|
||||
assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 168:33]
|
||||
assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 170:28]
|
||||
assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28]
|
||||
assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33]
|
||||
assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33]
|
||||
assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 177:33]
|
||||
assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33]
|
||||
assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 178:33]
|
||||
assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 176:33]
|
||||
assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 180:28]
|
||||
assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 107:38]
|
||||
assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 104:38]
|
||||
assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 108:38]
|
||||
assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
ahb_haddr_q = _RAND_0[31:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
buf_state = _RAND_1[1:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
cmdbuf_vld = _RAND_2[0:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
cmdbuf_write = _RAND_3[0:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
ahb_hsize_q = _RAND_4[2:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
ahb_hready_q = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
ahb_hresp_q = _RAND_6[0:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
buf_read_error = _RAND_7[0:0];
|
||||
_RAND_8 = {2{`RANDOM}};
|
||||
buf_rdata = _RAND_8[63:0];
|
||||
_RAND_9 = {1{`RANDOM}};
|
||||
ahb_htrans_q = _RAND_9[1:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
ahb_hwrite_q = _RAND_10[0:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
_T_164 = _RAND_11[2:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
cmdbuf_wstrb = _RAND_12[7:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
cmdbuf_addr = _RAND_13[31:0];
|
||||
_RAND_14 = {2{`RANDOM}};
|
||||
cmdbuf_wdata = _RAND_14[63:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
ahb_haddr_q = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_state = 2'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_vld = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_write = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hsize_q = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hready_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hresp_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_read_error = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_rdata = 64'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_htrans_q = 2'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hwrite_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_164 = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_wstrb = 8'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_addr = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_wdata = 64'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge ahb_addr_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_haddr_q <= 32'h0;
|
||||
end else begin
|
||||
ahb_haddr_q <= io_ahb_sig_out_haddr;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
buf_state <= 2'h0;
|
||||
end else if (buf_state_en) begin
|
||||
if (_T_7) begin
|
||||
if (io_ahb_sig_out_hwrite) begin
|
||||
buf_state <= 2'h1;
|
||||
end else begin
|
||||
buf_state <= 2'h2;
|
||||
end
|
||||
end else if (_T_12) begin
|
||||
if (_T_17) begin
|
||||
buf_state <= 2'h0;
|
||||
end else if (io_ahb_sig_out_hwrite) begin
|
||||
buf_state <= 2'h1;
|
||||
end else begin
|
||||
buf_state <= 2'h2;
|
||||
end
|
||||
end else if (_T_30) begin
|
||||
if (io_ahb_sig_in_hresp) begin
|
||||
buf_state <= 2'h0;
|
||||
end else begin
|
||||
buf_state <= 2'h3;
|
||||
end
|
||||
end else begin
|
||||
buf_state <= 2'h0;
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(posedge bus_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_vld <= 1'h0;
|
||||
end else begin
|
||||
cmdbuf_vld <= _T_157 & _T_158;
|
||||
end
|
||||
end
|
||||
always @(posedge bus_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_write <= 1'h0;
|
||||
end else if (cmdbuf_wr_en) begin
|
||||
cmdbuf_write <= ahb_hwrite_q;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_addr_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hsize_q <= 3'h0;
|
||||
end else begin
|
||||
ahb_hsize_q <= io_ahb_sig_out_hsize;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hready_q <= 1'h0;
|
||||
end else begin
|
||||
ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hresp_q <= 1'h0;
|
||||
end else begin
|
||||
ahb_hresp_q <= io_ahb_sig_in_hresp;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else if (_T_7) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else if (_T_12) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else if (_T_30) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else begin
|
||||
buf_read_error <= _GEN_3;
|
||||
end
|
||||
end
|
||||
always @(posedge buf_rdata_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
buf_rdata <= 64'h0;
|
||||
end else begin
|
||||
buf_rdata <= io_axi_r_bits_data;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_htrans_q <= 2'h0;
|
||||
end else begin
|
||||
ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans;
|
||||
end
|
||||
end
|
||||
always @(posedge ahb_addr_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hwrite_q <= 1'h0;
|
||||
end else begin
|
||||
ahb_hwrite_q <= io_ahb_sig_out_hwrite;
|
||||
end
|
||||
end
|
||||
always @(posedge bus_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_164 <= 3'h0;
|
||||
end else if (cmdbuf_wr_en) begin
|
||||
_T_164 <= ahb_hsize_q;
|
||||
end
|
||||
end
|
||||
always @(posedge bus_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_wstrb <= 8'h0;
|
||||
end else if (cmdbuf_wr_en) begin
|
||||
cmdbuf_wstrb <= master_wstrb;
|
||||
end
|
||||
end
|
||||
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_addr <= 32'h0;
|
||||
end else begin
|
||||
cmdbuf_addr <= ahb_haddr_q;
|
||||
end
|
||||
end
|
||||
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_wdata <= 64'h0;
|
||||
end else begin
|
||||
cmdbuf_wdata <= io_ahb_sig_out_hwdata;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"axi4_to_ahb.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"axi4_to_ahb"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
1406
axi4_to_ahb.fir
1406
axi4_to_ahb.fir
File diff suppressed because it is too large
Load Diff
1139
axi4_to_ahb.v
1139
axi4_to_ahb.v
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,89 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_valid",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
|
||||
"~dbg|dbg>io_dbg_dma_io_dma_dbg_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dbg_dma_io_dma_dbg_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_addr",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_addr"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_dma_dbg_dctl_dbg_cmd_wrdata",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dbg_dec_dbg_dctl_dbg_cmd_wrdata"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_type",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_type"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_write",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_write"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dbg|dbg>io_dbg_resume_req",
|
||||
"sources":[
|
||||
"~dbg|dbg>io_dec_tlu_mpc_halted_only",
|
||||
"~dbg|dbg>io_dec_tlu_debug_mode",
|
||||
"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
|
||||
"~dbg|dbg>io_core_dbg_cmd_done",
|
||||
"~dbg|dbg>io_dmi_reg_wr_en",
|
||||
"~dbg|dbg>io_dmi_reg_en",
|
||||
"~dbg|dbg>io_dbg_dma_io_dma_dbg_ready",
|
||||
"~dbg|dbg>io_dmi_reg_addr",
|
||||
"~dbg|dbg>reset"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"dbg.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~dbg|dbg>rst_temp"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~dbg|dbg>dbg_dm_rst_l"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"dbg"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
|
|
@ -1,3 +1 @@
|
|||
/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
|
||||
/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
|
||||
/home/waleedbinehsan/Desktop/Quasar/mem.sv
|
||||
/home/waleedbinehsan/Desktop/Quasar-master/gated_latch.v
|
||||
|
|
@ -0,0 +1,506 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_axi_ar_ready",
|
||||
"~lsu|lsu>io_axi_aw_ready",
|
||||
"~lsu|lsu>io_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_single_ecc_error_incr",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
||||
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_trigger_match_m",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_trigger_pkt_any_0_store",
|
||||
"~lsu|lsu>io_trigger_pkt_any_1_store",
|
||||
"~lsu|lsu>io_trigger_pkt_any_0_load",
|
||||
"~lsu|lsu>io_trigger_pkt_any_0_select",
|
||||
"~lsu|lsu>io_trigger_pkt_any_3_store",
|
||||
"~lsu|lsu>io_trigger_pkt_any_2_store",
|
||||
"~lsu|lsu>io_trigger_pkt_any_1_load",
|
||||
"~lsu|lsu>io_trigger_pkt_any_1_select",
|
||||
"~lsu|lsu>io_trigger_pkt_any_3_load",
|
||||
"~lsu|lsu>io_trigger_pkt_any_3_select",
|
||||
"~lsu|lsu>io_trigger_pkt_any_2_load",
|
||||
"~lsu|lsu>io_trigger_pkt_any_2_select",
|
||||
"~lsu|lsu>io_trigger_pkt_any_0_tdata2",
|
||||
"~lsu|lsu>io_trigger_pkt_any_0_match_pkt",
|
||||
"~lsu|lsu>io_trigger_pkt_any_1_tdata2",
|
||||
"~lsu|lsu>io_trigger_pkt_any_1_match_pkt",
|
||||
"~lsu|lsu>io_trigger_pkt_any_3_tdata2",
|
||||
"~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
|
||||
"~lsu|lsu>io_trigger_pkt_any_2_tdata2",
|
||||
"~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_rden",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_p_valid",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
||||
"~lsu|lsu>io_lsu_p_bits_load",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_p_bits_store",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_axi_ar_ready",
|
||||
"~lsu|lsu>io_axi_aw_ready",
|
||||
"~lsu|lsu>io_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_wren",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_p_valid",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
||||
"~lsu|lsu>io_lsu_p_bits_load",
|
||||
"~lsu|lsu>io_lsu_p_bits_store",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_load_stall_any",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_pic_picm_wren",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_wr_data_hi",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_pic_picm_mken",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_p_valid",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
||||
"~lsu|lsu>io_lsu_p_bits_store",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_p_valid",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
||||
"~lsu|lsu>io_lsu_p_bits_load",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_p_valid",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
||||
"~lsu|lsu>io_lsu_p_bits_load",
|
||||
"~lsu|lsu>io_lsu_p_bits_store",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_result_m",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_lsu_store_stall_any",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
"~lsu|lsu>io_lsu_p_bits_dword",
|
||||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
"~lsu|lsu>io_dccm_rd_data_lo",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"lsu.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"lsu"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"lsu_bus_buffer.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"lsu_bus_buffer"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
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Load Diff
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Load Diff
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|
|
@ -0,0 +1 @@
|
|||
sbt.internal.DslEntry
|
||||
Binary file not shown.
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|
|
@ -1 +1 @@
|
|||
38779017
|
||||
-1895719532
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
[debug] "not up to date. inChanged = true, force = false
|
||||
[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")...
|
||||
[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")
|
||||
[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar-master/project/"), "quasar-master-build")...
|
||||
[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar-master/project/"), "quasar-master-build")
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar-master/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
|
||||
|
|
@ -1 +1 @@
|
|||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
||||
[debug] Full compilation, no sources in previous analysis.
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
||||
[debug] Copy resource mappings:
|
||||
[debug]
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
|
||||
/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
|
||||
/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
|
|
|||
|
|
@ -968,10 +968,6 @@
|
|||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~quasar_wrapper|exu>i0_rs2_d"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~quasar_wrapper|dbg>rst_not"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~quasar_wrapper|dbg>rst_temp"
|
||||
|
|
|
|||
24396
quasar_wrapper.fir
24396
quasar_wrapper.fir
File diff suppressed because it is too large
Load Diff
13741
quasar_wrapper.v
13741
quasar_wrapper.v
File diff suppressed because it is too large
Load Diff
|
|
@ -101,8 +101,6 @@ class dbg extends Module with lib with RequireAsyncReset {
|
|||
dontTouch(dbg_dm_rst_l)
|
||||
val rst_temp = (dbg_dm_rst_l.asBool() & reset.asBool()).asAsyncReset()
|
||||
dontTouch(rst_temp)
|
||||
val rst_not = (!dbg_dm_rst_l.asBool).asAsyncReset()
|
||||
dontTouch(rst_not)
|
||||
|
||||
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool()
|
||||
val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
|
||||
|
|
@ -126,7 +124,7 @@ class dbg extends Module with lib with RequireAsyncReset {
|
|||
RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
|
||||
} // sbcs_misc_reg
|
||||
|
||||
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, rst_not) {
|
||||
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
|
||||
RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
|
||||
} // sbcs_error_reg
|
||||
sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
|
||||
|
|
@ -457,3 +455,7 @@ class dbg extends Module with lib with RequireAsyncReset {
|
|||
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
|
||||
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
|
||||
}
|
||||
|
||||
object dbg_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -303,3 +303,7 @@ class dec extends Module with param with RequireAsyncReset{
|
|||
// debug command read data
|
||||
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
||||
}
|
||||
|
||||
object dec_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -330,8 +330,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
|
|||
val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)}
|
||||
io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)}
|
||||
|
||||
|
||||
|
||||
io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r
|
||||
val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)}
|
||||
val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)}
|
||||
|
|
|
|||
|
|
@ -508,3 +508,7 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
|
|||
io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||
}
|
||||
|
||||
object dma extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dma_ctrl()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -232,3 +232,7 @@ class exu extends Module with lib with RequireAsyncReset{
|
|||
io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d)
|
||||
io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
|
||||
}
|
||||
|
||||
object exu_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -117,3 +117,7 @@ class ifu extends Module with lib with RequireAsyncReset {
|
|||
io.iccm_ready := mem_ctl.io.iccm_ready
|
||||
io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
||||
}
|
||||
|
||||
object ifu_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,14 +74,14 @@ class ahb_channel extends Bundle{
|
|||
val in = new ahb_in
|
||||
val out = new ahb_out
|
||||
}
|
||||
class axi_channels(val BUS_TAG :Int=1) extends Bundle with lib{
|
||||
class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
|
||||
val aw = Decoupled(new write_addr(BUS_TAG))
|
||||
val w = Decoupled(new write_data())
|
||||
val b = Flipped(Decoupled(new write_resp(BUS_TAG)))
|
||||
val ar = Decoupled(new read_addr(BUS_TAG))
|
||||
val r = Flipped(Decoupled(new read_data(BUS_TAG)))
|
||||
}
|
||||
class read_addr(val TAG : Int) extends Bundle with lib { // read_address
|
||||
class read_addr(val TAG : Int=3) extends Bundle with lib { // read_address
|
||||
val id = UInt(TAG.W)
|
||||
val addr = UInt(32.W)
|
||||
val region = UInt(4.W)
|
||||
|
|
@ -93,13 +93,13 @@ class read_addr(val TAG : Int) extends Bundle with lib { // read_address
|
|||
val prot = UInt(3.W)
|
||||
val qos = UInt(4.W)
|
||||
}
|
||||
class read_data(val TAG : Int) extends Bundle with lib { // read_data
|
||||
class read_data(val TAG : Int=3) extends Bundle with lib { // read_data
|
||||
val id = UInt(TAG.W)
|
||||
val data = UInt(64.W)
|
||||
val resp = UInt(2.W)
|
||||
val last = Bool()
|
||||
}
|
||||
class write_addr(val TAG : Int) extends Bundle with lib { // write_address
|
||||
class write_addr(val TAG : Int=3) extends Bundle with lib { // write_address
|
||||
val id = UInt(TAG.W)
|
||||
val addr = UInt(32.W)
|
||||
val region = UInt(4.W)
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@ trait param {
|
|||
val BTB_INDEX3_HI = 0x19
|
||||
val BTB_INDEX3_LO = 0x12
|
||||
val BTB_SIZE = 0x200
|
||||
val BUILD_AHB_LITE = 0x1
|
||||
val BUILD_AXI4 = 0x0
|
||||
val BUILD_AXI_NATIVE = 0x0
|
||||
val BUILD_AHB_LITE = 0x0
|
||||
val BUILD_AXI4 = 0x1
|
||||
val BUILD_AXI_NATIVE = 0x1
|
||||
val BUS_PRTY_DEFAULT = 0x3
|
||||
val DATA_ACCESS_ADDR0 = 0x00000000
|
||||
val DATA_ACCESS_ADDR1 = 0xC0000000
|
||||
|
|
|
|||
|
|
@ -319,3 +319,6 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
|
||||
|
||||
}
|
||||
object lsu_top extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
|
||||
}
|
||||
|
|
@ -5,6 +5,7 @@ import lib._
|
|||
import include._
|
||||
import chisel3.experimental.{ChiselEnum, chiselName}
|
||||
import chisel3.util.ImplicitConversions.intToUInt
|
||||
import ifu._
|
||||
|
||||
@chiselName
|
||||
class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
||||
|
|
@ -182,6 +183,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
|||
(io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)),
|
||||
(io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)),
|
||||
(io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1))))
|
||||
|
||||
val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r,
|
||||
(io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U),
|
||||
(io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)),
|
||||
|
|
@ -295,7 +297,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
|||
val obuf_merge_en = WireInit(Bool(), false.B)
|
||||
val obuf_merge_in = obuf_merge_en
|
||||
val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0)
|
||||
//val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
|
||||
val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1)
|
||||
val obuf_cmd_done = WireInit(Bool(), false.B)
|
||||
|
|
@ -616,3 +617,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
|||
io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
|
||||
lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
|
||||
}
|
||||
|
||||
object bus_buffer extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
|
||||
}
|
||||
|
|
@ -3,7 +3,6 @@ import chisel3._
|
|||
import chisel3.util._
|
||||
import lib._
|
||||
import include._
|
||||
import ifu._
|
||||
|
||||
class lsu_bus_intf extends Module with RequireAsyncReset with lib {
|
||||
val io = IO (new Bundle {
|
||||
|
|
|
|||
|
|
@ -405,3 +405,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
}
|
||||
|
||||
}
|
||||
|
||||
object pic_gen extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -83,9 +83,6 @@ class quasar extends Module with RequireAsyncReset with lib {
|
|||
val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
|
||||
val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
|
||||
val active_clk = rvclkhdr(clock, active_state.asBool, io.scan_mode)
|
||||
val core_dbg_cmd_done = dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
||||
val core_dbg_cmd_fail = dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
||||
val core_dbg_rddata = Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
||||
|
||||
// Lets start with IFU
|
||||
ifu.io.ifu_dec <> dec.io.ifu_dec
|
||||
|
|
@ -106,7 +103,7 @@ class quasar extends Module with RequireAsyncReset with lib {
|
|||
ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
|
||||
ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
|
||||
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||
ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
|
||||
ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
|
||||
|
||||
// Lets start with Dec
|
||||
dec.reset := io.core_rst_l
|
||||
|
|
|
|||
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Reference in New Issue