LSU Top updated
This commit is contained in:
Laraib Khan
parent
92b7b00a3a
commit
8143bb1772
|
|
@ -180,6 +180,7 @@
|
|||
"sink":"~lsu|lsu>io_lsu_store_stall_any",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
|
|
@ -188,7 +189,6 @@
|
|||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_force_halt",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
|
|
@ -380,6 +380,7 @@
|
|||
"sink":"~lsu|lsu>io_lsu_load_stall_any",
|
||||
"sources":[
|
||||
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu|lsu>io_dec_lsu_offset_d",
|
||||
|
|
@ -388,7 +389,6 @@
|
|||
"~lsu|lsu>io_lsu_p_bits_half",
|
||||
"~lsu|lsu>io_lsu_p_bits_word",
|
||||
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
||||
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
||||
"~lsu|lsu>io_dec_tlu_force_halt",
|
||||
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
||||
"~lsu|lsu>io_dccm_rd_data_hi",
|
||||
|
|
|
|||
|
|
@ -1,11 +1,4 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
|
||||
|
|
@ -31,6 +24,14 @@
|
|||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
|
||||
|
|
@ -56,6 +57,14 @@
|
|||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
|
||||
|
|
@ -109,13 +118,6 @@
|
|||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
|
||||
|
|
|
|||
352
lsu_lsc_ctl.fir
352
lsu_lsc_ctl.fir
|
|
@ -783,205 +783,195 @@ circuit lsu_lsc_ctl :
|
|||
node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103]
|
||||
node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
|
||||
node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34]
|
||||
node _T_153 = bits(io.lsu_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:62]
|
||||
reg _T_154 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:48]
|
||||
_T_154 <= _T_153 @[lsu_lsc_ctl.scala 224:48]
|
||||
node _T_155 = bits(io.end_addr_d, 2, 2) @[lsu_lsc_ctl.scala 224:124]
|
||||
reg _T_156 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:110]
|
||||
_T_156 <= _T_155 @[lsu_lsc_ctl.scala 224:110]
|
||||
node int = neq(_T_154, _T_156) @[lsu_lsc_ctl.scala 224:72]
|
||||
node _T_157 = bits(io.lsu_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:62]
|
||||
reg _T_158 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:48]
|
||||
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 225:48]
|
||||
node _T_159 = bits(io.end_addr_m, 2, 2) @[lsu_lsc_ctl.scala 225:124]
|
||||
reg _T_160 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:110]
|
||||
_T_160 <= _T_159 @[lsu_lsc_ctl.scala 225:110]
|
||||
node int1 = neq(_T_158, _T_160) @[lsu_lsc_ctl.scala 225:72]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
|
||||
reg _T_161 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
|
||||
_T_161 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
|
||||
io.lsu_addr_m <= _T_161 @[lsu_lsc_ctl.scala 227:24]
|
||||
reg _T_162 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
|
||||
_T_162 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
|
||||
io.lsu_addr_r <= _T_162 @[lsu_lsc_ctl.scala 228:24]
|
||||
node _T_163 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:60]
|
||||
node _T_164 = mux(int, end_addr_pre_m, _T_163) @[lsu_lsc_ctl.scala 229:27]
|
||||
node _T_165 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:117]
|
||||
reg _T_166 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:103]
|
||||
_T_166 <= _T_165 @[lsu_lsc_ctl.scala 229:103]
|
||||
node _T_167 = cat(_T_164, _T_166) @[Cat.scala 29:58]
|
||||
io.end_addr_m <= _T_167 @[lsu_lsc_ctl.scala 229:17]
|
||||
node _T_168 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:61]
|
||||
node _T_169 = mux(int1, end_addr_pre_r, _T_168) @[lsu_lsc_ctl.scala 230:27]
|
||||
node _T_170 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:118]
|
||||
reg _T_171 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:104]
|
||||
_T_171 <= _T_170 @[lsu_lsc_ctl.scala 230:104]
|
||||
node _T_172 = cat(_T_169, _T_171) @[Cat.scala 29:58]
|
||||
io.end_addr_r <= _T_172 @[lsu_lsc_ctl.scala 230:17]
|
||||
node _T_173 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
|
||||
node _T_174 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
|
||||
node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
|
||||
node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72]
|
||||
reg _T_153 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62]
|
||||
_T_153 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62]
|
||||
io.lsu_addr_m <= _T_153 @[lsu_lsc_ctl.scala 226:24]
|
||||
reg _T_154 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
|
||||
_T_154 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
|
||||
io.lsu_addr_r <= _T_154 @[lsu_lsc_ctl.scala 227:24]
|
||||
node _T_155 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
|
||||
node _T_156 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 228:71]
|
||||
node _T_157 = mux(_T_155, end_addr_pre_m, _T_156) @[lsu_lsc_ctl.scala 228:27]
|
||||
node _T_158 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 228:128]
|
||||
reg _T_159 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:114]
|
||||
_T_159 <= _T_158 @[lsu_lsc_ctl.scala 228:114]
|
||||
node _T_160 = cat(_T_157, _T_159) @[Cat.scala 29:58]
|
||||
io.end_addr_m <= _T_160 @[lsu_lsc_ctl.scala 228:17]
|
||||
node _T_161 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
|
||||
node _T_162 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 229:71]
|
||||
node _T_163 = mux(_T_161, end_addr_pre_r, _T_162) @[lsu_lsc_ctl.scala 229:27]
|
||||
node _T_164 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 229:128]
|
||||
reg _T_165 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
|
||||
_T_165 <= _T_164 @[lsu_lsc_ctl.scala 229:114]
|
||||
node _T_166 = cat(_T_163, _T_165) @[Cat.scala 29:58]
|
||||
io.end_addr_r <= _T_166 @[lsu_lsc_ctl.scala 229:17]
|
||||
node _T_167 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 230:41]
|
||||
node _T_168 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 230:69]
|
||||
node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 230:87]
|
||||
node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44]
|
||||
node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[lib.scala 406:18]
|
||||
rvclkhdr_1.io.en <= _T_175 @[lib.scala 407:17]
|
||||
rvclkhdr_1.io.en <= _T_170 @[lib.scala 407:17]
|
||||
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
||||
reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_175 : @[Reg.scala 28:19]
|
||||
_T_177 <= _T_173 @[Reg.scala 28:23]
|
||||
reg _T_172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_170 : @[Reg.scala 28:19]
|
||||
_T_172 <= _T_167 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
end_addr_pre_m <= _T_177 @[lsu_lsc_ctl.scala 231:18]
|
||||
node _T_178 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
|
||||
node _T_179 = and(io.lsu_pkt_m.valid, int) @[lsu_lsc_ctl.scala 232:69]
|
||||
node _T_180 = or(_T_179, io.clk_override) @[lsu_lsc_ctl.scala 232:76]
|
||||
node _T_181 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
end_addr_pre_m <= _T_172 @[lsu_lsc_ctl.scala 230:18]
|
||||
node _T_173 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 231:41]
|
||||
node _T_174 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 231:69]
|
||||
node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
|
||||
node _T_176 = bits(_T_175, 0, 0) @[lib.scala 8:44]
|
||||
node _T_177 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
|
||||
rvclkhdr_2.clock <= clock
|
||||
rvclkhdr_2.reset <= reset
|
||||
rvclkhdr_2.io.clk <= clock @[lib.scala 406:18]
|
||||
rvclkhdr_2.io.en <= _T_180 @[lib.scala 407:17]
|
||||
rvclkhdr_2.io.en <= _T_176 @[lib.scala 407:17]
|
||||
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
||||
reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_180 : @[Reg.scala 28:19]
|
||||
_T_182 <= _T_178 @[Reg.scala 28:23]
|
||||
reg _T_178 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_176 : @[Reg.scala 28:19]
|
||||
_T_178 <= _T_173 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
end_addr_pre_r <= _T_182 @[lsu_lsc_ctl.scala 232:18]
|
||||
reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
|
||||
_T_183 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_in_dccm_m <= _T_183 @[lsu_lsc_ctl.scala 233:24]
|
||||
reg _T_184 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
|
||||
_T_184 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
|
||||
io.addr_in_dccm_r <= _T_184 @[lsu_lsc_ctl.scala 234:24]
|
||||
reg _T_185 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
|
||||
_T_185 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
|
||||
io.addr_in_pic_m <= _T_185 @[lsu_lsc_ctl.scala 235:24]
|
||||
reg _T_186 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_186 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_in_pic_r <= _T_186 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg _T_187 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
|
||||
_T_187 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
|
||||
io.addr_external_m <= _T_187 @[lsu_lsc_ctl.scala 237:24]
|
||||
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
|
||||
node _T_188 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
|
||||
node _T_189 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
end_addr_pre_r <= _T_178 @[lsu_lsc_ctl.scala 231:18]
|
||||
reg _T_179 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
|
||||
_T_179 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 232:62]
|
||||
io.addr_in_dccm_m <= _T_179 @[lsu_lsc_ctl.scala 232:24]
|
||||
reg _T_180 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
|
||||
_T_180 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_in_dccm_r <= _T_180 @[lsu_lsc_ctl.scala 233:24]
|
||||
reg _T_181 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
|
||||
_T_181 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 234:62]
|
||||
io.addr_in_pic_m <= _T_181 @[lsu_lsc_ctl.scala 234:24]
|
||||
reg _T_182 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
|
||||
_T_182 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 235:62]
|
||||
io.addr_in_pic_r <= _T_182 @[lsu_lsc_ctl.scala 235:24]
|
||||
reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_183 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_external_m <= _T_183 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66]
|
||||
node _T_184 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77]
|
||||
node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
|
||||
rvclkhdr_3.clock <= clock
|
||||
rvclkhdr_3.reset <= reset
|
||||
rvclkhdr_3.io.clk <= clock @[lib.scala 406:18]
|
||||
rvclkhdr_3.io.en <= _T_188 @[lib.scala 407:17]
|
||||
rvclkhdr_3.io.en <= _T_184 @[lib.scala 407:17]
|
||||
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
||||
reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_188 : @[Reg.scala 28:19]
|
||||
when _T_184 : @[Reg.scala 28:19]
|
||||
bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_190 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
|
||||
io.lsu_fir_addr <= _T_190 @[lsu_lsc_ctl.scala 242:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
|
||||
node _T_191 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
|
||||
node _T_192 = and(io.lsu_pkt_r.valid, _T_191) @[lsu_lsc_ctl.scala 246:41]
|
||||
node _T_193 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
|
||||
node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 246:94]
|
||||
node _T_195 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
|
||||
node _T_196 = and(_T_194, _T_195) @[lsu_lsc_ctl.scala 246:108]
|
||||
io.lsu_commit_r <= _T_196 @[lsu_lsc_ctl.scala 246:19]
|
||||
node _T_197 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
|
||||
node _T_198 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
|
||||
node _T_199 = bits(_T_198, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_200 = mux(_T_199, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_201 = or(_T_197, _T_200) @[lsu_lsc_ctl.scala 247:59]
|
||||
node _T_202 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
|
||||
node _T_203 = mux(_T_202, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
|
||||
node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 247:89]
|
||||
io.store_data_m <= _T_204 @[lsu_lsc_ctl.scala 247:29]
|
||||
node _T_205 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33]
|
||||
lsu_ld_datafn_m <= _T_205 @[lsu_lsc_ctl.scala 268:27]
|
||||
node _T_206 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49]
|
||||
node _T_207 = mux(_T_206, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33]
|
||||
lsu_ld_datafn_corr_r <= _T_207 @[lsu_lsc_ctl.scala 269:27]
|
||||
node _T_208 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:74]
|
||||
node _T_209 = bits(_T_208, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_211 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:133]
|
||||
node _T_212 = cat(UInt<24>("h00"), _T_211) @[Cat.scala 29:58]
|
||||
node _T_213 = and(_T_210, _T_212) @[lsu_lsc_ctl.scala 270:102]
|
||||
node _T_214 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43]
|
||||
node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_217 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102]
|
||||
node _T_218 = cat(UInt<16>("h00"), _T_217) @[Cat.scala 29:58]
|
||||
node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 271:71]
|
||||
node _T_220 = or(_T_213, _T_219) @[lsu_lsc_ctl.scala 270:141]
|
||||
node _T_221 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||
node _T_222 = and(_T_221, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43]
|
||||
node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_225 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102]
|
||||
node _T_226 = bits(_T_225, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_227 = mux(_T_226, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_228 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||
node _T_229 = cat(_T_227, _T_228) @[Cat.scala 29:58]
|
||||
node _T_230 = and(_T_224, _T_229) @[lsu_lsc_ctl.scala 272:71]
|
||||
node _T_231 = or(_T_220, _T_230) @[lsu_lsc_ctl.scala 271:114]
|
||||
node _T_232 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17]
|
||||
node _T_233 = and(_T_232, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43]
|
||||
node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_236 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101]
|
||||
node _T_237 = bits(_T_236, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_238 = mux(_T_237, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_239 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125]
|
||||
node _T_240 = cat(_T_238, _T_239) @[Cat.scala 29:58]
|
||||
node _T_241 = and(_T_235, _T_240) @[lsu_lsc_ctl.scala 273:71]
|
||||
node _T_242 = or(_T_231, _T_241) @[lsu_lsc_ctl.scala 272:134]
|
||||
node _T_243 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_244 = mux(_T_243, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_245 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60]
|
||||
node _T_246 = and(_T_244, _T_245) @[lsu_lsc_ctl.scala 274:43]
|
||||
node _T_247 = or(_T_242, _T_246) @[lsu_lsc_ctl.scala 273:134]
|
||||
io.lsu_exu.lsu_result_m <= _T_247 @[lsu_lsc_ctl.scala 270:35]
|
||||
node _T_248 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66]
|
||||
node _T_249 = bits(_T_248, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_251 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130]
|
||||
node _T_252 = cat(UInt<24>("h00"), _T_251) @[Cat.scala 29:58]
|
||||
node _T_253 = and(_T_250, _T_252) @[lsu_lsc_ctl.scala 275:94]
|
||||
node _T_254 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_255 = bits(_T_254, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_256 = mux(_T_255, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_257 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107]
|
||||
node _T_258 = cat(UInt<16>("h00"), _T_257) @[Cat.scala 29:58]
|
||||
node _T_259 = and(_T_256, _T_258) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_260 = or(_T_253, _T_259) @[lsu_lsc_ctl.scala 275:138]
|
||||
node _T_261 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||
node _T_262 = and(_T_261, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_264 = mux(_T_263, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107]
|
||||
node _T_266 = bits(_T_265, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_267 = mux(_T_266, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_268 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||
node _T_269 = cat(_T_267, _T_268) @[Cat.scala 29:58]
|
||||
node _T_270 = and(_T_264, _T_269) @[lsu_lsc_ctl.scala 277:71]
|
||||
node _T_271 = or(_T_260, _T_270) @[lsu_lsc_ctl.scala 276:119]
|
||||
node _T_272 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17]
|
||||
node _T_273 = and(_T_272, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43]
|
||||
node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106]
|
||||
node _T_277 = bits(_T_276, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_278 = mux(_T_277, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_279 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135]
|
||||
node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58]
|
||||
node _T_281 = and(_T_275, _T_280) @[lsu_lsc_ctl.scala 278:71]
|
||||
node _T_282 = or(_T_271, _T_281) @[lsu_lsc_ctl.scala 277:144]
|
||||
node _T_283 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_284 = mux(_T_283, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_285 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65]
|
||||
node _T_286 = and(_T_284, _T_285) @[lsu_lsc_ctl.scala 279:43]
|
||||
node _T_287 = or(_T_282, _T_286) @[lsu_lsc_ctl.scala 278:144]
|
||||
io.lsu_result_corr_r <= _T_287 @[lsu_lsc_ctl.scala 275:27]
|
||||
node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 241:52]
|
||||
io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 241:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 243:28]
|
||||
node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 245:68]
|
||||
node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 245:41]
|
||||
node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:96]
|
||||
node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 245:94]
|
||||
node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:110]
|
||||
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 245:108]
|
||||
io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 245:19]
|
||||
node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 246:52]
|
||||
node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:69]
|
||||
node _T_195 = bits(_T_194, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_196 = mux(_T_195, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 246:59]
|
||||
node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 246:133]
|
||||
node _T_199 = mux(_T_198, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 246:94]
|
||||
node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 246:89]
|
||||
io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 246:29]
|
||||
node _T_201 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 267:33]
|
||||
lsu_ld_datafn_m <= _T_201 @[lsu_lsc_ctl.scala 267:27]
|
||||
node _T_202 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 268:49]
|
||||
node _T_203 = mux(_T_202, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 268:33]
|
||||
lsu_ld_datafn_corr_r <= _T_203 @[lsu_lsc_ctl.scala 268:27]
|
||||
node _T_204 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 269:74]
|
||||
node _T_205 = bits(_T_204, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_206 = mux(_T_205, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_207 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 269:133]
|
||||
node _T_208 = cat(UInt<24>("h00"), _T_207) @[Cat.scala 29:58]
|
||||
node _T_209 = and(_T_206, _T_208) @[lsu_lsc_ctl.scala 269:102]
|
||||
node _T_210 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 270:43]
|
||||
node _T_211 = bits(_T_210, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_212 = mux(_T_211, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_213 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 270:102]
|
||||
node _T_214 = cat(UInt<16>("h00"), _T_213) @[Cat.scala 29:58]
|
||||
node _T_215 = and(_T_212, _T_214) @[lsu_lsc_ctl.scala 270:71]
|
||||
node _T_216 = or(_T_209, _T_215) @[lsu_lsc_ctl.scala 269:141]
|
||||
node _T_217 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 271:17]
|
||||
node _T_218 = and(_T_217, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 271:43]
|
||||
node _T_219 = bits(_T_218, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_220 = mux(_T_219, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_221 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 271:102]
|
||||
node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_223 = mux(_T_222, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_224 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 271:125]
|
||||
node _T_225 = cat(_T_223, _T_224) @[Cat.scala 29:58]
|
||||
node _T_226 = and(_T_220, _T_225) @[lsu_lsc_ctl.scala 271:71]
|
||||
node _T_227 = or(_T_216, _T_226) @[lsu_lsc_ctl.scala 270:114]
|
||||
node _T_228 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||
node _T_229 = and(_T_228, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 272:43]
|
||||
node _T_230 = bits(_T_229, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_232 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 272:101]
|
||||
node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_234 = mux(_T_233, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_235 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||
node _T_236 = cat(_T_234, _T_235) @[Cat.scala 29:58]
|
||||
node _T_237 = and(_T_231, _T_236) @[lsu_lsc_ctl.scala 272:71]
|
||||
node _T_238 = or(_T_227, _T_237) @[lsu_lsc_ctl.scala 271:134]
|
||||
node _T_239 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_240 = mux(_T_239, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_241 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 273:60]
|
||||
node _T_242 = and(_T_240, _T_241) @[lsu_lsc_ctl.scala 273:43]
|
||||
node _T_243 = or(_T_238, _T_242) @[lsu_lsc_ctl.scala 272:134]
|
||||
io.lsu_exu.lsu_result_m <= _T_243 @[lsu_lsc_ctl.scala 269:35]
|
||||
node _T_244 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 274:66]
|
||||
node _T_245 = bits(_T_244, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_246 = mux(_T_245, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_247 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 274:130]
|
||||
node _T_248 = cat(UInt<24>("h00"), _T_247) @[Cat.scala 29:58]
|
||||
node _T_249 = and(_T_246, _T_248) @[lsu_lsc_ctl.scala 274:94]
|
||||
node _T_250 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 275:43]
|
||||
node _T_251 = bits(_T_250, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_253 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 275:107]
|
||||
node _T_254 = cat(UInt<16>("h00"), _T_253) @[Cat.scala 29:58]
|
||||
node _T_255 = and(_T_252, _T_254) @[lsu_lsc_ctl.scala 275:71]
|
||||
node _T_256 = or(_T_249, _T_255) @[lsu_lsc_ctl.scala 274:138]
|
||||
node _T_257 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17]
|
||||
node _T_258 = and(_T_257, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_259 = bits(_T_258, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_260 = mux(_T_259, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_261 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 276:107]
|
||||
node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_263 = mux(_T_262, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 276:135]
|
||||
node _T_265 = cat(_T_263, _T_264) @[Cat.scala 29:58]
|
||||
node _T_266 = and(_T_260, _T_265) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_267 = or(_T_256, _T_266) @[lsu_lsc_ctl.scala 275:119]
|
||||
node _T_268 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||
node _T_269 = and(_T_268, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_270 = bits(_T_269, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_271 = mux(_T_270, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_272 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 277:106]
|
||||
node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_274 = mux(_T_273, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||
node _T_276 = cat(_T_274, _T_275) @[Cat.scala 29:58]
|
||||
node _T_277 = and(_T_271, _T_276) @[lsu_lsc_ctl.scala 277:71]
|
||||
node _T_278 = or(_T_267, _T_277) @[lsu_lsc_ctl.scala 276:144]
|
||||
node _T_279 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_280 = mux(_T_279, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_281 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 278:65]
|
||||
node _T_282 = and(_T_280, _T_281) @[lsu_lsc_ctl.scala 278:43]
|
||||
node _T_283 = or(_T_278, _T_282) @[lsu_lsc_ctl.scala 277:144]
|
||||
io.lsu_result_corr_r <= _T_283 @[lsu_lsc_ctl.scala 274:27]
|
||||
|
||||
|
|
|
|||
382
lsu_lsc_ctl.v
382
lsu_lsc_ctl.v
|
|
@ -375,10 +375,6 @@ module lsu_lsc_ctl(
|
|||
reg [31:0] _RAND_51;
|
||||
reg [31:0] _RAND_52;
|
||||
reg [31:0] _RAND_53;
|
||||
reg [31:0] _RAND_54;
|
||||
reg [31:0] _RAND_55;
|
||||
reg [31:0] _RAND_56;
|
||||
reg [31:0] _RAND_57;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25]
|
||||
wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25]
|
||||
|
|
@ -526,92 +522,86 @@ module lsu_lsc_ctl(
|
|||
reg _T_143; // @[lsu_lsc_ctl.scala 219:65]
|
||||
wire [5:0] _T_146 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_146; // @[lsu_lsc_ctl.scala 221:66]
|
||||
reg _T_154; // @[lsu_lsc_ctl.scala 224:48]
|
||||
reg _T_156; // @[lsu_lsc_ctl.scala 224:110]
|
||||
wire int_ = _T_154 != _T_156; // @[lsu_lsc_ctl.scala 224:72]
|
||||
reg _T_158; // @[lsu_lsc_ctl.scala 225:48]
|
||||
reg _T_160; // @[lsu_lsc_ctl.scala 225:110]
|
||||
wire int1 = _T_158 != _T_160; // @[lsu_lsc_ctl.scala 225:72]
|
||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72]
|
||||
reg [31:0] _T_161; // @[lsu_lsc_ctl.scala 227:62]
|
||||
reg [31:0] _T_162; // @[lsu_lsc_ctl.scala 228:62]
|
||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72]
|
||||
reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 226:62]
|
||||
reg [31:0] _T_154; // @[lsu_lsc_ctl.scala 227:62]
|
||||
reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20]
|
||||
wire [28:0] _T_164 = int_ ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
||||
reg [2:0] _T_166; // @[lsu_lsc_ctl.scala 229:103]
|
||||
wire [28:0] _T_157 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 228:27]
|
||||
reg [2:0] _T_159; // @[lsu_lsc_ctl.scala 228:114]
|
||||
reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20]
|
||||
wire [28:0] _T_169 = int1 ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27]
|
||||
reg [2:0] _T_171; // @[lsu_lsc_ctl.scala 230:104]
|
||||
wire _T_174 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69]
|
||||
wire [28:0] _T_163 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
||||
reg [2:0] _T_165; // @[lsu_lsc_ctl.scala 229:114]
|
||||
wire _T_168 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 230:69]
|
||||
wire _T_169 = _T_168 | io_clk_override; // @[lsu_lsc_ctl.scala 230:87]
|
||||
wire _T_174 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 231:69]
|
||||
wire _T_175 = _T_174 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87]
|
||||
wire _T_179 = io_lsu_pkt_m_valid & int_; // @[lsu_lsc_ctl.scala 232:69]
|
||||
wire _T_180 = _T_179 | io_clk_override; // @[lsu_lsc_ctl.scala 232:76]
|
||||
reg _T_183; // @[lsu_lsc_ctl.scala 233:62]
|
||||
reg _T_184; // @[lsu_lsc_ctl.scala 234:62]
|
||||
reg _T_185; // @[lsu_lsc_ctl.scala 235:62]
|
||||
reg _T_186; // @[lsu_lsc_ctl.scala 236:62]
|
||||
reg _T_187; // @[lsu_lsc_ctl.scala 237:62]
|
||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 238:66]
|
||||
wire _T_188 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 239:77]
|
||||
reg _T_179; // @[lsu_lsc_ctl.scala 232:62]
|
||||
reg _T_180; // @[lsu_lsc_ctl.scala 233:62]
|
||||
reg _T_181; // @[lsu_lsc_ctl.scala 234:62]
|
||||
reg _T_182; // @[lsu_lsc_ctl.scala 235:62]
|
||||
reg _T_183; // @[lsu_lsc_ctl.scala 236:62]
|
||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 237:66]
|
||||
wire _T_184 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 238:77]
|
||||
reg [31:0] bus_read_data_r; // @[Reg.scala 27:20]
|
||||
wire _T_191 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68]
|
||||
wire _T_192 = io_lsu_pkt_r_valid & _T_191; // @[lsu_lsc_ctl.scala 246:41]
|
||||
wire _T_193 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96]
|
||||
wire _T_194 = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 246:94]
|
||||
wire _T_195 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 246:110]
|
||||
wire _T_198 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69]
|
||||
wire [31:0] _T_200 = _T_198 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_201 = io_picm_mask_data_m | _T_200; // @[lsu_lsc_ctl.scala 247:59]
|
||||
wire [31:0] _T_203 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94]
|
||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 268:33]
|
||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 269:33]
|
||||
wire _T_208 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 270:74]
|
||||
wire [31:0] _T_210 = _T_208 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_212 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_213 = _T_210 & _T_212; // @[lsu_lsc_ctl.scala 270:102]
|
||||
wire _T_214 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 271:43]
|
||||
wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_218 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 271:71]
|
||||
wire [31:0] _T_220 = _T_213 | _T_219; // @[lsu_lsc_ctl.scala 270:141]
|
||||
wire _T_221 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 272:17]
|
||||
wire _T_222 = _T_221 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 272:43]
|
||||
wire [31:0] _T_224 = _T_222 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_227 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_229 = {_T_227,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_230 = _T_224 & _T_229; // @[lsu_lsc_ctl.scala 272:71]
|
||||
wire [31:0] _T_231 = _T_220 | _T_230; // @[lsu_lsc_ctl.scala 271:114]
|
||||
wire _T_233 = _T_221 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 273:43]
|
||||
wire [31:0] _T_235 = _T_233 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_238 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_240 = {_T_238,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_241 = _T_235 & _T_240; // @[lsu_lsc_ctl.scala 273:71]
|
||||
wire [31:0] _T_242 = _T_231 | _T_241; // @[lsu_lsc_ctl.scala 272:134]
|
||||
wire [31:0] _T_244 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_246 = _T_244 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 274:43]
|
||||
wire _T_248 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 275:66]
|
||||
wire [31:0] _T_250 = _T_248 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_252 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_253 = _T_250 & _T_252; // @[lsu_lsc_ctl.scala 275:94]
|
||||
wire _T_254 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 276:43]
|
||||
wire [31:0] _T_256 = _T_254 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_258 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_259 = _T_256 & _T_258; // @[lsu_lsc_ctl.scala 276:71]
|
||||
wire [31:0] _T_260 = _T_253 | _T_259; // @[lsu_lsc_ctl.scala 275:138]
|
||||
wire _T_261 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 277:17]
|
||||
wire _T_262 = _T_261 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 277:43]
|
||||
wire [31:0] _T_264 = _T_262 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_267 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_269 = {_T_267,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_270 = _T_264 & _T_269; // @[lsu_lsc_ctl.scala 277:71]
|
||||
wire [31:0] _T_271 = _T_260 | _T_270; // @[lsu_lsc_ctl.scala 276:119]
|
||||
wire _T_273 = _T_261 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 278:43]
|
||||
wire [31:0] _T_275 = _T_273 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_278 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_280 = {_T_278,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_281 = _T_275 & _T_280; // @[lsu_lsc_ctl.scala 278:71]
|
||||
wire [31:0] _T_282 = _T_271 | _T_281; // @[lsu_lsc_ctl.scala 277:144]
|
||||
wire [31:0] _T_284 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_286 = _T_284 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 279:43]
|
||||
wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 245:68]
|
||||
wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 245:41]
|
||||
wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 245:96]
|
||||
wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 245:94]
|
||||
wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 245:110]
|
||||
wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 246:69]
|
||||
wire [31:0] _T_196 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 246:59]
|
||||
wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_exu_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 246:94]
|
||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 267:33]
|
||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 268:33]
|
||||
wire _T_204 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 269:74]
|
||||
wire [31:0] _T_206 = _T_204 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_208 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_209 = _T_206 & _T_208; // @[lsu_lsc_ctl.scala 269:102]
|
||||
wire _T_210 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 270:43]
|
||||
wire [31:0] _T_212 = _T_210 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_214 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_215 = _T_212 & _T_214; // @[lsu_lsc_ctl.scala 270:71]
|
||||
wire [31:0] _T_216 = _T_209 | _T_215; // @[lsu_lsc_ctl.scala 269:141]
|
||||
wire _T_217 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 271:17]
|
||||
wire _T_218 = _T_217 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 271:43]
|
||||
wire [31:0] _T_220 = _T_218 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_223 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_225 = {_T_223,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_226 = _T_220 & _T_225; // @[lsu_lsc_ctl.scala 271:71]
|
||||
wire [31:0] _T_227 = _T_216 | _T_226; // @[lsu_lsc_ctl.scala 270:114]
|
||||
wire _T_229 = _T_217 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 272:43]
|
||||
wire [31:0] _T_231 = _T_229 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_234 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_236 = {_T_234,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_237 = _T_231 & _T_236; // @[lsu_lsc_ctl.scala 272:71]
|
||||
wire [31:0] _T_238 = _T_227 | _T_237; // @[lsu_lsc_ctl.scala 271:134]
|
||||
wire [31:0] _T_240 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_242 = _T_240 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 273:43]
|
||||
wire _T_244 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 274:66]
|
||||
wire [31:0] _T_246 = _T_244 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_248 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_249 = _T_246 & _T_248; // @[lsu_lsc_ctl.scala 274:94]
|
||||
wire _T_250 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 275:43]
|
||||
wire [31:0] _T_252 = _T_250 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_254 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_255 = _T_252 & _T_254; // @[lsu_lsc_ctl.scala 275:71]
|
||||
wire [31:0] _T_256 = _T_249 | _T_255; // @[lsu_lsc_ctl.scala 274:138]
|
||||
wire _T_257 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 276:17]
|
||||
wire _T_258 = _T_257 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 276:43]
|
||||
wire [31:0] _T_260 = _T_258 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_263 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_265 = {_T_263,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_266 = _T_260 & _T_265; // @[lsu_lsc_ctl.scala 276:71]
|
||||
wire [31:0] _T_267 = _T_256 | _T_266; // @[lsu_lsc_ctl.scala 275:119]
|
||||
wire _T_269 = _T_257 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 277:43]
|
||||
wire [31:0] _T_271 = _T_269 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_274 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_276 = {_T_274,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_277 = _T_271 & _T_276; // @[lsu_lsc_ctl.scala 277:71]
|
||||
wire [31:0] _T_278 = _T_267 | _T_277; // @[lsu_lsc_ctl.scala 276:144]
|
||||
wire [31:0] _T_280 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_282 = _T_280 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 278:43]
|
||||
lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25]
|
||||
.reset(addrcheck_reset),
|
||||
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
||||
|
|
@ -653,18 +643,18 @@ module lsu_lsc_ctl(
|
|||
.io_clk(rvclkhdr_3_io_clk),
|
||||
.io_en(rvclkhdr_3_io_en)
|
||||
);
|
||||
assign io_lsu_exu_lsu_result_m = _T_242 | _T_246; // @[lsu_lsc_ctl.scala 270:35]
|
||||
assign io_lsu_result_corr_r = _T_282 | _T_286; // @[lsu_lsc_ctl.scala 275:27]
|
||||
assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 244:28]
|
||||
assign io_lsu_addr_m = _T_161; // @[lsu_lsc_ctl.scala 227:24]
|
||||
assign io_lsu_addr_r = _T_162; // @[lsu_lsc_ctl.scala 228:24]
|
||||
assign io_lsu_exu_lsu_result_m = _T_238 | _T_242; // @[lsu_lsc_ctl.scala 269:35]
|
||||
assign io_lsu_result_corr_r = _T_278 | _T_282; // @[lsu_lsc_ctl.scala 274:27]
|
||||
assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 243:28]
|
||||
assign io_lsu_addr_m = _T_153; // @[lsu_lsc_ctl.scala 226:24]
|
||||
assign io_lsu_addr_r = _T_154; // @[lsu_lsc_ctl.scala 227:24]
|
||||
assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24]
|
||||
assign io_end_addr_m = {_T_164,_T_166}; // @[lsu_lsc_ctl.scala 229:17]
|
||||
assign io_end_addr_r = {_T_169,_T_171}; // @[lsu_lsc_ctl.scala 230:17]
|
||||
assign io_store_data_m = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 247:29]
|
||||
assign io_end_addr_m = {_T_157,_T_159}; // @[lsu_lsc_ctl.scala 228:17]
|
||||
assign io_end_addr_r = {_T_163,_T_165}; // @[lsu_lsc_ctl.scala 229:17]
|
||||
assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 246:29]
|
||||
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16]
|
||||
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42]
|
||||
assign io_lsu_commit_r = _T_194 & _T_195; // @[lsu_lsc_ctl.scala 246:19]
|
||||
assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 245:19]
|
||||
assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32]
|
||||
assign io_lsu_error_pkt_r_valid = _T_112; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 186:30]
|
||||
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_111; // @[lsu_lsc_ctl.scala 184:24 lsu_lsc_ctl.scala 185:46]
|
||||
|
|
@ -672,15 +662,15 @@ module lsu_lsc_ctl(
|
|||
assign io_lsu_error_pkt_r_bits_exc_type = _T_110_bits_exc_type; // @[lsu_lsc_ctl.scala 184:24]
|
||||
assign io_lsu_error_pkt_r_bits_mscause = _T_110_bits_mscause; // @[lsu_lsc_ctl.scala 184:24]
|
||||
assign io_lsu_error_pkt_r_bits_addr = _T_110_bits_addr; // @[lsu_lsc_ctl.scala 184:24]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 241:28]
|
||||
assign io_lsu_fir_error = _T_113; // @[lsu_lsc_ctl.scala 187:38]
|
||||
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42]
|
||||
assign io_addr_in_dccm_m = _T_183; // @[lsu_lsc_ctl.scala 233:24]
|
||||
assign io_addr_in_dccm_r = _T_184; // @[lsu_lsc_ctl.scala 234:24]
|
||||
assign io_addr_in_dccm_m = _T_179; // @[lsu_lsc_ctl.scala 232:24]
|
||||
assign io_addr_in_dccm_r = _T_180; // @[lsu_lsc_ctl.scala 233:24]
|
||||
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42]
|
||||
assign io_addr_in_pic_m = _T_185; // @[lsu_lsc_ctl.scala 235:24]
|
||||
assign io_addr_in_pic_r = _T_186; // @[lsu_lsc_ctl.scala 236:24]
|
||||
assign io_addr_external_m = _T_187; // @[lsu_lsc_ctl.scala 237:24]
|
||||
assign io_addr_in_pic_m = _T_181; // @[lsu_lsc_ctl.scala 234:24]
|
||||
assign io_addr_in_pic_r = _T_182; // @[lsu_lsc_ctl.scala 235:24]
|
||||
assign io_addr_external_m = _T_183; // @[lsu_lsc_ctl.scala 236:24]
|
||||
assign io_lsu_pkt_d_valid = _T_128 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
|
||||
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 208:20]
|
||||
|
|
@ -740,9 +730,9 @@ module lsu_lsc_ctl(
|
|||
assign rvclkhdr_io_clk = clock; // @[lib.scala 419:18]
|
||||
assign rvclkhdr_io_en = _T_105 | io_clk_override; // @[lib.scala 420:17]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18]
|
||||
assign rvclkhdr_1_io_en = _T_174 | io_clk_override; // @[lib.scala 407:17]
|
||||
assign rvclkhdr_1_io_en = _T_168 | io_clk_override; // @[lib.scala 407:17]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18]
|
||||
assign rvclkhdr_2_io_en = _T_179 | io_clk_override; // @[lib.scala 407:17]
|
||||
assign rvclkhdr_2_io_en = _T_174 | io_clk_override; // @[lib.scala 407:17]
|
||||
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18]
|
||||
assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 407:17]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
|
|
@ -861,41 +851,33 @@ initial begin
|
|||
_RAND_39 = {1{`RANDOM}};
|
||||
_T_143 = _RAND_39[0:0];
|
||||
_RAND_40 = {1{`RANDOM}};
|
||||
_T_154 = _RAND_40[0:0];
|
||||
store_data_pre_m = _RAND_40[31:0];
|
||||
_RAND_41 = {1{`RANDOM}};
|
||||
_T_156 = _RAND_41[0:0];
|
||||
_T_153 = _RAND_41[31:0];
|
||||
_RAND_42 = {1{`RANDOM}};
|
||||
_T_158 = _RAND_42[0:0];
|
||||
_T_154 = _RAND_42[31:0];
|
||||
_RAND_43 = {1{`RANDOM}};
|
||||
_T_160 = _RAND_43[0:0];
|
||||
end_addr_pre_m = _RAND_43[28:0];
|
||||
_RAND_44 = {1{`RANDOM}};
|
||||
store_data_pre_m = _RAND_44[31:0];
|
||||
_T_159 = _RAND_44[2:0];
|
||||
_RAND_45 = {1{`RANDOM}};
|
||||
_T_161 = _RAND_45[31:0];
|
||||
end_addr_pre_r = _RAND_45[28:0];
|
||||
_RAND_46 = {1{`RANDOM}};
|
||||
_T_162 = _RAND_46[31:0];
|
||||
_T_165 = _RAND_46[2:0];
|
||||
_RAND_47 = {1{`RANDOM}};
|
||||
end_addr_pre_m = _RAND_47[28:0];
|
||||
_T_179 = _RAND_47[0:0];
|
||||
_RAND_48 = {1{`RANDOM}};
|
||||
_T_166 = _RAND_48[2:0];
|
||||
_T_180 = _RAND_48[0:0];
|
||||
_RAND_49 = {1{`RANDOM}};
|
||||
end_addr_pre_r = _RAND_49[28:0];
|
||||
_T_181 = _RAND_49[0:0];
|
||||
_RAND_50 = {1{`RANDOM}};
|
||||
_T_171 = _RAND_50[2:0];
|
||||
_T_182 = _RAND_50[0:0];
|
||||
_RAND_51 = {1{`RANDOM}};
|
||||
_T_183 = _RAND_51[0:0];
|
||||
_RAND_52 = {1{`RANDOM}};
|
||||
_T_184 = _RAND_52[0:0];
|
||||
addr_external_r = _RAND_52[0:0];
|
||||
_RAND_53 = {1{`RANDOM}};
|
||||
_T_185 = _RAND_53[0:0];
|
||||
_RAND_54 = {1{`RANDOM}};
|
||||
_T_186 = _RAND_54[0:0];
|
||||
_RAND_55 = {1{`RANDOM}};
|
||||
_T_187 = _RAND_55[0:0];
|
||||
_RAND_56 = {1{`RANDOM}};
|
||||
addr_external_r = _RAND_56[0:0];
|
||||
_RAND_57 = {1{`RANDOM}};
|
||||
bus_read_data_r = _RAND_57[31:0];
|
||||
bus_read_data_r = _RAND_53[31:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
access_fault_m = 1'h0;
|
||||
|
|
@ -1017,54 +999,42 @@ initial begin
|
|||
if (reset) begin
|
||||
_T_143 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_154 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_156 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_158 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_160 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
store_data_pre_m = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_161 = 32'h0;
|
||||
_T_153 = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_162 = 32'h0;
|
||||
_T_154 = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
end_addr_pre_m = 29'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_166 = 3'h0;
|
||||
_T_159 = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
end_addr_pre_r = 29'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_171 = 3'h0;
|
||||
_T_165 = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_179 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_180 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_181 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_182 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_183 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_184 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_185 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_186 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_187 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
addr_external_r = 1'h0;
|
||||
end
|
||||
|
|
@ -1367,34 +1337,6 @@ end // initial
|
|||
_T_143 <= io_lsu_pkt_m_valid & _T_136;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_154 <= 1'h0;
|
||||
end else begin
|
||||
_T_154 <= io_lsu_addr_d[2];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_156 <= 1'h0;
|
||||
end else begin
|
||||
_T_156 <= io_end_addr_d[2];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_158 <= 1'h0;
|
||||
end else begin
|
||||
_T_158 <= io_lsu_addr_m[2];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_160 <= 1'h0;
|
||||
end else begin
|
||||
_T_160 <= io_end_addr_m[2];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
store_data_pre_m <= 32'h0;
|
||||
|
|
@ -1408,79 +1350,79 @@ end // initial
|
|||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_161 <= 32'h0;
|
||||
_T_153 <= 32'h0;
|
||||
end else begin
|
||||
_T_161 <= io_lsu_addr_d;
|
||||
_T_153 <= io_lsu_addr_d;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_162 <= 32'h0;
|
||||
_T_154 <= 32'h0;
|
||||
end else begin
|
||||
_T_162 <= io_lsu_addr_m;
|
||||
_T_154 <= io_lsu_addr_m;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
end_addr_pre_m <= 29'h0;
|
||||
end else if (_T_175) begin
|
||||
end else if (_T_169) begin
|
||||
end_addr_pre_m <= io_end_addr_d[31:3];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_166 <= 3'h0;
|
||||
_T_159 <= 3'h0;
|
||||
end else begin
|
||||
_T_166 <= io_end_addr_d[2:0];
|
||||
_T_159 <= io_end_addr_d[2:0];
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
end_addr_pre_r <= 29'h0;
|
||||
end else if (_T_180) begin
|
||||
end else if (_T_175) begin
|
||||
end_addr_pre_r <= io_end_addr_m[31:3];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_171 <= 3'h0;
|
||||
_T_165 <= 3'h0;
|
||||
end else begin
|
||||
_T_171 <= io_end_addr_m[2:0];
|
||||
_T_165 <= io_end_addr_m[2:0];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_179 <= 1'h0;
|
||||
end else begin
|
||||
_T_179 <= io_addr_in_dccm_d;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_180 <= 1'h0;
|
||||
end else begin
|
||||
_T_180 <= io_addr_in_dccm_m;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_181 <= 1'h0;
|
||||
end else begin
|
||||
_T_181 <= io_addr_in_pic_d;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_182 <= 1'h0;
|
||||
end else begin
|
||||
_T_182 <= io_addr_in_pic_m;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_183 <= 1'h0;
|
||||
end else begin
|
||||
_T_183 <= io_addr_in_dccm_d;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_184 <= 1'h0;
|
||||
end else begin
|
||||
_T_184 <= io_addr_in_dccm_m;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_185 <= 1'h0;
|
||||
end else begin
|
||||
_T_185 <= io_addr_in_pic_d;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_186 <= 1'h0;
|
||||
end else begin
|
||||
_T_186 <= io_addr_in_pic_m;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_187 <= 1'h0;
|
||||
end else begin
|
||||
_T_187 <= addrcheck_io_addr_external_d;
|
||||
_T_183 <= addrcheck_io_addr_external_d;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
|
|
@ -1493,7 +1435,7 @@ end // initial
|
|||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
bus_read_data_r <= 32'h0;
|
||||
end else if (_T_188) begin
|
||||
end else if (_T_184) begin
|
||||
bus_read_data_r <= io_bus_read_data_m;
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
package lsu
|
||||
|
||||
import lib._
|
||||
import chisel3._
|
||||
import chisel3.{withClock, _}
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import mem._
|
||||
|
|
@ -65,9 +65,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
// val end_addr_m = WireInit(0.U(32.W))
|
||||
// val end_addr_r = WireInit(0.U(32.W))
|
||||
val lsu_busreq_r = WireInit(Bool(),false.B)
|
||||
// val ldst_dual_d = WireInit(Bool(),false.B)
|
||||
// val ldst_dual_m = WireInit(Bool(),false.B)
|
||||
// val ldst_dual_r = WireInit(Bool(),false.B)
|
||||
val ldst_dual_d = WireInit(Bool(),false.B)
|
||||
val ldst_dual_m = WireInit(Bool(),false.B)
|
||||
val ldst_dual_r = WireInit(Bool(),false.B)
|
||||
|
||||
val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
|
||||
// io.lsu_exu.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
|
||||
|
|
@ -138,9 +138,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||
lsu_lsc_ctl.io.flush_m_up := flush_m_up
|
||||
lsu_lsc_ctl.io.flush_r := flush_r
|
||||
lsu_lsc_ctl.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
|
||||
lsu_lsc_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
|
||||
lsu_lsc_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d
|
||||
lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m
|
||||
lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r
|
||||
lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu
|
||||
lsu_lsc_ctl.io.lsu_p <> io.lsu_p
|
||||
lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
|
|
@ -153,9 +153,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
//Outputs
|
||||
|
||||
|
||||
// ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
|
||||
// ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
|
||||
// ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
|
||||
ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= withClock(clkdomain.io.lsu_c1_m_clk){RegNext(lsu_lsc_ctl.io.end_addr_d(2),0.U)}//=/= lsu_lsc_ctl.io.end_addr_m(2)
|
||||
ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= withClock(clkdomain.io.lsu_c1_r_clk){RegNext(lsu_lsc_ctl.io.end_addr_m(2),0.U)}//=/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
|
||||
io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
|
||||
io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r
|
||||
|
|
@ -164,8 +164,8 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
// DCCM Control
|
||||
//Inputs
|
||||
dccm_ctl.io.clk_override := io.clk_override
|
||||
dccm_ctl.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
|
||||
dccm_ctl.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
dccm_ctl.io.ldst_dual_m := ldst_dual_m
|
||||
dccm_ctl.io.ldst_dual_r := ldst_dual_r
|
||||
dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||
dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
|
|
@ -224,9 +224,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
io.lsu_pic <> dccm_ctl.io.lsu_pic
|
||||
//Store Buffer
|
||||
//Inputs
|
||||
stbuf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
|
||||
stbuf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
|
||||
stbuf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
stbuf.io.ldst_dual_d := ldst_dual_d
|
||||
stbuf.io.ldst_dual_m := ldst_dual_m
|
||||
stbuf.io.ldst_dual_r := ldst_dual_r
|
||||
stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
|
||||
stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
|
|
@ -327,9 +327,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk
|
||||
bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
bus_intf.io.lsu_busreq_m := lsu_busreq_m
|
||||
bus_intf.io.ldst_dual_d := lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
|
||||
bus_intf.io.ldst_dual_m := lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
|
||||
bus_intf.io.ldst_dual_r := lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
|
||||
bus_intf.io.ldst_dual_d := ldst_dual_d
|
||||
bus_intf.io.ldst_dual_m := ldst_dual_m
|
||||
bus_intf.io.ldst_dual_r := ldst_dual_r
|
||||
bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
|
||||
bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r & Fill(32,lsu_busreq_r)
|
||||
bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
|
||||
|
|
|
|||
|
|
@ -166,13 +166,15 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
|||
val fwd_data = WireInit(UInt(32.W), 0.U)
|
||||
val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_))
|
||||
val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_))
|
||||
io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _),
|
||||
io.ld_fwddata_buf_lo := Cat(
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _),
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _),
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _),
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) |
|
||||
(ld_fwddata_buf_lo_initial & ibuf_data)
|
||||
|
||||
io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _),
|
||||
io.ld_fwddata_buf_hi := Cat(
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _),
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _),
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _),
|
||||
(0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) |
|
||||
|
|
|
|||
|
|
@ -26,9 +26,9 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
|
|||
|
||||
val flush_m_up = Input(UInt(1.W))
|
||||
val flush_r = Input(UInt(1.W))
|
||||
val ldst_dual_d = Input(Bool())
|
||||
val ldst_dual_m = Input(Bool())
|
||||
val ldst_dual_r = Input(Bool())
|
||||
val ldst_dual_d = Input(UInt(1.W))
|
||||
val ldst_dual_m = Input(UInt(1.W))
|
||||
val ldst_dual_r = Input(UInt(1.W))
|
||||
|
||||
val lsu_exu = new lsu_exu()
|
||||
|
||||
|
|
@ -221,15 +221,14 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
|
|||
val dma_mem_wdata_shifted = io.dma_lsc_ctl.dma_mem_wdata(63,0) >> Cat(io.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||
val store_data_d = Mux(io.dma_lsc_ctl.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.lsu_exu.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage
|
||||
val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_exu.lsu_result_m(31,0),store_data_d(31,0))
|
||||
val int = withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d(2),0.U)} =/= withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2),0.U)}
|
||||
val int1 = withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m(2),0.U)} =/= withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2),0.U)}
|
||||
|
||||
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
|
||||
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
|
||||
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
|
||||
io.end_addr_m := Cat(Mux(int,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)})
|
||||
io.end_addr_r := Cat(Mux(int1,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)})
|
||||
io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)})
|
||||
io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)})
|
||||
end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode)
|
||||
end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & int) | io.clk_override),clock,io.scan_mode)
|
||||
end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode)
|
||||
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
|
||||
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
|
||||
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue