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decode updated

This commit is contained in:
waleed-lm 2020-12-10 17:41:24 +05:00
parent f59510b304
commit 8229bfbc95
4 changed files with 800 additions and 752 deletions
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@ -46630,10 +46630,10 @@ module dec_decode_ctl(
reg x_d_bits_i0load; // @[lib.scala 368:16] reg x_d_bits_i0load; // @[lib.scala 368:16]
reg [4:0] x_d_bits_i0rd; // @[lib.scala 368:16] reg [4:0] x_d_bits_i0rd; // @[lib.scala 368:16]
wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31] wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31]
reg [2:0] _T_704; // @[dec_decode_ctl.scala 622:80] reg [2:0] _T_706; // @[dec_decode_ctl.scala 622:80]
wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_704}; // @[Cat.scala 29:58] wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_706}; // @[Cat.scala 29:58]
wire _T_710 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49] wire _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49]
wire i0_r_ctl_en = _T_710 | io_clk_override; // @[dec_decode_ctl.scala 625:53] wire i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 625:53]
reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
reg r_d_bits_i0load; // @[lib.scala 368:16] reg r_d_bits_i0load; // @[lib.scala 368:16]
wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56] wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56]
@ -46642,10 +46642,10 @@ module dec_decode_ctl(
wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45] wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45]
wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87] wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87]
reg r_d_bits_i0v; // @[lib.scala 368:16] reg r_d_bits_i0v; // @[lib.scala 368:16]
wire _T_746 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51] wire _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51]
wire r_d_in_bits_i0v = r_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 657:49] wire r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 657:49]
wire _T_757 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47] wire _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47]
wire i0_wen_r = r_d_in_bits_i0v & _T_757; // @[dec_decode_ctl.scala 665:45] wire i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 665:45]
reg [4:0] r_d_bits_i0rd; // @[lib.scala 368:16] reg [4:0] r_d_bits_i0rd; // @[lib.scala 368:16]
reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47] reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47]
wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85] wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85]
@ -46795,34 +46795,34 @@ module dec_decode_ctl(
wire _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 390:67] wire _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 390:67]
reg _T_339; // @[dec_decode_ctl.scala 402:69] reg _T_339; // @[dec_decode_ctl.scala 402:69]
wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40]
wire _T_905 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43] wire _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43]
reg x_d_bits_i0v; // @[lib.scala 368:16] reg x_d_bits_i0v; // @[lib.scala 368:16]
wire _T_879 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59] wire _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59]
wire _T_880 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91] wire _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91]
wire i0_rs1_depend_i0_x = _T_879 & _T_880; // @[dec_decode_ctl.scala 738:74] wire i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 738:74]
wire _T_881 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59] wire _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59]
wire _T_882 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91] wire _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91]
wire i0_rs1_depend_i0_r = _T_881 & _T_882; // @[dec_decode_ctl.scala 739:74] wire i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 739:74]
wire [1:0] _T_894 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63] wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63]
wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_894; // @[dec_decode_ctl.scala 745:24] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 745:24]
wire _T_907 = _T_905 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58] wire _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58]
reg i0_x_c_load; // @[Reg.scala 15:16] reg i0_x_c_load; // @[Reg.scala 27:20]
reg i0_r_c_load; // @[Reg.scala 15:16] reg i0_r_c_load; // @[Reg.scala 27:20]
wire _T_890_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61] wire _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61]
wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_890_load; // @[dec_decode_ctl.scala 744:24] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 744:24]
wire load_ldst_bypass_d = _T_907 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78] wire load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78]
wire _T_883 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59] wire _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59]
wire _T_884 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91] wire _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91]
wire i0_rs2_depend_i0_x = _T_883 & _T_884; // @[dec_decode_ctl.scala 741:74] wire i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 741:74]
wire _T_885 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59] wire _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59]
wire _T_886 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91] wire _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91]
wire i0_rs2_depend_i0_r = _T_885 & _T_886; // @[dec_decode_ctl.scala 742:74] wire i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 742:74]
wire [1:0] _T_903 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63] wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63]
wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_903; // @[dec_decode_ctl.scala 747:24] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 747:24]
wire _T_910 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43] wire _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43]
wire _T_899_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61] wire _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61]
wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_899_load; // @[dec_decode_ctl.scala 746:24] wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 746:24]
wire store_data_bypass_d = _T_910 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63] wire store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63]
wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42]
reg r_d_bits_csrwen; // @[lib.scala 368:16] reg r_d_bits_csrwen; // @[lib.scala 368:16]
reg r_d_valid; // @[lib.scala 368:16] reg r_d_valid; // @[lib.scala 368:16]
@ -46864,9 +46864,9 @@ module dec_decode_ctl(
wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61] wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61]
wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75] wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75]
reg r_d_bits_csrwonly; // @[lib.scala 368:16] reg r_d_bits_csrwonly; // @[lib.scala 368:16]
wire _T_767 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42] wire _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42]
reg [31:0] i0_result_r_raw; // @[lib.scala 358:16] reg [31:0] i0_result_r_raw; // @[lib.scala 358:16]
wire [31:0] i0_result_corr_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27] wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27]
reg x_d_bits_csrwonly; // @[lib.scala 368:16] reg x_d_bits_csrwonly; // @[lib.scala 368:16]
wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43] wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43]
reg wbd_bits_csrwonly; // @[lib.scala 368:16] reg wbd_bits_csrwonly; // @[lib.scala 368:16]
@ -46896,13 +46896,13 @@ module dec_decode_ctl(
wire _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 513:34] wire _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 513:34]
wire _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 512:79] wire _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 512:79]
wire _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 513:47] wire _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 513:47]
wire _T_825 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60] wire _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60]
wire _T_826 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99] wire _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99]
wire _T_827 = _T_825 & _T_826; // @[dec_decode_ctl.scala 708:80] wire _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 708:80]
wire _T_828 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36] wire _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36]
wire _T_829 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75] wire _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75]
wire _T_830 = _T_828 & _T_829; // @[dec_decode_ctl.scala 709:56] wire _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 709:56]
wire i0_nonblock_div_stall = _T_827 | _T_830; // @[dec_decode_ctl.scala 708:113] wire i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 708:113]
wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21] wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21]
wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45] wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45]
wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65] wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65]
@ -46922,8 +46922,8 @@ module dec_decode_ctl(
wire _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 528:51] wire _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 528:51]
wire _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 556:44] wire _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 556:44]
wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58] wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58]
wire _T_707 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49] wire _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49]
wire i0_x_ctl_en = _T_707 | io_clk_override; // @[dec_decode_ctl.scala 624:53] wire i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 624:53]
reg x_t_legal; // @[lib.scala 368:16] reg x_t_legal; // @[lib.scala 368:16]
reg x_t_icaf; // @[lib.scala 368:16] reg x_t_icaf; // @[lib.scala 368:16]
reg x_t_icaf_f1; // @[lib.scala 368:16] reg x_t_icaf_f1; // @[lib.scala 368:16]
@ -46980,133 +46980,133 @@ module dec_decode_ctl(
wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 616:44] wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 616:44]
wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 617:44] wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 617:44]
wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 618:44] wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 618:44]
reg i0_x_c_mul; // @[Reg.scala 15:16] reg i0_x_c_mul; // @[Reg.scala 27:20]
reg i0_x_c_alu; // @[Reg.scala 15:16] reg i0_x_c_alu; // @[Reg.scala 27:20]
reg i0_r_c_mul; // @[Reg.scala 15:16] reg i0_r_c_mul; // @[Reg.scala 27:20]
reg i0_r_c_alu; // @[Reg.scala 15:16] reg i0_r_c_alu; // @[Reg.scala 27:20]
wire _T_713 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49] wire _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49]
wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50]
reg x_d_bits_i0store; // @[lib.scala 368:16] reg x_d_bits_i0store; // @[lib.scala 368:16]
reg x_d_bits_i0div; // @[lib.scala 368:16] reg x_d_bits_i0div; // @[lib.scala 368:16]
reg x_d_bits_csrwen; // @[lib.scala 368:16] reg x_d_bits_csrwen; // @[lib.scala 368:16]
reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 368:16] reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 368:16]
wire _T_736 = x_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 650:47] wire _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 650:47]
wire _T_740 = x_d_valid & _T_746; // @[dec_decode_ctl.scala 651:33] wire _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 651:33]
wire _T_759 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49] wire _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49]
wire _T_760 = i0_wen_r & _T_759; // @[dec_decode_ctl.scala 666:47] wire _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 666:47]
wire _T_761 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70] wire _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70]
wire _T_764 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47] wire _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47]
wire _T_771 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71] wire _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71]
wire [11:0] _T_784 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] wire [11:0] _T_786 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
reg [11:0] last_br_immed_x; // @[lib.scala 358:16] reg [11:0] last_br_immed_x; // @[lib.scala 358:16]
wire _T_802 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45] wire _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45]
wire div_e1_to_r = _T_802 | _T_548; // @[dec_decode_ctl.scala 689:58] wire div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 689:58]
wire _T_805 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77] wire _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77]
wire _T_806 = _T_802 & _T_805; // @[dec_decode_ctl.scala 691:60] wire _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 691:60]
wire _T_808 = _T_802 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33] wire _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33]
wire _T_809 = _T_806 | _T_808; // @[dec_decode_ctl.scala 691:94] wire _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 691:94]
wire _T_811 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33] wire _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33]
wire _T_812 = _T_811 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60] wire _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60]
wire div_flush = _T_809 | _T_812; // @[dec_decode_ctl.scala 692:62] wire div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 692:62]
wire _T_813 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51] wire _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51]
wire _T_814 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26] wire _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26]
wire _T_815 = io_dec_div_active & _T_814; // @[dec_decode_ctl.scala 698:24] wire _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 698:24]
wire _T_816 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56] wire _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56]
wire _T_817 = _T_815 & _T_816; // @[dec_decode_ctl.scala 698:39] wire _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 698:39]
wire _T_818 = _T_817 & i0_wen_r; // @[dec_decode_ctl.scala 698:77] wire _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 698:77]
wire nonblock_div_cancel = _T_813 | _T_818; // @[dec_decode_ctl.scala 697:65] wire nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 697:65]
wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 701:55] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 701:55]
wire _T_820 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62] wire _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62]
wire _T_821 = io_dec_div_active & _T_820; // @[dec_decode_ctl.scala 703:60] wire _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 703:60]
wire _T_822 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81] wire _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81]
wire _T_823 = _T_821 & _T_822; // @[dec_decode_ctl.scala 703:79] wire _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 703:79]
reg _T_824; // @[dec_decode_ctl.scala 705:54] reg _T_826; // @[dec_decode_ctl.scala 705:54]
reg [4:0] _T_833; // @[Reg.scala 27:20] reg [4:0] _T_835; // @[Reg.scala 27:20]
reg [31:0] i0_inst_x; // @[lib.scala 358:16] reg [31:0] i0_inst_x; // @[lib.scala 358:16]
reg [31:0] i0_inst_r; // @[lib.scala 358:16] reg [31:0] i0_inst_r; // @[lib.scala 358:16]
reg [31:0] i0_inst_wb; // @[lib.scala 358:16] reg [31:0] i0_inst_wb; // @[lib.scala 358:16]
reg [31:0] _T_840; // @[lib.scala 358:16] reg [31:0] _T_842; // @[lib.scala 358:16]
reg [30:0] i0_pc_wb; // @[lib.scala 358:16] reg [30:0] i0_pc_wb; // @[lib.scala 358:16]
reg [30:0] _T_843; // @[lib.scala 358:16] reg [30:0] _T_845; // @[lib.scala 358:16]
reg [30:0] dec_i0_pc_r; // @[lib.scala 358:16] reg [30:0] dec_i0_pc_r; // @[lib.scala 358:16]
wire [31:0] _T_845 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_847 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_846 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_848 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_849 = _T_845[12:1] + _T_846[12:1]; // @[lib.scala 52:31] wire [12:0] _T_851 = _T_847[12:1] + _T_848[12:1]; // @[lib.scala 52:31]
wire [18:0] _T_852 = _T_845[31:13] + 19'h1; // @[lib.scala 53:27] wire [18:0] _T_854 = _T_847[31:13] + 19'h1; // @[lib.scala 53:27]
wire [18:0] _T_855 = _T_845[31:13] - 19'h1; // @[lib.scala 54:27] wire [18:0] _T_857 = _T_847[31:13] - 19'h1; // @[lib.scala 54:27]
wire _T_858 = ~_T_849[12]; // @[lib.scala 56:28] wire _T_860 = ~_T_851[12]; // @[lib.scala 56:28]
wire _T_859 = _T_846[12] ^ _T_858; // @[lib.scala 56:26] wire _T_861 = _T_848[12] ^ _T_860; // @[lib.scala 56:26]
wire _T_862 = ~_T_846[12]; // @[lib.scala 57:20] wire _T_864 = ~_T_848[12]; // @[lib.scala 57:20]
wire _T_864 = _T_862 & _T_849[12]; // @[lib.scala 57:26] wire _T_866 = _T_864 & _T_851[12]; // @[lib.scala 57:26]
wire _T_868 = _T_846[12] & _T_858; // @[lib.scala 58:26] wire _T_870 = _T_848[12] & _T_860; // @[lib.scala 58:26]
wire [18:0] _T_870 = _T_859 ? _T_845[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_872 = _T_861 ? _T_847[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_871 = _T_864 ? _T_852 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_873 = _T_866 ? _T_854 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_872 = _T_868 ? _T_855 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_874 = _T_870 ? _T_857 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_873 = _T_870 | _T_871; // @[Mux.scala 27:72] wire [18:0] _T_875 = _T_872 | _T_873; // @[Mux.scala 27:72]
wire [18:0] _T_874 = _T_873 | _T_872; // @[Mux.scala 27:72] wire [18:0] _T_876 = _T_875 | _T_874; // @[Mux.scala 27:72]
wire [31:0] temp_pred_correct_npc_x = {_T_874,_T_849[11:0],1'h0}; // @[Cat.scala 29:58] wire [31:0] temp_pred_correct_npc_x = {_T_876,_T_851[11:0],1'h0}; // @[Cat.scala 29:58]
wire _T_890_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61] wire _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61]
wire _T_890_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61] wire _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61]
wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_890_mul; // @[dec_decode_ctl.scala 744:24] wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 744:24]
wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_890_alu; // @[dec_decode_ctl.scala 744:24] wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 744:24]
wire _T_899_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61] wire _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61]
wire _T_899_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61] wire _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61]
wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_899_mul; // @[dec_decode_ctl.scala 746:24] wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 746:24]
wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_899_alu; // @[dec_decode_ctl.scala 746:24] wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 746:24]
wire _T_912 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73] wire _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73]
wire _T_913 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130] wire _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130]
wire i0_rs1_nonblock_load_bypass_en_d = _T_912 & _T_913; // @[dec_decode_ctl.scala 764:100] wire i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 764:100]
wire _T_914 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73] wire _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73]
wire _T_915 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130] wire _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130]
wire i0_rs2_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 766:100] wire i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 766:100]
wire _T_917 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66] wire _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66]
wire _T_918 = i0_rs1_depth_d[0] & _T_917; // @[dec_decode_ctl.scala 769:45] wire _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 769:45]
wire _T_920 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108] wire _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108]
wire _T_923 = _T_917 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196] wire _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196]
wire _T_924 = i0_rs1_depth_d[1] & _T_923; // @[dec_decode_ctl.scala 769:153] wire _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 769:153]
wire [2:0] i0_rs1bypass = {_T_918,_T_920,_T_924}; // @[Cat.scala 29:58] wire [2:0] i0_rs1bypass = {_T_920,_T_922,_T_926}; // @[Cat.scala 29:58]
wire _T_928 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67] wire _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67]
wire _T_929 = i0_rs2_depth_d[0] & _T_928; // @[dec_decode_ctl.scala 771:45] wire _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 771:45]
wire _T_931 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109] wire _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109]
wire _T_934 = _T_928 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196] wire _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196]
wire _T_935 = i0_rs2_depth_d[1] & _T_934; // @[dec_decode_ctl.scala 771:153] wire _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 771:153]
wire [2:0] i0_rs2bypass = {_T_929,_T_931,_T_935}; // @[Cat.scala 29:58] wire [2:0] i0_rs2bypass = {_T_931,_T_933,_T_937}; // @[Cat.scala 29:58]
wire _T_941 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86] wire _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86]
wire _T_943 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107] wire _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107]
wire _T_944 = _T_943 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124] wire _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124]
wire _T_945 = _T_941 | _T_944; // @[dec_decode_ctl.scala 773:104] wire _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 773:104]
wire _T_950 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86] wire _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86]
wire _T_952 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107] wire _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107]
wire _T_953 = _T_952 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124] wire _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124]
wire _T_954 = _T_950 | _T_953; // @[dec_decode_ctl.scala 774:104] wire _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 774:104]
wire _T_961 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6] wire _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6]
wire _T_963 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25] wire _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25]
wire _T_964 = _T_961 & _T_963; // @[dec_decode_ctl.scala 780:23] wire _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 780:23]
wire _T_965 = _T_964 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42] wire _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42]
wire [31:0] _T_967 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_969 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_968 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_970 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_969 = _T_965 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_971 = _T_967 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_970 = _T_967 | _T_968; // @[Mux.scala 27:72] wire [31:0] _T_972 = _T_969 | _T_970; // @[Mux.scala 27:72]
wire _T_978 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6] wire _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6]
wire _T_980 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25] wire _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25]
wire _T_981 = _T_978 & _T_980; // @[dec_decode_ctl.scala 785:23] wire _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 785:23]
wire _T_982 = _T_981 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42] wire _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42]
wire [31:0] _T_984 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_986 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_985 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_987 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_986 = _T_982 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_988 = _T_984 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72] wire [31:0] _T_989 = _T_986 | _T_987; // @[Mux.scala 27:72]
wire _T_990 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68] wire _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68]
wire _T_991 = io_dec_ib0_valid_d & _T_990; // @[dec_decode_ctl.scala 787:50] wire _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 787:50]
wire _T_992 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89] wire _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89]
wire _T_993 = _T_991 & _T_992; // @[dec_decode_ctl.scala 787:87] wire _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 787:87]
wire _T_995 = _T_993 & _T_496; // @[dec_decode_ctl.scala 787:121] wire _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 787:121]
wire _T_997 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6] wire _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6]
wire _T_998 = _T_997 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38] wire _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38]
wire _T_999 = _T_998 & i0_dp_load; // @[dec_decode_ctl.scala 789:50] wire _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 789:50]
wire _T_1004 = _T_998 & i0_dp_store; // @[dec_decode_ctl.scala 790:50] wire _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 790:50]
wire [11:0] _T_1008 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1010 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
wire [11:0] _T_1009 = _T_999 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1011 = _T_1001 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1010 = _T_1004 ? _T_1008 : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1012 = _T_1006 ? _T_1010 : 12'h0; // @[Mux.scala 27:72]
rvclkhdr rvclkhdr ( // @[lib.scala 327:22] rvclkhdr rvclkhdr ( // @[lib.scala 327:22]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -47318,11 +47318,11 @@ module dec_decode_ctl(
assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 594:35] assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 594:35]
assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 595:35] assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 595:35]
assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 603:32] assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 603:32]
assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_970 | _T_969; // @[dec_decode_ctl.scala 777:42] assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 777:42]
assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_987 | _T_986; // @[dec_decode_ctl.scala 782:42] assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 782:42]
assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 241:36] assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 241:36]
assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_945}; // @[dec_decode_ctl.scala 773:45] assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 773:45]
assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_954}; // @[dec_decode_ctl.scala 774:45] assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 774:45]
assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 397:32] assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 397:32]
assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 398:37] assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 398:37]
assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 399:37] assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 399:37]
@ -47331,18 +47331,18 @@ module dec_decode_ctl(
assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 402:34] assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 402:34]
assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 542:34] assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 542:34]
assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 424:29] assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 424:29]
assign io_dec_alu_dec_i0_br_immed_d = _T_771 ? i0_br_offset : _T_784; // @[dec_decode_ctl.scala 681:32] assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 681:32]
assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 393:29] assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 393:29]
assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 394:34] assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 394:34]
assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 395:34] assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 395:34]
assign io_dec_div_dec_div_cancel = _T_813 | _T_818; // @[dec_decode_ctl.scala 700:37] assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 700:37]
assign io_dec_i0_inst_wb1 = _T_840; // @[dec_decode_ctl.scala 723:22] assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 723:22]
assign io_dec_i0_pc_wb1 = _T_843; // @[dec_decode_ctl.scala 726:20] assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 726:20]
assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 597:19] assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 597:19]
assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 598:19] assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 598:19]
assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 664:27] assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 664:27]
assign io_dec_i0_wen_r = _T_760 & _T_761; // @[dec_decode_ctl.scala 666:32] assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 666:32]
assign io_dec_i0_wdata_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26] assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26]
assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 409:24 dec_decode_ctl.scala 411:35] assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 409:24 dec_decode_ctl.scala 411:35]
assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 408:29] assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 408:29]
assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 414:40] assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 414:40]
@ -47353,17 +47353,17 @@ module dec_decode_ctl(
assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 420:40] assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 420:40]
assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 418:40] assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 418:40]
assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 417:40] assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 417:40]
assign io_div_waddr_wb = _T_833; // @[dec_decode_ctl.scala 711:19] assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 711:19]
assign io_dec_lsu_valid_raw_d = _T_995 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26] assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26]
assign io_dec_lsu_offset_d = _T_1009 | _T_1010; // @[dec_decode_ctl.scala 788:23] assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 788:23]
assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 433:24] assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 433:24]
assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 499:24] assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 499:24]
assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 436:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 436:24]
assign io_dec_csr_wen_r = _T_352 & _T_757; // @[dec_decode_ctl.scala 441:20] assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 441:20]
assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 437:23] assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 437:23]
assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 484:24] assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 484:24]
assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 444:27] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 444:27]
assign io_dec_tlu_i0_valid_r = r_d_valid & _T_746; // @[dec_decode_ctl.scala 548:29] assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 548:29]
assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 582:39] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 582:39]
assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 582:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 582:39]
assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 582:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 582:39]
@ -47384,7 +47384,7 @@ module dec_decode_ctl(
assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 321:29 dec_decode_ctl.scala 331:29] assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 321:29 dec_decode_ctl.scala 331:29]
assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 468:22] assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 468:22]
assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25] assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25]
assign io_dec_div_active = _T_824; // @[dec_decode_ctl.scala 705:21] assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 705:21]
assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30] assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30]
assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 329:16] assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 329:16]
@ -47403,19 +47403,19 @@ module dec_decode_ctl(
assign rvclkhdr_4_io_en = shift_illegal & _T_467; // @[lib.scala 355:17] assign rvclkhdr_4_io_en = shift_illegal & _T_467; // @[lib.scala 355:17]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 364:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 364:18]
assign rvclkhdr_5_io_en = _T_707 | io_clk_override; // @[lib.scala 365:17] assign rvclkhdr_5_io_en = _T_709 | io_clk_override; // @[lib.scala 365:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 366:24] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 364:18] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 364:18]
assign rvclkhdr_6_io_en = _T_707 | io_clk_override; // @[lib.scala 365:17] assign rvclkhdr_6_io_en = _T_709 | io_clk_override; // @[lib.scala 365:17]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 366:24] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 364:18] assign rvclkhdr_7_io_clk = clock; // @[lib.scala 364:18]
assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[lib.scala 365:17] assign rvclkhdr_7_io_en = _T_709 | io_clk_override; // @[lib.scala 365:17]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 366:24] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 364:18] assign rvclkhdr_8_io_clk = clock; // @[lib.scala 364:18]
assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[lib.scala 365:17] assign rvclkhdr_8_io_en = _T_712 | io_clk_override; // @[lib.scala 365:17]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 366:24] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 364:18] assign rvclkhdr_9_io_clk = clock; // @[lib.scala 364:18]
assign rvclkhdr_9_io_en = _T_713 | io_clk_override; // @[lib.scala 365:17] assign rvclkhdr_9_io_en = _T_715 | io_clk_override; // @[lib.scala 365:17]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 366:24] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18]
assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 355:17] assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 355:17]
@ -47523,7 +47523,7 @@ initial begin
_RAND_19 = {1{`RANDOM}}; _RAND_19 = {1{`RANDOM}};
x_d_bits_i0rd = _RAND_19[4:0]; x_d_bits_i0rd = _RAND_19[4:0];
_RAND_20 = {1{`RANDOM}}; _RAND_20 = {1{`RANDOM}};
_T_704 = _RAND_20[2:0]; _T_706 = _RAND_20[2:0];
_RAND_21 = {1{`RANDOM}}; _RAND_21 = {1{`RANDOM}};
nonblock_load_valid_m_delay = _RAND_21[0:0]; nonblock_load_valid_m_delay = _RAND_21[0:0];
_RAND_22 = {1{`RANDOM}}; _RAND_22 = {1{`RANDOM}};
@ -47647,9 +47647,9 @@ initial begin
_RAND_81 = {1{`RANDOM}}; _RAND_81 = {1{`RANDOM}};
last_br_immed_x = _RAND_81[11:0]; last_br_immed_x = _RAND_81[11:0];
_RAND_82 = {1{`RANDOM}}; _RAND_82 = {1{`RANDOM}};
_T_824 = _RAND_82[0:0]; _T_826 = _RAND_82[0:0];
_RAND_83 = {1{`RANDOM}}; _RAND_83 = {1{`RANDOM}};
_T_833 = _RAND_83[4:0]; _T_835 = _RAND_83[4:0];
_RAND_84 = {1{`RANDOM}}; _RAND_84 = {1{`RANDOM}};
i0_inst_x = _RAND_84[31:0]; i0_inst_x = _RAND_84[31:0];
_RAND_85 = {1{`RANDOM}}; _RAND_85 = {1{`RANDOM}};
@ -47657,11 +47657,11 @@ initial begin
_RAND_86 = {1{`RANDOM}}; _RAND_86 = {1{`RANDOM}};
i0_inst_wb = _RAND_86[31:0]; i0_inst_wb = _RAND_86[31:0];
_RAND_87 = {1{`RANDOM}}; _RAND_87 = {1{`RANDOM}};
_T_840 = _RAND_87[31:0]; _T_842 = _RAND_87[31:0];
_RAND_88 = {1{`RANDOM}}; _RAND_88 = {1{`RANDOM}};
i0_pc_wb = _RAND_88[30:0]; i0_pc_wb = _RAND_88[30:0];
_RAND_89 = {1{`RANDOM}}; _RAND_89 = {1{`RANDOM}};
_T_843 = _RAND_89[30:0]; _T_845 = _RAND_89[30:0];
_RAND_90 = {1{`RANDOM}}; _RAND_90 = {1{`RANDOM}};
dec_i0_pc_r = _RAND_90[30:0]; dec_i0_pc_r = _RAND_90[30:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
@ -47726,7 +47726,7 @@ initial begin
x_d_bits_i0rd = 5'h0; x_d_bits_i0rd = 5'h0;
end end
if (reset) begin if (reset) begin
_T_704 = 3'h0; _T_706 = 3'h0;
end end
if (reset) begin if (reset) begin
nonblock_load_valid_m_delay = 1'h0; nonblock_load_valid_m_delay = 1'h0;
@ -47773,6 +47773,12 @@ initial begin
if (reset) begin if (reset) begin
x_d_bits_i0v = 1'h0; x_d_bits_i0v = 1'h0;
end end
if (reset) begin
i0_x_c_load = 1'h0;
end
if (reset) begin
i0_r_c_load = 1'h0;
end
if (reset) begin if (reset) begin
r_d_bits_csrwen = 1'h0; r_d_bits_csrwen = 1'h0;
end end
@ -47878,6 +47884,18 @@ initial begin
if (reset) begin if (reset) begin
r_d_bits_i0div = 1'h0; r_d_bits_i0div = 1'h0;
end end
if (reset) begin
i0_x_c_mul = 1'h0;
end
if (reset) begin
i0_x_c_alu = 1'h0;
end
if (reset) begin
i0_r_c_mul = 1'h0;
end
if (reset) begin
i0_r_c_alu = 1'h0;
end
if (reset) begin if (reset) begin
x_d_bits_i0store = 1'h0; x_d_bits_i0store = 1'h0;
end end
@ -47894,10 +47912,10 @@ initial begin
last_br_immed_x = 12'h0; last_br_immed_x = 12'h0;
end end
if (reset) begin if (reset) begin
_T_824 = 1'h0; _T_826 = 1'h0;
end end
if (reset) begin if (reset) begin
_T_833 = 5'h0; _T_835 = 5'h0;
end end
if (reset) begin if (reset) begin
i0_inst_x = 32'h0; i0_inst_x = 32'h0;
@ -47909,13 +47927,13 @@ initial begin
i0_inst_wb = 32'h0; i0_inst_wb = 32'h0;
end end
if (reset) begin if (reset) begin
_T_840 = 32'h0; _T_842 = 32'h0;
end end
if (reset) begin if (reset) begin
i0_pc_wb = 31'h0; i0_pc_wb = 31'h0;
end end
if (reset) begin if (reset) begin
_T_843 = 31'h0; _T_845 = 31'h0;
end end
if (reset) begin if (reset) begin
dec_i0_pc_r = 31'h0; dec_i0_pc_r = 31'h0;
@ -47926,26 +47944,6 @@ end // initial
`FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL
`endif `endif
`endif // SYNTHESIS `endif // SYNTHESIS
always @(posedge io_active_clk) begin
if (i0_x_ctl_en) begin
i0_x_c_load <= i0_d_c_load;
end
if (i0_r_ctl_en) begin
i0_r_c_load <= i0_x_c_load;
end
if (i0_x_ctl_en) begin
i0_x_c_mul <= i0_d_c_mul;
end
if (i0_x_ctl_en) begin
i0_x_c_alu <= i0_d_c_alu;
end
if (i0_r_ctl_en) begin
i0_r_c_mul <= i0_x_c_mul;
end
if (i0_r_ctl_en) begin
i0_r_c_alu <= i0_x_c_alu;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
tlu_wr_pause_r1 <= 1'h0; tlu_wr_pause_r1 <= 1'h0;
@ -48108,9 +48106,9 @@ end // initial
end end
always @(posedge io_active_clk or posedge reset) begin always @(posedge io_active_clk or posedge reset) begin
if (reset) begin if (reset) begin
_T_704 <= 3'h0; _T_706 <= 3'h0;
end else begin end else begin
_T_704 <= i0_pipe_en[3:1]; _T_706 <= i0_pipe_en[3:1];
end end
end end
always @(posedge io_active_clk or posedge reset) begin always @(posedge io_active_clk or posedge reset) begin
@ -48131,7 +48129,7 @@ end // initial
if (reset) begin if (reset) begin
r_d_bits_i0v <= 1'h0; r_d_bits_i0v <= 1'h0;
end else begin end else begin
r_d_bits_i0v <= _T_736 & _T_280; r_d_bits_i0v <= _T_738 & _T_280;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
@ -48242,6 +48240,20 @@ end // initial
x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d;
end end
end end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
i0_x_c_load <= 1'h0;
end else if (i0_x_ctl_en) begin
i0_x_c_load <= i0_d_c_load;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
i0_r_c_load <= 1'h0;
end else if (i0_r_ctl_en) begin
i0_r_c_load <= i0_x_c_load;
end
end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_bits_csrwen <= 1'h0; r_d_bits_csrwen <= 1'h0;
@ -48253,7 +48265,7 @@ end // initial
if (reset) begin if (reset) begin
r_d_valid <= 1'h0; r_d_valid <= 1'h0;
end else begin end else begin
r_d_valid <= _T_740 & _T_280; r_d_valid <= _T_742 & _T_280;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
@ -48324,7 +48336,7 @@ end // initial
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
i0_result_r_raw <= 32'h0; i0_result_r_raw <= 32'h0;
end else if (_T_764) begin end else if (_T_766) begin
i0_result_r_raw <= io_lsu_result_m; i0_result_r_raw <= io_lsu_result_m;
end else begin end else begin
i0_result_r_raw <= io_decode_exu_exu_i0_result_x; i0_result_r_raw <= io_decode_exu_exu_i0_result_x;
@ -48493,6 +48505,34 @@ end // initial
r_d_bits_i0div <= x_d_bits_i0div; r_d_bits_i0div <= x_d_bits_i0div;
end end
end end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
i0_x_c_mul <= 1'h0;
end else if (i0_x_ctl_en) begin
i0_x_c_mul <= i0_d_c_mul;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
i0_x_c_alu <= 1'h0;
end else if (i0_x_ctl_en) begin
i0_x_c_alu <= i0_d_c_alu;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
i0_r_c_mul <= 1'h0;
end else if (i0_r_ctl_en) begin
i0_r_c_mul <= i0_x_c_mul;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
i0_r_c_alu <= 1'h0;
end else if (i0_r_ctl_en) begin
i0_r_c_alu <= i0_x_c_alu;
end
end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_bits_i0store <= 1'h0; x_d_bits_i0store <= 1'h0;
@ -48525,7 +48565,7 @@ end // initial
if (reset) begin if (reset) begin
last_br_immed_x <= 12'h0; last_br_immed_x <= 12'h0;
end else if (io_decode_exu_i0_ap_predict_nt) begin end else if (io_decode_exu_i0_ap_predict_nt) begin
last_br_immed_x <= _T_784; last_br_immed_x <= _T_786;
end else if (_T_314) begin end else if (_T_314) begin
last_br_immed_x <= i0_pcall_imm[11:0]; last_br_immed_x <= i0_pcall_imm[11:0];
end else begin end else begin
@ -48534,16 +48574,16 @@ end // initial
end end
always @(posedge io_free_clk or posedge reset) begin always @(posedge io_free_clk or posedge reset) begin
if (reset) begin if (reset) begin
_T_824 <= 1'h0; _T_826 <= 1'h0;
end else begin end else begin
_T_824 <= i0_div_decode_d | _T_823; _T_826 <= i0_div_decode_d | _T_825;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
_T_833 <= 5'h0; _T_835 <= 5'h0;
end else if (i0_div_decode_d) begin end else if (i0_div_decode_d) begin
_T_833 <= i0r_rd; _T_835 <= i0r_rd;
end end
end end
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
@ -48571,9 +48611,9 @@ end // initial
end end
always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
_T_840 <= 32'h0; _T_842 <= 32'h0;
end else begin end else begin
_T_840 <= i0_inst_wb; _T_842 <= i0_inst_wb;
end end
end end
always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
@ -48585,9 +48625,9 @@ end // initial
end end
always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
_T_843 <= 31'h0; _T_845 <= 31'h0;
end else begin end else begin
_T_843 <= i0_pc_wb; _T_845 <= i0_pc_wb;
end end
end end
always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin

8
src/main/scala/dec/dec_decode_ctl.scala
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@ -617,8 +617,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
i0_d_c.load := i0_dp.load & i0_legal_decode_d i0_d_c.load := i0_dp.load & i0_legal_decode_d
i0_d_c.alu := i0_dp.alu & i0_legal_decode_d i0_d_c.alu := i0_dp.alu & i0_legal_decode_d
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)} val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)}
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)} val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)}
i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
@ -667,7 +667,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
io.dec_i0_wdata_r := i0_result_corr_r io.dec_i0_wdata_r := i0_result_corr_r
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
if ( LOAD_TO_USE_PLUS1 == 1 ) { if ( LOAD_TO_USE_PLUS1) {
i0_result_x := io.decode_exu.exu_i0_result_x i0_result_x := io.decode_exu.exu_i0_result_x
i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
} }
@ -747,7 +747,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U))
// stores will bypass load data in the lsu pipe // stores will bypass load data in the lsu pipe
if (LOAD_TO_USE_PLUS1 == 1) { if (LOAD_TO_USE_PLUS1) {
i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store)
load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load
store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load)

BIN
target/scala-2.12/classes/dec/dec_decode_ctl.class
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