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Update beh_ib_func.scala

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Junaid Ahmed 2020-09-23 13:56:14 +05:00 committed by GitHub
parent 0ef2742e74
commit 854445ca27
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1 changed files with 28 additions and 39 deletions
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61
src/main/scala/lib/beh_ib_func.scala
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@ -7,8 +7,7 @@ import chisel3.util.HasBlackBoxResource
import chisel3.withClock import chisel3.withClock
object beh_ib_func extends RequireAsyncReset { object beh_ib_func extends RequireAsyncReset {
// use this for rvdffsc = > io.out := RegEnable(io.din & repl(io.din.getWidth, io.clear), 0.U, io.en)
// use this for rvdffs = > io.out := RegEnable(io.din, 0.U, io.en)
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
def rvsyncss(din:UInt) = RegNext(RegNext(din,0.U),0.U) def rvsyncss(din:UInt) = RegNext(RegNext(din,0.U),0.U)
@ -37,18 +36,18 @@ object beh_ib_func extends RequireAsyncReset {
//WIDTH will be inferred //WIDTH will be inferred
def rvmaskandmatch(mask:UInt,data:UInt,masken:UInt) = { //Done for verification and testing def rvmaskandmatch(mask:UInt,data:UInt,masken:UInt) = { //Done for verification and testing
val matchvec = Wire(Vec(data.getWidth,UInt(1.W))) val matchvec = Wire(Vec(data.getWidth,UInt(1.W)))
val masken_or_fullmask = masken.asBool & ~mask(data.getWidth-1,0).andR val masken_or_fullmask = masken.asBool & (~(mask(data.getWidth-1,0).andR))
matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt
for(i <- 1 to data.getWidth-1) for(i <- 1 to data.getWidth-1)
{matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)} {matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)}
matchvec.asUInt matchvec.asUInt.andR
} }
def rvrangecheck(addr:UInt,CCM_SADR:Int=0, CCM_SIZE:Int=128) = { def rvrangecheck(addr:UInt,CCM_SADR:Int=0, CCM_SIZE:Int=128) = {
val REGION_BITS = 4 val REGION_BITS = 4
val MASK_BITS = 10 + log2Ceil(CCM_SIZE) val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = Wire(CCM_SIZE.U(32.W)) val start_addr = Wire(CCM_SADR.U(32.W))
val region = start_addr(31,(32-REGION_BITS)) val region = start_addr(31,(32-REGION_BITS))
val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
val in_range = Wire(UInt(1.W)) val in_range = Wire(UInt(1.W))
@ -61,12 +60,12 @@ object beh_ib_func extends RequireAsyncReset {
def rvecc_encode(din:UInt):UInt = { def rvecc_encode(din:UInt):UInt = {
val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1) val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1) val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0) val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0) val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0) val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
val w0 = Wire(Vec(18,UInt(1.W))) val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W))) val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W))) val w2 = Wire(Vec(18,UInt(1.W)))
@ -84,7 +83,7 @@ object beh_ib_func extends RequireAsyncReset {
if(mask4(i)==1) {w4(y) := din(i); y = y +1 } if(mask4(i)==1) {w4(y) := din(i); y = y +1 }
if(mask5(i)==1) {w5(z) := din(i); z = z +1 } if(mask5(i)==1) {w5(z) := din(i); z = z +1 }
} }
val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR)) val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
val ecc_out = Cat(din.xorR ^ w6.xorR, w6) val ecc_out = Cat(din.xorR ^ w6.xorR, w6)
ecc_out ecc_out
} }
@ -94,12 +93,12 @@ object beh_ib_func extends RequireAsyncReset {
def rveven_paritycheck(data_in:UInt,parity_in:UInt) = (data_in.xorR.asUInt) ^ parity_in def rveven_paritycheck(data_in:UInt,parity_in:UInt) = (data_in.xorR.asUInt) ^ parity_in
def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= { def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0).reverse
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1).reverse
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1).reverse
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0).reverse
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0).reverse
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1).reverse
val w0 = Wire(Vec(18,UInt(1.W))) val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W))) val w1 = Wire(Vec(18,UInt(1.W)))
@ -122,8 +121,8 @@ object beh_ib_func extends RequireAsyncReset {
} }
val ecc_check = Cat((din.xorR ^ ecc_in.xorR) & ~sed_ded ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR)) val ecc_check = Cat((din.xorR ^ ecc_in.xorR) & ~sed_ded ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR))
val single_ecc_error = en & (ecc_check!= 0.U) & ((din.xorR ^ ecc_in.xorR) & ~sed_ded) val single_ecc_error = en & (ecc_check=/= 0.U) & ((din.xorR ^ ecc_in.xorR) & ~sed_ded)
val double_ecc_error = en & (ecc_check!= 0.U) & ((din.xorR ^ ecc_in.xorR) & ~sed_ded) val double_ecc_error = en & (ecc_check=/= 0.U) & ~((din.xorR ^ ecc_in.xorR) & ~sed_ded)
val error_mask = Wire(Vec(39,UInt(1.W))) val error_mask = Wire(Vec(39,UInt(1.W)))
for(i <- 1 until 40){ for(i <- 1 until 40){
@ -133,7 +132,7 @@ object beh_ib_func extends RequireAsyncReset {
val dout_plus_parity = Mux(single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity) val dout_plus_parity = Mux(single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
val dout = Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2)) val dout = Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
val ecc_out = Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) val ecc_out = Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === 1.U(7.W)), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
(ecc_out,dout,dout,single_ecc_error,double_ecc_error) (ecc_out,dout,dout,single_ecc_error,double_ecc_error)
} }
@ -147,6 +146,7 @@ object beh_ib_func extends RequireAsyncReset {
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W))) val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W))) val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W))) val w2 = Wire(Vec(35,UInt(1.W)))
@ -158,7 +158,7 @@ object beh_ib_func extends RequireAsyncReset {
var j = 0;var k = 0;var m = 0; var n =0; var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0 var x = 0;var y = 0;var z = 0
for(i <- 0 to 63) for(i <- 63 to 0)
{ {
if(mask0(i)==1) {w0(j) := din(i); j = j +1 } if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 } if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
@ -204,22 +204,11 @@ object beh_ib_func extends RequireAsyncReset {
if(mask6(i)==1) {w6(z) := din(i); z = z +1 } if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
} }
val ecc_check = Cat((ecc_in(6) ^ w5.asUInt.xorR) ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR)) val ecc_check = Cat((ecc_in(6) ^ w6.asUInt.xorR) ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR))
val ecc_error = en & (ecc_check(6,0) != 0.U) val ecc_error = en & (ecc_check(6,0) =/= 0.U)
ecc_error ecc_error
} }
////rvdffe ///////////////////////////////////////////////////////////////////////
def rvdffe(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
val obj = Module(new rvclkhdr())
val l1clk = obj.io.l1clk
obj.io.clk := clk
obj.io.en := en
obj.io.scan_mode := scan_mode
withClock(l1clk) {
RegNext(din,0.U)
}
} }
}