Master updated with one object

src/main/scala/lib/ahb_to_axi4.scala

@@ -180,6 +180,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
   bus_clk                 := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
 }
 
-object ahb_to_axi4 extends App {
+//object ahb_to_axi4 extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(3)))
+ // println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(3)))
-}
+//}

src/main/scala/lib/axi4_to_ahb.scala

@@ -335,6 +335,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe
   ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
 }
 
-object axi4_to_ahb extends App {
+//object axi4_to_ahb extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3)))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3)))
-}
+//}