fir_error updated
This commit is contained in:
Laraib Khan
parent
bfeaa72eda
commit
8c477719a6
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@ -125,6 +125,14 @@
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
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"sources":[
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
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609
lsu_lsc_ctl.fir
609
lsu_lsc_ctl.fir
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@ -3,7 +3,7 @@ circuit lsu_lsc_ctl :
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module lsu_addrcheck :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
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output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
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node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27]
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node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49]
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@ -350,15 +350,15 @@ circuit lsu_lsc_ctl :
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module lsu_lsc_ctl :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
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output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
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wire end_addr_pre_m : UInt<29>
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end_addr_pre_m <= UInt<29>("h00")
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wire end_addr_pre_r : UInt<29>
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end_addr_pre_r <= UInt<29>("h00")
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wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
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wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29]
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wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29]
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wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
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wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29]
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wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29]
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wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 98:29]
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node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
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node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
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@ -451,6 +451,7 @@ circuit lsu_lsc_ctl :
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addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
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addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
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addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
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addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 124:42]
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addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
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addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
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addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
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@ -569,221 +570,231 @@ circuit lsu_lsc_ctl :
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reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67]
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_T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67]
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io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30]
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reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:48]
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_T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:48]
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reg _T_112 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:75]
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_T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:75]
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io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 188:38]
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dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27]
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dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27]
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dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22]
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dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27]
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dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27]
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node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30]
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dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 195:27]
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node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56]
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node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62]
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dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 196:27]
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node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
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node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62]
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dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 197:27]
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node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
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node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62]
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dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 198:27]
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node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
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node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62]
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dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 199:27]
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dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39]
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dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
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dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
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dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:26]
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dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 192:27]
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dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 193:22]
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dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 194:27]
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dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 195:27]
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node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 196:30]
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dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 196:27]
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node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
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node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 197:62]
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dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 197:27]
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node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
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node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 198:62]
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dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 198:27]
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node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
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node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 199:62]
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dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 199:27]
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node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 200:56]
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node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 200:62]
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dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 200:27]
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dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
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||||
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
|
||||
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 203:39]
|
||||
wire lsu_ld_datafn_r : UInt<32>
|
||||
lsu_ld_datafn_r <= UInt<32>("h00")
|
||||
wire lsu_ld_datafn_corr_r : UInt<32>
|
||||
lsu_ld_datafn_corr_r <= UInt<32>("h00")
|
||||
wire lsu_ld_datafn_m : UInt<32>
|
||||
lsu_ld_datafn_m <= UInt<32>("h00")
|
||||
node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50]
|
||||
node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26]
|
||||
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 208:20]
|
||||
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20]
|
||||
node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64]
|
||||
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 212:61]
|
||||
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45]
|
||||
node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 212:43]
|
||||
node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90]
|
||||
io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 212:24]
|
||||
node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68]
|
||||
node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 213:65]
|
||||
node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49]
|
||||
node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 213:47]
|
||||
lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 213:24]
|
||||
node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
|
||||
node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 214:65]
|
||||
node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
|
||||
node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 214:47]
|
||||
lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 214:24]
|
||||
wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65]
|
||||
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 216:28]
|
||||
wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65]
|
||||
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 217:28]
|
||||
reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65]
|
||||
io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 218:28]
|
||||
reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
|
||||
_T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65]
|
||||
io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 219:28]
|
||||
node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59]
|
||||
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100]
|
||||
node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 209:50]
|
||||
node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 209:26]
|
||||
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.stack <= _T_123.bits.stack @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
|
||||
io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 211:20]
|
||||
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 211:20]
|
||||
node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:64]
|
||||
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 213:61]
|
||||
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:45]
|
||||
node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 213:43]
|
||||
node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 213:90]
|
||||
io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 213:24]
|
||||
node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
|
||||
node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 214:65]
|
||||
node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
|
||||
node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 214:47]
|
||||
lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 214:24]
|
||||
node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:68]
|
||||
node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 215:65]
|
||||
node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:49]
|
||||
node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 215:47]
|
||||
lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 215:24]
|
||||
wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 217:65]
|
||||
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.stack <= _T_138.bits.stack @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 217:28]
|
||||
wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
_T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
|
||||
reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 218:65]
|
||||
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.stack <= _T_140.bits.stack @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 218:28]
|
||||
io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 218:28]
|
||||
reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
|
||||
_T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 219:65]
|
||||
io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 219:28]
|
||||
reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:65]
|
||||
_T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 220:65]
|
||||
io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 220:28]
|
||||
node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 222:59]
|
||||
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 222:100]
|
||||
node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58]
|
||||
node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 221:66]
|
||||
node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63]
|
||||
node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91]
|
||||
node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122]
|
||||
node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 222:34]
|
||||
node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73]
|
||||
node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:95]
|
||||
node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:114]
|
||||
node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 223:34]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72]
|
||||
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62]
|
||||
_T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62]
|
||||
io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 226:24]
|
||||
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
|
||||
_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
|
||||
io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 227:24]
|
||||
node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 222:66]
|
||||
node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 223:63]
|
||||
node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 223:91]
|
||||
node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
|
||||
node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 223:34]
|
||||
node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 224:73]
|
||||
node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 224:95]
|
||||
node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 224:114]
|
||||
node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 224:34]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
|
||||
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
|
||||
_T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
|
||||
io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 227:24]
|
||||
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
|
||||
_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
|
||||
io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 228:24]
|
||||
node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
|
||||
node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 228:71]
|
||||
node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 228:27]
|
||||
node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 228:128]
|
||||
reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:114]
|
||||
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 228:114]
|
||||
node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
|
||||
node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 229:27]
|
||||
node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
|
||||
reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
|
||||
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 229:114]
|
||||
node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
|
||||
io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 228:17]
|
||||
io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 229:17]
|
||||
node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
|
||||
node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 229:71]
|
||||
node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 229:27]
|
||||
node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 229:128]
|
||||
reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
|
||||
_T_164 <= _T_163 @[lsu_lsc_ctl.scala 229:114]
|
||||
node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
|
||||
node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27]
|
||||
node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
|
||||
reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
|
||||
_T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114]
|
||||
node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
|
||||
io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 229:17]
|
||||
node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 230:41]
|
||||
node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 230:69]
|
||||
node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 230:87]
|
||||
io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17]
|
||||
node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
|
||||
node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
|
||||
node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
|
||||
node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
|
||||
node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23]
|
||||
|
|
@ -794,10 +805,10 @@ circuit lsu_lsc_ctl :
|
|||
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
|
||||
reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
|
||||
_T_171 <= _T_166 @[lib.scala 383:16]
|
||||
end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 230:18]
|
||||
node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 231:41]
|
||||
node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 231:69]
|
||||
node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
|
||||
end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 231:18]
|
||||
node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
|
||||
node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 232:69]
|
||||
node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
|
||||
node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
|
||||
node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23]
|
||||
|
|
@ -808,25 +819,25 @@ circuit lsu_lsc_ctl :
|
|||
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
|
||||
reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
|
||||
_T_177 <= _T_172 @[lib.scala 383:16]
|
||||
end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 231:18]
|
||||
reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
|
||||
_T_178 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 232:62]
|
||||
io.addr_in_dccm_m <= _T_178 @[lsu_lsc_ctl.scala 232:24]
|
||||
reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
|
||||
_T_179 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_in_dccm_r <= _T_179 @[lsu_lsc_ctl.scala 233:24]
|
||||
reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
|
||||
_T_180 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 234:62]
|
||||
io.addr_in_pic_m <= _T_180 @[lsu_lsc_ctl.scala 234:24]
|
||||
reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
|
||||
_T_181 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 235:62]
|
||||
io.addr_in_pic_r <= _T_181 @[lsu_lsc_ctl.scala 235:24]
|
||||
reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_182 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_external_m <= _T_182 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66]
|
||||
node _T_183 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77]
|
||||
end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 232:18]
|
||||
reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
|
||||
_T_178 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_in_dccm_m <= _T_178 @[lsu_lsc_ctl.scala 233:24]
|
||||
reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
|
||||
_T_179 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
|
||||
io.addr_in_dccm_r <= _T_179 @[lsu_lsc_ctl.scala 234:24]
|
||||
reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
|
||||
_T_180 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
|
||||
io.addr_in_pic_m <= _T_180 @[lsu_lsc_ctl.scala 235:24]
|
||||
reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_181 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_in_pic_r <= _T_181 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
|
||||
_T_182 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
|
||||
io.addr_external_m <= _T_182 @[lsu_lsc_ctl.scala 237:24]
|
||||
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
|
||||
node _T_183 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
|
||||
node _T_184 = bits(_T_183, 0, 0) @[lib.scala 8:44]
|
||||
node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23]
|
||||
|
|
@ -837,111 +848,111 @@ circuit lsu_lsc_ctl :
|
|||
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
|
||||
reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
|
||||
bus_read_data_r <= io.bus_read_data_m @[lib.scala 383:16]
|
||||
node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 241:52]
|
||||
io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 241:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 243:28]
|
||||
node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 245:68]
|
||||
node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 245:41]
|
||||
node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:96]
|
||||
node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 245:94]
|
||||
node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:110]
|
||||
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 245:108]
|
||||
io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 245:19]
|
||||
node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 246:52]
|
||||
node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:69]
|
||||
node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
|
||||
io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 242:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
|
||||
node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
|
||||
node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 246:41]
|
||||
node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
|
||||
node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 246:94]
|
||||
node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
|
||||
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 246:108]
|
||||
io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 246:19]
|
||||
node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
|
||||
node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
|
||||
node _T_195 = bits(_T_194, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_196 = mux(_T_195, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 246:59]
|
||||
node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 246:133]
|
||||
node _T_199 = mux(_T_198, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 246:94]
|
||||
node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 246:89]
|
||||
io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 246:29]
|
||||
node _T_201 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 267:53]
|
||||
node _T_202 = mux(_T_201, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 267:33]
|
||||
lsu_ld_datafn_m <= _T_202 @[lsu_lsc_ctl.scala 267:27]
|
||||
node _T_203 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 268:49]
|
||||
node _T_204 = mux(_T_203, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 268:33]
|
||||
lsu_ld_datafn_corr_r <= _T_204 @[lsu_lsc_ctl.scala 268:27]
|
||||
node _T_205 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 269:66]
|
||||
node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 247:59]
|
||||
node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
|
||||
node _T_199 = mux(_T_198, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
|
||||
node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 247:89]
|
||||
io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 247:29]
|
||||
node _T_201 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 268:53]
|
||||
node _T_202 = mux(_T_201, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33]
|
||||
lsu_ld_datafn_m <= _T_202 @[lsu_lsc_ctl.scala 268:27]
|
||||
node _T_203 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49]
|
||||
node _T_204 = mux(_T_203, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33]
|
||||
lsu_ld_datafn_corr_r <= _T_204 @[lsu_lsc_ctl.scala 269:27]
|
||||
node _T_205 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:66]
|
||||
node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_208 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 269:125]
|
||||
node _T_208 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:125]
|
||||
node _T_209 = cat(UInt<24>("h00"), _T_208) @[Cat.scala 29:58]
|
||||
node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 269:94]
|
||||
node _T_211 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 270:43]
|
||||
node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 270:94]
|
||||
node _T_211 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43]
|
||||
node _T_212 = bits(_T_211, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_213 = mux(_T_212, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_214 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 270:102]
|
||||
node _T_214 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102]
|
||||
node _T_215 = cat(UInt<16>("h00"), _T_214) @[Cat.scala 29:58]
|
||||
node _T_216 = and(_T_213, _T_215) @[lsu_lsc_ctl.scala 270:71]
|
||||
node _T_217 = or(_T_210, _T_216) @[lsu_lsc_ctl.scala 269:133]
|
||||
node _T_218 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 271:17]
|
||||
node _T_219 = and(_T_218, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 271:43]
|
||||
node _T_216 = and(_T_213, _T_215) @[lsu_lsc_ctl.scala 271:71]
|
||||
node _T_217 = or(_T_210, _T_216) @[lsu_lsc_ctl.scala 270:133]
|
||||
node _T_218 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||
node _T_219 = and(_T_218, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43]
|
||||
node _T_220 = bits(_T_219, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_222 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 271:102]
|
||||
node _T_222 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102]
|
||||
node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_224 = mux(_T_223, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_225 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 271:125]
|
||||
node _T_225 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||
node _T_226 = cat(_T_224, _T_225) @[Cat.scala 29:58]
|
||||
node _T_227 = and(_T_221, _T_226) @[lsu_lsc_ctl.scala 271:71]
|
||||
node _T_228 = or(_T_217, _T_227) @[lsu_lsc_ctl.scala 270:114]
|
||||
node _T_229 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||
node _T_230 = and(_T_229, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 272:43]
|
||||
node _T_227 = and(_T_221, _T_226) @[lsu_lsc_ctl.scala 272:71]
|
||||
node _T_228 = or(_T_217, _T_227) @[lsu_lsc_ctl.scala 271:114]
|
||||
node _T_229 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17]
|
||||
node _T_230 = and(_T_229, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43]
|
||||
node _T_231 = bits(_T_230, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_232 = mux(_T_231, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_233 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 272:101]
|
||||
node _T_233 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101]
|
||||
node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_235 = mux(_T_234, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_236 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||
node _T_236 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125]
|
||||
node _T_237 = cat(_T_235, _T_236) @[Cat.scala 29:58]
|
||||
node _T_238 = and(_T_232, _T_237) @[lsu_lsc_ctl.scala 272:71]
|
||||
node _T_239 = or(_T_228, _T_238) @[lsu_lsc_ctl.scala 271:134]
|
||||
node _T_238 = and(_T_232, _T_237) @[lsu_lsc_ctl.scala 273:71]
|
||||
node _T_239 = or(_T_228, _T_238) @[lsu_lsc_ctl.scala 272:134]
|
||||
node _T_240 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_242 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 273:60]
|
||||
node _T_243 = and(_T_241, _T_242) @[lsu_lsc_ctl.scala 273:43]
|
||||
node _T_244 = or(_T_239, _T_243) @[lsu_lsc_ctl.scala 272:134]
|
||||
io.lsu_result_m <= _T_244 @[lsu_lsc_ctl.scala 269:27]
|
||||
node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 274:66]
|
||||
node _T_242 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60]
|
||||
node _T_243 = and(_T_241, _T_242) @[lsu_lsc_ctl.scala 274:43]
|
||||
node _T_244 = or(_T_239, _T_243) @[lsu_lsc_ctl.scala 273:134]
|
||||
io.lsu_result_m <= _T_244 @[lsu_lsc_ctl.scala 270:27]
|
||||
node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66]
|
||||
node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_248 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 274:130]
|
||||
node _T_248 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130]
|
||||
node _T_249 = cat(UInt<24>("h00"), _T_248) @[Cat.scala 29:58]
|
||||
node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 274:94]
|
||||
node _T_251 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 275:43]
|
||||
node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 275:94]
|
||||
node _T_251 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_252 = bits(_T_251, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_253 = mux(_T_252, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_254 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 275:107]
|
||||
node _T_254 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107]
|
||||
node _T_255 = cat(UInt<16>("h00"), _T_254) @[Cat.scala 29:58]
|
||||
node _T_256 = and(_T_253, _T_255) @[lsu_lsc_ctl.scala 275:71]
|
||||
node _T_257 = or(_T_250, _T_256) @[lsu_lsc_ctl.scala 274:138]
|
||||
node _T_258 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17]
|
||||
node _T_259 = and(_T_258, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_256 = and(_T_253, _T_255) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_257 = or(_T_250, _T_256) @[lsu_lsc_ctl.scala 275:138]
|
||||
node _T_258 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||
node _T_259 = and(_T_258, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_261 = mux(_T_260, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_262 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 276:107]
|
||||
node _T_262 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107]
|
||||
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_264 = mux(_T_263, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 276:135]
|
||||
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||
node _T_266 = cat(_T_264, _T_265) @[Cat.scala 29:58]
|
||||
node _T_267 = and(_T_261, _T_266) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_268 = or(_T_257, _T_267) @[lsu_lsc_ctl.scala 275:119]
|
||||
node _T_269 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||
node _T_270 = and(_T_269, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_267 = and(_T_261, _T_266) @[lsu_lsc_ctl.scala 277:71]
|
||||
node _T_268 = or(_T_257, _T_267) @[lsu_lsc_ctl.scala 276:119]
|
||||
node _T_269 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17]
|
||||
node _T_270 = and(_T_269, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43]
|
||||
node _T_271 = bits(_T_270, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_273 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 277:106]
|
||||
node _T_273 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106]
|
||||
node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_275 = mux(_T_274, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135]
|
||||
node _T_277 = cat(_T_275, _T_276) @[Cat.scala 29:58]
|
||||
node _T_278 = and(_T_272, _T_277) @[lsu_lsc_ctl.scala 277:71]
|
||||
node _T_279 = or(_T_268, _T_278) @[lsu_lsc_ctl.scala 276:144]
|
||||
node _T_278 = and(_T_272, _T_277) @[lsu_lsc_ctl.scala 278:71]
|
||||
node _T_279 = or(_T_268, _T_278) @[lsu_lsc_ctl.scala 277:144]
|
||||
node _T_280 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_281 = mux(_T_280, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_282 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 278:65]
|
||||
node _T_283 = and(_T_281, _T_282) @[lsu_lsc_ctl.scala 278:43]
|
||||
node _T_284 = or(_T_279, _T_283) @[lsu_lsc_ctl.scala 277:144]
|
||||
io.lsu_result_corr_r <= _T_284 @[lsu_lsc_ctl.scala 274:27]
|
||||
node _T_282 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65]
|
||||
node _T_283 = and(_T_281, _T_282) @[lsu_lsc_ctl.scala 279:43]
|
||||
node _T_284 = or(_T_279, _T_283) @[lsu_lsc_ctl.scala 278:144]
|
||||
io.lsu_result_corr_r <= _T_284 @[lsu_lsc_ctl.scala 275:27]
|
||||
|
||||
|
|
|
|||
409
lsu_lsc_ctl.v
409
lsu_lsc_ctl.v
|
|
@ -228,6 +228,7 @@ module lsu_lsc_ctl(
|
|||
input [31:0] io_lsu_exu_exu_lsu_rs2_d,
|
||||
input io_lsu_p_valid,
|
||||
input io_lsu_p_bits_fast_int,
|
||||
input io_lsu_p_bits_stack,
|
||||
input io_lsu_p_bits_by,
|
||||
input io_lsu_p_bits_half,
|
||||
input io_lsu_p_bits_word,
|
||||
|
|
@ -279,6 +280,7 @@ module lsu_lsc_ctl(
|
|||
input [63:0] io_dma_lsc_ctl_dma_mem_wdata,
|
||||
output io_lsu_pkt_d_valid,
|
||||
output io_lsu_pkt_d_bits_fast_int,
|
||||
output io_lsu_pkt_d_bits_stack,
|
||||
output io_lsu_pkt_d_bits_by,
|
||||
output io_lsu_pkt_d_bits_half,
|
||||
output io_lsu_pkt_d_bits_word,
|
||||
|
|
@ -292,6 +294,7 @@ module lsu_lsc_ctl(
|
|||
output io_lsu_pkt_d_bits_store_data_bypass_m,
|
||||
output io_lsu_pkt_m_valid,
|
||||
output io_lsu_pkt_m_bits_fast_int,
|
||||
output io_lsu_pkt_m_bits_stack,
|
||||
output io_lsu_pkt_m_bits_by,
|
||||
output io_lsu_pkt_m_bits_half,
|
||||
output io_lsu_pkt_m_bits_word,
|
||||
|
|
@ -305,6 +308,7 @@ module lsu_lsc_ctl(
|
|||
output io_lsu_pkt_m_bits_store_data_bypass_m,
|
||||
output io_lsu_pkt_r_valid,
|
||||
output io_lsu_pkt_r_bits_fast_int,
|
||||
output io_lsu_pkt_r_bits_stack,
|
||||
output io_lsu_pkt_r_bits_by,
|
||||
output io_lsu_pkt_r_bits_half,
|
||||
output io_lsu_pkt_r_bits_word,
|
||||
|
|
@ -371,6 +375,8 @@ module lsu_lsc_ctl(
|
|||
reg [31:0] _RAND_49;
|
||||
reg [31:0] _RAND_50;
|
||||
reg [31:0] _RAND_51;
|
||||
reg [31:0] _RAND_52;
|
||||
reg [31:0] _RAND_53;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire addrcheck_reset; // @[lsu_lsc_ctl.scala 118:25]
|
||||
wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 118:25]
|
||||
|
|
@ -476,126 +482,128 @@ module lsu_lsc_ctl(
|
|||
reg [31:0] _T_109_bits_addr; // @[lib.scala 393:16]
|
||||
reg _T_110; // @[lsu_lsc_ctl.scala 186:83]
|
||||
reg _T_111; // @[lsu_lsc_ctl.scala 187:67]
|
||||
reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 188:48]
|
||||
wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30]
|
||||
wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62]
|
||||
wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62]
|
||||
wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62]
|
||||
wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62]
|
||||
wire _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64]
|
||||
wire _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 212:61]
|
||||
wire _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 212:45]
|
||||
wire _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 212:43]
|
||||
wire _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68]
|
||||
wire _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 213:65]
|
||||
wire _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 213:49]
|
||||
wire _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 214:65]
|
||||
wire _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 214:49]
|
||||
reg _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65]
|
||||
reg _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_141; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_142; // @[lsu_lsc_ctl.scala 219:65]
|
||||
reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 188:75]
|
||||
wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 196:30]
|
||||
wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 197:62]
|
||||
wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 198:62]
|
||||
wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 199:62]
|
||||
wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 200:62]
|
||||
wire _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 213:64]
|
||||
wire _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 213:61]
|
||||
wire _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 213:45]
|
||||
wire _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 213:43]
|
||||
wire _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 214:68]
|
||||
wire _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 214:65]
|
||||
wire _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 214:49]
|
||||
wire _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 215:65]
|
||||
wire _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 215:49]
|
||||
reg _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_stack; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_by; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_half; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_word; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_dword; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_load; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_store; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_dma; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_stack; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_by; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_half; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_word; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_dword; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_load; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_store; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_dma; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_141; // @[lsu_lsc_ctl.scala 219:65]
|
||||
reg _T_142; // @[lsu_lsc_ctl.scala 220:65]
|
||||
wire [5:0] _T_145 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 221:66]
|
||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72]
|
||||
reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 226:62]
|
||||
reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 227:62]
|
||||
wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 222:66]
|
||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72]
|
||||
reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 227:62]
|
||||
reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 228:62]
|
||||
reg [28:0] end_addr_pre_m; // @[lib.scala 383:16]
|
||||
wire [28:0] _T_156 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 228:27]
|
||||
reg [2:0] _T_158; // @[lsu_lsc_ctl.scala 228:114]
|
||||
wire [28:0] _T_156 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
||||
reg [2:0] _T_158; // @[lsu_lsc_ctl.scala 229:114]
|
||||
reg [28:0] end_addr_pre_r; // @[lib.scala 383:16]
|
||||
wire [28:0] _T_162 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
||||
reg [2:0] _T_164; // @[lsu_lsc_ctl.scala 229:114]
|
||||
wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 230:69]
|
||||
wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 231:69]
|
||||
reg _T_178; // @[lsu_lsc_ctl.scala 232:62]
|
||||
reg _T_179; // @[lsu_lsc_ctl.scala 233:62]
|
||||
reg _T_180; // @[lsu_lsc_ctl.scala 234:62]
|
||||
reg _T_181; // @[lsu_lsc_ctl.scala 235:62]
|
||||
reg _T_182; // @[lsu_lsc_ctl.scala 236:62]
|
||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 237:66]
|
||||
wire [28:0] _T_162 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27]
|
||||
reg [2:0] _T_164; // @[lsu_lsc_ctl.scala 230:114]
|
||||
wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69]
|
||||
wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 232:69]
|
||||
reg _T_178; // @[lsu_lsc_ctl.scala 233:62]
|
||||
reg _T_179; // @[lsu_lsc_ctl.scala 234:62]
|
||||
reg _T_180; // @[lsu_lsc_ctl.scala 235:62]
|
||||
reg _T_181; // @[lsu_lsc_ctl.scala 236:62]
|
||||
reg _T_182; // @[lsu_lsc_ctl.scala 237:62]
|
||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 238:66]
|
||||
reg [31:0] bus_read_data_r; // @[lib.scala 383:16]
|
||||
wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 245:68]
|
||||
wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 245:41]
|
||||
wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 245:96]
|
||||
wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 245:94]
|
||||
wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 245:110]
|
||||
wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 246:69]
|
||||
wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68]
|
||||
wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 246:41]
|
||||
wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96]
|
||||
wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 246:94]
|
||||
wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 246:110]
|
||||
wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69]
|
||||
wire [31:0] _T_196 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 246:59]
|
||||
wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 246:94]
|
||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 267:33]
|
||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 268:33]
|
||||
wire _T_205 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 269:66]
|
||||
wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 247:59]
|
||||
wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94]
|
||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 268:33]
|
||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 269:33]
|
||||
wire _T_205 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 270:66]
|
||||
wire [31:0] _T_207 = _T_205 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_209 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 269:94]
|
||||
wire _T_211 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 270:43]
|
||||
wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 270:94]
|
||||
wire _T_211 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 271:43]
|
||||
wire [31:0] _T_213 = _T_211 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_215 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_216 = _T_213 & _T_215; // @[lsu_lsc_ctl.scala 270:71]
|
||||
wire [31:0] _T_217 = _T_210 | _T_216; // @[lsu_lsc_ctl.scala 269:133]
|
||||
wire _T_218 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 271:17]
|
||||
wire _T_219 = _T_218 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 271:43]
|
||||
wire [31:0] _T_216 = _T_213 & _T_215; // @[lsu_lsc_ctl.scala 271:71]
|
||||
wire [31:0] _T_217 = _T_210 | _T_216; // @[lsu_lsc_ctl.scala 270:133]
|
||||
wire _T_218 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 272:17]
|
||||
wire _T_219 = _T_218 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 272:43]
|
||||
wire [31:0] _T_221 = _T_219 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_224 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_226 = {_T_224,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_227 = _T_221 & _T_226; // @[lsu_lsc_ctl.scala 271:71]
|
||||
wire [31:0] _T_228 = _T_217 | _T_227; // @[lsu_lsc_ctl.scala 270:114]
|
||||
wire _T_230 = _T_218 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 272:43]
|
||||
wire [31:0] _T_227 = _T_221 & _T_226; // @[lsu_lsc_ctl.scala 272:71]
|
||||
wire [31:0] _T_228 = _T_217 | _T_227; // @[lsu_lsc_ctl.scala 271:114]
|
||||
wire _T_230 = _T_218 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 273:43]
|
||||
wire [31:0] _T_232 = _T_230 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_235 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_237 = {_T_235,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_238 = _T_232 & _T_237; // @[lsu_lsc_ctl.scala 272:71]
|
||||
wire [31:0] _T_239 = _T_228 | _T_238; // @[lsu_lsc_ctl.scala 271:134]
|
||||
wire [31:0] _T_238 = _T_232 & _T_237; // @[lsu_lsc_ctl.scala 273:71]
|
||||
wire [31:0] _T_239 = _T_228 | _T_238; // @[lsu_lsc_ctl.scala 272:134]
|
||||
wire [31:0] _T_241 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_243 = _T_241 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 273:43]
|
||||
wire _T_245 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 274:66]
|
||||
wire [31:0] _T_243 = _T_241 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 274:43]
|
||||
wire _T_245 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 275:66]
|
||||
wire [31:0] _T_247 = _T_245 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_249 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_250 = _T_247 & _T_249; // @[lsu_lsc_ctl.scala 274:94]
|
||||
wire _T_251 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 275:43]
|
||||
wire [31:0] _T_250 = _T_247 & _T_249; // @[lsu_lsc_ctl.scala 275:94]
|
||||
wire _T_251 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 276:43]
|
||||
wire [31:0] _T_253 = _T_251 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_255 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_256 = _T_253 & _T_255; // @[lsu_lsc_ctl.scala 275:71]
|
||||
wire [31:0] _T_257 = _T_250 | _T_256; // @[lsu_lsc_ctl.scala 274:138]
|
||||
wire _T_258 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 276:17]
|
||||
wire _T_259 = _T_258 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 276:43]
|
||||
wire [31:0] _T_256 = _T_253 & _T_255; // @[lsu_lsc_ctl.scala 276:71]
|
||||
wire [31:0] _T_257 = _T_250 | _T_256; // @[lsu_lsc_ctl.scala 275:138]
|
||||
wire _T_258 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 277:17]
|
||||
wire _T_259 = _T_258 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 277:43]
|
||||
wire [31:0] _T_261 = _T_259 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [23:0] _T_264 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_266 = {_T_264,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_267 = _T_261 & _T_266; // @[lsu_lsc_ctl.scala 276:71]
|
||||
wire [31:0] _T_268 = _T_257 | _T_267; // @[lsu_lsc_ctl.scala 275:119]
|
||||
wire _T_270 = _T_258 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 277:43]
|
||||
wire [31:0] _T_267 = _T_261 & _T_266; // @[lsu_lsc_ctl.scala 277:71]
|
||||
wire [31:0] _T_268 = _T_257 | _T_267; // @[lsu_lsc_ctl.scala 276:119]
|
||||
wire _T_270 = _T_258 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 278:43]
|
||||
wire [31:0] _T_272 = _T_270 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [15:0] _T_275 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_277 = {_T_275,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_278 = _T_272 & _T_277; // @[lsu_lsc_ctl.scala 277:71]
|
||||
wire [31:0] _T_279 = _T_268 | _T_278; // @[lsu_lsc_ctl.scala 276:144]
|
||||
wire [31:0] _T_278 = _T_272 & _T_277; // @[lsu_lsc_ctl.scala 278:71]
|
||||
wire [31:0] _T_279 = _T_268 | _T_278; // @[lsu_lsc_ctl.scala 277:144]
|
||||
wire [31:0] _T_281 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_283 = _T_281 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 278:43]
|
||||
wire [31:0] _T_283 = _T_281 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 279:43]
|
||||
lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25]
|
||||
.reset(addrcheck_reset),
|
||||
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
||||
|
|
@ -641,18 +649,18 @@ module lsu_lsc_ctl(
|
|||
.io_clk(rvclkhdr_3_io_clk),
|
||||
.io_en(rvclkhdr_3_io_en)
|
||||
);
|
||||
assign io_lsu_result_m = _T_239 | _T_243; // @[lsu_lsc_ctl.scala 269:27]
|
||||
assign io_lsu_result_corr_r = _T_279 | _T_283; // @[lsu_lsc_ctl.scala 274:27]
|
||||
assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 243:28]
|
||||
assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 226:24]
|
||||
assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 227:24]
|
||||
assign io_lsu_result_m = _T_239 | _T_243; // @[lsu_lsc_ctl.scala 270:27]
|
||||
assign io_lsu_result_corr_r = _T_279 | _T_283; // @[lsu_lsc_ctl.scala 275:27]
|
||||
assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 244:28]
|
||||
assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 227:24]
|
||||
assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 228:24]
|
||||
assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 115:24]
|
||||
assign io_end_addr_m = {_T_156,_T_158}; // @[lsu_lsc_ctl.scala 228:17]
|
||||
assign io_end_addr_r = {_T_162,_T_164}; // @[lsu_lsc_ctl.scala 229:17]
|
||||
assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 246:29]
|
||||
assign io_end_addr_m = {_T_156,_T_158}; // @[lsu_lsc_ctl.scala 229:17]
|
||||
assign io_end_addr_r = {_T_162,_T_164}; // @[lsu_lsc_ctl.scala 230:17]
|
||||
assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 247:29]
|
||||
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16]
|
||||
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42]
|
||||
assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 245:19]
|
||||
assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 246:19]
|
||||
assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32]
|
||||
assign io_lsu_error_pkt_r_valid = _T_111; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 187:30]
|
||||
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_110; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 186:46]
|
||||
|
|
@ -660,54 +668,57 @@ module lsu_lsc_ctl(
|
|||
assign io_lsu_error_pkt_r_bits_exc_type = _T_109_bits_exc_type; // @[lsu_lsc_ctl.scala 185:24]
|
||||
assign io_lsu_error_pkt_r_bits_mscause = _T_109_bits_mscause; // @[lsu_lsc_ctl.scala 185:24]
|
||||
assign io_lsu_error_pkt_r_bits_addr = _T_109_bits_addr; // @[lsu_lsc_ctl.scala 185:24]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 241:28]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28]
|
||||
assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 188:38]
|
||||
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42]
|
||||
assign io_addr_in_dccm_m = _T_178; // @[lsu_lsc_ctl.scala 232:24]
|
||||
assign io_addr_in_dccm_r = _T_179; // @[lsu_lsc_ctl.scala 233:24]
|
||||
assign io_addr_in_dccm_m = _T_178; // @[lsu_lsc_ctl.scala 233:24]
|
||||
assign io_addr_in_dccm_r = _T_179; // @[lsu_lsc_ctl.scala 234:24]
|
||||
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42]
|
||||
assign io_addr_in_pic_m = _T_180; // @[lsu_lsc_ctl.scala 234:24]
|
||||
assign io_addr_in_pic_r = _T_181; // @[lsu_lsc_ctl.scala 235:24]
|
||||
assign io_addr_external_m = _T_182; // @[lsu_lsc_ctl.scala 236:24]
|
||||
assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
|
||||
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20]
|
||||
assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28]
|
||||
assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28]
|
||||
assign io_lsu_pkt_r_bits_fast_int = _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_addr_in_pic_m = _T_180; // @[lsu_lsc_ctl.scala 235:24]
|
||||
assign io_addr_in_pic_r = _T_181; // @[lsu_lsc_ctl.scala 236:24]
|
||||
assign io_addr_external_m = _T_182; // @[lsu_lsc_ctl.scala 237:24]
|
||||
assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 209:20 lsu_lsc_ctl.scala 213:24]
|
||||
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 209:20]
|
||||
assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28]
|
||||
assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_stack = _T_138_bits_stack; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28]
|
||||
assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 218:28 lsu_lsc_ctl.scala 220:28]
|
||||
assign io_lsu_pkt_r_bits_fast_int = _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_stack = _T_140_bits_stack; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 218:28]
|
||||
assign addrcheck_reset = reset;
|
||||
assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 120:42]
|
||||
assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 122:42]
|
||||
|
|
@ -792,83 +803,87 @@ initial begin
|
|||
_RAND_12 = {1{`RANDOM}};
|
||||
_T_138_bits_fast_int = _RAND_12[0:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
_T_138_bits_by = _RAND_13[0:0];
|
||||
_T_138_bits_stack = _RAND_13[0:0];
|
||||
_RAND_14 = {1{`RANDOM}};
|
||||
_T_138_bits_half = _RAND_14[0:0];
|
||||
_T_138_bits_by = _RAND_14[0:0];
|
||||
_RAND_15 = {1{`RANDOM}};
|
||||
_T_138_bits_word = _RAND_15[0:0];
|
||||
_T_138_bits_half = _RAND_15[0:0];
|
||||
_RAND_16 = {1{`RANDOM}};
|
||||
_T_138_bits_dword = _RAND_16[0:0];
|
||||
_T_138_bits_word = _RAND_16[0:0];
|
||||
_RAND_17 = {1{`RANDOM}};
|
||||
_T_138_bits_load = _RAND_17[0:0];
|
||||
_T_138_bits_dword = _RAND_17[0:0];
|
||||
_RAND_18 = {1{`RANDOM}};
|
||||
_T_138_bits_store = _RAND_18[0:0];
|
||||
_T_138_bits_load = _RAND_18[0:0];
|
||||
_RAND_19 = {1{`RANDOM}};
|
||||
_T_138_bits_unsign = _RAND_19[0:0];
|
||||
_T_138_bits_store = _RAND_19[0:0];
|
||||
_RAND_20 = {1{`RANDOM}};
|
||||
_T_138_bits_dma = _RAND_20[0:0];
|
||||
_T_138_bits_unsign = _RAND_20[0:0];
|
||||
_RAND_21 = {1{`RANDOM}};
|
||||
_T_138_bits_store_data_bypass_d = _RAND_21[0:0];
|
||||
_T_138_bits_dma = _RAND_21[0:0];
|
||||
_RAND_22 = {1{`RANDOM}};
|
||||
_T_138_bits_load_ldst_bypass_d = _RAND_22[0:0];
|
||||
_T_138_bits_store_data_bypass_d = _RAND_22[0:0];
|
||||
_RAND_23 = {1{`RANDOM}};
|
||||
_T_138_bits_store_data_bypass_m = _RAND_23[0:0];
|
||||
_T_138_bits_load_ldst_bypass_d = _RAND_23[0:0];
|
||||
_RAND_24 = {1{`RANDOM}};
|
||||
_T_140_bits_fast_int = _RAND_24[0:0];
|
||||
_T_138_bits_store_data_bypass_m = _RAND_24[0:0];
|
||||
_RAND_25 = {1{`RANDOM}};
|
||||
_T_140_bits_by = _RAND_25[0:0];
|
||||
_T_140_bits_fast_int = _RAND_25[0:0];
|
||||
_RAND_26 = {1{`RANDOM}};
|
||||
_T_140_bits_half = _RAND_26[0:0];
|
||||
_T_140_bits_stack = _RAND_26[0:0];
|
||||
_RAND_27 = {1{`RANDOM}};
|
||||
_T_140_bits_word = _RAND_27[0:0];
|
||||
_T_140_bits_by = _RAND_27[0:0];
|
||||
_RAND_28 = {1{`RANDOM}};
|
||||
_T_140_bits_dword = _RAND_28[0:0];
|
||||
_T_140_bits_half = _RAND_28[0:0];
|
||||
_RAND_29 = {1{`RANDOM}};
|
||||
_T_140_bits_load = _RAND_29[0:0];
|
||||
_T_140_bits_word = _RAND_29[0:0];
|
||||
_RAND_30 = {1{`RANDOM}};
|
||||
_T_140_bits_store = _RAND_30[0:0];
|
||||
_T_140_bits_dword = _RAND_30[0:0];
|
||||
_RAND_31 = {1{`RANDOM}};
|
||||
_T_140_bits_unsign = _RAND_31[0:0];
|
||||
_T_140_bits_load = _RAND_31[0:0];
|
||||
_RAND_32 = {1{`RANDOM}};
|
||||
_T_140_bits_dma = _RAND_32[0:0];
|
||||
_T_140_bits_store = _RAND_32[0:0];
|
||||
_RAND_33 = {1{`RANDOM}};
|
||||
_T_140_bits_store_data_bypass_d = _RAND_33[0:0];
|
||||
_T_140_bits_unsign = _RAND_33[0:0];
|
||||
_RAND_34 = {1{`RANDOM}};
|
||||
_T_140_bits_load_ldst_bypass_d = _RAND_34[0:0];
|
||||
_T_140_bits_dma = _RAND_34[0:0];
|
||||
_RAND_35 = {1{`RANDOM}};
|
||||
_T_140_bits_store_data_bypass_m = _RAND_35[0:0];
|
||||
_T_140_bits_store_data_bypass_d = _RAND_35[0:0];
|
||||
_RAND_36 = {1{`RANDOM}};
|
||||
_T_141 = _RAND_36[0:0];
|
||||
_T_140_bits_load_ldst_bypass_d = _RAND_36[0:0];
|
||||
_RAND_37 = {1{`RANDOM}};
|
||||
_T_142 = _RAND_37[0:0];
|
||||
_T_140_bits_store_data_bypass_m = _RAND_37[0:0];
|
||||
_RAND_38 = {1{`RANDOM}};
|
||||
store_data_pre_m = _RAND_38[31:0];
|
||||
_T_141 = _RAND_38[0:0];
|
||||
_RAND_39 = {1{`RANDOM}};
|
||||
_T_152 = _RAND_39[31:0];
|
||||
_T_142 = _RAND_39[0:0];
|
||||
_RAND_40 = {1{`RANDOM}};
|
||||
_T_153 = _RAND_40[31:0];
|
||||
store_data_pre_m = _RAND_40[31:0];
|
||||
_RAND_41 = {1{`RANDOM}};
|
||||
end_addr_pre_m = _RAND_41[28:0];
|
||||
_T_152 = _RAND_41[31:0];
|
||||
_RAND_42 = {1{`RANDOM}};
|
||||
_T_158 = _RAND_42[2:0];
|
||||
_T_153 = _RAND_42[31:0];
|
||||
_RAND_43 = {1{`RANDOM}};
|
||||
end_addr_pre_r = _RAND_43[28:0];
|
||||
end_addr_pre_m = _RAND_43[28:0];
|
||||
_RAND_44 = {1{`RANDOM}};
|
||||
_T_164 = _RAND_44[2:0];
|
||||
_T_158 = _RAND_44[2:0];
|
||||
_RAND_45 = {1{`RANDOM}};
|
||||
_T_178 = _RAND_45[0:0];
|
||||
end_addr_pre_r = _RAND_45[28:0];
|
||||
_RAND_46 = {1{`RANDOM}};
|
||||
_T_179 = _RAND_46[0:0];
|
||||
_T_164 = _RAND_46[2:0];
|
||||
_RAND_47 = {1{`RANDOM}};
|
||||
_T_180 = _RAND_47[0:0];
|
||||
_T_178 = _RAND_47[0:0];
|
||||
_RAND_48 = {1{`RANDOM}};
|
||||
_T_181 = _RAND_48[0:0];
|
||||
_T_179 = _RAND_48[0:0];
|
||||
_RAND_49 = {1{`RANDOM}};
|
||||
_T_182 = _RAND_49[0:0];
|
||||
_T_180 = _RAND_49[0:0];
|
||||
_RAND_50 = {1{`RANDOM}};
|
||||
addr_external_r = _RAND_50[0:0];
|
||||
_T_181 = _RAND_50[0:0];
|
||||
_RAND_51 = {1{`RANDOM}};
|
||||
bus_read_data_r = _RAND_51[31:0];
|
||||
_T_182 = _RAND_51[0:0];
|
||||
_RAND_52 = {1{`RANDOM}};
|
||||
addr_external_r = _RAND_52[0:0];
|
||||
_RAND_53 = {1{`RANDOM}};
|
||||
bus_read_data_r = _RAND_53[31:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
access_fault_m = 1'h0;
|
||||
|
|
@ -909,6 +924,9 @@ initial begin
|
|||
if (reset) begin
|
||||
_T_138_bits_fast_int = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_138_bits_stack = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_138_bits_by = 1'h0;
|
||||
end
|
||||
|
|
@ -945,6 +963,9 @@ initial begin
|
|||
if (reset) begin
|
||||
_T_140_bits_fast_int = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_140_bits_stack = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_140_bits_by = 1'h0;
|
||||
end
|
||||
|
|
@ -1111,7 +1132,7 @@ end // initial
|
|||
_T_111 <= _T_81 & _T_82;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_112 <= 2'h0;
|
||||
end else if (fir_nondccm_access_error_m) begin
|
||||
|
|
@ -1131,6 +1152,13 @@ end // initial
|
|||
_T_138_bits_fast_int <= io_lsu_pkt_d_bits_fast_int;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_138_bits_stack <= 1'h0;
|
||||
end else begin
|
||||
_T_138_bits_stack <= io_lsu_pkt_d_bits_stack;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_138_bits_by <= 1'h0;
|
||||
|
|
@ -1215,6 +1243,13 @@ end // initial
|
|||
_T_140_bits_fast_int <= io_lsu_pkt_m_bits_fast_int;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_140_bits_stack <= 1'h0;
|
||||
end else begin
|
||||
_T_140_bits_stack <= io_lsu_pkt_m_bits_stack;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_140_bits_by <= 1'h0;
|
||||
|
|
|
|||
|
|
@ -525,6 +525,7 @@ class alu_pkt_t extends Bundle {
|
|||
|
||||
class lsu_pkt_t extends Bundle {
|
||||
val fast_int = Bool()
|
||||
val stack = Bool()
|
||||
val by = Bool()
|
||||
val half = Bool()
|
||||
val word = Bool()
|
||||
|
|
@ -545,7 +546,6 @@ class lsu_error_pkt_t extends Bundle {
|
|||
val mscause = UInt(4.W)
|
||||
val addr = UInt(32.W)
|
||||
}
|
||||
|
||||
class dec_pkt_t extends Bundle {
|
||||
val alu = Bool()
|
||||
val rs1 = Bool()
|
||||
|
|
|
|||
|
|
@ -185,9 +185,10 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
|
|||
io.lsu_error_pkt_r := rvdffe(lsu_error_pkt_m,(lsu_error_pkt_m.valid | lsu_error_pkt_m.bits.single_ecc_error | io.clk_override),clock,io.scan_mode)
|
||||
io.lsu_error_pkt_r.bits.single_ecc_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m.bits.single_ecc_error, 0.U)}
|
||||
io.lsu_error_pkt_r.valid := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m.valid, 0.U)}
|
||||
io.lsu_fir_error := RegNext(lsu_fir_error_m,0.U)
|
||||
io.lsu_fir_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_fir_error_m,0.U)}
|
||||
}
|
||||
dma_pkt_d.bits.unsign := 0.U
|
||||
dma_pkt_d.bits.stack := 0.U
|
||||
dma_pkt_d.bits.fast_int := 0.U
|
||||
dma_pkt_d.valid := io.dma_lsc_ctl.dma_dccm_req
|
||||
dma_pkt_d.bits.dma := 1.U
|
||||
|
|
|
|||
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Reference in New Issue