Expanded fixed
This commit is contained in:
waleed-lm
parent
d7b56da4e9
commit
9240176bc5
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@ -7,6 +7,7 @@
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<content url="file://$MODULE_DIR$/../..">
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<sourceFolder url="file://$MODULE_DIR$/../../src/main/scala" isTestSource="false" />
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<sourceFolder url="file://$MODULE_DIR$/../../src/test/scala" isTestSource="true" />
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<sourceFolder url="file://$MODULE_DIR$/../../src/main/resources" type="java-resource" />
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<excludeFolder url="file://$MODULE_DIR$/../../target" />
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</content>
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<orderEntry type="inheritedJdk" />
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@ -0,0 +1,14 @@
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module TEC_RV_ICG(
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(
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input logic SE, EN, CK,
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output Q
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);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always @(CK, enable) begin
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if(!CK)
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en_ff = enable;
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end
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assign Q = CK & en_ff;
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endmodule
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@ -2,7 +2,7 @@
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circuit el2_ifu_bp_ctl :
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module el2_ifu_bp_ctl :
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input clock : Clock
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input reset : UInt<1>
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input reset : AsyncReset
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output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>}
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wire leak_one_f : UInt<1>
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@ -195,8 +195,8 @@ circuit el2_ifu_bp_ctl :
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btb_bank0e_rd_data_f <= _T_121 @[Mux.scala 27:72]
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node _T_122 = bits(tag_match_way0_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 167:65]
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node _T_123 = bits(_T_122, 0, 0) @[el2_ifu_bp_ctl.scala 167:69]
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node _T_124 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 168:30]
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node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_bp_ctl.scala 168:34]
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node _T_124 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 168:65]
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node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_bp_ctl.scala 168:69]
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node _T_126 = mux(_T_123, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_127 = mux(_T_125, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_128 = or(_T_126, _T_127) @[Mux.scala 27:72]
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@ -341,7 +341,7 @@ circuit el2_ifu_bp_ctl :
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node _T_226 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 229:73]
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node _T_227 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 230:40]
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node _T_228 = bits(_T_227, 0, 0) @[el2_ifu_bp_ctl.scala 230:44]
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node _T_229 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 230:73]
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node _T_229 = bits(btb_vbank0_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 230:73]
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node _T_230 = mux(_T_225, _T_226, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_231 = mux(_T_228, _T_229, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_232 = or(_T_230, _T_231) @[Mux.scala 27:72]
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5212
el2_ifu_bp_ctl.v
5212
el2_ifu_bp_ctl.v
File diff suppressed because it is too large
Load Diff
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@ -3,7 +3,7 @@ circuit el2_ifu_ifc_ctl :
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module el2_ifu_ifc_ctl :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
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output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
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wire fetch_addr_bf : UInt<31>
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fetch_addr_bf <= UInt<1>("h00")
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@ -149,8 +149,8 @@ circuit el2_ifu_ifc_ctl :
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node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
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node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
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node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
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reg _T_80 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
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_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:19]
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reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:45]
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_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:45]
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state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
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flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
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node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
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@ -208,64 +208,60 @@ circuit el2_ifu_ifc_ctl :
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wire _T_130 : UInt<4> @[Mux.scala 27:72]
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_T_130 <= _T_129 @[Mux.scala 27:72]
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fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
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node _T_131 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
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reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
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_T_132 <= _T_131 @[el2_ifu_ifc_ctl.scala 119:26]
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fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 119:16]
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node _T_133 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
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idle <= _T_133 @[el2_ifu_ifc_ctl.scala 121:8]
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node _T_134 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
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wfm <= _T_134 @[el2_ifu_ifc_ctl.scala 122:7]
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node _T_135 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
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fb_full_f_ns <= _T_135 @[el2_ifu_ifc_ctl.scala 124:16]
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reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
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fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
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reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
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_T_136 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
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fb_write_f <= _T_136 @[el2_ifu_ifc_ctl.scala 126:14]
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node _T_137 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
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node _T_138 = or(_T_137, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
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node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
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node _T_140 = and(fb_full_f, _T_139) @[el2_ifu_ifc_ctl.scala 129:17]
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node _T_141 = or(_T_140, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
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node _T_142 = and(io.ifc_fetch_req_bf_raw, _T_141) @[el2_ifu_ifc_ctl.scala 128:60]
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node _T_143 = or(wfm, _T_142) @[el2_ifu_ifc_ctl.scala 128:33]
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io.ifu_pmu_fetch_stall <= _T_143 @[el2_ifu_ifc_ctl.scala 128:26]
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node _T_144 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_145 = bits(_T_144, 31, 28) @[el2_lib.scala 211:25]
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node iccm_acc_in_region_bf = eq(_T_145, UInt<4>("h0e")) @[el2_lib.scala 211:47]
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node _T_146 = bits(_T_144, 31, 16) @[el2_lib.scala 214:14]
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node iccm_acc_in_range_bf = eq(_T_146, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
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io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
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node _T_147 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
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node _T_148 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
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node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
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node _T_150 = and(fb_full_f, _T_149) @[el2_ifu_ifc_ctl.scala 136:16]
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node _T_151 = or(_T_147, _T_150) @[el2_ifu_ifc_ctl.scala 135:53]
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node _T_152 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
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node _T_153 = and(wfm, _T_152) @[el2_ifu_ifc_ctl.scala 137:11]
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node _T_154 = or(_T_151, _T_153) @[el2_ifu_ifc_ctl.scala 136:62]
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node _T_155 = or(_T_154, idle) @[el2_ifu_ifc_ctl.scala 137:35]
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node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
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node _T_157 = and(_T_155, _T_156) @[el2_ifu_ifc_ctl.scala 137:44]
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node _T_158 = or(_T_157, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
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io.ifc_dma_access_ok <= _T_158 @[el2_ifu_ifc_ctl.scala 135:24]
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node _T_159 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
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node _T_160 = and(_T_159, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
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io.ifc_region_acc_fault_bf <= _T_160 @[el2_ifu_ifc_ctl.scala 139:30]
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node _T_161 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
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node _T_162 = cat(_T_161, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_163 = dshr(io.dec_tlu_mrac_ff, _T_162) @[el2_ifu_ifc_ctl.scala 140:53]
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node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
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node _T_165 = not(_T_164) @[el2_ifu_ifc_ctl.scala 140:34]
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io.ifc_fetch_uncacheable_bf <= _T_165 @[el2_ifu_ifc_ctl.scala 140:31]
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reg _T_166 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
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_T_166 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
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io.ifc_fetch_req_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:22]
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node _T_167 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
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reg _T_168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_167 : @[Reg.scala 28:19]
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_T_168 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
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node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 119:17]
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idle <= _T_131 @[el2_ifu_ifc_ctl.scala 119:8]
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node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 120:16]
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wfm <= _T_132 @[el2_ifu_ifc_ctl.scala 120:7]
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node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 122:30]
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fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctl.scala 122:16]
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reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 123:52]
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fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 123:52]
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reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 124:50]
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_T_134 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 124:50]
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fb_write_f <= _T_134 @[el2_ifu_ifc_ctl.scala 124:14]
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node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 127:40]
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node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 127:61]
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node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 127:19]
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node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctl.scala 127:17]
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node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctl.scala 127:84]
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node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctl.scala 126:60]
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node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctl.scala 126:33]
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io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctl.scala 126:26]
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node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 216:25]
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node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 216:47]
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node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 219:14]
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node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 219:29]
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io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 132:25]
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node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 133:30]
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node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 134:39]
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node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 134:18]
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node _T_148 = and(fb_full_f, _T_147) @[el2_ifu_ifc_ctl.scala 134:16]
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node _T_149 = or(_T_145, _T_148) @[el2_ifu_ifc_ctl.scala 133:53]
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node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:13]
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node _T_151 = and(wfm, _T_150) @[el2_ifu_ifc_ctl.scala 135:11]
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node _T_152 = or(_T_149, _T_151) @[el2_ifu_ifc_ctl.scala 134:62]
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node _T_153 = or(_T_152, idle) @[el2_ifu_ifc_ctl.scala 135:35]
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node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:46]
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node _T_155 = and(_T_153, _T_154) @[el2_ifu_ifc_ctl.scala 135:44]
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node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 135:67]
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io.ifc_dma_access_ok <= _T_156 @[el2_ifu_ifc_ctl.scala 133:24]
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node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:33]
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node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 137:55]
|
||||
io.ifc_region_acc_fault_bf <= _T_158 @[el2_ifu_ifc_ctl.scala 137:30]
|
||||
node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 138:78]
|
||||
node _T_160 = cat(_T_159, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_161 = dshr(io.dec_tlu_mrac_ff, _T_160) @[el2_ifu_ifc_ctl.scala 138:53]
|
||||
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_ifc_ctl.scala 138:53]
|
||||
node _T_163 = not(_T_162) @[el2_ifu_ifc_ctl.scala 138:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_163 @[el2_ifu_ifc_ctl.scala 138:31]
|
||||
reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 140:57]
|
||||
_T_164 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 140:57]
|
||||
io.ifc_fetch_req_f <= _T_164 @[el2_ifu_ifc_ctl.scala 140:22]
|
||||
node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:88]
|
||||
reg _T_166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_165 : @[Reg.scala 28:19]
|
||||
_T_166 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
io.ifc_fetch_addr_f <= _T_168 @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
io.ifc_fetch_addr_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -62,8 +62,8 @@ module el2_ifu_ifc_ctl(
|
|||
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
||||
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:45]
|
||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 119:17]
|
||||
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -76,7 +76,7 @@ module el2_ifu_ifc_ctl(
|
|||
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 124:50]
|
||||
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
|
||||
|
|
@ -102,7 +102,7 @@ module el2_ifu_ifc_ctl(
|
|||
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 122:30]
|
||||
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
|
|
@ -132,39 +132,39 @@ module el2_ifu_ifc_ctl(
|
|||
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
wire _T_138 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
wire _T_139 = ~_T_138; // @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
wire _T_140 = fb_full_f & _T_139; // @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
wire _T_141 = _T_140 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
wire _T_142 = io_ifc_fetch_req_bf_raw & _T_141; // @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
wire [31:0] _T_144 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_144[31:28] == 4'he; // @[el2_lib.scala 211:47]
|
||||
wire iccm_acc_in_range_bf = _T_144[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
|
||||
wire _T_147 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
wire _T_150 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
wire _T_151 = _T_147 | _T_150; // @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
wire _T_152 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
wire _T_153 = wfm & _T_152; // @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
wire _T_154 = _T_151 | _T_153; // @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
wire _T_155 = _T_154 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
wire _T_157 = _T_155 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
wire _T_159 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
wire [4:0] _T_162 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_163 = io_dec_tlu_mrac_ff >> _T_162; // @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
reg _T_166; // @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
reg [30:0] _T_168; // @[Reg.scala 27:20]
|
||||
assign io_ifc_fetch_addr_f = _T_168; // @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 120:16]
|
||||
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 123:52]
|
||||
wire _T_136 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 127:61]
|
||||
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctl.scala 127:19]
|
||||
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctl.scala 127:17]
|
||||
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84]
|
||||
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60]
|
||||
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 216:47]
|
||||
wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 219:29]
|
||||
wire _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30]
|
||||
wire _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16]
|
||||
wire _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53]
|
||||
wire _T_150 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 135:13]
|
||||
wire _T_151 = wfm & _T_150; // @[el2_ifu_ifc_ctl.scala 135:11]
|
||||
wire _T_152 = _T_149 | _T_151; // @[el2_ifu_ifc_ctl.scala 134:62]
|
||||
wire _T_153 = _T_152 | idle; // @[el2_ifu_ifc_ctl.scala 135:35]
|
||||
wire _T_155 = _T_153 & _T_2; // @[el2_ifu_ifc_ctl.scala 135:44]
|
||||
wire _T_157 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 137:33]
|
||||
wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53]
|
||||
reg _T_164; // @[el2_ifu_ifc_ctl.scala 140:57]
|
||||
reg [30:0] _T_166; // @[Reg.scala 27:20]
|
||||
assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23]
|
||||
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
|
||||
assign io_ifc_fetch_req_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_142; // @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_163[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctl.scala 126:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[el2_ifu_ifc_ctl.scala 138:31]
|
||||
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
assign io_ifc_iccm_access_bf = _T_144[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_159 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
assign io_ifc_dma_access_ok = _T_157 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30]
|
||||
assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -211,9 +211,9 @@ initial begin
|
|||
_RAND_4 = {1{`RANDOM}};
|
||||
fb_full_f = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_166 = _RAND_5[0:0];
|
||||
_T_164 = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
_T_168 = _RAND_6[30:0];
|
||||
_T_166 = _RAND_6[30:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
dma_iccm_stall_any_f = 1'h0;
|
||||
|
|
@ -231,10 +231,10 @@ initial begin
|
|||
fb_full_f = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_166 = 1'h0;
|
||||
_T_164 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_168 = 31'h0;
|
||||
_T_166 = 31'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
|
|
@ -256,39 +256,39 @@ end // initial
|
|||
miss_a <= _T_48 & _T_2;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge io_active_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
state <= 2'h0;
|
||||
end else begin
|
||||
state <= {next_state_1,next_state_0};
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge io_active_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
fb_write_f <= 4'h0;
|
||||
end else begin
|
||||
fb_write_f <= _T_128 | _T_125;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge io_active_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
fb_full_f <= 1'h0;
|
||||
end else begin
|
||||
fb_full_f <= fb_write_ns[3];
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
always @(posedge io_active_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_166 <= 1'h0;
|
||||
_T_164 <= 1'h0;
|
||||
end else begin
|
||||
_T_166 <= io_ifc_fetch_req_bf;
|
||||
_T_164 <= io_ifc_fetch_req_bf;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_168 <= 31'h0;
|
||||
_T_166 <= 31'h0;
|
||||
end else if (fetch_bf_en) begin
|
||||
_T_168 <= io_ifc_fetch_addr_bf;
|
||||
_T_166 <= io_ifc_fetch_addr_bf;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
/home/waleedbinehsan/Desktop/SweRV-Chisel/rvdff.v
|
||||
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/TEC_RV_ICG.v
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
module TEC_RV_ICG(
|
||||
(
|
||||
input logic SE, EN, CK,
|
||||
output Q
|
||||
);
|
||||
logic en_ff;
|
||||
logic enable;
|
||||
assign enable = EN | SE;
|
||||
always @(CK, enable) begin
|
||||
if(!CK)
|
||||
en_ff = enable;
|
||||
end
|
||||
assign Q = CK & en_ff;
|
||||
endmodule
|
||||
|
|
@ -6,7 +6,7 @@ import chisel3.util._
|
|||
import chisel3.experimental.chiselName
|
||||
|
||||
@chiselName
|
||||
class el2_ifu_bp_ctl extends Module with el2_lib {
|
||||
class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
|
||||
val io = IO (new Bundle {
|
||||
val active_clk = Input(Clock())
|
||||
val ic_hit_f = Input(Bool())
|
||||
|
|
@ -227,7 +227,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
|
|||
val btb_rd_ret_f = btb_sel_data_f(0)
|
||||
|
||||
btb_sel_data_f := Mux1H(Seq(btb_sel_f(1).asBool-> btb_vbank1_rd_data_f(16,1),
|
||||
btb_sel_f(0).asBool-> btb_vbank1_rd_data_f(16,1)))
|
||||
btb_sel_f(0).asBool-> btb_vbank0_rd_data_f(16,1)))
|
||||
|
||||
io.ifu_bp_hit_taken_f := (vwayhit_f & hist1_raw).orR & io.ifc_fetch_req_f & !leak_one_f_d1 & !io.dec_tlu_bpred_disable
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ import chisel3.util._
|
|||
class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
val free_clk = Input(Clock())
|
||||
val active_clk = Input(Bool())
|
||||
val active_clk = Input(Clock())
|
||||
val scan_mode = Input(Bool())
|
||||
val ic_hit_f = Input(Bool())
|
||||
val ifu_ic_mb_empty = Input(Bool())
|
||||
|
|
@ -99,7 +99,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
val next_state_0 = (!goto_idle & leave_idle) | (state(0) & !goto_idle)
|
||||
|
||||
state := RegNext(Cat(next_state_1, next_state_0), init = 0.U)
|
||||
state := withClock(io.active_clk) {RegNext(Cat(next_state_1, next_state_0), init = 0.U)}
|
||||
|
||||
flush_fb := io.exu_flush_final
|
||||
|
||||
|
|
@ -116,14 +116,12 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
(!flush_fb & !fb_right & !fb_right2 & !fb_left).asBool -> fb_write_f(3,0)
|
||||
))
|
||||
|
||||
fb_full_f_ns := RegNext(fb_write_ns(3), init = 0.U)
|
||||
|
||||
idle := state === 0.U(2.W)
|
||||
wfm := state === 3.U(2.W)
|
||||
|
||||
fb_full_f_ns := fb_write_ns(3)
|
||||
val fb_full_f = RegNext(fb_full_f_ns, init = 0.U)
|
||||
fb_write_f := RegNext(fb_write_ns, 0.U)
|
||||
val fb_full_f = withClock(io.active_clk) {RegNext(fb_full_f_ns, init = 0.U)}
|
||||
fb_write_f := withClock(io.active_clk) {RegNext(fb_write_ns, 0.U)}
|
||||
|
||||
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw &
|
||||
((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
|
||||
|
|
@ -139,9 +137,10 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf
|
||||
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
|
||||
|
||||
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)
|
||||
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
|
||||
|
||||
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
|
||||
//rvdffe(io.ifc_fetch_addr_bf,(io.exu_flush_final|io.ifc_fetch_req_f).asBool,clock,io.scan_mode)
|
||||
}
|
||||
|
||||
object ifu_ifc extends App {
|
||||
|
|
|
|||
|
|
@ -375,4 +375,63 @@ trait el2_lib extends param{
|
|||
val ecc_error = en & (ecc_check(6,0) =/= 0.U)
|
||||
ecc_error
|
||||
}
|
||||
|
||||
|
||||
|
||||
class TEC_RV_ICG extends BlackBox with HasBlackBoxResource {
|
||||
val io = IO(new Bundle {
|
||||
val Q = Output(Clock())
|
||||
val CK = Input(Clock())
|
||||
val EN = Input(Bool())
|
||||
val SE = Input(Bool())
|
||||
})
|
||||
addResource("/vsrc/TEC_RV_ICG.v")
|
||||
}
|
||||
|
||||
class rvclkhdr extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val l1clk = Output(Clock())
|
||||
val clk = Input(Clock())
|
||||
val en = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
val clkhdr = { Module(new TEC_RV_ICG) }
|
||||
io.l1clk := clkhdr.io.Q
|
||||
clkhdr.io.CK := io.clk
|
||||
clkhdr.io.EN := io.en
|
||||
clkhdr.io.SE := io.scan_mode
|
||||
}
|
||||
|
||||
object rvclkhdr {
|
||||
def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = {
|
||||
val cg = Module(new rvclkhdr)
|
||||
cg.io.clk := clk
|
||||
cg.io.en := en
|
||||
cg.io.scan_mode := scan_mode
|
||||
cg.io.l1clk
|
||||
}
|
||||
}
|
||||
|
||||
object rvdffe {
|
||||
def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
RegNext(din, 0.U)
|
||||
}
|
||||
}
|
||||
def apply(din: Bundle, en: Bool, clk: Clock, scan_mode: Bool) = {
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
RegNext(din,0.U.asTypeOf(din.cloneType))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
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|
@ -0,0 +1,14 @@
|
|||
module TEC_RV_ICG(
|
||||
(
|
||||
input logic SE, EN, CK,
|
||||
output Q
|
||||
);
|
||||
logic en_ff;
|
||||
logic enable;
|
||||
assign enable = EN | SE;
|
||||
always @(CK, enable) begin
|
||||
if(!CK)
|
||||
en_ff = enable;
|
||||
end
|
||||
assign Q = CK & en_ff;
|
||||
endmodule
|
||||
Loading…
Reference in New Issue