ifu added

ifu.anno.json

@@ -358,22 +358,6 @@
     "target":"ifu.gated_latch",
     "resourceId":"/vsrc/gated_latch.sv"
   },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way1_p1_f"
-  },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way0_p1_f"
-  },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way1_f"
-  },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu|ifu_bp_ctl>btb_bank0_rd_data_way0_f"
-  },
   {
     "class":"firrtl.transforms.DontTouchAnnotation",
     "target":"~ifu|ifu_mem_ctl>ifc_region_acc_okay"

ifu_bp_ctl.anno.json

@@ -150,22 +150,6 @@
     "target":"ifu_bp_ctl.gated_latch",
     "resourceId":"/vsrc/gated_latch.sv"
   },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way1_p1_f"
-  },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way0_p1_f"
-  },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way1_f"
-  },
-  {
-    "class":"firrtl.transforms.DontTouchAnnotation",
-    "target":"~ifu_bp_ctl|ifu_bp_ctl>btb_bank0_rd_data_way0_f"
-  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."

src/main/scala/dbg/dbg.scala

@@ -4,6 +4,14 @@
 //import chisel3.util._
 //import lib._
 //
+//
+//class dbg_dma extends Bundle {
+//  val dbg_dma_bubble        = Input(Bool())     // Debug needs a bubble to send a valid
+//  val dma_dbg_ready         = Output(Bool())    // DMA is ready to accept debug request
+//
+//}
+//
+//
 //object state_t {
 //  val idle            = 0.U(4.W)
 //  val halting         = 1.U(4.W)
@@ -30,7 +38,7 @@
 //  val done            = 9.U(4.W)
 //}
 //
-//class dbg extends Module with el2_lib with RequireAsyncReset {
+//class dbg extends Module with lib with RequireAsyncReset {
 //  val io = IO(new Bundle {
 //    val dbg_cmd_addr              = Output(UInt(32.W))
 //    val dbg_cmd_wrdata            = Output(UInt(32.W))
@@ -42,8 +50,11 @@
 //    val core_dbg_rddata           = Input(UInt(32.W))
 //    val core_dbg_cmd_done         = Input(Bool())
 //    val core_dbg_cmd_fail         = Input(Bool())
-//    val dbg_dma_bubble            = Output(Bool())
-//    val dma_dbg_ready             = Input(Bool())
+//    val dbg_dma = Flipped(new dbg_dma)
+//    val sb_axi = new axi_channels(SB_BUS_TAG)
+//    val dbg_dec_dma = Flipped(new dec_dbg)
+//   // val dbg_dma_bubble            = Output(Bool())
+//   // val dma_dbg_ready             = Input(Bool())
 //    val dbg_halt_req              = Output(Bool())
 //    val dbg_resume_req            = Output(Bool())
 //    val dec_tlu_debug_mode        = Input(Bool())

src/main/scala/ifu/ifu.scala

@@ -109,6 +109,13 @@ class ifu extends Module with lib with RequireAsyncReset {
   bp_ctl.io.exu_flush_final := io.exu_flush_final
   bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
   bp_ctl.io.dec_fa_error_index :=   io.dec_fa_error_index
+//  bp_ctl.btb_bank0_rd_data_way1_out.suggestName("bp_ctl.btb_bank0_rd_data_way1_out")
+  // for(i <- 0 until BTB_ARRAY_DEPTH) {dontTouch(bp_ctl.btb_bank0_rd_data_way0_out(i))}
+ // dontTouch(bp_ctl.btb_bank0_rd_data_way1_out(0))
+//  dontTouch(bp_ctl.btb_bank0_rd_data_way0_f)
+//  dontTouch(bp_ctl.btb_bank0_rd_data_way1_f)
+//  dontTouch(bp_ctl.btb_bank0_rd_data_way0_p1_f)
+//  dontTouch(bp_ctl.btb_bank0_rd_data_way1_p1_f)
 
   // mem-ctl Inputs
   mem_ctl.io.free_l2clk := io.free_l2clk

src/main/scala/ifu/ifu_bp_ctl.scala

@@ -416,7 +416,8 @@ if(!BTB_FULLYA) {
   val bht_wr_addr2 = br0_hashed_wb
   val bht_rd_addr_f = bht_rd_addr_hashed_f
   val bht_rd_addr_p1_f = bht_rd_addr_hashed_p1_f
-
+  val btb_bank0_rd_data_way0_out = Wire(Vec(LRU_SIZE,UInt(BTB_DWIDTH.W)))
+  val btb_bank0_rd_data_way1_out = Wire(Vec(LRU_SIZE,UInt(BTB_DWIDTH.W)))
   // BTB
   // Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid
 if(!BTB_FULLYA) {
@@ -429,20 +430,14 @@ if(!BTB_FULLYA) {
 
    vwayhit_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
     io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
-  val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
-  val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
 
+  btb_bank0_rd_data_way0_out := (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
+  btb_bank0_rd_data_way1_out := (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
   btb_bank0_rd_data_way0_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
-  dontTouch(btb_bank0_rd_data_way0_f)
-
   btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
-  dontTouch(btb_bank0_rd_data_way1_f)
   // BTB read muxing
   btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
-  dontTouch(btb_bank0_rd_data_way0_p1_f)
-
   btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
-  dontTouch(btb_bank0_rd_data_way1_p1_f)
 }
 //  if(BTB_FULLYA){
 //    val fetch_mp_collision_f = WireInit(Bool(),init = false.B)