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Chisel Freeze

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waleed-lm 2020-12-15 12:01:57 +05:00
parent e24a5f750f
commit 95f191bcb9
22 changed files with 12949 additions and 10439 deletions
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axi4_to_ahb.fir
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axi4_to_ahb.v
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@ -27,7 +27,7 @@ module axi4_to_ahb(
input io_clk_override, input io_clk_override,
output io_axi_aw_ready, output io_axi_aw_ready,
input io_axi_aw_valid, input io_axi_aw_valid,
input io_axi_aw_bits_id, input [2:0] io_axi_aw_bits_id,
input [31:0] io_axi_aw_bits_addr, input [31:0] io_axi_aw_bits_addr,
input [3:0] io_axi_aw_bits_region, input [3:0] io_axi_aw_bits_region,
input [7:0] io_axi_aw_bits_len, input [7:0] io_axi_aw_bits_len,
@ -45,10 +45,10 @@ module axi4_to_ahb(
input io_axi_b_ready, input io_axi_b_ready,
output io_axi_b_valid, output io_axi_b_valid,
output [1:0] io_axi_b_bits_resp, output [1:0] io_axi_b_bits_resp,
output io_axi_b_bits_id, output [2:0] io_axi_b_bits_id,
output io_axi_ar_ready, output io_axi_ar_ready,
input io_axi_ar_valid, input io_axi_ar_valid,
input io_axi_ar_bits_id, input [2:0] io_axi_ar_bits_id,
input [31:0] io_axi_ar_bits_addr, input [31:0] io_axi_ar_bits_addr,
input [3:0] io_axi_ar_bits_region, input [3:0] io_axi_ar_bits_region,
input [7:0] io_axi_ar_bits_len, input [7:0] io_axi_ar_bits_len,
@ -60,7 +60,7 @@ module axi4_to_ahb(
input [3:0] io_axi_ar_bits_qos, input [3:0] io_axi_ar_bits_qos,
input io_axi_r_ready, input io_axi_r_ready,
output io_axi_r_valid, output io_axi_r_valid,
output io_axi_r_bits_id, output [2:0] io_axi_r_bits_id,
output [63:0] io_axi_r_bits_data, output [63:0] io_axi_r_bits_data,
output [1:0] io_axi_r_bits_resp, output [1:0] io_axi_r_bits_resp,
output io_axi_r_bits_last, output io_axi_r_bits_last,
@ -144,31 +144,31 @@ module axi4_to_ahb(
wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] wire rvclkhdr_9_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_9_io_en; // @[lib.scala 343:22] wire rvclkhdr_9_io_en; // @[lib.scala 343:22]
wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22]
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 31:22 axi4_to_ahb.scala 340:12] wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12]
reg [2:0] buf_state; // @[axi4_to_ahb.scala 37:45] reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45]
wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 57:21 axi4_to_ahb.scala 169:11] wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11]
reg wrbuf_vld; // @[axi4_to_ahb.scala 308:51] reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51]
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 309:51] reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 146:27] wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27]
wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 147:30] wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30]
wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hready_q; // @[axi4_to_ahb.scala 328:52] reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52]
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 329:52] reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52]
wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 190:58] wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58]
wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 190:36] wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36]
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 32:27 axi4_to_ahb.scala 341:17] wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17]
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 330:57] reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57]
wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 190:72] wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72]
wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 190:70] wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70]
wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hresp_q; // @[axi4_to_ahb.scala 331:52] reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52]
wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 204:37] wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37]
wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 236:33] wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33]
wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 236:48] wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48]
wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30]
wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67]
wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67]
@ -177,11 +177,11 @@ module axi4_to_ahb(
wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
reg cmd_doneQ; // @[axi4_to_ahb.scala 326:52] reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52]
wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 246:34] wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34]
wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 246:50] wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50]
wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 164:33] wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 157:33]
wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
@ -190,9 +190,9 @@ module axi4_to_ahb(
wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67]
wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67]
wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58]
wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 149:20] wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20]
wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 149:14] wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14]
wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 175:41] wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41]
wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67]
wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
@ -200,19 +200,19 @@ module axi4_to_ahb(
wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58]
wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 176:26] wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26]
wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 189:61] wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61]
wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 189:41] wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41]
wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 189:26] wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26]
wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 193:174] wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174]
wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 193:88] wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88]
wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 201:39] wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39]
wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 201:37] wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37]
wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 201:70] wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70]
wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 201:55] wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55]
wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 201:53] wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53]
wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 247:36] wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36]
wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 247:51] wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 240:51]
wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
@ -220,15 +220,15 @@ module axi4_to_ahb(
wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67]
wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58]
wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 203:82] wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82]
wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 203:97] wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97]
wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 203:67] wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67]
wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 203:26] wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26]
wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 248:42] wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 241:42]
wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 248:40] wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 241:40]
wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 248:99] wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99]
wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 248:65] wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65]
wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 248:26] wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26]
wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67]
wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67]
wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67]
@ -236,15 +236,15 @@ module axi4_to_ahb(
wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67]
wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67]
wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58]
reg wrbuf_tag; // @[Reg.scala 27:20] reg [2:0] wrbuf_tag; // @[Reg.scala 27:20]
reg [31:0] wrbuf_addr; // @[lib.scala 374:16] reg [31:0] wrbuf_addr; // @[lib.scala 374:16]
wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 150:21] wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21]
reg [2:0] wrbuf_size; // @[Reg.scala 27:20] reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 151:21] wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[lib.scala 374:16] reg [63:0] wrbuf_data; // @[lib.scala 374:16]
wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55] wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55]
wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39] wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39]
wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
@ -252,29 +252,29 @@ module axi4_to_ahb(
wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 156:33] wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 149:33]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12] wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12]
reg slvbuf_write; // @[Reg.scala 27:20] reg slvbuf_write; // @[Reg.scala 27:20]
wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23] wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23]
reg slvbuf_error; // @[Reg.scala 27:20] reg slvbuf_error; // @[Reg.scala 27:20]
wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 292:88] wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88]
wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58]
wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55] wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55]
reg slvbuf_tag; // @[Reg.scala 27:20] reg [2:0] slvbuf_tag; // @[Reg.scala 27:20]
wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66] wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66]
reg [31:0] last_bus_addr; // @[Reg.scala 27:20] reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91] wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91]
reg [63:0] buf_data; // @[lib.scala 374:16] reg [63:0] buf_data; // @[lib.scala 374:16]
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 33:27 axi4_to_ahb.scala 342:17] wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 332:57] reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57]
wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 293:79] wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79]
wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57]
wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94]
wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76]
wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54] wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54]
wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38] wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38]
wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16]
wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16]
@ -282,14 +282,14 @@ module axi4_to_ahb(
wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16]
wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16]
wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16]
wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 182:30] wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30]
wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51] wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51]
wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 195:33] wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33]
wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 210:64] wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64]
wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 210:48] wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48]
wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 210:79] wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79]
wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 256:33] wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33]
wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 256:48] wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48]
wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
@ -298,39 +298,39 @@ module axi4_to_ahb(
wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67]
wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58]
wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 185:49] wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49]
wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 191:34] wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34]
wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 191:32] wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32]
reg [31:0] buf_addr; // @[lib.scala 374:16] reg [31:0] buf_addr; // @[lib.scala 374:16]
wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 196:30] wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30]
wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 197:48] wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48]
wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 197:62] wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62]
wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 197:36] wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36]
wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 212:63] wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63]
wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 212:78] wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78]
wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 212:47] wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47]
wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 212:36] wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36]
wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 222:41] wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41]
reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
reg [7:0] buf_byteen; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20]
wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 142:52] wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52]
wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 143:48] wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48]
wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 143:48] wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48]
wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 143:48] wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48]
wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 143:48] wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48]
wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 143:48] wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48]
wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 143:48] wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48]
wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 143:62] wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62]
wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 143:48] wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48]
wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16]
wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16]
@ -338,17 +338,17 @@ module axi4_to_ahb(
wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16]
wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16]
wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16]
wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 240:30] wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30]
wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 241:65] wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65]
reg buf_aligned; // @[Reg.scala 27:20] reg buf_aligned; // @[Reg.scala 27:20]
wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 241:44] wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44]
wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 241:92] wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92]
wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 241:163] wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163]
wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 241:79] wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79]
wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 241:29] wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29]
wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 255:38] wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38]
wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 254:80] wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80]
wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 254:34] wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34]
wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67]
wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67]
wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
@ -356,17 +356,17 @@ module axi4_to_ahb(
wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67]
wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 242:47] wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47]
wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 242:36] wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36]
wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 242:61] wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61]
wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 252:62] wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62]
wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 252:33] wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33]
wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 257:61] wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61]
wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 257:75] wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75]
wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 260:40] wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40]
wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 261:30] wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30]
wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67]
@ -415,92 +415,92 @@ module axi4_to_ahb(
wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 278:24] wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24]
wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 277:48] wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48]
wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 278:54] wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54]
wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 278:33] wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33]
wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 278:93] wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93]
wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 278:72] wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72]
wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 279:25] wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25]
wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 279:62] wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62]
wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 279:97] wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97]
wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 279:74] wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74]
wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 279:132] wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132]
wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 279:109] wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109]
wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 279:168] wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168]
wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 279:145] wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145]
wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 280:28] wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28]
wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 279:181] wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181]
wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 280:63] wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63]
wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 280:40] wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40]
wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 280:99] wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99]
wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 280:76] wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76]
wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 279:38] wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38]
wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 278:106] wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106]
wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 272:60] wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60]
wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 135:15] wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15]
wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 136:56] wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56]
wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 136:15] wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15]
wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 135:63] wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63]
wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 137:15] wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15]
wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 136:96] wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96]
wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 272:43] wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43]
wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33] wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33]
wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 276:38] wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38]
wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 276:71] wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71]
wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 129:55] wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55]
wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 129:16] wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16]
wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 128:64] wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64]
wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 130:60] wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60]
wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 130:89] wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89]
wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 130:123] wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123]
wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 130:21] wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21]
wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 129:93] wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93]
wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 276:21] wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21]
wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 276:15] wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15]
wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 283:81] wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81]
wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58]
wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
reg [1:0] buf_size; // @[Reg.scala 27:20] reg [1:0] buf_size; // @[Reg.scala 27:20]
wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 283:138] wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138]
wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 287:37] wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 280:37]
wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58] wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20] reg buf_write; // @[Reg.scala 27:20]
wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 296:44] wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44]
wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 296:56] wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56]
wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 296:75] wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75]
wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49]
wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52]
wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49]
wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 301:33] wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33]
wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 301:31] wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31]
wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 303:36] wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36]
wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 303:34] wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34]
wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22]
wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38]
wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21]
wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22] wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22]
wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55]
wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91]
wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55]
reg buf_tag; // @[Reg.scala 27:20] reg [2:0] buf_tag; // @[Reg.scala 27:20]
wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 326:92] wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92]
wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43]
wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58]
wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 335:57] wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57]
wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 335:81] wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81]
wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50]
wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 336:60] wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60]
rvclkhdr rvclkhdr ( // @[lib.scala 343:22] rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -561,25 +561,25 @@ module axi4_to_ahb(
.io_en(rvclkhdr_9_io_en), .io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode) .io_scan_mode(rvclkhdr_9_io_scan_mode)
); );
assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19]
assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18]
assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18] assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 149:18]
assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22] assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22]
assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20] assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20]
assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19] assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19]
assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18] assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 153:18]
assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20] assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20]
assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 163:22] assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22]
assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22] assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22]
assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 306:22] assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 299:22]
assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 282:20] assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20]
assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 285:21] assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 278:21]
assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 286:24] assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 279:24]
assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 287:20] assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 280:20]
assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 283:20] assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20]
assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 197:25 axi4_to_ahb.scala 212:25 axi4_to_ahb.scala 222:25 axi4_to_ahb.scala 242:25 axi4_to_ahb.scala 257:25] assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25]
assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 288:21] assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21]
assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 289:21] assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21]
assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
@ -662,7 +662,7 @@ initial begin
_RAND_7 = {1{`RANDOM}}; _RAND_7 = {1{`RANDOM}};
cmd_doneQ = _RAND_7[0:0]; cmd_doneQ = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}}; _RAND_8 = {1{`RANDOM}};
wrbuf_tag = _RAND_8[0:0]; wrbuf_tag = _RAND_8[2:0];
_RAND_9 = {1{`RANDOM}}; _RAND_9 = {1{`RANDOM}};
wrbuf_addr = _RAND_9[31:0]; wrbuf_addr = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}}; _RAND_10 = {1{`RANDOM}};
@ -676,7 +676,7 @@ initial begin
_RAND_14 = {1{`RANDOM}}; _RAND_14 = {1{`RANDOM}};
slvbuf_error = _RAND_14[0:0]; slvbuf_error = _RAND_14[0:0];
_RAND_15 = {1{`RANDOM}}; _RAND_15 = {1{`RANDOM}};
slvbuf_tag = _RAND_15[0:0]; slvbuf_tag = _RAND_15[2:0];
_RAND_16 = {1{`RANDOM}}; _RAND_16 = {1{`RANDOM}};
last_bus_addr = _RAND_16[31:0]; last_bus_addr = _RAND_16[31:0];
_RAND_17 = {2{`RANDOM}}; _RAND_17 = {2{`RANDOM}};
@ -696,7 +696,7 @@ initial begin
_RAND_24 = {1{`RANDOM}}; _RAND_24 = {1{`RANDOM}};
buf_write = _RAND_24[0:0]; buf_write = _RAND_24[0:0];
_RAND_25 = {1{`RANDOM}}; _RAND_25 = {1{`RANDOM}};
buf_tag = _RAND_25[0:0]; buf_tag = _RAND_25[2:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
if (reset) begin if (reset) begin
buf_state = 3'h0; buf_state = 3'h0;
@ -723,7 +723,7 @@ initial begin
cmd_doneQ = 1'h0; cmd_doneQ = 1'h0;
end end
if (reset) begin if (reset) begin
wrbuf_tag = 1'h0; wrbuf_tag = 3'h0;
end end
if (reset) begin if (reset) begin
wrbuf_addr = 32'h0; wrbuf_addr = 32'h0;
@ -744,7 +744,7 @@ initial begin
slvbuf_error = 1'h0; slvbuf_error = 1'h0;
end end
if (reset) begin if (reset) begin
slvbuf_tag = 1'h0; slvbuf_tag = 3'h0;
end end
if (reset) begin if (reset) begin
last_bus_addr = 32'h0; last_bus_addr = 32'h0;
@ -774,7 +774,7 @@ initial begin
buf_write = 1'h0; buf_write = 1'h0;
end end
if (reset) begin if (reset) begin
buf_tag = 1'h0; buf_tag = 3'h0;
end end
`endif // RANDOMIZE `endif // RANDOMIZE
end // initial end // initial
@ -880,7 +880,7 @@ end // initial
end end
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin
if (reset) begin if (reset) begin
wrbuf_tag <= 1'h0; wrbuf_tag <= 3'h0;
end else if (wrbuf_en) begin end else if (wrbuf_en) begin
wrbuf_tag <= io_axi_aw_bits_id; wrbuf_tag <= io_axi_aw_bits_id;
end end
@ -943,7 +943,7 @@ end // initial
end end
always @(posedge buf_clk or posedge reset) begin always @(posedge buf_clk or posedge reset) begin
if (reset) begin if (reset) begin
slvbuf_tag <= 1'h0; slvbuf_tag <= 3'h0;
end else if (slvbuf_wr_en) begin end else if (slvbuf_wr_en) begin
slvbuf_tag <= buf_tag; slvbuf_tag <= buf_tag;
end end
@ -1127,7 +1127,7 @@ end // initial
end end
always @(posedge buf_clk or posedge reset) begin always @(posedge buf_clk or posedge reset) begin
if (reset) begin if (reset) begin
buf_tag <= 1'h0; buf_tag <= 3'h0;
end else if (buf_wr_en) begin end else if (buf_wr_en) begin
if (wr_cmd_vld) begin if (wr_cmd_vld) begin
buf_tag <= wrbuf_tag; buf_tag <= wrbuf_tag;

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quasar_wrapper.fir
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quasar_wrapper.v
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5
src/main/scala/lib/ahb_to_axi4.scala
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@ -5,13 +5,13 @@ import chisel3.experimental.chiselName
import include._ import include._
@chiselName @chiselName
class ahb_to_axi4 extends Module with lib with RequireAsyncReset { class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
val io = IO(new Bundle { val io = IO(new Bundle {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val bus_clk_en = Input(Bool()) val bus_clk_en = Input(Bool())
val clk_override = Input(Bool()) val clk_override = Input(Bool())
val axi = new axi_channels(1) val axi = new axi_channels(TAG)
val ahb = new Bundle{ val ahb = new Bundle{
val sig = Flipped(new ahb_channel()) val sig = Flipped(new ahb_channel())
val hsel = Input(Bool()) val hsel = Input(Bool())
@ -19,7 +19,6 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
}) })
io.axi <> 0.U.asTypeOf(io.axi) io.axi <> 0.U.asTypeOf(io.axi)
val idle:: wr :: rd :: pend :: Nil = Enum(4) val idle:: wr :: rd :: pend :: Nil = Enum(4)
val TAG= 1
val master_wstrb = WireInit(0.U(8.W)) val master_wstrb = WireInit(0.U(8.W))
val buf_state_en = WireInit(false.B) val buf_state_en = WireInit(false.B)

19
src/main/scala/lib/axi4_to_ahb.scala
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@ -4,26 +4,19 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import include._ import include._
trait Config { class axi4_to_ahb_IO(val TAG : Int) extends Bundle {
val TAG = 1
}
class axi4_to_ahb_IO extends Bundle with Config {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val bus_clk_en = Input(Bool()) val bus_clk_en = Input(Bool())
val clk_override = Input(Bool()) val clk_override = Input(Bool())
// AXI-4 signals // AXI-4 signals
val axi = Flipped(new axi_channels(1)) val axi = Flipped(new axi_channels(TAG))
// AHB-Lite signals // AHB-Lite signals
val ahb = new ahb_channel() val ahb = new ahb_channel()
} }
class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncReset {
val io = IO(new axi4_to_ahb_IO(TAG))
class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config {
val io = IO(new axi4_to_ahb_IO)
val buf_rst = WireInit(0.U(1.W)) val buf_rst = WireInit(0.U(1.W))
buf_rst :=0.U buf_rst :=0.U
io.ahb.out.htrans := 0.U io.ahb.out.htrans := 0.U
@ -341,3 +334,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config {
ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode)
ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
} }
object axi4 extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3)))
}

2
src/main/scala/lib/param.scala
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@ -22,7 +22,7 @@ trait param {
val BTB_INDEX3_LO = 0x12 val BTB_INDEX3_LO = 0x12
val BTB_SIZE = 0x200 val BTB_SIZE = 0x200
val BUILD_AHB_LITE = 0x1 val BUILD_AHB_LITE = 0x1
val BUILD_AXI4 = 0x1 val BUILD_AXI4 = 0x0
val BUILD_AXI_NATIVE = 0x0 val BUILD_AXI_NATIVE = 0x0
val BUS_PRTY_DEFAULT = 0x3 val BUS_PRTY_DEFAULT = 0x3
val DATA_ACCESS_ADDR0 = 0x00000000 val DATA_ACCESS_ADDR0 = 0x00000000

17
src/main/scala/quasar.scala
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@ -67,8 +67,10 @@ class quasar_bundle extends Bundle with lib{
val soft_int = Input(Bool()) val soft_int = Input(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
} }
class quasar extends Module with RequireAsyncReset with lib { class quasar extends Module with RequireAsyncReset with lib {
val io = IO (new quasar_bundle) val io = IO (new quasar_bundle)
val ifu = Module(new ifu) val ifu = Module(new ifu)
val dec = Module(new dec) val dec = Module(new dec)
val dbg = Module(new dbg) val dbg = Module(new dbg)
@ -234,15 +236,16 @@ class quasar extends Module with RequireAsyncReset with lib {
io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1 io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2 io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3 io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
io.dmi_reg_rdata := dbg.io.dmi_reg_rdata
// LSU Outputs // LSU Outputs
io.dccm <> lsu.io.dccm io.dccm <> lsu.io.dccm
if(BUILD_AHB_LITE) { if(BUILD_AHB_LITE) {
val sb_axi4_to_ahb = Module(new axi4_to_ahb()) val sb_axi4_to_ahb = Module(new axi4_to_ahb(SB_BUS_TAG))
val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) val ifu_axi4_to_ahb = Module(new axi4_to_ahb(IFU_BUS_TAG))
val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) val lsu_axi4_to_ahb = Module(new axi4_to_ahb(LSU_BUS_TAG))
val dma_ahb_to_axi4 = Module(new ahb_to_axi4()) val dma_ahb_to_axi4 = Module(new ahb_to_axi4(DMA_BUS_TAG))
lsu_axi4_to_ahb.io.scan_mode := io.scan_mode lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en
@ -250,12 +253,12 @@ class quasar extends Module with RequireAsyncReset with lib {
lsu_axi4_to_ahb.io.axi <> lsu.io.axi lsu_axi4_to_ahb.io.axi <> lsu.io.axi
lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb
ifu_axi4_to_ahb.io.scan_mode := io.scan_mode ifu_axi4_to_ahb.io.scan_mode := io.scan_mode
ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en
ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
ifu_axi4_to_ahb.io.axi <> ifu.io.ifu ifu_axi4_to_ahb.io.axi <> ifu.io.ifu
ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb
ifu_axi4_to_ahb.io.axi.b.ready := true.B
sb_axi4_to_ahb.io.scan_mode := io.scan_mode sb_axi4_to_ahb.io.scan_mode := io.scan_mode
sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en
@ -284,7 +287,7 @@ class quasar extends Module with RequireAsyncReset with lib {
ifu.io.ifu <> io.ifu_axi ifu.io.ifu <> io.ifu_axi
lsu.io.axi <> io.lsu_axi lsu.io.axi <> io.lsu_axi
} }
io.dmi_reg_rdata := 0.U
} }
object QUASAR extends App { object QUASAR extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar())) println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))

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