colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

dec update

This commit is contained in:
​Laraib Khan 2020-11-24 13:19:06 +05:00
parent c4d5618ac1
commit 964d3960a2
10 changed files with 4441 additions and 4306 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4847
el2_swerv_wrapper.fir
View File

File diff suppressed because one or more lines are too long

3894
el2_swerv_wrapper.v
View File

File diff suppressed because it is too large Load Diff

2
firrtl_black_box_resource_files.f
View File

@ -1 +1,3 @@
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv

0
src/main/scala/SweRV_Wrapper.scala → src/main/scala/el2_swerv_wrapper.scala
View File

2
src/main/scala/lib/el2_lib.scala
View File

@ -1,7 +1,7 @@
package lib package lib
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import el2_mem.waleed.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int} import el2_mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
trait param { trait param {
val BHT_ADDR_HI = 9 val BHT_ADDR_HI = 9
val BHT_ADDR_LO = 2 val BHT_ADDR_LO = 2

BIN
target/scala-2.12/classes/SWERV_Wrp$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/SWERV_Wrp$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/SWERV_Wrp.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/el2_swerv_wrapper$$anon$1.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/el2_swerv_wrapper.class
View File

Binary file not shown.