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This commit is contained in:
​Laraib Khan 2020-11-24 13:19:06 +05:00
parent c4d5618ac1
commit 964d3960a2
10 changed files with 4441 additions and 4306 deletions
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el2_swerv_wrapper.fir
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el2_swerv_wrapper.v
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firrtl_black_box_resource_files.f
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/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv

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src/main/scala/SweRV_Wrapper.scala → src/main/scala/el2_swerv_wrapper.scala
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src/main/scala/lib/el2_lib.scala
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package lib package lib
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import el2_mem.waleed.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int} import el2_mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
trait param { trait param {
val BHT_ADDR_HI = 9 val BHT_ADDR_HI = 9
val BHT_ADDR_LO = 2 val BHT_ADDR_LO = 2

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