dec update

2020-11-24 13:19:06 +05:00 · 2020-11-24 13:19:06 +05:00 · 964d3960a2
parent c4d5618ac1
commit 964d3960a2
10 changed files with 4441 additions and 4306 deletions
--- a/el2_swerv_wrapper.fir
+++ b/el2_swerv_wrapper.fir
--- a/el2_swerv_wrapper.v
+++ b/el2_swerv_wrapper.v
--- a/firrtl_black_box_resource_files.f
+++ b/firrtl_black_box_resource_files.f
@ -1 +1,3 @@
 /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
+/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
+/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv
--- a/src/main/scala/el2_swerv_wrapper.scala
+++ b/src/main/scala/el2_swerv_wrapper.scala
--- a/src/main/scala/lib/el2_lib.scala
+++ b/src/main/scala/lib/el2_lib.scala
@ -1,7 +1,7 @@
 package lib
 import chisel3._
 import chisel3.util._
-import el2_mem.waleed.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
+import el2_mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
 trait param {
  val BHT_ADDR_HI            = 9
  val BHT_ADDR_LO            = 2
--- a/target/scala-2.12/classes/SWERV_Wrp$.class
+++ b/target/scala-2.12/classes/SWERV_Wrp$.class
--- a/target/scala-2.12/classes/SWERV_Wrp$delayedInit$body.class
+++ b/target/scala-2.12/classes/SWERV_Wrp$delayedInit$body.class
--- a/target/scala-2.12/classes/SWERV_Wrp.class
+++ b/target/scala-2.12/classes/SWERV_Wrp.class
--- a/target/scala-2.12/classes/el2_swerv_wrapper$$anon$1.class
+++ b/target/scala-2.12/classes/el2_swerv_wrapper$$anon$1.class
--- a/target/scala-2.12/classes/el2_swerv_wrapper.class
+++ b/target/scala-2.12/classes/el2_swerv_wrapper.class