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Makefile updated

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waleed-lm 2020-12-21 10:02:58 +05:00
parent a4d822502c
commit 97c713a42d
15 changed files with 5 additions and 473181 deletions
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90
design/dmi_wrapper.sv
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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule

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design/firrtl_black_box_resource_files.f
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/home/waleedbinehsan/Downloads/Quasar/design/gated_latch.sv

14
design/gated_latch.sv
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module gated_latch
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

173
design/mem.sv
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module mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//`endif
//ICCM ports
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1,
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
assign ic_wr_data [0] = ic_wr_data_0;
assign ic_wr_data [1] = ic_wr_data_1;
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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design/quasar.anno.json
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design/quasar.fir
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design/quasar.v
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design/quasar_wrapper.anno.json
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design/quasar_wrapper.fir
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design/quasar_wrapper.v
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design/sbox.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~sbox|sbox>io_s_box_out_valid",
"sources":[
"~sbox|sbox>io_op"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~sbox|sbox>io_inv_s_box_out_bits",
"sources":[
"~sbox|sbox>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~sbox|sbox>io_s_box_out_bits",
"sources":[
"~sbox|sbox>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~sbox|sbox>io_inv_s_box_out_valid",
"sources":[
"~sbox|sbox>io_op"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"sbox"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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design/sbox.fir
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit sbox :
module sbox :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<4>, flip op : UInt<1>, s_box_out : {valid : UInt<1>, bits : UInt<4>}, inv_s_box_out : {valid : UInt<1>, bits : UInt<4>}}
node _T = eq(io.op, UInt<1>("h00")) @[quasar_wrapper.scala 183:32]
io.s_box_out.valid <= _T @[quasar_wrapper.scala 183:29]
io.inv_s_box_out.valid <= io.op @[quasar_wrapper.scala 184:29]
node _T_1 = eq(io.in, UInt<1>("h00")) @[quasar_wrapper.scala 185:74]
node _T_2 = bits(_T_1, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_3 = eq(io.in, UInt<1>("h01")) @[quasar_wrapper.scala 185:74]
node _T_4 = bits(_T_3, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_5 = eq(io.in, UInt<2>("h02")) @[quasar_wrapper.scala 185:74]
node _T_6 = bits(_T_5, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_7 = eq(io.in, UInt<2>("h03")) @[quasar_wrapper.scala 185:74]
node _T_8 = bits(_T_7, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_9 = eq(io.in, UInt<3>("h04")) @[quasar_wrapper.scala 185:74]
node _T_10 = bits(_T_9, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_11 = eq(io.in, UInt<3>("h05")) @[quasar_wrapper.scala 185:74]
node _T_12 = bits(_T_11, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_13 = eq(io.in, UInt<3>("h06")) @[quasar_wrapper.scala 185:74]
node _T_14 = bits(_T_13, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_15 = eq(io.in, UInt<3>("h07")) @[quasar_wrapper.scala 185:74]
node _T_16 = bits(_T_15, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_17 = eq(io.in, UInt<4>("h08")) @[quasar_wrapper.scala 185:74]
node _T_18 = bits(_T_17, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_19 = eq(io.in, UInt<4>("h09")) @[quasar_wrapper.scala 185:74]
node _T_20 = bits(_T_19, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_21 = eq(io.in, UInt<4>("h0a")) @[quasar_wrapper.scala 185:74]
node _T_22 = bits(_T_21, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_23 = eq(io.in, UInt<4>("h0b")) @[quasar_wrapper.scala 185:74]
node _T_24 = bits(_T_23, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_25 = eq(io.in, UInt<4>("h0c")) @[quasar_wrapper.scala 185:74]
node _T_26 = bits(_T_25, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_27 = eq(io.in, UInt<4>("h0d")) @[quasar_wrapper.scala 185:74]
node _T_28 = bits(_T_27, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_29 = eq(io.in, UInt<4>("h0e")) @[quasar_wrapper.scala 185:74]
node _T_30 = bits(_T_29, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_31 = eq(io.in, UInt<4>("h0f")) @[quasar_wrapper.scala 185:74]
node _T_32 = bits(_T_31, 0, 0) @[quasar_wrapper.scala 185:89]
node _T_33 = mux(_T_2, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_34 = mux(_T_4, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_35 = mux(_T_6, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_36 = mux(_T_8, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_37 = mux(_T_10, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_38 = mux(_T_12, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_39 = mux(_T_14, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_40 = mux(_T_16, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_41 = mux(_T_18, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_42 = mux(_T_20, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_43 = mux(_T_22, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_44 = mux(_T_24, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_45 = mux(_T_26, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_46 = mux(_T_28, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_47 = mux(_T_30, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_48 = mux(_T_32, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_49 = or(_T_33, _T_34) @[Mux.scala 27:72]
node _T_50 = or(_T_49, _T_35) @[Mux.scala 27:72]
node _T_51 = or(_T_50, _T_36) @[Mux.scala 27:72]
node _T_52 = or(_T_51, _T_37) @[Mux.scala 27:72]
node _T_53 = or(_T_52, _T_38) @[Mux.scala 27:72]
node _T_54 = or(_T_53, _T_39) @[Mux.scala 27:72]
node _T_55 = or(_T_54, _T_40) @[Mux.scala 27:72]
node _T_56 = or(_T_55, _T_41) @[Mux.scala 27:72]
node _T_57 = or(_T_56, _T_42) @[Mux.scala 27:72]
node _T_58 = or(_T_57, _T_43) @[Mux.scala 27:72]
node _T_59 = or(_T_58, _T_44) @[Mux.scala 27:72]
node _T_60 = or(_T_59, _T_45) @[Mux.scala 27:72]
node _T_61 = or(_T_60, _T_46) @[Mux.scala 27:72]
node _T_62 = or(_T_61, _T_47) @[Mux.scala 27:72]
node _T_63 = or(_T_62, _T_48) @[Mux.scala 27:72]
wire _T_64 : UInt<4> @[Mux.scala 27:72]
_T_64 <= _T_63 @[Mux.scala 27:72]
io.s_box_out.bits <= _T_64 @[quasar_wrapper.scala 185:21]
node _T_65 = eq(io.in, UInt<1>("h00")) @[quasar_wrapper.scala 186:78]
node _T_66 = bits(_T_65, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_67 = eq(io.in, UInt<1>("h01")) @[quasar_wrapper.scala 186:78]
node _T_68 = bits(_T_67, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_69 = eq(io.in, UInt<2>("h02")) @[quasar_wrapper.scala 186:78]
node _T_70 = bits(_T_69, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_71 = eq(io.in, UInt<2>("h03")) @[quasar_wrapper.scala 186:78]
node _T_72 = bits(_T_71, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_73 = eq(io.in, UInt<3>("h04")) @[quasar_wrapper.scala 186:78]
node _T_74 = bits(_T_73, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_75 = eq(io.in, UInt<3>("h05")) @[quasar_wrapper.scala 186:78]
node _T_76 = bits(_T_75, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_77 = eq(io.in, UInt<3>("h06")) @[quasar_wrapper.scala 186:78]
node _T_78 = bits(_T_77, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_79 = eq(io.in, UInt<3>("h07")) @[quasar_wrapper.scala 186:78]
node _T_80 = bits(_T_79, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_81 = eq(io.in, UInt<4>("h08")) @[quasar_wrapper.scala 186:78]
node _T_82 = bits(_T_81, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_83 = eq(io.in, UInt<4>("h09")) @[quasar_wrapper.scala 186:78]
node _T_84 = bits(_T_83, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_85 = eq(io.in, UInt<4>("h0a")) @[quasar_wrapper.scala 186:78]
node _T_86 = bits(_T_85, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_87 = eq(io.in, UInt<4>("h0b")) @[quasar_wrapper.scala 186:78]
node _T_88 = bits(_T_87, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_89 = eq(io.in, UInt<4>("h0c")) @[quasar_wrapper.scala 186:78]
node _T_90 = bits(_T_89, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_91 = eq(io.in, UInt<4>("h0d")) @[quasar_wrapper.scala 186:78]
node _T_92 = bits(_T_91, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_93 = eq(io.in, UInt<4>("h0e")) @[quasar_wrapper.scala 186:78]
node _T_94 = bits(_T_93, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_95 = eq(io.in, UInt<4>("h0f")) @[quasar_wrapper.scala 186:78]
node _T_96 = bits(_T_95, 0, 0) @[quasar_wrapper.scala 186:93]
node _T_97 = mux(_T_66, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_98 = mux(_T_68, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_99 = mux(_T_70, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_100 = mux(_T_72, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_101 = mux(_T_74, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_102 = mux(_T_76, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_103 = mux(_T_78, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_104 = mux(_T_80, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_105 = mux(_T_82, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_106 = mux(_T_84, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_107 = mux(_T_86, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_108 = mux(_T_88, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_109 = mux(_T_90, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_110 = mux(_T_92, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_111 = mux(_T_94, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_112 = mux(_T_96, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_113 = or(_T_97, _T_98) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_99) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_100) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_101) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_102) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_103) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_104) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_105) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_106) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_107) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_108) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_109) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_110) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_111) @[Mux.scala 27:72]
node _T_127 = or(_T_126, _T_112) @[Mux.scala 27:72]
wire _T_128 : UInt<4> @[Mux.scala 27:72]
_T_128 <= _T_127 @[Mux.scala 27:72]
io.inv_s_box_out.bits <= _T_128 @[quasar_wrapper.scala 186:25]

98
design/sbox.v
View File

@ -1,98 +0,0 @@
module sbox(
input clock,
input reset,
input [3:0] io_in,
input io_op,
output io_s_box_out_valid,
output [3:0] io_s_box_out_bits,
output io_inv_s_box_out_valid,
output [3:0] io_inv_s_box_out_bits
);
wire _T_1 = io_in == 4'h0; // @[quasar_wrapper.scala 185:74]
wire _T_3 = io_in == 4'h1; // @[quasar_wrapper.scala 185:74]
wire _T_5 = io_in == 4'h2; // @[quasar_wrapper.scala 185:74]
wire _T_7 = io_in == 4'h3; // @[quasar_wrapper.scala 185:74]
wire _T_9 = io_in == 4'h4; // @[quasar_wrapper.scala 185:74]
wire _T_11 = io_in == 4'h5; // @[quasar_wrapper.scala 185:74]
wire _T_13 = io_in == 4'h6; // @[quasar_wrapper.scala 185:74]
wire _T_15 = io_in == 4'h7; // @[quasar_wrapper.scala 185:74]
wire _T_17 = io_in == 4'h8; // @[quasar_wrapper.scala 185:74]
wire _T_19 = io_in == 4'h9; // @[quasar_wrapper.scala 185:74]
wire _T_21 = io_in == 4'ha; // @[quasar_wrapper.scala 185:74]
wire _T_23 = io_in == 4'hb; // @[quasar_wrapper.scala 185:74]
wire _T_25 = io_in == 4'hc; // @[quasar_wrapper.scala 185:74]
wire _T_27 = io_in == 4'hd; // @[quasar_wrapper.scala 185:74]
wire _T_29 = io_in == 4'he; // @[quasar_wrapper.scala 185:74]
wire _T_31 = io_in == 4'hf; // @[quasar_wrapper.scala 185:74]
wire [2:0] _T_33 = _T_1 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [1:0] _T_34 = _T_3 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [3:0] _T_35 = _T_5 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_36 = _T_7 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_38 = _T_11 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_39 = _T_13 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [2:0] _T_41 = _T_17 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_42 = _T_19 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_43 = _T_21 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [2:0] _T_44 = _T_23 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_45 = _T_25 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [1:0] _T_46 = _T_27 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [3:0] _T_47 = _T_29 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_48 = _T_31 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [2:0] _GEN_0 = {{1'd0}, _T_34}; // @[Mux.scala 27:72]
wire [2:0] _T_49 = _T_33 | _GEN_0; // @[Mux.scala 27:72]
wire [3:0] _GEN_1 = {{1'd0}, _T_49}; // @[Mux.scala 27:72]
wire [3:0] _T_50 = _GEN_1 | _T_35; // @[Mux.scala 27:72]
wire [3:0] _T_51 = _T_50 | _T_36; // @[Mux.scala 27:72]
wire [3:0] _T_53 = _T_51 | _T_38; // @[Mux.scala 27:72]
wire [3:0] _T_54 = _T_53 | _T_39; // @[Mux.scala 27:72]
wire [3:0] _GEN_2 = {{3'd0}, _T_15}; // @[Mux.scala 27:72]
wire [3:0] _T_55 = _T_54 | _GEN_2; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_41}; // @[Mux.scala 27:72]
wire [3:0] _T_56 = _T_55 | _GEN_3; // @[Mux.scala 27:72]
wire [3:0] _T_57 = _T_56 | _T_42; // @[Mux.scala 27:72]
wire [3:0] _T_58 = _T_57 | _T_43; // @[Mux.scala 27:72]
wire [3:0] _GEN_4 = {{1'd0}, _T_44}; // @[Mux.scala 27:72]
wire [3:0] _T_59 = _T_58 | _GEN_4; // @[Mux.scala 27:72]
wire [3:0] _GEN_5 = {{1'd0}, _T_45}; // @[Mux.scala 27:72]
wire [3:0] _T_60 = _T_59 | _GEN_5; // @[Mux.scala 27:72]
wire [3:0] _GEN_6 = {{2'd0}, _T_46}; // @[Mux.scala 27:72]
wire [3:0] _T_61 = _T_60 | _GEN_6; // @[Mux.scala 27:72]
wire [3:0] _T_62 = _T_61 | _T_47; // @[Mux.scala 27:72]
wire [2:0] _T_97 = _T_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_98 = _T_3 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_99 = _T_5 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_101 = _T_9 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_102 = _T_11 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _T_13 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_17 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [1:0] _T_106 = _T_19 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_107 = _T_21 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_23 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_25 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [2:0] _T_110 = _T_27 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [1:0] _T_111 = _T_29 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [3:0] _T_112 = _T_31 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [2:0] _T_113 = _T_97 | _T_98; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_113}; // @[Mux.scala 27:72]
wire [3:0] _T_114 = _GEN_7 | _T_99; // @[Mux.scala 27:72]
wire [3:0] _GEN_8 = {{3'd0}, _T_7}; // @[Mux.scala 27:72]
wire [3:0] _T_115 = _T_114 | _GEN_8; // @[Mux.scala 27:72]
wire [3:0] _T_116 = _T_115 | _T_101; // @[Mux.scala 27:72]
wire [3:0] _T_117 = _T_116 | _T_102; // @[Mux.scala 27:72]
wire [3:0] _T_118 = _T_117 | _T_103; // @[Mux.scala 27:72]
wire [3:0] _T_120 = _T_118 | _T_105; // @[Mux.scala 27:72]
wire [3:0] _GEN_9 = {{2'd0}, _T_106}; // @[Mux.scala 27:72]
wire [3:0] _T_121 = _T_120 | _GEN_9; // @[Mux.scala 27:72]
wire [3:0] _GEN_10 = {{1'd0}, _T_107}; // @[Mux.scala 27:72]
wire [3:0] _T_122 = _T_121 | _GEN_10; // @[Mux.scala 27:72]
wire [3:0] _T_123 = _T_122 | _T_108; // @[Mux.scala 27:72]
wire [3:0] _T_124 = _T_123 | _T_109; // @[Mux.scala 27:72]
wire [3:0] _GEN_11 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [3:0] _T_125 = _T_124 | _GEN_11; // @[Mux.scala 27:72]
wire [3:0] _GEN_12 = {{2'd0}, _T_111}; // @[Mux.scala 27:72]
wire [3:0] _T_126 = _T_125 | _GEN_12; // @[Mux.scala 27:72]
assign io_s_box_out_valid = ~io_op; // @[quasar_wrapper.scala 183:29]
assign io_s_box_out_bits = _T_62 | _T_48; // @[quasar_wrapper.scala 185:21]
assign io_inv_s_box_out_valid = io_op; // @[quasar_wrapper.scala 184:29]
assign io_inv_s_box_out_bits = _T_126 | _T_112; // @[quasar_wrapper.scala 186:25]
endmodule

83697
generated_rtl/quasar_wrapper.sv
View File

File diff suppressed because it is too large Load Diff

5
tools/Makefile
View File

@ -136,6 +136,11 @@ help:
clean:
rm -rvf ${RV_ROOT}/design/*.v
rm -rvf ${RV_ROOT}/design/*.sv
rm -rvf ${RV_ROOT}/design/*.f
rm -rvf ${RV_ROOT}/design/*.json
rm -rvf ${RV_ROOT}/design/*.fir
rm -rvf ${RV_ROOT}/verif/sim/*.log
rm -rvf ${RV_ROOT}/verif/sim/*.s
rm -rvf ${RV_ROOT}/verif/sim/*.hex