LSU & EXU added

This commit is contained in:
​Laraib Khan 2020-12-16 17:29:40 +05:00
parent 09739661c2
commit 9a6d820227
18 changed files with 5921 additions and 5920 deletions

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -232,3 +232,7 @@ class exu extends Module with lib with RequireAsyncReset{
io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d)
io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
} }
object exu_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
}

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@ -109,7 +109,6 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe //there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe

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@ -183,6 +183,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)),
(io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)),
(io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1))))
val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r,
(io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U),
(io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)),

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@ -3,8 +3,6 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import lib._ import lib._
import include._ import include._
import snapshot._
import ifu._
class lsu_bus_intf extends Module with RequireAsyncReset with lib { class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val io = IO (new Bundle { val io = IO (new Bundle {

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@ -4,7 +4,6 @@ import chisel3.experimental.chiselName
import chisel3.util._ import chisel3.util._
import lib._ import lib._
import include._ import include._
import snapshot._
@chiselName @chiselName
class lsu_clkdomain extends Module with RequireAsyncReset with lib{ class lsu_clkdomain extends Module with RequireAsyncReset with lib{

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