LSU & EXU added

src/main/scala/exu/exu.scala

@@ -231,4 +231,8 @@ class exu extends Module with lib with RequireAsyncReset{
   io.exu_bp.exu_mp_eghr                   :=  final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write
   io.exu_flush_path_final		 	 := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r,  i0_flush_path_d)
   io.dec_exu.tlu_exu.exu_npc_r			 		 := Mux(i0_pred_correct_upper_r===1.U,  pred_correct_npc_r, i0_flush_path_upper_r)
-}
+}
+
+object exu_main extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
+}

src/main/scala/exu/exu_alu_ctl.scala

@@ -109,7 +109,6 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
   val target_mispredict   =  io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
 
   io.flush_upper_out     :=   (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x   & !io.dec_tlu_flush_lower_r
-  //there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
   io.flush_final_out     := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) |  io.dec_tlu_flush_lower_r
   //there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
 

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -183,6 +183,7 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
     (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)),
     (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)),
     (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1))))
+
   val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r,
     (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U),
     (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)),

src/main/scala/lsu/lsu_bus_intf.scala

@@ -3,8 +3,6 @@ import chisel3._
 import chisel3.util._
 import lib._
 import include._
-import snapshot._
-import ifu._
 
 class  lsu_bus_intf extends Module with RequireAsyncReset with lib {
   val io = IO (new Bundle {

src/main/scala/lsu/lsu_clkdomain.scala

@@ -4,7 +4,6 @@ import chisel3.experimental.chiselName
 import chisel3.util._
 import lib._
 import include._
-import snapshot._
 
 @chiselName
 class lsu_clkdomain extends Module  with RequireAsyncReset with lib{