I$ disable error fixed
This commit is contained in:
waleed-lm
parent
b0fee672bc
commit
9aab86c2aa
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@ -113,8 +113,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
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Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
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Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
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Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
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Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
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Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
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Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
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miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
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}
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is (crit_wrd_rdy_C){ // Critical word hit but not complete, its going to be available in next cycle
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@ -159,7 +159,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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miss_pending := miss_state =/= idle_C
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val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
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val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
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!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
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!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
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(miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
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val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
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@ -200,12 +200,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
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val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
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val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
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Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
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Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
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Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
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Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
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val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
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val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
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val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))),
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Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
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Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
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val scnd_miss_req_q = WireInit(Bool(), false.B)
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val reset_ic_ff = WireInit(Bool(), false.B)
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val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
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@ -237,7 +237,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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val reset_tag_valid_for_miss = WireInit(Bool(), false.B)
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val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
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val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
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!sel_mb_addr -> io.ifc_fetch_addr_bf))
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!sel_mb_addr -> io.ifc_fetch_addr_bf))
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val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B)
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val sel_mb_status_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss
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val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f)
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@ -286,9 +286,9 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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val final_data_out1 = VecInit(io.ic.rd_data, ic_byp_data_only_new, io.ic.rd_data, ic_byp_data_only_new)
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val final_data_out2 = VecInit(1.U, io.iccm.rd_data, 1.U, 1.U)
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val ic_final_data = if(ICCM_ICACHE) Fill(64, sel_byp_data | sel_iccm_data | sel_ic_data) & io.ic.rd_data else
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if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else
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if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else
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if (ICACHE_ONLY) Fill(64, sel_byp_data | sel_ic_data) & io.ic.rd_data else
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if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
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if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
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val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm.rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
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else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
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val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
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@ -313,8 +313,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W)))
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for(i<- 0 until ICACHE_NUM_BEATS){
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val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
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ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
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ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
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ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
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ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
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val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
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val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f)))
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ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
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@ -329,16 +329,16 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U
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val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i)))
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val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) |
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(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
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(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
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(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
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(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
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(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
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(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
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(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
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(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
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val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U)
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val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
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( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
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(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
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( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
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(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
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ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
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val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0)
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val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U)
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@ -348,12 +348,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U)
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val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i)))
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val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i)))
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ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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(ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) |
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ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0))))
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ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
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(ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) |
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ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0))))
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val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool,
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Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))),
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Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0)))))
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@ -458,8 +458,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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}
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err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
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bus_ifu_bus_clk_en := io.ifu_bus_clk_en
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val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
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val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
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val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
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val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
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val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
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scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
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val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)}
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@ -535,8 +535,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
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// Request Address Count
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val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2),
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Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
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Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
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Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
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Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
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bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
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// Command beat Count
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val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
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@ -630,115 +630,110 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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((miss_state===miss_wait_C) & !miss_state_en) |
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((miss_state===crit_wrd_rdy_C) & !miss_state_en) |
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((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) |
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(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
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(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
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val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
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io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
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io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
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reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)}
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// I$ status and P-LRU
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val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
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val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
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ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
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val ifu_status_wr_addr_ff = withClock(io.free_clk) {
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RegNext(ifu_status_wr_addr_w_debug, 0.U)
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}
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val way_status_wr_en = WireInit(Bool(), false.B)
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val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array)
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val way_status_wr_en_ff = withClock(io.free_clk) {
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RegNext(way_status_wr_en_w_debug, false.B)
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}
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val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
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val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array,
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if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new)
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val way_status_new_ff = withClock(io.free_clk) {
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RegNext(way_status_new_w_debug, 0.U)
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}
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val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
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val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
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val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
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for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
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way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
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// I$ status and P-LRU
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||||
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
|
||||
val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
|
||||
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_status_wr_addr_w_debug, 0.U)
|
||||
}
|
||||
val way_status_wr_en = WireInit(Bool(), false.B)
|
||||
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array)
|
||||
val way_status_wr_en_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_wr_en_w_debug, false.B)
|
||||
}
|
||||
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array,
|
||||
if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new)
|
||||
val way_status_new_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_new_w_debug, 0.U)
|
||||
}
|
||||
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
|
||||
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
|
||||
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
|
||||
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
|
||||
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
|
||||
val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
|
||||
// io.test_way_status_out := test_way_status_out
|
||||
// io.test_way_status_out := test_way_status_out
|
||||
val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
|
||||
//io.test_way_status_clken := test_way_status_clken
|
||||
way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
|
||||
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array,
|
||||
io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
|
||||
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
|
||||
}
|
||||
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
|
||||
val ifu_tag_wren_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_tag_wren_w_debug, 0.U)
|
||||
}
|
||||
val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid)
|
||||
val ic_valid_ff = withClock(io.free_clk) {
|
||||
RegNext(ic_valid_w_debug, false.B)
|
||||
}
|
||||
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
|
||||
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
|
||||
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
|
||||
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
|
||||
reset_all_tags).reverse.reduce(Cat(_, _)))
|
||||
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
|
||||
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
|
||||
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
|
||||
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
|
||||
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array,
|
||||
io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
|
||||
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
|
||||
}
|
||||
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
|
||||
val ifu_tag_wren_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_tag_wren_w_debug, 0.U)
|
||||
}
|
||||
val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid)
|
||||
val ic_valid_ff = withClock(io.free_clk) {
|
||||
RegNext(ic_valid_w_debug, false.B)
|
||||
}
|
||||
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
|
||||
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
|
||||
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
|
||||
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
|
||||
reset_all_tags).reverse.reduce(Cat(_, _)))
|
||||
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
|
||||
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
|
||||
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
|
||||
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
|
||||
|
||||
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
|
||||
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
|
||||
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
|
||||
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
|
||||
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
|
||||
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
|
||||
|
||||
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
|
||||
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
|
||||
val ic_tag_valid_unq = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
|
||||
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
|
||||
else 0.U(ICACHE_NUM_WAYS.W)
|
||||
// Making sudo LRU
|
||||
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
if (ICACHE_NUM_WAYS == 4) {
|
||||
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
|
||||
|
||||
// Making sudo LRU
|
||||
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
if (ICACHE_NUM_WAYS == 4) {
|
||||
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
|
||||
way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
|
||||
|
||||
way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
|
||||
|
||||
way_status_rep_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
|
||||
}
|
||||
else {
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
|
||||
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
|
||||
way_status_hit_new := io.ic.rd_hit(0)
|
||||
way_status_rep_new := replace_way_mb_any(0)
|
||||
}
|
||||
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
|
||||
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
|
||||
val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
|
||||
|
||||
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
|
||||
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
|
||||
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
|
||||
way_status_rep_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
|
||||
}
|
||||
else {
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
|
||||
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
|
||||
way_status_hit_new := io.ic.rd_hit(0)
|
||||
way_status_rep_new := replace_way_mb_any(0)
|
||||
}
|
||||
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
|
||||
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
|
||||
val bus_wren = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
|
||||
else (0 until ICACHE_NUM_WAYS).map(i => 0.U)
|
||||
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
|
||||
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
|
||||
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
|
||||
|
||||
bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
|
||||
if(!ICACHE_ENABLE){
|
||||
for(i<- 0 until ICACHE_NUM_WAYS){
|
||||
|
||||
bus_wren(i) := 0.U
|
||||
}
|
||||
ic_tag_valid_unq := 0.U
|
||||
way_status := 0.U
|
||||
replace_way_mb_any := 0.U
|
||||
replace_way_mb_any := (0 until ICACHE_NUM_WAYS).map(i =>0.U)
|
||||
way_status_hit_new := 0.U
|
||||
way_status_rep_new := 0.U
|
||||
way_status_new := 0.U
|
||||
|
|
@ -770,16 +765,17 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)}
|
||||
// Memory protection each access enable with its Mask
|
||||
val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) |
|
||||
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
|
||||
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |
|
||||
(INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) |
|
||||
(INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) |
|
||||
(INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) |
|
||||
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
|
||||
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
|
||||
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
|
||||
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
|
||||
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |
|
||||
(INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) |
|
||||
(INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) |
|
||||
(INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) |
|
||||
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
|
||||
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
|
||||
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
|
||||
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
|
||||
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
|
||||
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
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}
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}
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@ -0,0 +1,39 @@
|
|||
import re
|
||||
infile= open("./configs/snapshots/default/param.vh",'r')
|
||||
params = []
|
||||
lines = infile.readlines()
|
||||
for line in lines:
|
||||
patern_1=re.match(r'(.*):(.*)' , line )
|
||||
if ((patern_1)):
|
||||
lesson_group2=patern_1.group(1)
|
||||
splittedl = lesson_group2.split()
|
||||
split_data=''
|
||||
for x in splittedl:
|
||||
split_data=split_data+" "+x
|
||||
lesson_group3=patern_1.group(2)
|
||||
splittedl2 = lesson_group3.split()
|
||||
split_data2=''
|
||||
for x in splittedl2:
|
||||
split_data2=split_data2+" "+x
|
||||
else:
|
||||
continue
|
||||
params.append(split_data+" = " + split_data2)
|
||||
|
||||
#writing to a file
|
||||
filename2 = "./verif/LEC/LEC_RTL/Golden_RTL/parameter.sv"
|
||||
#w+ tells python we are opening the file to write into it
|
||||
outfile = open(filename2, 'w+')
|
||||
outfile.write("#(parameter"+"\n")
|
||||
outfile.write("\t"+" AWIDTH = 7,"+"\n")
|
||||
outfile.write("\t"+" TAG = 1'h1,"+"\n")
|
||||
for x in params:
|
||||
if ("DCCM_INDEX_BITS") in x:
|
||||
y="// " + "DCCM_INDEX_BITS = 4'hC ,"
|
||||
outfile.write("\t"+str(y)+"\n")
|
||||
else:
|
||||
outfile.write("\t"+str(x)+"\n")
|
||||
outfile.write(")"+"\n")
|
||||
outfile.close() #Close file
|
||||
print("Done...!")
|
||||
|
||||
|
||||
Loading…
Reference in New Issue