I$ disable error fixed
This commit is contained in:
waleed-lm
parent
b0fee672bc
commit
9aab86c2aa
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@ -692,9 +692,9 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
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ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
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((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
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((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
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val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
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val ic_tag_valid_unq = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
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Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
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Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
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else 0.U(ICACHE_NUM_WAYS.W)
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// Making sudo LRU
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// Making sudo LRU
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val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
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val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
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if (ICACHE_NUM_WAYS == 4) {
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if (ICACHE_NUM_WAYS == 4) {
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@ -724,21 +724,16 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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}
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}
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way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
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way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
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way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
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way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
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val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
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val bus_wren = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
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else (0 until ICACHE_NUM_WAYS).map(i => 0.U)
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val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
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val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
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val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
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val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
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ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
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ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
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bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
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bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
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if(!ICACHE_ENABLE){
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if(!ICACHE_ENABLE){
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for(i<- 0 until ICACHE_NUM_WAYS){
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bus_wren(i) := 0.U
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}
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ic_tag_valid_unq := 0.U
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way_status := 0.U
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way_status := 0.U
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replace_way_mb_any := 0.U
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replace_way_mb_any := (0 until ICACHE_NUM_WAYS).map(i =>0.U)
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way_status_hit_new := 0.U
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way_status_hit_new := 0.U
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way_status_rep_new := 0.U
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way_status_rep_new := 0.U
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way_status_new := 0.U
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way_status_new := 0.U
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@ -783,3 +778,4 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
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ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
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ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
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}
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}
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@ -0,0 +1,39 @@
|
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|
import re
|
||||||
|
infile= open("./configs/snapshots/default/param.vh",'r')
|
||||||
|
params = []
|
||||||
|
lines = infile.readlines()
|
||||||
|
for line in lines:
|
||||||
|
patern_1=re.match(r'(.*):(.*)' , line )
|
||||||
|
if ((patern_1)):
|
||||||
|
lesson_group2=patern_1.group(1)
|
||||||
|
splittedl = lesson_group2.split()
|
||||||
|
split_data=''
|
||||||
|
for x in splittedl:
|
||||||
|
split_data=split_data+" "+x
|
||||||
|
lesson_group3=patern_1.group(2)
|
||||||
|
splittedl2 = lesson_group3.split()
|
||||||
|
split_data2=''
|
||||||
|
for x in splittedl2:
|
||||||
|
split_data2=split_data2+" "+x
|
||||||
|
else:
|
||||||
|
continue
|
||||||
|
params.append(split_data+" = " + split_data2)
|
||||||
|
|
||||||
|
#writing to a file
|
||||||
|
filename2 = "./verif/LEC/LEC_RTL/Golden_RTL/parameter.sv"
|
||||||
|
#w+ tells python we are opening the file to write into it
|
||||||
|
outfile = open(filename2, 'w+')
|
||||||
|
outfile.write("#(parameter"+"\n")
|
||||||
|
outfile.write("\t"+" AWIDTH = 7,"+"\n")
|
||||||
|
outfile.write("\t"+" TAG = 1'h1,"+"\n")
|
||||||
|
for x in params:
|
||||||
|
if ("DCCM_INDEX_BITS") in x:
|
||||||
|
y="// " + "DCCM_INDEX_BITS = 4'hC ,"
|
||||||
|
outfile.write("\t"+str(y)+"\n")
|
||||||
|
else:
|
||||||
|
outfile.write("\t"+str(x)+"\n")
|
||||||
|
outfile.write(")"+"\n")
|
||||||
|
outfile.close() #Close file
|
||||||
|
print("Done...!")
|
||||||
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue