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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-01 18:00:07 +05:00
parent 6c3eda7075
commit 9ae43ddb94
6 changed files with 953 additions and 953 deletions
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axi4_to_ahb.fir
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axi4_to_ahb.v
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@ -132,31 +132,31 @@ module axi4_to_ahb(
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 463:12] wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 462:12]
reg [2:0] buf_state; // @[axi4_to_ahb.scala 68:45] reg [2:0] buf_state; // @[axi4_to_ahb.scala 68:45]
wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30] wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 88:21 axi4_to_ahb.scala 220:11] wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 88:21 axi4_to_ahb.scala 219:11]
reg wrbuf_vld; // @[axi4_to_ahb.scala 381:48] reg wrbuf_vld; // @[axi4_to_ahb.scala 380:48]
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 382:48] reg wrbuf_data_vld; // @[axi4_to_ahb.scala 381:48]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 197:27] wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 196:27]
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 198:30] wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 197:30]
wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30] wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hready_q; // @[axi4_to_ahb.scala 442:12] reg ahb_hready_q; // @[axi4_to_ahb.scala 441:12]
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 445:12] reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 444:12]
wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 260:58] wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 259:58]
wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 260:36] wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 259:36]
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 464:17] wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 463:17]
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 448:12] reg ahb_hwrite_q; // @[axi4_to_ahb.scala 447:12]
wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 260:72] wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 259:72]
wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 260:70] wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 259:70]
wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30] wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hresp_q; // @[axi4_to_ahb.scala 451:12] reg ahb_hresp_q; // @[axi4_to_ahb.scala 450:12]
wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 274:37] wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 273:37]
wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30] wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 306:33] wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 305:33]
wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 306:48] wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 305:48]
wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30]
wire _GEN_15 = _T_279 & _T_190; // @[Conditional.scala 39:67] wire _GEN_15 = _T_279 & _T_190; // @[Conditional.scala 39:67]
wire _GEN_19 = _T_186 ? _T_190 : _GEN_15; // @[Conditional.scala 39:67] wire _GEN_19 = _T_186 ? _T_190 : _GEN_15; // @[Conditional.scala 39:67]
@ -165,11 +165,11 @@ module axi4_to_ahb(
wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
reg cmd_doneQ; // @[axi4_to_ahb.scala 433:12] reg cmd_doneQ; // @[axi4_to_ahb.scala 432:12]
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 316:34] wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 315:34]
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 316:50] wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 315:50]
wire _T_441 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire _T_441 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 215:32] wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 214:32]
wire _GEN_1 = _T_441 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_1 = _T_441 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
@ -178,9 +178,9 @@ module axi4_to_ahb(
wire _GEN_69 = _T_134 ? _T_154 : _GEN_51; // @[Conditional.scala 39:67] wire _GEN_69 = _T_134 ? _T_154 : _GEN_51; // @[Conditional.scala 39:67]
wire _GEN_83 = _T_99 ? _T_109 : _GEN_69; // @[Conditional.scala 39:67] wire _GEN_83 = _T_99 ? _T_109 : _GEN_69; // @[Conditional.scala 39:67]
wire buf_state_en = _T_47 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] wire buf_state_en = _T_47 ? master_valid : _GEN_83; // @[Conditional.scala 40:58]
wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 200:20] wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 199:20]
wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 200:14] wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 199:14]
wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 245:41] wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 244:41]
wire _GEN_8 = _T_279 & _T_49; // @[Conditional.scala 39:67] wire _GEN_8 = _T_279 & _T_49; // @[Conditional.scala 39:67]
wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_184 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] wire _GEN_46 = _T_184 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
@ -188,19 +188,19 @@ module axi4_to_ahb(
wire _GEN_81 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_81 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
wire buf_write_in = _T_47 ? _T_49 : _GEN_97; // @[Conditional.scala 40:58] wire buf_write_in = _T_47 ? _T_49 : _GEN_97; // @[Conditional.scala 40:58]
wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 246:26] wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 245:26]
wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 259:61] wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 258:61]
wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 259:41] wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 258:41]
wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 259:26] wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 258:26]
wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 263:174] wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 262:174]
wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 263:88] wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 262:88]
wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 271:39] wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 270:39]
wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 271:37] wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 270:37]
wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 271:70] wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 270:70]
wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 271:55] wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 270:55]
wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 271:53] wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 270:53]
wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 317:66] wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 316:66]
wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 317:81] wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 316:81]
wire _GEN_4 = _T_279 & _T_286; // @[Conditional.scala 39:67] wire _GEN_4 = _T_279 & _T_286; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_186 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_26 = _T_186 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_184 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] wire _GEN_45 = _T_184 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
@ -208,15 +208,15 @@ module axi4_to_ahb(
wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67] wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67]
wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58] wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58]
wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 273:82] wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 272:82]
wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 273:97] wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 272:97]
wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 273:67] wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 272:67]
wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 273:26] wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 272:26]
wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 318:42] wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 317:42]
wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 318:40] wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 317:40]
wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 318:119] wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 317:119]
wire [2:0] _T_295 = _T_147 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 318:75] wire [2:0] _T_295 = _T_147 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 317:75]
wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 318:26] wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 317:26]
wire [2:0] _GEN_5 = _T_279 ? _T_296 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_5 = _T_279 ? _T_296 : 3'h0; // @[Conditional.scala 39:67]
wire [2:0] _GEN_18 = _T_186 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_186 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67]
wire [2:0] _GEN_34 = _T_184 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_184 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67]
@ -227,14 +227,14 @@ module axi4_to_ahb(
wire [2:0] _T_1 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 68:49] wire [2:0] _T_1 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 68:49]
reg wrbuf_tag; // @[Reg.scala 27:20] reg wrbuf_tag; // @[Reg.scala 27:20]
reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16]
wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 201:21] wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 200:21]
reg [2:0] wrbuf_size; // @[Reg.scala 27:20] reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 202:21] wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 201:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 278:39] wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 277:39]
wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 327:55] wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 326:55]
wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 327:39] wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 326:39]
wire _GEN_14 = _T_279 ? _T_360 : _T_441; // @[Conditional.scala 39:67] wire _GEN_14 = _T_279 ? _T_360 : _T_441; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
@ -242,29 +242,29 @@ module axi4_to_ahb(
wire _GEN_73 = _T_134 ? _T_156 : _GEN_52; // @[Conditional.scala 39:67] wire _GEN_73 = _T_134 ? _T_156 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 207:32] wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 206:32]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 462:12] wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 461:12]
reg slvbuf_write; // @[Reg.scala 27:20] reg slvbuf_write; // @[Reg.scala 27:20]
wire [1:0] _T_594 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 364:23] wire [1:0] _T_594 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 363:23]
reg slvbuf_error; // @[Reg.scala 27:20] reg slvbuf_error; // @[Reg.scala 27:20]
wire [1:0] _T_596 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_596 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_597 = _T_596 & 2'h2; // @[axi4_to_ahb.scala 364:88] wire [1:0] _T_597 = _T_596 & 2'h2; // @[axi4_to_ahb.scala 363:88]
wire [3:0] slave_opc = {_T_594,_T_597}; // @[Cat.scala 29:58] wire [3:0] slave_opc = {_T_594,_T_597}; // @[Cat.scala 29:58]
wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 208:49] wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 207:49]
reg slvbuf_tag; // @[Reg.scala 27:20] reg slvbuf_tag; // @[Reg.scala 27:20]
wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 211:65] wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 210:65]
reg [31:0] last_bus_addr; // @[Reg.scala 27:20] reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
wire [63:0] _T_601 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] wire [63:0] _T_601 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_602 = buf_state == 3'h5; // @[axi4_to_ahb.scala 365:91] wire _T_602 = buf_state == 3'h5; // @[axi4_to_ahb.scala 364:91]
reg [63:0] buf_data; // @[el2_lib.scala 514:16] reg [63:0] buf_data; // @[el2_lib.scala 514:16]
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 465:17] wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 464:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 454:12] reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 453:12]
wire [63:0] _T_605 = _T_602 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 365:79] wire [63:0] _T_605 = _T_602 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 364:79]
wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 218:56] wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 217:56]
wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 218:91] wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 217:91]
wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 218:74] wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 217:74]
wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 249:54] wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 248:54]
wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 249:38] wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 248:38]
wire [2:0] _T_84 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] wire [2:0] _T_84 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : _T_84; // @[Mux.scala 98:16] wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : _T_84; // @[Mux.scala 98:16]
wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16] wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16]
@ -273,14 +273,14 @@ module axi4_to_ahb(
wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16] wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16]
wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16] wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16]
wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16] wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16]
wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 252:30] wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 251:30]
wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 254:51] wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 253:51]
wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 265:33] wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 264:33]
wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 280:64] wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 279:64]
wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 280:48] wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 279:48]
wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 280:79] wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 279:79]
wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 325:33] wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 324:33]
wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 325:48] wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 324:48]
wire _GEN_12 = _T_279 & _T_352; // @[Conditional.scala 39:67] wire _GEN_12 = _T_279 & _T_352; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_186 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] wire _GEN_32 = _T_186 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
wire _GEN_48 = _T_184 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] wire _GEN_48 = _T_184 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
@ -289,39 +289,39 @@ module axi4_to_ahb(
wire _GEN_88 = _T_99 ? _T_124 : _GEN_75; // @[Conditional.scala 39:67] wire _GEN_88 = _T_99 ? _T_124 : _GEN_75; // @[Conditional.scala 39:67]
wire bypass_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] wire bypass_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58]
wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 255:45] wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 254:45]
wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 261:34] wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 260:34]
wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 261:32] wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 260:32]
reg [31:0] buf_addr; // @[el2_lib.scala 514:16] reg [31:0] buf_addr; // @[el2_lib.scala 514:16]
wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 266:30] wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 265:30]
wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 267:44] wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 266:44]
wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 267:58] wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 266:58]
wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 267:32] wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 266:32]
wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 282:59] wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 281:59]
wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 282:74] wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 281:74]
wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 282:43] wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 281:43]
wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 282:32] wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 281:32]
wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 292:37] wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 291:37]
reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
reg [7:0] buf_byteen; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20]
wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 181:52] wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 180:52]
wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 182:48] wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 181:48]
wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 182:48] wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 181:48]
wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 182:48] wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 181:48]
wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 182:48] wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 181:48]
wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 182:48] wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 181:48]
wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 182:48] wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 181:48]
wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 182:62] wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 181:62]
wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 182:48] wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 181:48]
wire [2:0] _T_221 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] wire [2:0] _T_221 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
wire [2:0] _T_222 = _T_217 ? 3'h6 : _T_221; // @[Mux.scala 98:16] wire [2:0] _T_222 = _T_217 ? 3'h6 : _T_221; // @[Mux.scala 98:16]
wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16] wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16]
@ -330,17 +330,17 @@ module axi4_to_ahb(
wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16] wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16]
wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16] wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16]
wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16] wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16]
wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 310:30] wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 309:30]
wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 311:65] wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 310:65]
reg buf_aligned; // @[Reg.scala 27:20] reg buf_aligned; // @[Reg.scala 27:20]
wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 311:44] wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 310:44]
wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 311:92] wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 310:92]
wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 311:163] wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 310:163]
wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 311:79] wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 310:79]
wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 311:29] wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 310:29]
wire _T_347 = _T_230 | _T_271; // @[axi4_to_ahb.scala 324:118] wire _T_347 = _T_230 | _T_271; // @[axi4_to_ahb.scala 323:118]
wire _T_348 = _T_107 & _T_347; // @[axi4_to_ahb.scala 324:82] wire _T_348 = _T_107 & _T_347; // @[axi4_to_ahb.scala 323:82]
wire _T_349 = ahb_hresp_q | _T_348; // @[axi4_to_ahb.scala 324:32] wire _T_349 = ahb_hresp_q | _T_348; // @[axi4_to_ahb.scala 323:32]
wire _GEN_11 = _T_279 & _T_349; // @[Conditional.scala 39:67] wire _GEN_11 = _T_279 & _T_349; // @[Conditional.scala 39:67]
wire _GEN_24 = _T_186 ? _T_273 : _GEN_11; // @[Conditional.scala 39:67] wire _GEN_24 = _T_186 ? _T_273 : _GEN_11; // @[Conditional.scala 39:67]
wire _GEN_43 = _T_184 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] wire _GEN_43 = _T_184 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
@ -348,17 +348,17 @@ module axi4_to_ahb(
wire _GEN_74 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67] wire _GEN_74 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_99 ? _T_111 : _GEN_74; // @[Conditional.scala 39:67] wire _GEN_84 = _T_99 ? _T_111 : _GEN_74; // @[Conditional.scala 39:67]
wire cmd_done = _T_47 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] wire cmd_done = _T_47 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 312:43] wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 311:43]
wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 312:32] wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 311:32]
wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 312:57] wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 311:57]
wire _T_301 = _T_53 | _T_94; // @[axi4_to_ahb.scala 322:62] wire _T_301 = _T_53 | _T_94; // @[axi4_to_ahb.scala 321:62]
wire _T_302 = buf_state_en & _T_301; // @[axi4_to_ahb.scala 322:33] wire _T_302 = buf_state_en & _T_301; // @[axi4_to_ahb.scala 321:33]
wire _T_355 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 326:57] wire _T_355 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 325:57]
wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 326:71] wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 325:71]
wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 329:40] wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 328:40]
wire [2:0] _T_440 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 332:30] wire [2:0] _T_440 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 331:30]
wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_279 ? buf_state_en : _T_441; // @[Conditional.scala 39:67] wire _GEN_7 = _T_279 ? buf_state_en : _T_441; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67] wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67]
@ -407,72 +407,72 @@ module axi4_to_ahb(
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58] wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 350:24] wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 349:24]
wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 349:51] wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 348:48]
wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 350:57] wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 349:54]
wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 350:36] wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 349:33]
wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 350:91] wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 349:93]
wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 350:70] wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 349:72]
wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 351:25] wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 350:25]
wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 351:62] wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 350:62]
wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 351:97] wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 350:97]
wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 351:74] wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 350:74]
wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 351:132] wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 350:132]
wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 351:109] wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 350:109]
wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 351:168] wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 350:168]
wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 351:145] wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 350:145]
wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 352:28] wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 351:28]
wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 351:181] wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 350:181]
wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 352:63] wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 351:63]
wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 352:40] wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 351:40]
wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 352:99] wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 351:99]
wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 352:76] wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 351:76]
wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 351:38] wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 350:38]
wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 350:104] wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 349:106]
wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 344:60] wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 343:60]
wire [2:0] _T_482 = _T_445 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 344:43] wire [2:0] _T_482 = _T_445 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 343:43]
wire _T_486 = buf_state == 3'h3; // @[axi4_to_ahb.scala 347:33] wire _T_486 = buf_state == 3'h3; // @[axi4_to_ahb.scala 346:33]
wire _T_492 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 348:38] wire _T_492 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 347:38]
wire _T_495 = _T_492 & _T_49; // @[axi4_to_ahb.scala 348:72] wire _T_495 = _T_492 & _T_49; // @[axi4_to_ahb.scala 347:71]
wire [1:0] _T_529 = _T_495 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 348:21] wire [1:0] _T_529 = _T_495 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 347:21]
wire [31:0] _T_568 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_568 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_571 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_571 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_575 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_575 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 348:15] wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 347:15]
wire [1:0] _T_577 = _T_575 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 355:77] wire [1:0] _T_577 = _T_575 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 354:77]
wire [2:0] _T_578 = {1'h0,_T_577}; // @[Cat.scala 29:58] wire [2:0] _T_578 = {1'h0,_T_577}; // @[Cat.scala 29:58]
wire [1:0] _T_580 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_580 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
reg [1:0] buf_size; // @[Reg.scala 27:20] reg [1:0] buf_size; // @[Reg.scala 27:20]
wire [1:0] _T_582 = _T_580 & buf_size; // @[axi4_to_ahb.scala 355:135] wire [1:0] _T_582 = _T_580 & buf_size; // @[axi4_to_ahb.scala 354:134]
wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58] wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58]
wire _T_586 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 359:33] wire _T_586 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 358:33]
wire [1:0] _T_587 = {1'h1,_T_586}; // @[Cat.scala 29:58] wire [1:0] _T_587 = {1'h1,_T_586}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20] reg buf_write; // @[Reg.scala 27:20]
wire _T_609 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 368:40] wire _T_609 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 367:40]
wire _T_610 = _T_609 & io_ahb_hready; // @[axi4_to_ahb.scala 368:52] wire _T_610 = _T_609 & io_ahb_hready; // @[axi4_to_ahb.scala 367:52]
wire last_addr_en = _T_610 & io_ahb_hwrite; // @[axi4_to_ahb.scala 368:68] wire last_addr_en = _T_610 & io_ahb_hwrite; // @[axi4_to_ahb.scala 367:68]
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 370:47] wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 369:47]
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 371:50] wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 370:50]
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 372:49] wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 371:49]
wire _T_620 = ~wrbuf_en; // @[axi4_to_ahb.scala 373:33] wire _T_620 = ~wrbuf_en; // @[axi4_to_ahb.scala 372:33]
wire wrbuf_rst = wrbuf_cmd_sent & _T_620; // @[axi4_to_ahb.scala 373:31] wire wrbuf_rst = wrbuf_cmd_sent & _T_620; // @[axi4_to_ahb.scala 372:31]
wire _T_622 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 375:35] wire _T_622 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 374:35]
wire _T_623 = wrbuf_vld & _T_622; // @[axi4_to_ahb.scala 375:33] wire _T_623 = wrbuf_vld & _T_622; // @[axi4_to_ahb.scala 374:33]
wire _T_624 = ~_T_623; // @[axi4_to_ahb.scala 375:21] wire _T_624 = ~_T_623; // @[axi4_to_ahb.scala 374:21]
wire _T_627 = wrbuf_data_vld & _T_622; // @[axi4_to_ahb.scala 376:37] wire _T_627 = wrbuf_data_vld & _T_622; // @[axi4_to_ahb.scala 375:37]
wire _T_628 = ~_T_627; // @[axi4_to_ahb.scala 376:20] wire _T_628 = ~_T_627; // @[axi4_to_ahb.scala 375:20]
wire _T_631 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 377:21] wire _T_631 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 376:21]
wire _T_634 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 381:52] wire _T_634 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 380:52]
wire _T_635 = ~wrbuf_rst; // @[axi4_to_ahb.scala 381:88] wire _T_635 = ~wrbuf_rst; // @[axi4_to_ahb.scala 380:88]
wire _T_639 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 382:52] wire _T_639 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 381:52]
reg buf_tag; // @[Reg.scala 27:20] reg buf_tag; // @[Reg.scala 27:20]
wire _T_689 = ~slave_valid_pre; // @[axi4_to_ahb.scala 433:52] wire _T_689 = ~slave_valid_pre; // @[axi4_to_ahb.scala 432:52]
wire _T_702 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 457:43] wire _T_702 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 456:43]
wire _T_703 = _T_702 | io_clk_override; // @[axi4_to_ahb.scala 457:58] wire _T_703 = _T_702 | io_clk_override; // @[axi4_to_ahb.scala 456:58]
wire _T_706 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 458:54] wire _T_706 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 457:54]
wire _T_707 = _T_706 | io_clk_override; // @[axi4_to_ahb.scala 458:74] wire _T_707 = _T_706 | io_clk_override; // @[axi4_to_ahb.scala 457:74]
wire _T_709 = buf_state != 3'h0; // @[axi4_to_ahb.scala 459:50] wire _T_709 = buf_state != 3'h0; // @[axi4_to_ahb.scala 458:50]
wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 459:60] wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 458:60]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -533,25 +533,25 @@ module axi4_to_ahb(
.io_en(rvclkhdr_9_io_en), .io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode) .io_scan_mode(rvclkhdr_9_io_scan_mode)
); );
assign io_axi_awready = _T_624 & master_ready; // @[axi4_to_ahb.scala 375:18] assign io_axi_awready = _T_624 & master_ready; // @[axi4_to_ahb.scala 374:18]
assign io_axi_wready = _T_628 & master_ready; // @[axi4_to_ahb.scala 376:17] assign io_axi_wready = _T_628 & master_ready; // @[axi4_to_ahb.scala 375:17]
assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 207:17] assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 206:17]
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 208:16] assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 207:16]
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 209:14] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 208:14]
assign io_axi_arready = _T_631 & master_ready; // @[axi4_to_ahb.scala 377:18] assign io_axi_arready = _T_631 & master_ready; // @[axi4_to_ahb.scala 376:18]
assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 211:17] assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 210:17]
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 213:14] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 212:14]
assign io_axi_rdata = slvbuf_error ? _T_601 : _T_605; // @[axi4_to_ahb.scala 214:16] assign io_axi_rdata = slvbuf_error ? _T_601 : _T_605; // @[axi4_to_ahb.scala 213:16]
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 212:16] assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 211:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 378:16] assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 377:16]
assign io_ahb_haddr = bypass_en ? _T_568 : _T_571; // @[axi4_to_ahb.scala 354:16] assign io_ahb_haddr = bypass_en ? _T_568 : _T_571; // @[axi4_to_ahb.scala 353:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 357:17] assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 356:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 358:20] assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 357:20]
assign io_ahb_hprot = {{2'd0}, _T_587}; // @[axi4_to_ahb.scala 359:16] assign io_ahb_hprot = {{2'd0}, _T_587}; // @[axi4_to_ahb.scala 358:16]
assign io_ahb_hsize = bypass_en ? _T_578 : _T_583; // @[axi4_to_ahb.scala 355:16] assign io_ahb_hsize = bypass_en ? _T_578 : _T_583; // @[axi4_to_ahb.scala 354:16]
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 224:17 axi4_to_ahb.scala 255:21 axi4_to_ahb.scala 267:21 axi4_to_ahb.scala 282:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 312:21 axi4_to_ahb.scala 326:21] assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 223:17 axi4_to_ahb.scala 254:21 axi4_to_ahb.scala 266:21 axi4_to_ahb.scala 281:21 axi4_to_ahb.scala 291:21 axi4_to_ahb.scala 311:21 axi4_to_ahb.scala 325:21]
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 360:17] assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 359:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 361:17] assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 360:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]

16
src/main/scala/lib/axi4_to_ahb.scala
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@ -164,15 +164,15 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
val byteen = WireInit(0.U(8.W)) val byteen = WireInit(0.U(8.W))
val size = ("b11".U & Fill(2, (byteen(7, 0) === "hff".U))) | val size = ("b11".U & Fill(2, (byteen(7, 0) === "hff".U))) |
("b10".U & (Fill(2, ((byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U))))) | ("b10".U & (Fill(2, ((byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U(8.W)))))) |
("b01".U & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U))))) ("b01".U(2.W) & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U(8.W)) | (byteen(7, 0) === "h03".U(8.W))))))
size size
} }
def get_write_addr(byteen_e: UInt) = { def get_write_addr(byteen_e: UInt) = {
val byteen_e = WireInit(0.U(8.W)) val byteen_e = WireInit(0.U(8.W))
val addr = ("h0".U & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))))) | val addr = ("h0".U(3.W) & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U(8.W)) | (byteen_e(7, 0) === "h03".U(8.W)))))) |
("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) | ("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U(8.W))))) |
("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U))))) | ("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U(8.W)))))) |
("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U)))) ("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))
addr addr
} }
@ -345,13 +345,13 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
buf_byteen_in := wrbuf_byteen(7,0) buf_byteen_in := wrbuf_byteen(7,0)
buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0)) buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0))
buf_size_in := Mux((buf_aligned_in & (master_size(1,0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(),get_write_size(master_byteen(7,0)), master_size(1,0)) buf_size_in := Mux((buf_aligned_in & (master_size(1,0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(),get_write_size(master_byteen(7,0)), master_size(1,0))
buf_aligned_in := (master_opc(2, 0) === "b0".U) | // reads are always aligned since they are either DW or sideeffects buf_aligned_in := (master_opc(2, 0) === 0.U) | // reads are always aligned since they are either DW or sideeffects
(master_size(1, 0) === "b0".U) | (master_size(1, 0) === "b01".U) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned (master_size(1, 0) === 0.U) | (master_size(1, 0) === "b01".U(2.W)) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) | ((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) |
(master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U))) (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U)))
// Generate the ahb signals // Generate the ahb signals
io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0)))
io.ahb_hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0))))) io.ahb_hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0))))
io.ahb_hburst := "b0".U io.ahb_hburst := "b0".U
io.ahb_hmastlock := "b0".U io.ahb_hmastlock := "b0".U

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target/scala-2.12/classes/lib/AXImain$.class
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target/scala-2.12/classes/lib/AXImain$delayedInit$body.class
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