Bus-buffer testing start

el2_lsu_bus_buffer.anno.json

@@ -22,8 +22,8 @@
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo",
     "sources":[
-      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
     ]
   },
@@ -31,8 +31,8 @@
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi",
     "sources":[
-      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
     ]
   },
@@ -63,8 +63,8 @@
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
     "sources":[
-      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
     ]
   },
@@ -120,8 +120,8 @@
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo",
     "sources":[
-      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
     ]
   },

src/main/scala/lsu/el2_lsu_bus_buffer.scala

@@ -213,10 +213,10 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
   val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m
 
   val ibuf_byteen = WireInit(UInt(4.W), 0.U)
-  for (i <- 0 until 4) {
-    ld_byte_ibuf_hit_lo := ld_addr_ibuf_hit_lo & ibuf_byteen(i) & ldst_byteen_lo_m(i)
-    ld_byte_ibuf_hit_hi := ld_addr_ibuf_hit_hi & ibuf_byteen(i) & ldst_byteen_hi_m(i)
-  }
+
+  ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m
+  ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m
+
   val buf_data = Wire(Vec(DEPTH, UInt(32.W)))
   buf_data := buf_data.map(i=> 0.U)
   val fwd_data = WireInit(UInt(32.W), 0.U)