Bus-buffer testing start

el2_lsu_bus_buffer.anno.json

@@ -144,6 +144,32 @@
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_data_en",
+    "sources":[
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_tlu_force_halt",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_rvalid",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_rready",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_tlu_wb_coalescing_disable",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_r_load",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_no_word_merge_r",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_is_sideeffects_r",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_load",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_r",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_r_store",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_rid",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_bvalid",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_bready",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_bid"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data",

src/main/scala/lsu/el2_lsu_bus_buffer.scala

@@ -108,6 +108,7 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
     val test = Output(UInt())
     val data_hi = Output(UInt())
     val data_lo = Output(UInt())
+    val data_en = Output(UInt())
   })
   def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
   def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
@@ -541,7 +542,7 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
     buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())})
     buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode))
     buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & !buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_))
-
+  io.data_en := (0 until DEPTH).map(i=>buf_data_en(i).asUInt()).reverse.reduce(Cat(_,_))
   val buf_numvld_any = (0 until DEPTH).map(i=>(buf_state(i)=/=idle_C).asUInt).reverse.reduce(_ +& _)
   buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
   buf_numvld_cmd_any :=  (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)