Merge branch 'master' into lsu

# Conflicts:
#	src/main/scala/lib/GCD.scala
#	src/main/scala/lib/beh_lib.scala

EL2_IC_DATA.anno.json

@@ -0,0 +1,18 @@
+[
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"EL2_IC_DATA"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

EL2_IC_DATA.fir

@@ -0,0 +1,26 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit EL2_IC_DATA : 
+  module EL2_IC_DATA : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<15>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip mask : UInt<1>[2][2]}
+    
+    smem ic_memory : UInt<26>[2][2][512], undefined @[el2_ifu_ic_mem.scala 209:30]
+    wire data : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 210:48]
+    data[0][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
+    data[0][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
+    data[1][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
+    data[1][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
+    wire mem_mask : UInt<1>[2] @[el2_ifu_ic_mem.scala 211:51]
+    mem_mask[0] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
+    mem_mask[1] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
+    wire mem_mask2 : UInt<1>[2][2] @[el2_ifu_ic_mem.scala 212:52]
+    mem_mask2[0][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
+    mem_mask2[0][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
+    mem_mask2[1][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
+    mem_mask2[1][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
+    io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 214:23]
+    io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 215:17]
+    io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 216:16]
+    io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 217:16]
+    

EL2_IC_DATA.v

@@ -0,0 +1,34 @@
+module EL2_IC_DATA(
+  input         clock,
+  input         reset,
+  input         io_rst_l,
+  input         io_clk_override,
+  input  [11:0] io_ic_rw_addr,
+  input  [1:0]  io_ic_wr_en,
+  input         io_ic_rd_en,
+  input  [70:0] io_ic_wr_data_0,
+  input  [70:0] io_ic_wr_data_1,
+  output [63:0] io_ic_rd_data,
+  input  [70:0] io_ic_debug_wr_data,
+  output [70:0] io_ic_debug_rd_data,
+  output [1:0]  io_ic_parerr,
+  output [1:0]  io_ic_eccerr,
+  input  [14:0] io_ic_debug_addr,
+  input         io_ic_debug_rd_en,
+  input         io_ic_debug_wr_en,
+  input         io_ic_debug_tag_array,
+  input  [1:0]  io_ic_debug_way,
+  input  [63:0] io_ic_premux_data,
+  input         io_ic_sel_premux_data,
+  input  [1:0]  io_ic_rd_hit,
+  input         io_scan_mode,
+  input         io_mask_0_0,
+  input         io_mask_0_1,
+  input         io_mask_1_0,
+  input         io_mask_1_1
+);
+  assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17]
+  assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23]
+  assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16]
+  assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16]
+endmodule

EL2_IC_TAG.anno.json

@@ -0,0 +1,93 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_1",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_0",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
+      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
+      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
+      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
+      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_1",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_0",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"EL2_IC_TAG"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

EL2_IC_TAG.v

@@ -0,0 +1,384 @@
+module rvecc_decode(
+  input  [31:0] io_din,
+  input  [6:0]  io_ecc_in,
+  output [6:0]  io_ecc_out,
+  output [31:0] io_dout,
+  output        io_single_ecc_error
+);
+  wire  w0_0 = io_din[0]; // @[beh_lib.scala 239:37]
+  wire  w0_1 = io_din[1]; // @[beh_lib.scala 239:37]
+  wire  w1_1 = io_din[2]; // @[beh_lib.scala 240:37]
+  wire  w0_2 = io_din[3]; // @[beh_lib.scala 239:37]
+  wire  w0_3 = io_din[4]; // @[beh_lib.scala 239:37]
+  wire  w1_3 = io_din[5]; // @[beh_lib.scala 240:37]
+  wire  w0_4 = io_din[6]; // @[beh_lib.scala 239:37]
+  wire  w2_3 = io_din[7]; // @[beh_lib.scala 241:37]
+  wire  w0_5 = io_din[8]; // @[beh_lib.scala 239:37]
+  wire  w1_5 = io_din[9]; // @[beh_lib.scala 240:37]
+  wire  w0_6 = io_din[10]; // @[beh_lib.scala 239:37]
+  wire  w0_7 = io_din[11]; // @[beh_lib.scala 239:37]
+  wire  w1_7 = io_din[12]; // @[beh_lib.scala 240:37]
+  wire  w0_8 = io_din[13]; // @[beh_lib.scala 239:37]
+  wire  w2_7 = io_din[14]; // @[beh_lib.scala 241:37]
+  wire  w0_9 = io_din[15]; // @[beh_lib.scala 239:37]
+  wire  w1_9 = io_din[16]; // @[beh_lib.scala 240:37]
+  wire  w0_10 = io_din[17]; // @[beh_lib.scala 239:37]
+  wire  w3_7 = io_din[18]; // @[beh_lib.scala 242:37]
+  wire  w0_11 = io_din[19]; // @[beh_lib.scala 239:37]
+  wire  w1_11 = io_din[20]; // @[beh_lib.scala 240:37]
+  wire  w0_12 = io_din[21]; // @[beh_lib.scala 239:37]
+  wire  w2_11 = io_din[22]; // @[beh_lib.scala 241:37]
+  wire  w0_13 = io_din[23]; // @[beh_lib.scala 239:37]
+  wire  w1_13 = io_din[24]; // @[beh_lib.scala 240:37]
+  wire  w0_14 = io_din[25]; // @[beh_lib.scala 239:37]
+  wire  w0_15 = io_din[26]; // @[beh_lib.scala 239:37]
+  wire  w1_15 = io_din[27]; // @[beh_lib.scala 240:37]
+  wire  w0_16 = io_din[28]; // @[beh_lib.scala 239:37]
+  wire  w2_15 = io_din[29]; // @[beh_lib.scala 241:37]
+  wire  w0_17 = io_din[30]; // @[beh_lib.scala 239:37]
+  wire  w1_17 = io_din[31]; // @[beh_lib.scala 240:37]
+  wire [5:0] _T_100 = {w1_17,w0_17,w2_15,w0_16,w1_15,w0_15}; // @[beh_lib.scala 247:86]
+  wire  _T_101 = ^_T_100; // @[beh_lib.scala 247:93]
+  wire  _T_102 = io_ecc_in[5] ^ _T_101; // @[beh_lib.scala 247:81]
+  wire [6:0] _T_109 = {w0_10,w1_9,w0_9,w2_7,w0_8,w1_7,w0_7}; // @[beh_lib.scala 247:116]
+  wire [14:0] _T_117 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_109}; // @[beh_lib.scala 247:116]
+  wire  _T_118 = ^_T_117; // @[beh_lib.scala 247:123]
+  wire  _T_119 = io_ecc_in[4] ^ _T_118; // @[beh_lib.scala 247:111]
+  wire [6:0] _T_126 = {w0_6,w1_5,w0_5,w2_3,w0_4,w1_3,w0_3}; // @[beh_lib.scala 247:146]
+  wire [14:0] _T_134 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_126}; // @[beh_lib.scala 247:146]
+  wire  _T_135 = ^_T_134; // @[beh_lib.scala 247:153]
+  wire  _T_136 = io_ecc_in[3] ^ _T_135; // @[beh_lib.scala 247:141]
+  wire [8:0] _T_145 = {w0_9,w2_7,w0_6,w1_5,w0_5,w2_3,w0_2,w1_1,w0_1}; // @[beh_lib.scala 247:176]
+  wire [17:0] _T_154 = {w1_17,w0_17,w2_15,w0_14,w1_13,w0_13,w2_11,w0_10,w1_9,_T_145}; // @[beh_lib.scala 247:176]
+  wire  _T_155 = ^_T_154; // @[beh_lib.scala 247:183]
+  wire  _T_156 = io_ecc_in[2] ^ _T_155; // @[beh_lib.scala 247:171]
+  wire [8:0] _T_165 = {w0_8,w1_7,w0_6,w1_5,w0_4,w1_3,w0_2,w1_1,w0_0}; // @[beh_lib.scala 247:206]
+  wire [17:0] _T_174 = {w1_17,w0_16,w1_15,w0_14,w1_13,w0_12,w1_11,w0_10,w1_9,_T_165}; // @[beh_lib.scala 247:206]
+  wire  _T_175 = ^_T_174; // @[beh_lib.scala 247:213]
+  wire  _T_176 = io_ecc_in[1] ^ _T_175; // @[beh_lib.scala 247:201]
+  wire [8:0] _T_185 = {w0_8,w0_7,w0_6,w0_5,w0_4,w0_3,w0_2,w0_1,w0_0}; // @[beh_lib.scala 247:236]
+  wire [17:0] _T_194 = {w0_17,w0_16,w0_15,w0_14,w0_13,w0_12,w0_11,w0_10,w0_9,_T_185}; // @[beh_lib.scala 247:236]
+  wire  _T_195 = ^_T_194; // @[beh_lib.scala 247:243]
+  wire  _T_196 = io_ecc_in[0] ^ _T_195; // @[beh_lib.scala 247:231]
+  wire [6:0] ecc_check = {1'h0,_T_102,_T_119,_T_136,_T_156,_T_176,_T_196}; // @[Cat.scala 29:58]
+  wire  error_mask_0 = ecc_check[5:0] == 6'h1; // @[beh_lib.scala 255:39]
+  wire  error_mask_1 = ecc_check[5:0] == 6'h2; // @[beh_lib.scala 255:39]
+  wire  error_mask_2 = ecc_check[5:0] == 6'h3; // @[beh_lib.scala 255:39]
+  wire  error_mask_3 = ecc_check[5:0] == 6'h4; // @[beh_lib.scala 255:39]
+  wire  error_mask_4 = ecc_check[5:0] == 6'h5; // @[beh_lib.scala 255:39]
+  wire  error_mask_5 = ecc_check[5:0] == 6'h6; // @[beh_lib.scala 255:39]
+  wire  error_mask_6 = ecc_check[5:0] == 6'h7; // @[beh_lib.scala 255:39]
+  wire  error_mask_7 = ecc_check[5:0] == 6'h8; // @[beh_lib.scala 255:39]
+  wire  error_mask_8 = ecc_check[5:0] == 6'h9; // @[beh_lib.scala 255:39]
+  wire  error_mask_9 = ecc_check[5:0] == 6'ha; // @[beh_lib.scala 255:39]
+  wire  error_mask_10 = ecc_check[5:0] == 6'hb; // @[beh_lib.scala 255:39]
+  wire  error_mask_11 = ecc_check[5:0] == 6'hc; // @[beh_lib.scala 255:39]
+  wire  error_mask_12 = ecc_check[5:0] == 6'hd; // @[beh_lib.scala 255:39]
+  wire  error_mask_13 = ecc_check[5:0] == 6'he; // @[beh_lib.scala 255:39]
+  wire  error_mask_14 = ecc_check[5:0] == 6'hf; // @[beh_lib.scala 255:39]
+  wire  error_mask_15 = ecc_check[5:0] == 6'h10; // @[beh_lib.scala 255:39]
+  wire  error_mask_16 = ecc_check[5:0] == 6'h11; // @[beh_lib.scala 255:39]
+  wire  error_mask_17 = ecc_check[5:0] == 6'h12; // @[beh_lib.scala 255:39]
+  wire  error_mask_18 = ecc_check[5:0] == 6'h13; // @[beh_lib.scala 255:39]
+  wire  error_mask_19 = ecc_check[5:0] == 6'h14; // @[beh_lib.scala 255:39]
+  wire  error_mask_20 = ecc_check[5:0] == 6'h15; // @[beh_lib.scala 255:39]
+  wire  error_mask_21 = ecc_check[5:0] == 6'h16; // @[beh_lib.scala 255:39]
+  wire  error_mask_22 = ecc_check[5:0] == 6'h17; // @[beh_lib.scala 255:39]
+  wire  error_mask_23 = ecc_check[5:0] == 6'h18; // @[beh_lib.scala 255:39]
+  wire  error_mask_24 = ecc_check[5:0] == 6'h19; // @[beh_lib.scala 255:39]
+  wire  error_mask_25 = ecc_check[5:0] == 6'h1a; // @[beh_lib.scala 255:39]
+  wire  error_mask_26 = ecc_check[5:0] == 6'h1b; // @[beh_lib.scala 255:39]
+  wire  error_mask_27 = ecc_check[5:0] == 6'h1c; // @[beh_lib.scala 255:39]
+  wire  error_mask_28 = ecc_check[5:0] == 6'h1d; // @[beh_lib.scala 255:39]
+  wire  error_mask_29 = ecc_check[5:0] == 6'h1e; // @[beh_lib.scala 255:39]
+  wire  error_mask_30 = ecc_check[5:0] == 6'h1f; // @[beh_lib.scala 255:39]
+  wire  error_mask_31 = ecc_check[5:0] == 6'h20; // @[beh_lib.scala 255:39]
+  wire  error_mask_32 = ecc_check[5:0] == 6'h21; // @[beh_lib.scala 255:39]
+  wire  error_mask_33 = ecc_check[5:0] == 6'h22; // @[beh_lib.scala 255:39]
+  wire  error_mask_34 = ecc_check[5:0] == 6'h23; // @[beh_lib.scala 255:39]
+  wire  error_mask_35 = ecc_check[5:0] == 6'h24; // @[beh_lib.scala 255:39]
+  wire  error_mask_36 = ecc_check[5:0] == 6'h25; // @[beh_lib.scala 255:39]
+  wire  error_mask_37 = ecc_check[5:0] == 6'h26; // @[beh_lib.scala 255:39]
+  wire  error_mask_38 = ecc_check[5:0] == 6'h27; // @[beh_lib.scala 255:39]
+  wire [7:0] _T_310 = {io_ecc_in[3],io_din[3:1],io_ecc_in[2],w0_0,io_ecc_in[1:0]}; // @[Cat.scala 29:58]
+  wire [38:0] din_plus_parity = {io_ecc_in[6],io_din[31:26],io_ecc_in[5],io_din[25:11],io_ecc_in[4],io_din[10:4],_T_310}; // @[Cat.scala 29:58]
+  wire [9:0] _T_333 = {error_mask_18,error_mask_17,error_mask_16,error_mask_15,error_mask_14,error_mask_13,error_mask_12,error_mask_11,error_mask_10,error_mask_9}; // @[beh_lib.scala 258:70]
+  wire [18:0] _T_334 = {_T_333,error_mask_8,error_mask_7,error_mask_6,error_mask_5,error_mask_4,error_mask_3,error_mask_2,error_mask_1,error_mask_0}; // @[beh_lib.scala 258:70]
+  wire [9:0] _T_343 = {error_mask_28,error_mask_27,error_mask_26,error_mask_25,error_mask_24,error_mask_23,error_mask_22,error_mask_21,error_mask_20,error_mask_19}; // @[beh_lib.scala 258:70]
+  wire [9:0] _T_352 = {error_mask_38,error_mask_37,error_mask_36,error_mask_35,error_mask_34,error_mask_33,error_mask_32,error_mask_31,error_mask_30,error_mask_29}; // @[beh_lib.scala 258:70]
+  wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[beh_lib.scala 258:70]
+  wire [38:0] _T_355 = _T_354 ^ din_plus_parity; // @[beh_lib.scala 258:77]
+  wire [38:0] dout_plus_parity = io_single_ecc_error ? _T_355 : din_plus_parity; // @[beh_lib.scala 258:29]
+  wire [3:0] _T_361 = {dout_plus_parity[6:4],dout_plus_parity[2]}; // @[Cat.scala 29:58]
+  wire [27:0] _T_363 = {dout_plus_parity[37:32],dout_plus_parity[30:16],dout_plus_parity[14:8]}; // @[Cat.scala 29:58]
+  wire  _T_367 = ecc_check == 7'h40; // @[beh_lib.scala 261:60]
+  wire  _T_368 = dout_plus_parity[38] ^ _T_367; // @[beh_lib.scala 261:42]
+  wire [3:0] _T_375 = {dout_plus_parity[7],dout_plus_parity[3],dout_plus_parity[1:0]}; // @[Cat.scala 29:58]
+  wire [2:0] _T_377 = {_T_368,dout_plus_parity[31],dout_plus_parity[15]}; // @[Cat.scala 29:58]
+  assign io_ecc_out = {_T_377,_T_375}; // @[beh_lib.scala 248:14 beh_lib.scala 261:14]
+  assign io_dout = {_T_363,_T_361}; // @[beh_lib.scala 260:11]
+  assign io_single_ecc_error = 1'h0; // @[beh_lib.scala 250:23]
+endmodule
+module EL2_IC_TAG(
+  input         clock,
+  input         reset,
+  input         io_clk,
+  input         io_rst_l,
+  input         io_clk_override,
+  input         io_dec_tlu_core_ecc_disable,
+  input  [31:0] io_ic_rw_addr,
+  input  [1:0]  io_ic_wr_en,
+  input  [1:0]  io_ic_tag_valid,
+  input         io_ic_rd_en,
+  input  [12:0] io_ic_debug_addr,
+  input         io_ic_debug_rd_en,
+  input         io_ic_debug_wr_en,
+  input         io_ic_debug_tag_array,
+  input  [1:0]  io_ic_debug_way,
+  output [25:0] io_ictag_debug_rd_data,
+  input  [70:0] io_ic_debug_wr_data,
+  output [1:0]  io_ic_rd_hit,
+  output        io_ic_tag_perr,
+  input         io_scan_mode,
+  output [25:0] io_test,
+  output [31:0] io_test_ecc_data_out_0,
+  output [31:0] io_test_ecc_data_out_1,
+  output [6:0]  io_test_ecc_out_0,
+  output [6:0]  io_test_ecc_out_1,
+  output        io_test_ecc_sb_out_0,
+  output        io_test_ecc_sb_out_1,
+  output        io_test_ecc_db_out_0,
+  output        io_test_ecc_db_out_1
+);
+`ifdef RANDOMIZE_MEM_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_2;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+  reg [25:0] ic_way_tag_0 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [25:0] ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [6:0] ic_way_tag_0_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [25:0] ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [6:0] ic_way_tag_0__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
+  wire  ic_way_tag_0__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
+  wire  ic_way_tag_0__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
+  reg [6:0] ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
+  reg [25:0] ic_way_tag_1 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [25:0] ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [6:0] ic_way_tag_1_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [25:0] ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
+  wire [6:0] ic_way_tag_1__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
+  wire  ic_way_tag_1__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
+  wire  ic_way_tag_1__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
+  reg [6:0] ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
+  wire [31:0] rvecc_decode_io_din; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [6:0] rvecc_decode_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [6:0] rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [31:0] rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
+  wire  rvecc_decode_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [31:0] rvecc_decode_1_io_din; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [6:0] rvecc_decode_1_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [6:0] rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
+  wire [31:0] rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
+  wire  rvecc_decode_1_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
+  wire  _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 73:93]
+  wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
+  wire [1:0] ic_tag_wren = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 73:33]
+  wire  _T_5 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 75:68]
+  wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
+  wire [1:0] ic_debug_rd_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 75:93]
+  wire  _T_8 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 76:68]
+  wire [1:0] _T_10 = {_T_8,_T_8}; // @[Cat.scala 29:58]
+  wire [1:0] ic_debug_wr_way_en = _T_10 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 76:93]
+  wire  _T_11 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 77:55]
+  wire [1:0] _T_13 = {_T_11,_T_11}; // @[Cat.scala 29:58]
+  wire [1:0] _T_14 = _T_13 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 77:74]
+  wire [1:0] _T_15 = _T_14 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 77:88]
+  wire [1:0] ic_tag_clken = _T_15 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 77:109]
+  reg [31:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 80:30]
+  wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
+  wire [31:0] _T_30 = {13'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
+  wire [8:0] _T_134 = {_T_30[16],_T_30[14],_T_30[12],_T_30[10],_T_30[8],_T_30[6],_T_30[5],_T_30[3],_T_30[1]}; // @[el2_lib.scala 211:22]
+  wire [17:0] _T_143 = {_T_30[31],_T_30[30],_T_30[28],_T_30[27],_T_30[25],_T_30[23],_T_30[21],_T_30[20],_T_30[18],_T_134}; // @[el2_lib.scala 211:22]
+  wire  _T_144 = ^_T_143; // @[el2_lib.scala 211:29]
+  wire [8:0] _T_152 = {_T_30[15],_T_30[14],_T_30[11],_T_30[10],_T_30[7],_T_30[6],_T_30[4],_T_30[3],_T_30[0]}; // @[el2_lib.scala 211:39]
+  wire [17:0] _T_161 = {_T_30[31],_T_30[29],_T_30[28],_T_30[26],_T_30[25],_T_30[22],_T_30[21],_T_30[19],_T_30[18],_T_152}; // @[el2_lib.scala 211:39]
+  wire  _T_162 = ^_T_161; // @[el2_lib.scala 211:46]
+  wire [8:0] _T_170 = {_T_30[15],_T_30[14],_T_30[9],_T_30[8],_T_30[7],_T_30[6],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:56]
+  wire [17:0] _T_179 = {_T_30[30],_T_30[29],_T_30[28],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[17],_T_30[16],_T_170}; // @[el2_lib.scala 211:56]
+  wire  _T_180 = ^_T_179; // @[el2_lib.scala 211:63]
+  wire [6:0] _T_186 = {_T_30[12],_T_30[11],_T_30[10],_T_30[9],_T_30[8],_T_30[7],_T_30[6]}; // @[el2_lib.scala 211:73]
+  wire [14:0] _T_194 = {_T_30[27],_T_30[26],_T_30[25],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[13],_T_186}; // @[el2_lib.scala 211:73]
+  wire  _T_195 = ^_T_194; // @[el2_lib.scala 211:80]
+  wire [14:0] _T_209 = {_T_30[20],_T_30[19],_T_30[18],_T_30[17],_T_30[16],_T_30[15],_T_30[14],_T_30[13],_T_186}; // @[el2_lib.scala 211:90]
+  wire  _T_210 = ^_T_209; // @[el2_lib.scala 211:97]
+  wire [5:0] _T_215 = {_T_30[5],_T_30[4],_T_30[3],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:107]
+  wire  _T_216 = ^_T_215; // @[el2_lib.scala 211:114]
+  wire [5:0] _T_221 = {_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
+  wire  _T_222 = ^_T_30; // @[el2_lib.scala 212:13]
+  wire  _T_223 = ^_T_221; // @[el2_lib.scala 212:23]
+  wire  _T_224 = _T_222 ^ _T_223; // @[el2_lib.scala 212:18]
+  wire [6:0] _T_225 = {_T_224,_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
+  wire [25:0] _T_229 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
+  wire [25:0] _T_463 = {_T_225[4:0],2'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
+  wire  _T_478 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 119:44]
+  reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 123:38]
+  wire [25:0] _GEN_17 = ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 137:75]
+  wire [25:0] _GEN_18 = ic_way_tag_0_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
+  wire [36:0] w_tout_0 = {_GEN_18[25:21],_GEN_18[18:0],13'h0}; // @[Cat.scala 29:58]
+  wire [25:0] _GEN_22 = ic_way_tag_1_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
+  wire [36:0] w_tout_1 = {_GEN_22[25:21],_GEN_22[18:0],13'h0}; // @[Cat.scala 29:58]
+  wire  ic_tag_way_perr_0 = io_test_ecc_sb_out_0 | io_test_ecc_db_out_0; // @[el2_ifu_ic_mem.scala 165:54]
+  wire  ic_tag_way_perr_1 = io_test_ecc_sb_out_1 | io_test_ecc_db_out_1; // @[el2_ifu_ic_mem.scala 165:54]
+  wire [9:0] _T_533 = {ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
+  wire [18:0] _T_542 = {_T_533,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
+  wire [25:0] _T_549 = {_T_542,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
+  wire [25:0] _T_550 = _T_549 & ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
+  wire [9:0] _T_561 = {ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
+  wire [18:0] _T_570 = {_T_561,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
+  wire [25:0] _T_577 = {_T_570,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
+  wire [25:0] _T_578 = _T_577 & ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
+  wire [36:0] _T_636 = w_tout_0 & w_tout_1; // @[el2_ifu_ic_mem.scala 176:31]
+  wire [1:0] _T_637 = {ic_tag_way_perr_0,ic_tag_way_perr_1}; // @[Cat.scala 29:58]
+  wire [1:0] _T_638 = _T_637 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 177:55]
+  wire  _T_642 = w_tout_0[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
+  wire [1:0] _GEN_25 = {{1'd0}, _T_642}; // @[el2_ifu_ic_mem.scala 179:133]
+  wire [1:0] _T_643 = _GEN_25 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
+  wire  _T_646 = w_tout_1[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
+  wire [1:0] _GEN_26 = {{1'd0}, _T_646}; // @[el2_ifu_ic_mem.scala 179:133]
+  wire [1:0] _T_647 = _GEN_26 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
+  wire [3:0] _T_649 = {_T_643,_T_647}; // @[Cat.scala 29:58]
+  rvecc_decode rvecc_decode ( // @[el2_ifu_ic_mem.scala 149:27]
+    .io_din(rvecc_decode_io_din),
+    .io_ecc_in(rvecc_decode_io_ecc_in),
+    .io_ecc_out(rvecc_decode_io_ecc_out),
+    .io_dout(rvecc_decode_io_dout),
+    .io_single_ecc_error(rvecc_decode_io_single_ecc_error)
+  );
+  rvecc_decode rvecc_decode_1 ( // @[el2_ifu_ic_mem.scala 149:27]
+    .io_din(rvecc_decode_1_io_din),
+    .io_ecc_in(rvecc_decode_1_io_ecc_in),
+    .io_ecc_out(rvecc_decode_1_io_ecc_out),
+    .io_dout(rvecc_decode_1_io_dout),
+    .io_single_ecc_error(rvecc_decode_1_io_single_ecc_error)
+  );
+  assign ic_way_tag_0_ic_tag_data_raw_addr = ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
+  assign ic_way_tag_0_ic_tag_data_raw_data = ic_way_tag_0[ic_way_tag_0_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
+  assign ic_way_tag_0__T_487_data = _T_8 ? _T_229 : _T_463;
+  assign ic_way_tag_0__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
+  assign ic_way_tag_0__T_487_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
+  assign ic_way_tag_0__T_487_en = 1'h1;
+  assign ic_way_tag_1_ic_tag_data_raw_addr = ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
+  assign ic_way_tag_1_ic_tag_data_raw_data = ic_way_tag_1[ic_way_tag_1_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
+  assign ic_way_tag_1__T_487_data = _T_8 ? _T_229 : _T_463;
+  assign ic_way_tag_1__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
+  assign ic_way_tag_1__T_487_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
+  assign ic_way_tag_1__T_487_en = 1'h1;
+  assign io_ictag_debug_rd_data = _T_550 | _T_578; // @[el2_ifu_ic_mem.scala 175:26]
+  assign io_ic_rd_hit = _T_649[1:0]; // @[el2_ifu_ic_mem.scala 179:16]
+  assign io_ic_tag_perr = |_T_638; // @[el2_ifu_ic_mem.scala 177:18]
+  assign io_test = _T_636[25:0]; // @[el2_ifu_ic_mem.scala 176:13]
+  assign io_test_ecc_data_out_0 = rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
+  assign io_test_ecc_data_out_1 = rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
+  assign io_test_ecc_out_0 = rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
+  assign io_test_ecc_out_1 = rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
+  assign io_test_ecc_sb_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
+  assign io_test_ecc_sb_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
+  assign io_test_ecc_db_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
+  assign io_test_ecc_db_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
+  assign rvecc_decode_io_din = {11'h0,ic_way_tag_0_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
+  assign rvecc_decode_io_ecc_in = {2'h0,ic_way_tag_0_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
+  assign rvecc_decode_1_io_din = {11'h0,ic_way_tag_1_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
+  assign rvecc_decode_1_io_ecc_in = {2'h0,ic_way_tag_1_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_MEM_INIT
+  _RAND_0 = {1{`RANDOM}};
+  for (initvar = 0; initvar < 128; initvar = initvar+1)
+    ic_way_tag_0[initvar] = _RAND_0[25:0];
+  _RAND_2 = {1{`RANDOM}};
+  for (initvar = 0; initvar < 128; initvar = initvar+1)
+    ic_way_tag_1[initvar] = _RAND_2[25:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 = _RAND_1[6:0];
+  _RAND_3 = {1{`RANDOM}};
+  ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 = _RAND_3[6:0];
+  _RAND_4 = {1{`RANDOM}};
+  ic_rw_addr_ff = _RAND_4[31:0];
+  _RAND_5 = {1{`RANDOM}};
+  ic_debug_rd_way_en_ff = _RAND_5[1:0];
+`endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock) begin
+    if(ic_way_tag_0__T_487_en & ic_way_tag_0__T_487_mask) begin
+      ic_way_tag_0[ic_way_tag_0__T_487_addr] <= ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
+    end
+    if (_T_478) begin
+      ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
+    end else begin
+      ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
+    end
+    if(ic_way_tag_1__T_487_en & ic_way_tag_1__T_487_mask) begin
+      ic_way_tag_1[ic_way_tag_1__T_487_addr] <= ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
+    end
+    if (_T_478) begin
+      ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
+    end else begin
+      ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
+    end
+    if (reset) begin
+      ic_rw_addr_ff <= 32'h0;
+    end else begin
+      ic_rw_addr_ff <= io_ic_rw_addr;
+    end
+    if (reset) begin
+      ic_debug_rd_way_en_ff <= 2'h0;
+    end else begin
+      ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
+    end
+  end
+endmodule

README.md

@@ -1,136 +1,27 @@
-Chisel Project Template
+# EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
-=======================
 
-You've done the Chisel [tutorials](https://github.com/ucb-bar/chisel-tutorial), and now you 
+This repository contains the SweRV EL2 Core design in CHISEL
-are ready to start your own chisel project.  The following procedure should get you started
-with a clean running [Chisel3](https://github.com/freechipsproject/chisel3) project.
 
-> More and more users are finding IntelliJ to be a powerful tool for Chisel coding. See the 
+## Back ground
-[IntelliJ Installation Guide](https://github.com/ucb-bar/chisel-template/wiki/IntelliJ-Installation-Guide) for how to install it.
 
-## Make your own Chisel3 project
+The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
-### How to get started
-The first thing you want to do is clone this repo into a directory of your own.  I'd recommend creating a chisel projects directory somewhere
-```sh
-mkdir ~/ChiselProjects
-cd ~/ChiselProjects
 
-git clone https://github.com/ucb-bar/chisel-template.git MyChiselProject
+## Directory Structure
-cd MyChiselProject
-```
-### Make your project into a fresh git repo
-There may be more elegant way to do it, but the following works for me. **Note:** this project comes with a magnificent 339 line (at this writing) .gitignore file.
- You may want to edit that first in case we missed something, whack away at it, or start it from scratch.
 
-#### Clear out the old git stuff
+    ├── configs                 # Configurations Dir
-```sh
+    │   └── snapshots           # Where generated configuration files are created
-rm -rf .git
+    ├── design                  # Design root dir
-git init
+    │   ├── dbg                 #   Debugger
-git add .gitignore *
+    │   ├── dec                 #   Decode, Registers and Exceptions
-```
+    │   ├── dmi                 #   DMI block
+    │   ├── exu                 #   EXU (ALU/MUL/DIV)
+    │   ├── ifu                 #   Fetch & Branch Prediction
+    │   ├── include             
+    │   ├── lib
+    │   └── lsu                 #   Load/Store
+    ├── docs
+    ├── tools                   # Scripts/Makefiles
+    └── testbench               # (Very) simple testbench
+        ├── asm                 #   Example assembly files
+        └── hex                 #   Canned demo hex files
 
-#### Rename project in build.sbt file
-Use your favorite text editor to change the first line of the **build.sbt** file
-(it ships as ```name := "chisel-module-template"```) to correspond 
-to your project.<br/>
-Perhaps as ```name := "my-chisel-project"```
-
-#### Clean up the README.md file
-Again use you editor of choice to make the README specific to your project.
-Be sure to update (or delete) the License section and add a LICENSE file of your own.
-
-#### Commit your changes
-```
-git commit -m 'Starting MyChiselProject'
-```
-Connecting this up to github or some other remote host is an exercise left to the reader.
-
-### Did it work?
-You should now have a project based on Chisel3 that can be run.<br/>
-So go for it, at the command line in the project root.
-```sh
-sbt 'testOnly gcd.GCDTester -- -z Basic'
-```
->This tells the test harness to only run the test in GCDTester that contains the word Basic
-There are a number of other examples of ways to run tests in there, but we just want to see that
-one works.
-
-You should see a whole bunch of output that ends with something like the following lines
-```
-[info] [0.001] SEED 1540570744913
-test GCD Success: 168 tests passed in 1107 cycles in 0.067751 seconds 16339.24 Hz
-[info] [0.050] RAN 1102 CYCLES PASSED
-[info] GCDTester:
-[info] GCD
-[info] Basic test using Driver.execute
-[info] - should be used as an alternative way to run specification
-[info] using --backend-name verilator
-[info] running with --is-verbose
-[info] running with --generate-vcd-output on
-[info] running with --generate-vcd-output off
-[info] ScalaTest
-[info] Run completed in 3 seconds, 184 milliseconds.
-[info] Total number of tests run: 1
-[info] Suites: completed 1, aborted 0
-[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
-[info] All tests passed.
-[info] Passed: Total 1, Failed 0, Errors 0, Passed 1
-[success] Total time: 5 s, completed Oct 26, 2018 9:19:07 AM
-```
-If you see the above then...
-
-### It worked!
-You are ready to go. We have a few recommended practices and things to do.
-* Use packages and following conventions for [structure](http://www.scala-sbt.org/0.13/docs/Directories.html) and [naming](http://docs.scala-lang.org/style/naming-conventions.html)
-* Package names should be clearly reflected in the testing hierarchy
-* Build tests for all your work.
-* This template includes a dependency on the Chisel3 IOTesters, this is a reasonable starting point for most tests
-* You can remove this dependency in the build.sbt file if necessary
-* Change the name of your project in the build.sbt file
-* Change your README.md
-
-There are [instructions for generating Verilog](https://github.com/freechipsproject/chisel3/wiki/Frequently-Asked-Questions#get-me-verilog) on the Chisel wiki.
-
-Some backends (verilator for example) produce VCD files by default, while other backends (firrtl and treadle) do not.
-You can control the generation of VCD files with the `--generate-vcd-output` flag.
-
-To run the simulation and generate a VCD output file regardless of the backend:
-```bash
-sbt 'test:runMain gcd.GCDMain --generate-vcd-output on'
-```
-
-To run the simulation and suppress the generation of a VCD output file:
-```bash
-sbt 'test:runMain gcd.GCDMain --generate-vcd-output off'
-```
-
-## Development/Bug Fixes
-This is the release version of chisel-template. If you have bug fixes or
-changes you would like to see incorporated in this repo, please checkout
-the master branch and submit pull requests against it.
-
-## License
-This is free and unencumbered software released into the public domain.
-
-Anyone is free to copy, modify, publish, use, compile, sell, or
-distribute this software, either in source code form or as a compiled
-binary, for any purpose, commercial or non-commercial, and by any
-means.
-
-In jurisdictions that recognize copyright laws, the author or authors
-of this software dedicate any and all copyright interest in the
-software to the public domain. We make this dedication for the benefit
-of the public at large and to the detriment of our heirs and
-successors. We intend this dedication to be an overt act of
-relinquishment in perpetuity of all present and future rights to this
-software under copyright law.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
-OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-OTHER DEALINGS IN THE SOFTWARE.
-
-For more information, please refer to <http://unlicense.org/>

el2_dec_dec_ctl.anno.json

@@ -349,12 +349,6 @@
       "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
     ]
   },
-  {
-    "class":"logger.LogLevelAnnotation",
-    "globalLogLevel":{
-      
-    }
-  },
   {
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"

el2_ifu_bp_ctl.anno.json

@@ -0,0 +1,26 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_out",
+    "sources":[
+      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in",
+      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in2"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_ifu_bp_ctl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

el2_ifu_bp_ctl.fir

@@ -0,0 +1,12 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_ifu_bp_ctl : 
+  module el2_ifu_bp_ctl : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip in : UInt<32>, flip in2 : UInt<32>, out : UInt}
+    
+    node _T = bits(io.in, 9, 2) @[el2_lib.scala 35:30]
+    node _T_1 = bits(io.in2, 7, 0) @[el2_lib.scala 35:53]
+    node _T_2 = xor(_T, _T_1) @[el2_lib.scala 35:48]
+    io.out <= _T_2 @[el2_ifu_bp_ctl.scala 13:10]
+    

el2_ifu_bp_ctl.v

@@ -0,0 +1,9 @@
+module el2_ifu_bp_ctl(
+  input         clock,
+  input         reset,
+  input  [31:0] io_in,
+  input  [31:0] io_in2,
+  output [7:0]  io_out
+);
+  assign io_out = io_in[9:2] ^ io_in2[7:0]; // @[el2_ifu_bp_ctl.scala 13:10]
+endmodule

el2_ifu_ic_mem.anno.json

@@ -0,0 +1,18 @@
+[
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_ifu_ic_mem"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

el2_ifu_ic_mem.fir

@@ -0,0 +1,15 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_ifu_ic_mem : 
+  module el2_ifu_ic_mem : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
+    
+    io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18]
+    io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
+    io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16]
+    io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16]
+    io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26]
+    io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23]
+    io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17]
+    

el2_ifu_ic_mem.v

@@ -0,0 +1,38 @@
+module el2_ifu_ic_mem(
+  input         clock,
+  input         reset,
+  input         io_clk,
+  input         io_rst_l,
+  input         io_clk_override,
+  input         io_dec_tlu_core_ecc_disable,
+  input  [30:0] io_ic_rw_addr,
+  input  [1:0]  io_ic_wr_en,
+  input         io_ic_rd_en,
+  input  [8:0]  io_ic_debug_addr,
+  input         io_ic_debug_rd_en,
+  input         io_ic_debug_wr_en,
+  input         io_ic_debug_tag_array,
+  input  [1:0]  io_ic_debug_way,
+  input  [63:0] io_ic_premux_data,
+  input         io_ic_sel_premux_data,
+  input  [70:0] io_ic_wr_data_0,
+  input  [70:0] io_ic_wr_data_1,
+  output [63:0] io_ic_rd_data,
+  output [70:0] io_ic_debug_rd_data,
+  output [25:0] io_ictag_debug_rd_data,
+  input  [70:0] io_ic_debug_wr_data,
+  output [1:0]  io_ic_eccerr,
+  output [1:0]  io_ic_parerr,
+  input  [1:0]  io_ic_tag_valid,
+  output [1:0]  io_ic_rd_hit,
+  output        io_ic_tag_perr,
+  input         io_scan_mode
+);
+  assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 40:17]
+  assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 39:23]
+  assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26]
+  assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 37:16]
+  assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 36:16]
+  assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
+  assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18]
+endmodule

project/target/config-classes/$ea8b489c9f4dfe332eb6.cache

@@ -0,0 +1 @@
+sbt.internal.DslEntry

project/target/config-classes/$f7cc14b2623d339d7fbd.cache

@@ -0,0 +1 @@
+sbt.internal.DslEntry

project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs

@@ -1 +1 @@
-884984604
+338581136

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp

@@ -1 +1 @@
--1413115869
+23355001

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}

project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
-[debug] "not up to date. inChanged = true, force = false
+[debug] "not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")...
+[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")...
-[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")
+[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")

project/target/streams/runtime/dependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/externalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-
+/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/fullClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/managedClasspath/_global/streams/export

@@ -1 +1 @@
-
+/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

rvdffs.anno.json

@@ -0,0 +1,18 @@
+[
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"rvdffs"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

rvdffs.fir

@@ -0,0 +1,78 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit rvdffs : 
+  module rvdffs : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip din : UInt<32>, flip en : UInt<1>, flip clear : UInt<1>, out : UInt}
+    
+    wire _T : UInt<1>[32] @[el2_lib.scala 40:24]
+    _T[0] <= io.clear @[el2_lib.scala 40:24]
+    _T[1] <= io.clear @[el2_lib.scala 40:24]
+    _T[2] <= io.clear @[el2_lib.scala 40:24]
+    _T[3] <= io.clear @[el2_lib.scala 40:24]
+    _T[4] <= io.clear @[el2_lib.scala 40:24]
+    _T[5] <= io.clear @[el2_lib.scala 40:24]
+    _T[6] <= io.clear @[el2_lib.scala 40:24]
+    _T[7] <= io.clear @[el2_lib.scala 40:24]
+    _T[8] <= io.clear @[el2_lib.scala 40:24]
+    _T[9] <= io.clear @[el2_lib.scala 40:24]
+    _T[10] <= io.clear @[el2_lib.scala 40:24]
+    _T[11] <= io.clear @[el2_lib.scala 40:24]
+    _T[12] <= io.clear @[el2_lib.scala 40:24]
+    _T[13] <= io.clear @[el2_lib.scala 40:24]
+    _T[14] <= io.clear @[el2_lib.scala 40:24]
+    _T[15] <= io.clear @[el2_lib.scala 40:24]
+    _T[16] <= io.clear @[el2_lib.scala 40:24]
+    _T[17] <= io.clear @[el2_lib.scala 40:24]
+    _T[18] <= io.clear @[el2_lib.scala 40:24]
+    _T[19] <= io.clear @[el2_lib.scala 40:24]
+    _T[20] <= io.clear @[el2_lib.scala 40:24]
+    _T[21] <= io.clear @[el2_lib.scala 40:24]
+    _T[22] <= io.clear @[el2_lib.scala 40:24]
+    _T[23] <= io.clear @[el2_lib.scala 40:24]
+    _T[24] <= io.clear @[el2_lib.scala 40:24]
+    _T[25] <= io.clear @[el2_lib.scala 40:24]
+    _T[26] <= io.clear @[el2_lib.scala 40:24]
+    _T[27] <= io.clear @[el2_lib.scala 40:24]
+    _T[28] <= io.clear @[el2_lib.scala 40:24]
+    _T[29] <= io.clear @[el2_lib.scala 40:24]
+    _T[30] <= io.clear @[el2_lib.scala 40:24]
+    _T[31] <= io.clear @[el2_lib.scala 40:24]
+    node _T_1 = cat(_T[0], _T[1]) @[Cat.scala 29:58]
+    node _T_2 = cat(_T_1, _T[2]) @[Cat.scala 29:58]
+    node _T_3 = cat(_T_2, _T[3]) @[Cat.scala 29:58]
+    node _T_4 = cat(_T_3, _T[4]) @[Cat.scala 29:58]
+    node _T_5 = cat(_T_4, _T[5]) @[Cat.scala 29:58]
+    node _T_6 = cat(_T_5, _T[6]) @[Cat.scala 29:58]
+    node _T_7 = cat(_T_6, _T[7]) @[Cat.scala 29:58]
+    node _T_8 = cat(_T_7, _T[8]) @[Cat.scala 29:58]
+    node _T_9 = cat(_T_8, _T[9]) @[Cat.scala 29:58]
+    node _T_10 = cat(_T_9, _T[10]) @[Cat.scala 29:58]
+    node _T_11 = cat(_T_10, _T[11]) @[Cat.scala 29:58]
+    node _T_12 = cat(_T_11, _T[12]) @[Cat.scala 29:58]
+    node _T_13 = cat(_T_12, _T[13]) @[Cat.scala 29:58]
+    node _T_14 = cat(_T_13, _T[14]) @[Cat.scala 29:58]
+    node _T_15 = cat(_T_14, _T[15]) @[Cat.scala 29:58]
+    node _T_16 = cat(_T_15, _T[16]) @[Cat.scala 29:58]
+    node _T_17 = cat(_T_16, _T[17]) @[Cat.scala 29:58]
+    node _T_18 = cat(_T_17, _T[18]) @[Cat.scala 29:58]
+    node _T_19 = cat(_T_18, _T[19]) @[Cat.scala 29:58]
+    node _T_20 = cat(_T_19, _T[20]) @[Cat.scala 29:58]
+    node _T_21 = cat(_T_20, _T[21]) @[Cat.scala 29:58]
+    node _T_22 = cat(_T_21, _T[22]) @[Cat.scala 29:58]
+    node _T_23 = cat(_T_22, _T[23]) @[Cat.scala 29:58]
+    node _T_24 = cat(_T_23, _T[24]) @[Cat.scala 29:58]
+    node _T_25 = cat(_T_24, _T[25]) @[Cat.scala 29:58]
+    node _T_26 = cat(_T_25, _T[26]) @[Cat.scala 29:58]
+    node _T_27 = cat(_T_26, _T[27]) @[Cat.scala 29:58]
+    node _T_28 = cat(_T_27, _T[28]) @[Cat.scala 29:58]
+    node _T_29 = cat(_T_28, _T[29]) @[Cat.scala 29:58]
+    node _T_30 = cat(_T_29, _T[30]) @[Cat.scala 29:58]
+    node _T_31 = cat(_T_30, _T[31]) @[Cat.scala 29:58]
+    node _T_32 = and(io.din, _T_31) @[el2_ifu_ic_mem.scala 93:30]
+    reg _T_33 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when io.en : @[Reg.scala 28:19]
+      _T_33 <= _T_32 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.out <= _T_33 @[el2_ifu_ic_mem.scala 93:10]
+    

rvdffs.v

@@ -0,0 +1,70 @@
+module rvdffs(
+  input         clock,
+  input         reset,
+  input  [31:0] io_din,
+  input         io_en,
+  input         io_clear,
+  output [31:0] io_out
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+  wire [9:0] _T_9 = {io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
+  wire [18:0] _T_18 = {_T_9,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
+  wire [27:0] _T_27 = {_T_18,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
+  wire [31:0] _T_31 = {_T_27,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58]
+  wire [31:0] _T_32 = io_din & _T_31; // @[el2_ifu_ic_mem.scala 93:30]
+  reg [31:0] _T_33; // @[Reg.scala 27:20]
+  assign io_out = _T_33; // @[el2_ifu_ic_mem.scala 93:10]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  _T_33 = _RAND_0[31:0];
+`endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock) begin
+    if (reset) begin
+      _T_33 <= 32'h0;
+    end else if (io_en) begin
+      _T_33 <= _T_32;
+    end
+  end
+endmodule

src/main/scala/dec/el2_dec_dec_ctl.scala

@@ -168,6 +168,6 @@ class el2_dec_dec_ctl extends Module{
     pattern(List(-6,4,-3,-2,1,0)).reduce(_&_)
 }
 
-object dec extends App {
+//object dec extends App {
-  println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl()))
-}
+//}

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -0,0 +1,19 @@
+package ifu
+
+import lib._
+import chisel3._
+import chisel3.util._
+
+class el2_ifu_bp_ctl extends Module with el2_lib {
+  val io = IO (new Bundle {
+    val in = Input(UInt(32.W))
+    val in2 = Input(UInt(32.W))
+    val out = Output(UInt())
+  })
+  io.out := el2_btb_ghr_hash(io.in,io.in2)
+}
+
+//object ifu_ic extends App {
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
+//}
+

src/main/scala/ifu/el2_ifu_ic_mem.scala

@@ -0,0 +1,226 @@
+package ifu
+import lib._
+import chisel3._
+import chisel3.util._
+
+class el2_ifu_ic_mem extends Module with param{
+  val io = IO(new Bundle{
+    val clk = Input(Bool())
+    val rst_l = Input(Bool())
+    val clk_override = Input(Bool())
+    val dec_tlu_core_ecc_disable = Input(Bool())
+    val ic_rw_addr = Input(UInt(31.W))
+    val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_en = Input(Bool())
+    val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
+    val ic_debug_rd_en = Input(Bool())
+    val ic_debug_wr_en = Input(Bool())
+    val ic_debug_tag_array = Input(Bool())
+    val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_premux_data = Input(UInt(64.W))
+    val ic_sel_premux_data = Input(Bool())
+    val ic_wr_data = Vec(ICACHE_BANKS_WAY, Input(UInt(71.W)))
+    val ic_rd_data = Output(UInt(64.W))
+    val ic_debug_rd_data = Output(UInt(71.W))
+    val ictag_debug_rd_data = Output(UInt(26.W))
+    val ic_debug_wr_data = Input(UInt(71.W))
+    val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
+    val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W))
+    val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_perr = Output(Bool())
+    val scan_mode = Input(Bool())
+  })
+  io.ic_tag_perr := 0.U
+  io.ic_rd_hit := 0.U
+  io.ic_parerr := 0.U
+  io.ic_eccerr := 0.U
+  io.ictag_debug_rd_data := 0.U
+  io.ic_debug_rd_data := 0.U
+  io.ic_rd_data := 0.U
+  //val icache_tag = Module(new kncpa)
+}
+
+/////////// ICACHE TAG
+class EL2_IC_TAG extends Module with el2_lib with param {
+  val io = IO(new Bundle{
+    val clk = Input(Bool())
+    val rst_l = Input(Bool())
+    val clk_override = Input(Bool())
+    val dec_tlu_core_ecc_disable = Input(Bool())
+    val ic_rw_addr = Input(UInt(32.W))  // TODO : In SV we have 31:3 what should we do here
+    val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_en = Input(Bool())
+    val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+1).W))
+    val ic_debug_rd_en = Input(Bool())
+    val ic_debug_wr_en = Input(Bool())
+    val ic_debug_tag_array = Input(Bool())
+    val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ictag_debug_rd_data = Output(UInt(26.W))
+    val ic_debug_wr_data = Input(UInt(71.W))
+    val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_perr = Output(Bool())
+    val scan_mode = Input(Bool())
+
+    val test = Output(UInt(26.W))
+    val test_ecc_data_out = Output(Vec(ICACHE_NUM_WAYS,UInt(32.W)))
+    val test_ecc_out = Output(Vec(ICACHE_NUM_WAYS,UInt(7.W)))
+    val test_ecc_sb_out = Output(Vec(ICACHE_NUM_WAYS,UInt(1.W)))
+    val test_ecc_db_out = Output(Vec(ICACHE_NUM_WAYS,UInt(1.W)))
+  })
+
+  val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)===
+    repl(ICACHE_NUM_WAYS-1, 1.U))
+  val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
+  val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
+  val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en |
+    ic_debug_rd_way_en
+  val ic_rd_en_ff = RegNext(io.ic_rd_en, init=0.U)
+  val ic_rw_addr_ff = RegNext(io.ic_rw_addr, init=0.U)
+  val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
+  val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
+  val ic_tag_ecc = Wire(UInt(7.W))
+  val ic_tag_wr_data = Wire(UInt(26.W))
+  val ic_tag_parity = Wire(UInt(1.W))
+  ic_tag_ecc := 0.U
+  ic_tag_wr_data := 0.U
+  ic_tag_parity := 0.U
+  when((ICACHE_TAG_LO == 11).B){
+      when(ICACHE_ECC.B){
+      ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO)))
+      ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
+        Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
+        Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO)))
+        }
+      .otherwise{
+        ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO))
+        ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
+          Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
+          Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO)))
+        }
+    }
+
+    .otherwise{
+      when(ICACHE_ECC.B){
+        ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO)))
+        ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
+          Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
+          Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO)))
+      }
+        .otherwise{
+          ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO))
+          ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
+            Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
+            Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO)))
+        }
+      }
+
+  val ic_rw_addr_q = Mux(io.ic_debug_rd_en | io.ic_debug_wr_en,
+    io.ic_debug_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO),
+    io.ic_rw_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO))
+
+  val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
+
+  val ic_way_tag = if(ICACHE_ECC) SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W)))
+  else SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W)))
+  //val ic_tag_data_raw = if(ICACHE_ECC) Vec(ICACHE_NUM_WAYS, UInt(26.W)) else Vec(ICACHE_NUM_WAYS, UInt(22.W))
+
+  val write_data = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wr_data)
+
+  val mem_mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wren_q(i) & ic_tag_clken(i))
+
+  ic_way_tag.write(ic_rw_addr_q, write_data, mem_mask)
+
+  val ic_tag_data_raw = ic_way_tag.read(ic_rw_addr_q, 1.B)
+  //val w_tout = Wire(UInt(32.W))
+  val w_tout = if(ICACHE_ECC)ic_tag_data_raw.map(x=>Cat(ic_tag_data_raw(x)(25,21),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W)))
+  else ic_tag_data_raw.map(x=>Cat(0.U(4.W),ic_tag_data_raw(x)(32),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W)))
+
+  val ecc_decode = new Array[rvecc_decode](ICACHE_NUM_WAYS)
+  val parcheck = new Array[UInt](ICACHE_NUM_WAYS)
+  val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W)))
+  val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W)))
+  val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
+  val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
+
+  val ic_tag_way_perr = VecInit.tabulate(ICACHE_NUM_WAYS)(i => rveven_paritycheck(w_tout(i)(31,ICACHE_TAG_LO),w_tout(i)(31)))
+  for(i <- 0 until ICACHE_NUM_WAYS) {
+    ecc_decode(i) = Module(new rvecc_decode())
+    ecc_decode(i).io.en := ~io.dec_tlu_core_ecc_disable & ic_rd_en_ff
+    ecc_decode(i).io.sed_ded := 1.U
+    ecc_decode(i).io.din := Cat(0.U(11.W),ic_tag_data_raw(i)(20,0))
+    ecc_decode(i).io.ecc_in := Cat(0.U(2.W),ic_tag_data_raw(i)(25,21))
+
+    ic_tag_corrected_data_unc := io.test_ecc_data_out
+    ic_tag_corrected_ecc_unc := io.test_ecc_out
+    ic_tag_single_ecc_error := io.test_ecc_sb_out
+    ic_tag_double_ecc_error := io.test_ecc_db_out
+
+    io.test_ecc_data_out(i) := ecc_decode(i).io.dout
+    io.test_ecc_out(i) := ecc_decode(i).io.ecc_out
+    io.test_ecc_sb_out(i) := ecc_decode(i).io.single_ecc_error
+    io.test_ecc_db_out(i) := ecc_decode(i).io.double_ecc_error
+
+    ic_tag_way_perr(i) := ic_tag_single_ecc_error(i) | ic_tag_double_ecc_error(i)
+  }
+  val temp = if(ICACHE_ECC)
+    VecInit.tabulate(ICACHE_NUM_WAYS)(i=>repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)).reduce(_|_)
+  else
+    VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(0.U(4.W),repl(22,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i))).reduce(_|_)
+
+    for(i <- 0 until ICACHE_NUM_WAYS){
+      repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)
+    }
+  io.ictag_debug_rd_data := temp
+    io.test := w_tout.reduce(_&_)
+  io.ic_tag_perr := (ic_tag_way_perr.reduce(Cat(_,_)) & io.ic_tag_valid).orR
+  val w_tout_Vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=> w_tout(i))
+  io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reduce(Cat(_,_))
+}
+
+
+
+class EL2_IC_DATA extends Module with param{
+  val io = IO (new Bundle{
+    val rst_l = Input(UInt(1.W))
+    val clk_override = Input(UInt(1.W))
+    val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W))
+    val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_en = Input(UInt(1.W))
+    val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W)))
+    val ic_rd_data = Output(UInt(64.W))
+    val ic_debug_wr_data = Input(UInt(71.W))
+    val ic_debug_rd_data = Output(UInt(71.W))
+    val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
+    val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+3).W))
+    val ic_debug_rd_en = Input(UInt(1.W))
+    val ic_debug_wr_en = Input(UInt(1.W))
+    val ic_debug_tag_array = Input(UInt(1.W))
+    val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_premux_data = Input(UInt(64.W))
+    val ic_sel_premux_data = Input(UInt(1.W))
+    val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
+    val scan_mode = Input(UInt(1.W))
+    val mask = Input(Vec(2,Vec(2,Bool())))
+  })
+
+
+  // val data_memory = VecInit.tabulate(ICACHE_BANKS_WAY)(i => SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))))
+  // SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W)))
+  val mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>1.U)
+  val data_mem = (SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))), SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))))
+  data_mem(0).write(io.ic_rw_addr,io.ic_wr_data,mask)
+//  ic_memory.write(io.ic_rw_addr, io.ic_wr_data, io.mask)
+  io.ic_debug_rd_data := 0.U
+  io.ic_rd_data := 0.U
+  io.ic_eccerr := 0.U
+  io.ic_parerr := 0.U
+
+
+}
+
+object ifu_ic extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA()))
+}

src/main/scala/ifu/test.sc

@@ -0,0 +1 @@
+val a = 5

src/main/scala/lib/GCD.scala

@@ -0,0 +1,123 @@
+package lib
+
+import chisel3._
+import chisel3.util._
+/*
+///////////////////////////////////////////////////////////////
+class rvdff(val Width:Int = 1, val short:Int = 0) extends Module with RequireAsyncReset {
+  val io = IO(new Bundle {
+    val in = Input(UInt(Width.W))
+    val out = Output(UInt())
+  })
+  val inter = if(short==0) RegNext(io.in, init =0.U) else io.in
+  io.out := inter
+}
+
+/////////////////////////////////////////////////////////////
+class caller extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(32.W))
+    val out = Output(UInt())
+  })
+  val u0 = Module(new rvdff(32))
+  io <> u0.io
+}
+
+///////////////////////////////////////////////////////////////
+class reg1 extends Module with RequireAsyncReset{
+  val io = IO(new Bundle{
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
+
+  io.out := RegNext(io.in, init = 0.U)
+}
+
+class top extends Module with RequireAsyncReset{
+  val io = IO(new Bundle{
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
+  val negReset = (~reset.asBool).asAsyncReset
+  val r0 = Module(new reg1)
+  r0.io<>io
+  r0.reset := negReset
+}
+///////////////////////////////////////////////////////////////
+class rvbradder() extends Module {
+  val io = IO(new Bundle {
+    val pc = Input(UInt(31.W))
+    val offset = Input(UInt(12.W))
+    val dout = Output(UInt())
+  })
+  val inter = io.pc(11,0) +& io.offset
+  val cout = inter(inter.getWidth-1)
+  val pc_inc = io.pc(io.pc.getWidth-1, 12) + 1.U
+  val pc_dec = io.pc(io.pc.getWidth-1, 12) - 1.U
+  val sign = io.offset(io.offset.getWidth -1)
+
+  io.dout:= Cat(Fill(19,(sign ^(~cout))) & io.pc(io.pc.getWidth-1,12) |
+    (Fill(19,(~sign & cout)) & pc_inc) |
+    (Fill(19,(sign & ~cout)) & pc_dec) , inter(inter.getWidth-2,0))
+}
+
+///////////////////////////////////////////////////////////////
+class encoder_generator(val width:Int=4) extends Module {
+  val io = IO (new Bundle {
+    val in = Input (UInt(width.W))
+    val out = Output (UInt(log2Ceil(width).W))
+  })
+  var z:Array[UInt] = new Array[UInt](width)
+  for(i<- 0 until width){
+    z(i) = i.U
+  }
+  io.out := Mux1H(io.in , z)
+}
+
+///////////////////////////////////////////////////////////////
+class rvrangecheck(val CCM_SADR:Int = 0, val CCM_SIZE:Int = 128) extends Module {
+  val io = IO(new Bundle {
+    val addr = Input(UInt(32.W))
+    val in_range = Output(Bool())
+    val in_region = Output(Bool())
+    //val test = Output(UInt())
+  })
+  val start_addr = (CCM_SADR.U)(32.W)
+  val region = start_addr(31,28)
+  val MASK_BITS = 10+log2Ceil(CCM_SIZE)
+  io.in_region := io.addr(31,28) === region
+  val inter = if(CCM_SIZE == 48) io.addr(31, MASK_BITS) === start_addr(31, MASK_BITS) & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR)
+  else (io.addr(31,MASK_BITS)===start_addr(31,MASK_BITS))
+  io.in_range := inter
+}
+
+
+
+////////////////////////////////////////////////////////////////
+class tocopy extends Module{
+  val io = IO(new Bundle {
+    val in1 = Input(UInt(1.W))
+    val in2 = Input(UInt(1.W))
+    val out = Output(UInt())
+  })
+  io.out := io.in1 +& io.in2
+}
+class exp extends Module{
+  val io = IO(new Bundle{
+    val in1 = Input(UInt(1.W))
+    val in2 = Input(UInt(1.W))
+    val out = Output(UInt())
+  })
+
+  val mod_array= new Array[tocopy](2)
+  mod_array(0) = Module(new tocopy)
+  mod_array(0).io.in1:=io.in1
+  mod_array(0).io.in2:=io.in2
+  mod_array(1) = Module(new tocopy)
+  mod_array(1).io.in1:=io.in1
+  mod_array(1).io.in2:=io.in2
+  io.out:= mod_array(0).io.out +& mod_array(1).io.out
+}
+////////////////////////////////////////////////////////////////
+
+//println((new chisel3.stage.ChiselStage).emitVerilog(new exp))*/

src/main/scala/lib/beh_lib.scala

@@ -21,6 +21,42 @@ class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
 
 
 class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module{  //Done for verification and testing
+
+class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
+ val io = IO(new Bundle{
+val din  = Input(UInt(WIDTH.W))
+val dout = Output(UInt(WIDTH.W))
+})
+
+val flop = RegNext(io.din,0.U)
+
+if(SHORT == 1)
+{io.dout := io.din}
+else
+{io.dout := flop}
+}
+
+class rvdffsc extends Module with el2_lib {
+  val io = IO(new Bundle{
+    val din = Input(UInt(32.W))
+    val en = Input(Bool())
+    val clear = Input(Bool())
+    val out = Output(UInt())
+  })
+  io.out := RegEnable(io.din & repl(io.din.getWidth, io.clear), 0.U, io.en)
+}
+
+class rvdffs extends Module with el2_lib {
+  val io = IO(new Bundle{
+    val din = Input(UInt(32.W))
+    val en = Input(Bool())
+    val clear = Input(Bool())
+    val out = Output(UInt())
+  })
+  io.out := RegEnable(io.din, 0.U, io.en)
+}
+
+class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{  //Done for verification and testing
   val io = IO(new Bundle{
     val din   = Input(UInt(WIDTH.W))
     val dout  = Output(UInt(WIDTH.W))
@@ -31,6 +67,9 @@ class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module{  //Done for verifi
   {io.dout := io.din   }
   else
   {io.dout := sync_ff2 }
+  {	io.dout := io.din   }
+  else
+  {	io.dout := sync_ff2 }
 }
 
 
@@ -335,10 +374,239 @@ class rvbsadder extends Module{   //Done for verification and testing
     cg.io.scan_mode := scan_mode
     cg.io.l1clk
   }
+
+
+class rvbsadder extends Module{   //Done for verification and testing
+  val io = IO(new Bundle{
+    val pc     = Input(UInt(32.W)) // lsb is not using in code
+    val offset = Input(UInt(13.W)) // lsb is not using in code
+    val dout   = Output(UInt(31.W))
+  })
+  val w1 =  Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1))  //w1[12] =cout  offset[12]=sign
+
+  val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))&  io.pc(31,13))       |
+    ((Fill(19, ~io.offset(12) ^  w1(12))) & (io.pc(31,13)+1.U)) |
+    ((Fill(19, io.offset(12) ^  ~w1(12))) & (io.pc(31,13)-1.U))
+  io.dout := Cat(dout_upper,w1(11,0))
 }
 
 
 
+
+class rvtwoscomp(WIDTH:Int=32) extends Module{   //Done for verification and testing
+  val io = IO(new Bundle{
+    val din   = Input(UInt(WIDTH.W))
+    val dout  = Output(UInt(WIDTH.W))
+  })
+
+
+  val temp = Wire(Vec(WIDTH-1,UInt(1.W)))
+  val i:Int = 1
+
+  for(i <- 1 to WIDTH-1){
+    val done  = io.din(i-1,0).orR
+    temp(i-1) := Mux(done ,~io.din(i),io.din(i))
+  }
+  io.dout := Cat(temp.asUInt,io.din(0))
+}
+
+
+class rvmaskandmatch(WIDTH:Int=32) extends Module{     //Done for verification and testing
+  val io = IO(new Bundle{
+    val mask       = Input(UInt(WIDTH.W))
+    val data       = Input(UInt(WIDTH.W))
+    val masken     = Input(UInt(1.W))
+    val match_out  = Output(UInt(1.W))
+  })
+
+  val matchvec = Wire(Vec(WIDTH,UInt(1.W)))
+  val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR
+
+  matchvec(0)  :=  masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt
+
+  for(i <- 1 to WIDTH-1)
+  {matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)}
+  io.match_out := matchvec.asUInt
+}
+
+
+
+
+class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
+  val io = IO(new Bundle{
+    val addr       =  Input(UInt(32.W))
+    val in_range   =  Output(UInt(1.W))
+    val in_region  =  Output(UInt(1.W))
+  })
+  val REGION_BITS = 4
+  val MASK_BITS   = 10 + log2Ceil(CCM_SIZE)
+
+  val start_addr  = Wire(UInt(32.W))
+  start_addr  := CCM_SIZE.U
+  val region  = start_addr(31,(32-REGION_BITS))
+
+  io.in_region  := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
+  if(CCM_SIZE == 48)
+    io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
+  else
+    io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
+}
+
+
+
+// DONE
+class rveven_paritygen(WIDTH:Int= 16) extends Module{    //Done for verification and testing
+  val io = IO(new Bundle{
+    val data_in        =  Input (UInt(WIDTH.W))
+    val parity_out     =  Output(UInt(1.W))
+  })
+  io.parity_out := io.data_in.xorR.asUInt
+} // DONE
+
+
+// DONE
+class rveven_paritycheck(WIDTH:Int= 16) extends Module{    //Done for verification and testing
+  val io = IO(new Bundle{
+    val data_in        =  Input (UInt(WIDTH.W))
+    val parity_in      =  Input (UInt(1.W))
+    val parity_err     =  Output(UInt(1.W))
+  })
+  io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in
+} // DONE
+
+
+
+class rvecc_encode extends Module{   //Done for verification and testing
+  val io      =  IO(new Bundle{
+    val din     =  Input(UInt(32.W))
+    val ecc_out =  Output(UInt(7.W))
+  })
+  val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
+  val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
+  val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
+  val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
+  val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
+  val w0 = Wire(Vec(18,UInt(1.W)))
+  val w1 = Wire(Vec(18,UInt(1.W)))
+  val w2 = Wire(Vec(18,UInt(1.W)))
+  val w3 = Wire(Vec(15,UInt(1.W)))
+  val w4 = Wire(Vec(15,UInt(1.W)))
+  val w5 = Wire(Vec(6, UInt(1.W)))
+  var j = 0;var k = 0;var m = 0;
+  var x = 0;var y = 0;var z = 0
+
+  for(i <- 0 to 31)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 }
+    if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
+    if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
+  }
+  val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
+  io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
+}
+
+
+// Make generator and then make it a method
+class rvecc_decode extends Module{  //Done for verification and testing
+  val io      =  IO(new Bundle{
+    val en      =  Input(UInt(1.W))
+    val din     =  Input(UInt(32.W))
+    val ecc_in  =  Input(UInt(7.W))
+    val sed_ded =  Input(UInt(1.W))
+    val ecc_out =  Output(UInt(7.W))
+    val dout    =  Output(UInt(32.W))
+    val single_ecc_error = Output(UInt(1.W))
+    val double_ecc_error = Output(UInt(1.W))
+  })
+  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
+  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
+  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
+  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
+
+  val w0 = Wire(Vec(18,UInt(1.W)))
+  val w1 = Wire(Vec(18,UInt(1.W)))
+  val w2 = Wire(Vec(18,UInt(1.W)))
+  val w3 = Wire(Vec(15,UInt(1.W)))
+  val w4 = Wire(Vec(15,UInt(1.W)))
+  val w5 = Wire(Vec(6,UInt(1.W)))
+
+  var j = 0;var k = 0;var m = 0;  var n =0;
+  var x = 0;var y = 0;
+
+  for(i <- 0 to 31)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+  }
+
+  val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
+  io.ecc_out := ecc_check
+
+  io.single_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
+  io.double_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
+  val error_mask = Wire(Vec(39,UInt(1.W)))
+
+  for(i <- 1 until 40){
+    error_mask(i-1) := ecc_check(5,0) === i.asUInt
+  }
+  val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0))
+  val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
+
+  io.dout :=  Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
+  io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
+}
+
+
+
+
+
+
+class rvecc_encode_64 extends Module{    //Done for verification and testing
+  val io      =  IO(new Bundle{
+    val din     =  Input(UInt(64.W))
+    val ecc_out =  Output(UInt(7.W))
+  })
+  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
+  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
+  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
+  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
+
+  val w0 = Wire(Vec(35,UInt(1.W)))
+  val w1 = Wire(Vec(35,UInt(1.W)))
+  val w2 = Wire(Vec(35,UInt(1.W)))
+  val w3 = Wire(Vec(31,UInt(1.W)))
+  val w4 = Wire(Vec(31,UInt(1.W)))
+  val w5 = Wire(Vec(31,UInt(1.W)))
+  val w6 = Wire(Vec(7, UInt(1.W)))
+
+  var j = 0;var k = 0;var m = 0; var n =0;
+  var x = 0;var y = 0;var z = 0
+
+  for(i <- 0 to 63)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+    if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
+  }
+  io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
+}
   ////Instantiation example///////////////Can be use if using class instead of function rvdffe
   class my_class extends Module{
     val io = IO(new Bundle {
@@ -363,6 +631,46 @@ object main extends App{
 
 
 
+class rvecc_decode_64 extends Module{     //Done for verification and testing
+  val io        =  IO(new Bundle{
+    val en        =  Input(UInt(1.W))
+    val din       =  Input(UInt(64.W))
+    val ecc_in    =  Input(UInt(7.W))
+    val ecc_error =  Output(UInt(1.W))
+  })
+  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
+  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
+  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
+  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
+
+  val w0 = Wire(Vec(35,UInt(1.W)))
+  val w1 = Wire(Vec(35,UInt(1.W)))
+  val w2 = Wire(Vec(35,UInt(1.W)))
+  val w3 = Wire(Vec(31,UInt(1.W)))
+  val w4 = Wire(Vec(31,UInt(1.W)))
+  val w5 = Wire(Vec(31,UInt(1.W)))
+  val w6 = Wire(Vec(7, UInt(1.W)))
+
+  var j = 0;var k = 0;var m = 0;  var n =0;
+  var x = 0;var y = 0;var z = 0
+
+  for(i <- 0 to 63)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+    if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
+  }
+
+  val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
+  io.ecc_error := io.en & (ecc_check(6,0) != 0.U)
+}
 
 
 

src/main/scala/lib/el2_lib.scala

@@ -0,0 +1,278 @@
+package lib
+import chisel3._
+import chisel3.util._
+trait param {
+  val BHT_ADDR_HI            = 9
+  val BHT_ADDR_LO            = 2
+  val BHT_ARRAY_DEPTH        = 256
+  val BHT_GHR_HASH_1         = false
+  val BHT_GHR_SIZE           = 8
+  val BHT_SIZE               = 512
+  val BTB_ADDR_HI            = 9
+  val BTB_ADDR_LO            = 2
+  val BTB_ARRAY_DEPTH        = 256
+  val BTB_BTAG_FOLD          = false
+  val BTB_BTAG_SIZE          = 5
+  val BTB_FOLD2_INDEX_HASH   = false
+  val BTB_INDEX1_HI          = 9
+  val BTB_INDEX1_LO          = 2
+  val BTB_INDEX2_HI          = 17
+  val BTB_INDEX2_LO          = 10
+  val BTB_INDEX3_HI          = 25
+  val BTB_INDEX3_LO          = 18
+  val BTB_SIZE               = 512
+  val BUILD_AHB_LITE         = false
+  val BUILD_AXI4             = true
+  val BUILD_AXI_NATIVE       = true
+  val BUS_PRTY_DEFAULT       = 3
+  val DATA_ACCESS_ADDR0      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR1      = 0xC0000000 //.U(32.W)
+  val DATA_ACCESS_ADDR2      = 0xA0000000 //.U(32.W)
+  val DATA_ACCESS_ADDR3      = 0x80000000 //.U(32.W)
+  val DATA_ACCESS_ADDR4      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR5      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR6      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR7      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ENABLE0    = 0x1 //.U(1.W)
+  val DATA_ACCESS_ENABLE1    = 0x1 //.U(1.W)
+  val DATA_ACCESS_ENABLE2    = 0x1 //.U(1.W)
+  val DATA_ACCESS_ENABLE3    = 0x1 //.U(1.W)
+  val DATA_ACCESS_ENABLE4    = 0x0 //.U(1.W)
+  val DATA_ACCESS_ENABLE5    = 0x0 //.U(1.W)
+  val DATA_ACCESS_ENABLE6    = 0x0 //.U(1.W)
+  val DATA_ACCESS_ENABLE7    = 0x0 //.U(1.W)
+  val DATA_ACCESS_MASK0      = 0x7FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK1      = 0x3FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK2      = 0x1FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK3      = 0x0FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK4      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK5      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK6      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK7      = 0xFFFFFFFF //.U(32.W)
+  val DCCM_BANK_BITS         = 0x2  //.U(3.W)
+  val DCCM_BITS              = 0x10 //.U(5.W)
+  val DCCM_BYTE_WIDTH        = 0x4  //.U(3.W)
+  val DCCM_DATA_WIDTH        = 0x20 //.U(6.W)
+  val DCCM_ECC_WIDTH         = 0x7  //.U(3.W)
+  val DCCM_ENABLE            = 0x1  //.U(1.W)
+  val DCCM_FDATA_WIDTH       = 0x27 //.U(6.W)
+  val DCCM_INDEX_BITS        = 0xC  //.U(4.W)
+  val DCCM_NUM_BANKS         = 0x04 //.U(5.W)
+  val DCCM_REGION            = 0xF  //.U(4.W)
+  val DCCM_SADR              = 0xF0040000
+  val DCCM_SIZE              = 0x040
+  val DCCM_WIDTH_BITS        = 0x2 //.U(2.W)
+  val DMA_BUF_DEPTH          = 0x5 //.U(3.W)
+  val DMA_BUS_ID             = 0x1 //.U(1.W)
+  val DMA_BUS_PRTY           = 0x2 //.U(2.W)
+  val DMA_BUS_TAG            = 0x1 //.U(4.W)
+  val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W)
+  val ICACHE_2BANKS          = 1
+  val ICACHE_BANK_BITS       = 1
+  val ICACHE_BANK_HI         = 3
+  val ICACHE_BANK_LO         = 3
+  val ICACHE_BANK_WIDTH      = 8
+  val ICACHE_BANKS_WAY       = 2
+  val ICACHE_BEAT_ADDR_HI    = 5
+  val ICACHE_BEAT_BITS       = 3
+  val ICACHE_DATA_DEPTH      = 512
+  val ICACHE_DATA_INDEX_LO   = 4
+  val ICACHE_DATA_WIDTH      = 64
+  val ICACHE_ECC             = true
+  val ICACHE_ENABLE          = true
+  val ICACHE_FDATA_WIDTH     = 71
+  val ICACHE_INDEX_HI        = 12
+  val ICACHE_LN_SZ           = 64
+  val ICACHE_NUM_BEATS       = 8
+  val ICACHE_NUM_WAYS        = 2
+  val ICACHE_ONLY            = false
+  val ICACHE_SCND_LAST       = 6
+  val ICACHE_SIZE            = 16
+  val ICACHE_STATUS_BITS     = 1
+  val ICACHE_TAG_DEPTH       = 128
+  val ICACHE_TAG_INDEX_LO    = 6
+  val ICACHE_TAG_LO          = 13
+  val ICACHE_WAYPACK         = false
+  val ICCM_BANK_BITS         = 2
+  val ICCM_BANK_HI           = 0x03  //.U(5.W)
+  val ICCM_BANK_INDEX_LO     = 0x04  //.U(5.W)
+  val ICCM_BITS              = 0x10  //.U(5.W)
+  val ICCM_ENABLE            = 0x1   //.U(1.W)
+  val ICCM_ICACHE            = 0x1   //.U(1.W)
+  val ICCM_INDEX_BITS        = 0xC   //.U(4.W)
+  val ICCM_NUM_BANKS         = 0x04  //.U(5.W)
+  val ICCM_ONLY              = 0x0   //.U(1.W)
+  val ICCM_REGION            = 0xE   //.U(4.W)
+  val ICCM_SADR              = 0xEE000000 //.U(32.W)
+  val ICCM_SIZE              = 0x040 //.U(10.W)
+  val IFU_BUS_ID             = 0x1   //.U(1.W)
+  val IFU_BUS_PRTY           = 0x2   //.U(2.W)
+  val IFU_BUS_TAG            = 0x3   //.U(4.W)
+  val INST_ACCESS_ADDR0      = 0x00000000 //.U(32.W)
+  val INST_ACCESS_ADDR1      = 0xC0000000 //.U(32.W)
+  val INST_ACCESS_ADDR2      = 0xA0000000 //.U(32.W)
+  val INST_ACCESS_ADDR3      = 0x80000000 //.U(32.W)
+  val INST_ACCESS_ADDR4      = 0x00000000 //.U(32.W)
+  val INST_ACCESS_ADDR5      = 0x00000000 //.U(32.W)
+  val INST_ACCESS_ADDR6      = 0x00000000 //.U(32.W)
+  val INST_ACCESS_ADDR7      = 0x00000000 //.U(32.W)
+  val INST_ACCESS_ENABLE0    = 0x1 //.U(1.W)
+  val INST_ACCESS_ENABLE1    = 0x1 //.U(1.W)
+  val INST_ACCESS_ENABLE2    = 0x1 //.U(1.W)
+  val INST_ACCESS_ENABLE3    = 0x1 //.U(1.W)
+  val INST_ACCESS_ENABLE4    = 0x0 //.U(1.W)
+  val INST_ACCESS_ENABLE5    = 0x0 //.U(1.W)
+  val INST_ACCESS_ENABLE6    = 0x0 //.U(1.W)
+  val INST_ACCESS_ENABLE7    = 0x0 //.U(1.W)
+  val INST_ACCESS_MASK0      = 0x7FFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK1      = 0x3FFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK2      = 0x1FFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK3      = 0x0FFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK4      = 0xFFFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK5      = 0xFFFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK6      = 0xFFFFFFFF //.U(32.W)
+  val INST_ACCESS_MASK7      = 0xFFFFFFFF //.U(32.W)
+  val LOAD_TO_USE_PLUS1      = 0x0 //.U(1.W)
+  val LSU2DMA                = 0x0 //.U(1.W)
+  val LSU_BUS_ID             = 0x1 //.U(1.W)
+  val LSU_BUS_PRTY           = 0x2 //.U(2.W)
+  val LSU_BUS_TAG            = 0x3 //.U(4.W)
+  val LSU_NUM_NBLOAD         = 0x04 //.U(5.W)
+  val LSU_NUM_NBLOAD_WIDTH   = 0x2  //.U(3.W)
+  val LSU_SB_BITS            = 0x10 //.U(5.W)
+  val LSU_STBUF_DEPTH        = 0x4  //.U(4.W)
+  val NO_ICCM_NO_ICACHE      = 0x0  //.U(1.W)
+  val PIC_2CYCLE             = 0x0  //.U(1.W)
+  val PIC_BASE_ADDR          = 0xF00C0000 //.U(32.W)
+  val PIC_BITS               = 0x0F  //.U(5.W)
+  val PIC_INT_WORDS          = 0x1   //.U(4.W)
+  val PIC_REGION             = 0xF   //.U(4.W)
+  val PIC_SIZE               = 0x020 //.U(9.W)
+  val PIC_TOTAL_INT          = 0x1F  //.U(8.W)
+  val PIC_TOTAL_INT_PLUS1    = 0x020 //.U(9.W)
+  val RET_STACK_SIZE         = 0x8   //.U(4.W)
+  val SB_BUS_ID              = 0x1   //.U(1.W)
+  val SB_BUS_PRTY            = 0x2   //.U(2.W)
+  val SB_BUS_TAG             = 0x1   //.U(4.W)
+  val TIMER_LEGAL_EN         = 0x1   //.U(1.W)
+
+}
+
+trait el2_lib extends param{
+  def el2_btb_tag_hash(pc : UInt) =
+    (VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1))).reduce(_^_)
+
+  def el2_btb_tag_hash_fold(pc : UInt) =
+    pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
+
+  def el2_btb_addr_hash(pc : UInt) =
+    if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
+    else pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX2_HI,BTB_INDEX2_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
+
+  def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =
+    if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
+    else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
+
+  def repl(b:Int, a:UInt) : UInt =
+    VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
+
+  def rveven_paritycheck(data_in:UInt, parity_in:UInt) : UInt =
+    (data_in.xorR.asUInt) ^ parity_in
+
+  def rveven_paritygen(data_in : UInt) =
+    data_in.xorR.asUInt
+
+  def memory_cal =
+    (ICACHE_WAYPACK, ICACHE_ECC) match{
+        case(false,false) => 68
+        case(false,true)  => 71
+        case(true,false)  => 68*ICACHE_NUM_WAYS
+        case(true,true)   => 71*ICACHE_NUM_WAYS
+    }
+
+  val data_mem_size : Int = memory_cal
+  // Move rvecc_encode to a proper trait
+  def rvecc_encode(din:UInt) = {   //Done for verification and testing
+    val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
+    val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
+    val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
+    val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
+    val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
+    val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
+    val w0 = Wire(Vec(18,UInt(1.W)))
+    val w1 = Wire(Vec(18,UInt(1.W)))
+    val w2 = Wire(Vec(18,UInt(1.W)))
+    val w3 = Wire(Vec(15,UInt(1.W)))
+    val w4 = Wire(Vec(15,UInt(1.W)))
+    val w5 = Wire(Vec(6, UInt(1.W)))
+    var j = 0;var k = 0;var m = 0;
+    var x = 0;var y = 0;var z = 0
+
+    for(i <- 0 to 31)
+    {
+      if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
+      if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
+      if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
+      if(mask3(i)==1) {w3(x) := din(i); x = x +1 }
+      if(mask4(i)==1) {w4(y) := din(i); y = y +1 }
+      if(mask5(i)==1) {w5(z) := din(i); z = z +1 }
+    }
+    val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
+    Cat(din.xorR ^ w6.xorR, w6)
+  }
+
+
+  class rvecc_decode extends Module{  //Done for verification and testing
+    val io      =  IO(new Bundle{
+      val en      =  Input(UInt(1.W))
+      val din     =  Input(UInt(32.W))
+      val ecc_in  =  Input(UInt(7.W))
+      val sed_ded =  Input(UInt(1.W))
+      val ecc_out =  Output(UInt(7.W))
+      val dout    =  Output(UInt(32.W))
+      val single_ecc_error = Output(UInt(1.W))
+      val double_ecc_error = Output(UInt(1.W))
+    })
+    val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
+    val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
+    val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
+    val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+    val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+    val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
+
+    val w0 = Wire(Vec(18,UInt(1.W)))
+    val w1 = Wire(Vec(18,UInt(1.W)))
+    val w2 = Wire(Vec(18,UInt(1.W)))
+    val w3 = Wire(Vec(15,UInt(1.W)))
+    val w4 = Wire(Vec(15,UInt(1.W)))
+    val w5 = Wire(Vec(6,UInt(1.W)))
+
+    var j = 0;var k = 0;var m = 0;  var n =0;
+    var x = 0;var y = 0;
+
+    for(i <- 0 to 31)
+    {
+      if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+      if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+      if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+      if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+      if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+      if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+    }
+
+    val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
+
+    io.single_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
+    io.double_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
+    val error_mask = Wire(Vec(39,UInt(1.W)))
+
+    for(i <- 1 until 40){
+      error_mask(i-1) := ecc_check(5,0) === i.asUInt
+    }
+    val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0))
+    val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
+
+    io.dout :=  Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
+    io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
+  }
+}

src/test/scala/lib/Tester.scala

@@ -3,7 +3,7 @@ import java.io.File
 
 import chisel3.iotesters
 import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
-
+/*
 class Tester(c: encoder_generator) extends PeekPokeTester(c) {
 
   poke(c.io.in, 1)
@@ -29,3 +29,4 @@ object GCDMain extends App {
     c => new Tester(c)
   }
 }
+*/

target/scala-2.12/classes/ifu/test.sc

@@ -0,0 +1 @@
+val a = 5