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This commit is contained in:
​Laraib Khan 2020-11-27 16:33:17 +05:00
parent ab0b53b11f
commit 9f7ddbee4c
78 changed files with 78844 additions and 21681 deletions
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113
axi4_to_ahb.anno.json Normal file
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@ -0,0 +1,113 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_araddr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arsize",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arprot"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1288
axi4_to_ahb.fir Normal file
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438
axi4_to_ahb.v Normal file
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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module axi4_to_ahb(
input clock,
input reset,
input io_scan_mode,
input io_bus_clk_en,
input io_clk_override,
input io_axi_awvalid,
input io_axi_awid,
input [31:0] io_axi_awaddr,
input [2:0] io_axi_awsize,
input [2:0] io_axi_awprot,
input io_axi_wvalid,
input [63:0] io_axi_wdata,
input [7:0] io_axi_wstrb,
input io_axi_wlast,
input io_axi_bready,
input io_axi_arvalid,
input io_axi_arid,
input [31:0] io_axi_araddr,
input [2:0] io_axi_arsize,
input [2:0] io_axi_arprot,
input io_axi_rready,
input [63:0] io_ahb_hrdata,
input io_ahb_hready,
input io_ahb_hresp,
output io_axi_awready,
output io_axi_wready,
output io_axi_bvalid,
output [1:0] io_axi_bresp,
output io_axi_bid,
output io_axi_arready,
output io_axi_rvalid,
output io_axi_rid,
output [31:0] io_axi_rdata,
output [1:0] io_axi_rresp,
output io_axi_rlast,
output [31:0] io_ahb_haddr,
output [2:0] io_ahb_hburst,
output io_ahb_hmastlock,
output [3:0] io_ahb_hprot,
output [2:0] io_ahb_hsize,
output [1:0] io_ahb_htrans,
output io_ahb_hwrite,
output [63:0] io_ahb_hwdata
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [63:0] _RAND_6;
reg [63:0] _RAND_7;
reg [63:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 63:29]
wire wrbuf_en = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 216:11]
reg wrbuf_vld; // @[Reg.scala 27:20]
reg wrbuf_data_vld; // @[Reg.scala 27:20]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 193:27]
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 194:30]
wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 196:20]
wire [2:0] master_opc = {{1'd0}, _T_28}; // @[axi4_to_ahb.scala 196:14]
wire _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 252:89]
wire _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 252:70]
wire _T_151 = ~_T_150; // @[axi4_to_ahb.scala 252:55]
wire wrbuf_data_en = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34]
wire _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 186:33]
wire wrbuf_rst = _T_150 & _T_8; // @[axi4_to_ahb.scala 186:31]
wire _T_11 = wrbuf_vld & _T_151; // @[axi4_to_ahb.scala 188:33]
wire _T_15 = wrbuf_data_vld & _T_151; // @[axi4_to_ahb.scala 189:37]
reg [31:0] wrbuf_addr; // @[Reg.scala 27:20]
wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 197:21]
reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 198:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
wire buf_clk = rvclkhdr_2_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11]
reg [63:0] buf_data; // @[Reg.scala 27:20]
wire ahbm_data_clk = rvclkhdr_5_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 425:12]
wire _T_60 = wrbuf_en | wrbuf_data_en; // @[axi4_to_ahb.scala 214:74]
wire _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire buf_data_wr_en = master_valid & _T_69; // @[axi4_to_ahb.scala 230:38]
wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16]
wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16]
wire [2:0] _T_103 = wrbuf_byteen[4] ? 3'h4 : _T_102; // @[Mux.scala 98:16]
wire [2:0] _T_104 = wrbuf_byteen[3] ? 3'h3 : _T_103; // @[Mux.scala 98:16]
wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16]
wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16]
wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16]
wire [2:0] buf_cmd_byte_ptr = _T_149 ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
wire [1:0] _T_113 = master_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61]
reg [31:0] buf_addr; // @[Reg.scala 27:20]
wire _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 331:24]
wire _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 330:51]
wire _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 331:57]
wire _T_544 = _T_541 | _T_543; // @[axi4_to_ahb.scala 331:36]
wire _T_546 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 331:91]
wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 331:70]
wire _T_549 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 332:25]
wire _T_551 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 332:62]
wire _T_553 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 332:97]
wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 332:74]
wire _T_556 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 332:132]
wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 332:109]
wire _T_559 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 332:168]
wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 332:145]
wire _T_562 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 333:28]
wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 332:181]
wire _T_565 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 333:63]
wire _T_566 = _T_563 | _T_565; // @[axi4_to_ahb.scala 333:40]
wire _T_568 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 333:99]
wire _T_569 = _T_566 | _T_568; // @[axi4_to_ahb.scala 333:76]
wire _T_570 = _T_549 & _T_569; // @[axi4_to_ahb.scala 332:38]
wire buf_aligned_in = _T_547 | _T_570; // @[axi4_to_ahb.scala 331:104]
wire _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 325:55]
wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 325:38]
wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58]
wire _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 329:38]
wire _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 329:72]
wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 329:21]
wire [31:0] _T_575 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_578 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_582 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_536}; // @[axi4_to_ahb.scala 329:15]
wire [1:0] _T_584 = _T_582 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 336:80]
wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
wire _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 340:33]
wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20]
wire [31:0] buf_addr_in = _T_490[31:0]; // @[axi4_to_ahb.scala 325:15]
wire _T_652 = master_valid & io_bus_clk_en; // @[axi4_to_ahb.scala 379:61]
wire _T_664 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 391:66]
wire _T_688 = master_valid | io_clk_override; // @[axi4_to_ahb.scala 428:58]
wire _T_691 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54]
wire _T_692 = _T_691 | io_clk_override; // @[axi4_to_ahb.scala 429:74]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
assign io_axi_awready = ~_T_11; // @[axi4_to_ahb.scala 188:18]
assign io_axi_wready = ~_T_15; // @[axi4_to_ahb.scala 189:17]
assign io_axi_bvalid = 1'h0; // @[axi4_to_ahb.scala 203:17]
assign io_axi_bresp = 2'h0; // @[axi4_to_ahb.scala 204:16]
assign io_axi_bid = 1'h0; // @[axi4_to_ahb.scala 205:14]
assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18]
assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17]
assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14]
assign io_axi_rdata = ahb_hrdata_q[31:0]; // @[axi4_to_ahb.scala 210:16]
assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16]
assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 338:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 339:20]
assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 340:16]
assign io_ahb_hsize = master_valid ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16]
assign io_ahb_htrans = _T_113 & 2'h2; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
assign io_ahb_hwrite = master_valid ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 342:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = io_bus_clk_en & _T_688; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_4_io_en = io_bus_clk_en & _T_692; // @[el2_lib.scala 485:16]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_5_io_en = io_bus_clk_en & io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
buf_nxtstate = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wrbuf_vld = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
wrbuf_data_vld = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
wrbuf_addr = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
wrbuf_size = _RAND_4[2:0];
_RAND_5 = {1{`RANDOM}};
wrbuf_byteen = _RAND_5[7:0];
_RAND_6 = {2{`RANDOM}};
wrbuf_data = _RAND_6[63:0];
_RAND_7 = {2{`RANDOM}};
buf_data = _RAND_7[63:0];
_RAND_8 = {2{`RANDOM}};
ahb_hrdata_q = _RAND_8[63:0];
_RAND_9 = {1{`RANDOM}};
buf_addr = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
buf_write = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
buf_nxtstate = 3'h0;
end
if (reset) begin
wrbuf_vld = 1'h0;
end
if (reset) begin
wrbuf_data_vld = 1'h0;
end
if (reset) begin
wrbuf_addr = 32'h0;
end
if (reset) begin
wrbuf_size = 3'h0;
end
if (reset) begin
wrbuf_byteen = 8'h0;
end
if (reset) begin
wrbuf_data = 64'h0;
end
if (reset) begin
buf_data = 64'h0;
end
if (reset) begin
ahb_hrdata_q = 64'h0;
end
if (reset) begin
buf_addr = 32'h0;
end
if (reset) begin
buf_write = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_nxtstate <= 3'h0;
end else if (_T_149) begin
buf_nxtstate <= 3'h2;
end else begin
buf_nxtstate <= 3'h1;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_vld <= 1'h0;
end else if (wrbuf_en) begin
wrbuf_vld <= wrbuf_rst;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_data_vld <= 1'h0;
end else if (wrbuf_data_en) begin
wrbuf_data_vld <= wrbuf_rst;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wrbuf_addr <= 32'h0;
end else if (wrbuf_en) begin
wrbuf_addr <= io_axi_awaddr;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_size <= 3'h0;
end else if (wrbuf_en) begin
wrbuf_size <= io_axi_awsize;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_byteen <= 8'h0;
end else if (wrbuf_data_en) begin
wrbuf_byteen <= io_axi_wstrb;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wrbuf_data <= 64'h0;
end else if (wrbuf_data_en) begin
wrbuf_data <= io_axi_wdata;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_data <= 64'h0;
end else if (_T_664) begin
buf_data <= wrbuf_data;
end
end
always @(posedge ahbm_data_clk or posedge reset) begin
if (reset) begin
ahb_hrdata_q <= 64'h0;
end else begin
ahb_hrdata_q <= io_ahb_hrdata;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_addr <= 32'h0;
end else if (_T_652) begin
buf_addr <= buf_addr_in;
end
end
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
buf_write <= 1'h0;
end else if (master_valid) begin
buf_write <= _T_149;
end
end
endmodule

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"sources":[
"~el2_dbg|el2_dbg>io_dma_dbg_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
"~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only",
"~el2_dbg|el2_dbg>io_dec_tlu_debug_mode",
"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"~el2_dbg|el2_dbg>io_core_dbg_cmd_done",
"~el2_dbg|el2_dbg>io_dmi_reg_wr_en",
"~el2_dbg|el2_dbg>io_dmi_reg_en",
"~el2_dbg|el2_dbg>io_dma_dbg_ready",
"~el2_dbg|el2_dbg>io_dmi_reg_addr",
"~el2_dbg|el2_dbg>reset"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dbg.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dbg"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd1",
"sources":[
"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd0",
"sources":[
"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr0"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dec_gpr_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_gpr_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_wdata_rs1_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_way",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_way"
]
},
{
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},
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]
},
{
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]
},
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"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc4"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_ib0_valid_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_valid",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid",
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]
},
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]
},
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr",
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"targetDir":"."
}
]

71
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_dec_ib_ctl :
module el2_dec_ib_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31]
io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31]
io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 10:31]
io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31]
io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31]
io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31]
io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31]
io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31]
io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 17:31]
node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 31:60]
node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 31:41]
node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 32:38]
node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 32:36]
node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 33:36]
node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 35:55]
node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 35:37]
node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 36:55]
node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 36:37]
node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 37:55]
node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 37:37]
node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 38:55]
node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 38:37]
node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 40:40]
node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 41:40]
node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 44:20]
node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 45:21]
node _T_11 = cat(UInt<3>("h06"), dreg) @[Cat.scala 29:58]
node _T_12 = cat(_T_11, UInt<6>("h033")) @[Cat.scala 29:58]
node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 46:20]
node _T_14 = cat(dcsr, UInt<14>("h02073")) @[Cat.scala 29:58]
node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 47:21]
node _T_16 = cat(dcsr, UInt<13>("h01073")) @[Cat.scala 29:58]
node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
ib0_debug_in <= _T_23 @[Mux.scala 27:72]
node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 51:47]
io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 51:28]
node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 54:51]
node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 54:43]
io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 54:24]
node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 56:41]
io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 56:22]
node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 57:41]
node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 57:28]
io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 57:22]

101
el2_dec_ib_ctl.v Normal file
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@ -0,0 +1,101 @@
module el2_dec_ib_ctl(
input clock,
input reset,
input io_dbg_cmd_valid,
input io_dbg_cmd_write,
input [1:0] io_dbg_cmd_type,
input [31:0] io_dbg_cmd_addr,
input io_i0_brp_valid,
input [11:0] io_i0_brp_bits_toffset,
input [1:0] io_i0_brp_bits_hist,
input io_i0_brp_bits_br_error,
input io_i0_brp_bits_br_start_error,
input io_i0_brp_bits_bank,
input [30:0] io_i0_brp_bits_prett,
input io_i0_brp_bits_way,
input io_i0_brp_bits_ret,
input [7:0] io_ifu_i0_bp_index,
input [7:0] io_ifu_i0_bp_fghr,
input [4:0] io_ifu_i0_bp_btag,
input io_ifu_i0_pc4,
input io_ifu_i0_valid,
input io_ifu_i0_icaf,
input [1:0] io_ifu_i0_icaf_type,
input io_ifu_i0_icaf_f1,
input io_ifu_i0_dbecc,
input [31:0] io_ifu_i0_instr,
input [30:0] io_ifu_i0_pc,
output io_dec_ib0_valid_d,
output [1:0] io_dec_i0_icaf_type_d,
output [31:0] io_dec_i0_instr_d,
output [30:0] io_dec_i0_pc_d,
output io_dec_i0_pc4_d,
output io_dec_i0_brp_valid,
output [11:0] io_dec_i0_brp_bits_toffset,
output [1:0] io_dec_i0_brp_bits_hist,
output io_dec_i0_brp_bits_br_error,
output io_dec_i0_brp_bits_br_start_error,
output io_dec_i0_brp_bits_bank,
output [30:0] io_dec_i0_brp_bits_prett,
output io_dec_i0_brp_bits_way,
output io_dec_i0_brp_bits_ret,
output [7:0] io_dec_i0_bp_index,
output [7:0] io_dec_i0_bp_fghr,
output [4:0] io_dec_i0_bp_btag,
output io_dec_i0_icaf_d,
output io_dec_i0_icaf_f1_d,
output io_dec_i0_dbecc_d,
output io_dec_debug_wdata_rs1_d,
output io_dec_debug_fence_d
);
wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60]
wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41]
wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38]
wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36]
wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36]
wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55]
wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37]
wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37]
wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55]
wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37]
wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37]
wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40]
wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40]
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58]
wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58]
wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58]
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72]
wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72]
wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72]
wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72]
wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72]
wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72]
wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72]
wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72]
wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72]
wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51]
assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22]
assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31]
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22]
assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31]
assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31]
assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_bank = io_i0_brp_bits_bank; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31]
assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31]
assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31]
assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31]
assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31]
assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31]
assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28]
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24]
endmodule

514
el2_dec_tlu_ctl.anno.json Normal file
View File

@ -0,0 +1,514 @@
[
{
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},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt0",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_leak_one_r",
"sources":[
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_path_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_npc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r",
"sources":[
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_hist",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_hist_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_err_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_valid",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_mp_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_pmu_i0_br_ataken"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_middle",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_middle_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dec_tlu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_tlu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

8160
el2_dec_tlu_ctl.fir Normal file
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7181
el2_dec_tlu_ctl.v Normal file
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14
el2_dec_trigger.anno.json
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@ -12,13 +12,13 @@
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select",
@ -26,6 +26,12 @@
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"

2638
el2_dec_trigger.fir
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File diff suppressed because it is too large Load Diff

1228
el2_dec_trigger.v
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115
el2_dma_ctrl.anno.json Normal file
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@ -0,0 +1,115 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dma_ctrl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dma_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2267
el2_dma_ctrl.fir Normal file
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2045
el2_dma_ctrl.v Normal file
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6
el2_ifu.fir
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@ -6187,9 +6187,9 @@ circuit el2_ifu :
node _T_2554 = and(_T_2552, _T_2553) @[el2_ifu_mem_ctl.scala 563:59]
node _T_2555 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 563:77]
node bus_cmd_req_in = and(_T_2554, _T_2555) @[el2_ifu_mem_ctl.scala 563:75]
reg _T_2556 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 564:49]
_T_2556 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 564:49]
bus_cmd_sent <= _T_2556 @[el2_ifu_mem_ctl.scala 564:16]
reg _T_2556 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 564:53]
_T_2556 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 564:53]
bus_cmd_req_hold <= _T_2556 @[el2_ifu_mem_ctl.scala 564:20]
io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 566:22]
node _T_2557 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
node _T_2558 = mux(_T_2557, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]

85
el2_ifu.v
View File

@ -570,13 +570,13 @@ module el2_ifu_mem_ctl(
reg [31:0] _RAND_447;
reg [31:0] _RAND_448;
reg [31:0] _RAND_449;
reg [63:0] _RAND_450;
reg [31:0] _RAND_451;
reg [31:0] _RAND_450;
reg [63:0] _RAND_451;
reg [31:0] _RAND_452;
reg [31:0] _RAND_453;
reg [31:0] _RAND_454;
reg [63:0] _RAND_455;
reg [31:0] _RAND_456;
reg [31:0] _RAND_455;
reg [63:0] _RAND_456;
reg [31:0] _RAND_457;
reg [31:0] _RAND_458;
reg [31:0] _RAND_459;
@ -590,6 +590,7 @@ module el2_ifu_mem_ctl(
reg [31:0] _RAND_467;
reg [31:0] _RAND_468;
reg [31:0] _RAND_469;
reg [31:0] _RAND_470;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
@ -3407,8 +3408,10 @@ module el2_ifu_mem_ctl(
wire _GEN_41 = _T_2481 ? _T_2499 : _GEN_37; // @[Conditional.scala 39:67]
wire _GEN_43 = _T_2481 | _GEN_39; // @[Conditional.scala 39:67]
wire err_stop_state_en = _T_2476 ? _T_2480 : _GEN_41; // @[Conditional.scala 40:58]
reg bus_cmd_req_hold; // @[el2_ifu_mem_ctl.scala 564:53]
wire _T_2541 = ic_act_miss_f | bus_cmd_req_hold; // @[el2_ifu_mem_ctl.scala 560:45]
reg ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 561:55]
wire _T_2542 = ic_act_miss_f | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:64]
wire _T_2542 = _T_2541 | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:64]
wire _T_2544 = _T_2542 & _T_2573; // @[el2_ifu_mem_ctl.scala 560:85]
reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20]
wire _T_2546 = bus_cmd_beat_count == 3'h7; // @[el2_ifu_mem_ctl.scala 560:133]
@ -3420,6 +3423,8 @@ module el2_ifu_mem_ctl(
wire _T_2567 = io_ifu_axi_arvalid & ifu_bus_arready; // @[el2_ifu_mem_ctl.scala 595:35]
wire _T_2568 = _T_2567 & miss_pending; // @[el2_ifu_mem_ctl.scala 595:53]
wire bus_cmd_sent = _T_2568 & _T_2573; // @[el2_ifu_mem_ctl.scala 595:68]
wire _T_2553 = ~bus_cmd_sent; // @[el2_ifu_mem_ctl.scala 563:61]
wire _T_2554 = _T_2541 & _T_2553; // @[el2_ifu_mem_ctl.scala 563:59]
wire [2:0] _T_2558 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_2560 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_2562 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
@ -6899,55 +6904,57 @@ initial begin
_RAND_444 = {1{`RANDOM}};
dma_sb_err_state_ff = _RAND_444[0:0];
_RAND_445 = {1{`RANDOM}};
ifu_bus_cmd_valid = _RAND_445[0:0];
bus_cmd_req_hold = _RAND_445[0:0];
_RAND_446 = {1{`RANDOM}};
bus_cmd_beat_count = _RAND_446[2:0];
ifu_bus_cmd_valid = _RAND_446[0:0];
_RAND_447 = {1{`RANDOM}};
ifu_bus_arready_unq_ff = _RAND_447[0:0];
bus_cmd_beat_count = _RAND_447[2:0];
_RAND_448 = {1{`RANDOM}};
ifu_bus_arvalid_ff = _RAND_448[0:0];
ifu_bus_arready_unq_ff = _RAND_448[0:0];
_RAND_449 = {1{`RANDOM}};
ifc_dma_access_ok_prev = _RAND_449[0:0];
_RAND_450 = {2{`RANDOM}};
iccm_ecc_corr_data_ff = _RAND_450[38:0];
_RAND_451 = {1{`RANDOM}};
dma_mem_addr_ff = _RAND_451[1:0];
ifu_bus_arvalid_ff = _RAND_449[0:0];
_RAND_450 = {1{`RANDOM}};
ifc_dma_access_ok_prev = _RAND_450[0:0];
_RAND_451 = {2{`RANDOM}};
iccm_ecc_corr_data_ff = _RAND_451[38:0];
_RAND_452 = {1{`RANDOM}};
dma_mem_tag_ff = _RAND_452[2:0];
dma_mem_addr_ff = _RAND_452[1:0];
_RAND_453 = {1{`RANDOM}};
iccm_dma_rtag_temp = _RAND_453[2:0];
dma_mem_tag_ff = _RAND_453[2:0];
_RAND_454 = {1{`RANDOM}};
iccm_dma_rvalid_temp = _RAND_454[0:0];
_RAND_455 = {2{`RANDOM}};
iccm_dma_rdata_temp = _RAND_455[63:0];
_RAND_456 = {1{`RANDOM}};
iccm_ecc_corr_index_ff = _RAND_456[13:0];
iccm_dma_rtag_temp = _RAND_454[2:0];
_RAND_455 = {1{`RANDOM}};
iccm_dma_rvalid_temp = _RAND_455[0:0];
_RAND_456 = {2{`RANDOM}};
iccm_dma_rdata_temp = _RAND_456[63:0];
_RAND_457 = {1{`RANDOM}};
iccm_rd_ecc_single_err_ff = _RAND_457[0:0];
iccm_ecc_corr_index_ff = _RAND_457[13:0];
_RAND_458 = {1{`RANDOM}};
iccm_rw_addr_f = _RAND_458[13:0];
iccm_rd_ecc_single_err_ff = _RAND_458[0:0];
_RAND_459 = {1{`RANDOM}};
ifu_status_wr_addr_ff = _RAND_459[6:0];
iccm_rw_addr_f = _RAND_459[13:0];
_RAND_460 = {1{`RANDOM}};
way_status_wr_en_ff = _RAND_460[0:0];
ifu_status_wr_addr_ff = _RAND_460[6:0];
_RAND_461 = {1{`RANDOM}};
way_status_new_ff = _RAND_461[0:0];
way_status_wr_en_ff = _RAND_461[0:0];
_RAND_462 = {1{`RANDOM}};
ifu_tag_wren_ff = _RAND_462[1:0];
way_status_new_ff = _RAND_462[0:0];
_RAND_463 = {1{`RANDOM}};
ic_valid_ff = _RAND_463[0:0];
ifu_tag_wren_ff = _RAND_463[1:0];
_RAND_464 = {1{`RANDOM}};
_T_9747 = _RAND_464[0:0];
ic_valid_ff = _RAND_464[0:0];
_RAND_465 = {1{`RANDOM}};
_T_9748 = _RAND_465[0:0];
_T_9747 = _RAND_465[0:0];
_RAND_466 = {1{`RANDOM}};
_T_9749 = _RAND_466[0:0];
_T_9748 = _RAND_466[0:0];
_RAND_467 = {1{`RANDOM}};
_T_9753 = _RAND_467[0:0];
_T_9749 = _RAND_467[0:0];
_RAND_468 = {1{`RANDOM}};
_T_9754 = _RAND_468[0:0];
_T_9753 = _RAND_468[0:0];
_RAND_469 = {1{`RANDOM}};
_T_9775 = _RAND_469[0:0];
_T_9754 = _RAND_469[0:0];
_RAND_470 = {1{`RANDOM}};
_T_9775 = _RAND_470[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
flush_final_f = 1'h0;
@ -8278,6 +8285,9 @@ initial begin
if (reset) begin
dma_sb_err_state_ff = 1'h0;
end
if (reset) begin
bus_cmd_req_hold = 1'h0;
end
if (reset) begin
ifu_bus_cmd_valid = 1'h0;
end
@ -11616,6 +11626,13 @@ end // initial
dma_sb_err_state_ff <= perr_state == 3'h4;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
bus_cmd_req_hold <= 1'h0;
end else begin
bus_cmd_req_hold <= _T_2554 & _T_2573;
end
end
always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin
if (reset) begin
ifu_bus_cmd_valid <= 1'h0;

2
el2_ifu_aln_ctl.fir
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@ -2284,7 +2284,7 @@ circuit el2_ifu_aln_ctl :
module el2_ifu_aln_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]

127
el2_ifu_ifc_ctl.anno.json Normal file
View File

@ -0,0 +1,127 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_dma_access_ok",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_region_acc_fault_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_uncacheable_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_mrac_ff",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_ifc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_ifc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

295
el2_ifu_ifc_ctl.fir Normal file
View File

@ -0,0 +1,295 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ifc_ctl :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module el2_ifu_ifc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<31>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next_0 : UInt<1>
fetch_addr_next_0 <= UInt<1>("h00")
wire fetch_addr_next : UInt<31>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<31> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24]
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39]
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:45]
_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:45]
state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
wire _T_130 : UInt<4> @[Mux.scala 27:72]
_T_130 <= _T_129 @[Mux.scala 27:72]
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 119:17]
idle <= _T_131 @[el2_ifu_ifc_ctl.scala 119:8]
node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 120:16]
wfm <= _T_132 @[el2_ifu_ifc_ctl.scala 120:7]
node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 122:30]
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctl.scala 122:16]
reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 123:52]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 123:52]
reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 124:50]
_T_134 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 124:50]
fb_write_f <= _T_134 @[el2_ifu_ifc_ctl.scala 124:14]
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 127:40]
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 127:61]
node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 127:19]
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctl.scala 127:17]
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctl.scala 127:84]
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctl.scala 126:60]
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctl.scala 126:33]
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctl.scala 126:26]
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 224:25]
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 224:47]
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 227:14]
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 227:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 132:25]
node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 133:30]
node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 134:39]
node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 134:18]
node _T_148 = and(fb_full_f, _T_147) @[el2_ifu_ifc_ctl.scala 134:16]
node _T_149 = or(_T_145, _T_148) @[el2_ifu_ifc_ctl.scala 133:53]
node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:13]
node _T_151 = and(wfm, _T_150) @[el2_ifu_ifc_ctl.scala 135:11]
node _T_152 = or(_T_149, _T_151) @[el2_ifu_ifc_ctl.scala 134:62]
node _T_153 = or(_T_152, idle) @[el2_ifu_ifc_ctl.scala 135:35]
node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:46]
node _T_155 = and(_T_153, _T_154) @[el2_ifu_ifc_ctl.scala 135:44]
node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 135:67]
io.ifc_dma_access_ok <= _T_156 @[el2_ifu_ifc_ctl.scala 133:24]
node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:33]
node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 137:55]
io.ifc_region_acc_fault_bf <= _T_158 @[el2_ifu_ifc_ctl.scala 137:30]
node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 138:78]
node _T_160 = cat(_T_159, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_161 = dshr(io.dec_tlu_mrac_ff, _T_160) @[el2_ifu_ifc_ctl.scala 138:53]
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_ifc_ctl.scala 138:53]
node _T_163 = not(_T_162) @[el2_ifu_ifc_ctl.scala 138:34]
io.ifc_fetch_uncacheable_bf <= _T_163 @[el2_ifu_ifc_ctl.scala 138:31]
reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 140:57]
_T_164 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 140:57]
io.ifc_fetch_req_f <= _T_164 @[el2_ifu_ifc_ctl.scala 140:22]
node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:73]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr.io.en <= _T_165 @[el2_lib.scala 511:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_166 <= io.ifc_fetch_addr_bf @[el2_lib.scala 514:16]
io.ifc_fetch_addr_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:23]

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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_ifu_ifc_ctl(
input clock,
input reset,
input io_free_clk,
input io_active_clk,
input io_scan_mode,
input io_ic_hit_f,
input io_ifu_ic_mb_empty,
input io_ifu_fb_consume1,
input io_ifu_fb_consume2,
input io_dec_tlu_flush_noredir_wb,
input io_exu_flush_final,
input [30:0] io_exu_flush_path_final,
input io_ifu_bp_hit_taken_f,
input [30:0] io_ifu_bp_btb_target_f,
input io_ic_dma_active,
input io_ic_write_stall,
input io_dma_iccm_stall_any,
input [31:0] io_dec_tlu_mrac_ff,
output [30:0] io_ifc_fetch_addr_f,
output [30:0] io_ifc_fetch_addr_bf,
output io_ifc_fetch_req_f,
output io_ifu_pmu_fetch_stall,
output io_ifc_fetch_uncacheable_bf,
output io_ifc_fetch_req_bf,
output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:45]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 119:17]
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 124:50]
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 122:30]
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 120:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 123:52]
wire _T_136 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 127:61]
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctl.scala 127:19]
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctl.scala 127:17]
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84]
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60]
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 224:47]
wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 227:29]
wire _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30]
wire _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16]
wire _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53]
wire _T_150 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 135:13]
wire _T_151 = wfm & _T_150; // @[el2_ifu_ifc_ctl.scala 135:11]
wire _T_152 = _T_149 | _T_151; // @[el2_ifu_ifc_ctl.scala 134:62]
wire _T_153 = _T_152 | idle; // @[el2_ifu_ifc_ctl.scala 135:35]
wire _T_155 = _T_153 & _T_2; // @[el2_ifu_ifc_ctl.scala 135:44]
wire _T_157 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 137:33]
wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53]
reg _T_164; // @[el2_ifu_ifc_ctl.scala 140:57]
reg [30:0] _T_166; // @[el2_lib.scala 514:16]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23]
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctl.scala 126:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[el2_ifu_ifc_ctl.scala 138:31]
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25]
assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30]
assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
dma_iccm_stall_any_f = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
miss_a = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
state = _RAND_2[1:0];
_RAND_3 = {1{`RANDOM}};
fb_write_f = _RAND_3[3:0];
_RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_164 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_166 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
dma_iccm_stall_any_f = 1'h0;
end
if (reset) begin
miss_a = 1'h0;
end
if (reset) begin
state = 2'h0;
end
if (reset) begin
fb_write_f = 4'h0;
end
if (reset) begin
fb_full_f = 1'h0;
end
if (reset) begin
_T_164 = 1'h0;
end
if (reset) begin
_T_166 = 31'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
dma_iccm_stall_any_f <= 1'h0;
end else begin
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
miss_a <= 1'h0;
end else begin
miss_a <= _T_48 & _T_2;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
state <= 2'h0;
end else begin
state <= {next_state_1,next_state_0};
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
fb_write_f <= 4'h0;
end else begin
fb_write_f <= _T_128 | _T_125;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
fb_full_f <= 1'h0;
end else begin
fb_full_f <= fb_write_ns[3];
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
_T_164 <= 1'h0;
end else begin
_T_164 <= io_ifc_fetch_req_bf;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_166 <= 31'h0;
end else begin
_T_166 <= io_ifc_fetch_addr_bf;
end
end
endmodule

357
el2_ifu_mem_ctl.anno.json Normal file
View File

@ -0,0 +1,357 @@
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{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wren",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_en",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_uncacheable_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_force_halt",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_premux_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_size",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_sz",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_en",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wr_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_dma_active",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_flush_err_wb",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_i0_commit_cmt",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_fetch_val",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_data_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_ready",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_tag_array",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_valid",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_data_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_mem_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_mem_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

15682
el2_ifu_mem_ctl.fir Normal file
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File diff suppressed because it is too large Load Diff

11916
el2_ifu_mem_ctl.v Normal file
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File diff suppressed because it is too large Load Diff

2
el2_lsu.fir
View File

@ -15374,7 +15374,7 @@ circuit el2_lsu :
dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 241:46]
dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 242:46]
dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 243:46]
dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 244:46]
dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[el2_lsu.scala 244:46]
dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu.scala 246:46]
dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu.scala 246:46]
dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[el2_lsu.scala 246:46]

6
el2_lsu.v
View File

@ -4825,6 +4825,7 @@ module el2_lsu_clkdomain(
output io_lsu_c2_m_clk,
output io_lsu_c2_r_clk,
output io_lsu_store_c1_m_clk,
output io_lsu_store_c1_r_clk,
output io_lsu_stbuf_c1_clk,
output io_lsu_bus_obuf_c1_clk,
output io_lsu_bus_ibuf_c1_clk,
@ -4991,6 +4992,7 @@ module el2_lsu_clkdomain(
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:26]
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:26]
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:26]
assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:26]
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:26]
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:26]
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:26]
@ -10840,6 +10842,7 @@ module el2_lsu(
wire clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 161:30]
wire clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 161:30]
wire clkdomain_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 161:30]
wire clkdomain_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 161:30]
wire clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 161:30]
wire clkdomain_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 161:30]
wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 161:30]
@ -11324,6 +11327,7 @@ module el2_lsu(
.io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk),
.io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk),
.io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk),
.io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk),
.io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk),
.io_lsu_bus_obuf_c1_clk(clkdomain_io_lsu_bus_obuf_c1_clk),
.io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk),
@ -11545,7 +11549,7 @@ module el2_lsu(
assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 240:46]
assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 241:46]
assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 242:46]
assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 244:46]
assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 244:46]
assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 246:46]
assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[el2_lsu.scala 246:46]
assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[el2_lsu.scala 246:46]

48
el2_lsu_bus_intf.anno.json
View File

@ -13,6 +13,26 @@
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_load",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
@ -20,13 +40,13 @@
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
@ -39,26 +59,6 @@
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_load",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",

8624
el2_lsu_bus_intf.fir
View File

File diff suppressed because it is too large Load Diff

3465
el2_lsu_bus_intf.v
View File

File diff suppressed because it is too large Load Diff

4
el2_lsu_clkdomain.anno.json
View File

@ -5,8 +5,8 @@
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_clkdomain.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
"target":"el2_lsu_clkdomain.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",

415
el2_lsu_clkdomain.fir
View File

@ -1,12 +1,12 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_clkdomain :
extmodule TEC_RV_ICG :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr :
@ -14,23 +14,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_1 :
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_1 :
@ -38,23 +38,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_2 :
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_2 :
@ -62,23 +62,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_3 :
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_3 :
@ -86,23 +86,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_4 :
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_4 :
@ -110,23 +110,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_5 :
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_5 :
@ -134,23 +134,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_6 :
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_6 :
@ -158,23 +158,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_7 :
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_7 :
@ -182,23 +182,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_8 :
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_8 :
@ -206,23 +206,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_9 :
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_9 :
@ -230,23 +230,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_10 :
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_10 :
@ -254,23 +254,23 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule TEC_RV_ICG_11 :
extmodule gated_latch_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
defname = gated_latch
module rvclkhdr_11 :
@ -278,166 +278,165 @@ circuit el2_lsu_clkdomain :
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 332:24]
inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module el2_lsu_clkdomain :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:37]
wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:37]
wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:37]
wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:37]
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:52]
node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:71]
node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:52]
node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:71]
node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:52]
node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:71]
node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:48]
node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:67]
node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:48]
node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:67]
node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 70:50]
node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:72]
node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 71:50]
node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:72]
node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:56]
node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:78]
node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:108]
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:50]
node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:62]
node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:80]
node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:99]
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:34]
node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:63]
node _T_13 = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:81]
node lsu_bus_buf_c1_clken = bits(_T_13, 0, 0) @[el2_lsu_clkdomain.scala 75:100]
node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:49]
node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:70]
node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:91]
node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:115]
node _T_18 = or(_T_16, _T_17) @[el2_lsu_clkdomain.scala 77:113]
node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:146]
node _T_20 = or(_T_18, _T_19) @[el2_lsu_clkdomain.scala 77:144]
node lsu_free_c1_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 77:170]
node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:51]
node lsu_free_c2_clken = or(_T_21, io.clk_override) @[el2_lsu_clkdomain.scala 78:73]
reg _T_22 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:61]
_T_22 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:61]
lsu_free_c1_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 81:27]
reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:68]
_T_23 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:68]
lsu_c1_d_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 82:27]
reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:68]
_T_24 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:68]
lsu_c1_m_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 83:27]
reg _T_25 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:68]
_T_25 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:68]
lsu_c1_r_clken_q <= _T_25 @[el2_lsu_clkdomain.scala 84:27]
node _T_26 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:60]
inst rvclkhdr of rvclkhdr @[beh_lib.scala 341:20]
wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:36]
wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:36]
wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:36]
wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:36]
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:51]
node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:70]
node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:51]
node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:70]
node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:51]
node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:70]
node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:47]
node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:66]
node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:47]
node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:66]
node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[el2_lsu_clkdomain.scala 70:49]
node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:76]
node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[el2_lsu_clkdomain.scala 71:49]
node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:76]
node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:55]
node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:77]
node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:107]
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:49]
node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:61]
node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:79]
node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:98]
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:32]
node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:61]
node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:79]
node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:48]
node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:69]
node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:90]
node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:114]
node _T_17 = or(_T_15, _T_16) @[el2_lsu_clkdomain.scala 77:112]
node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:145]
node _T_19 = or(_T_17, _T_18) @[el2_lsu_clkdomain.scala 77:143]
node lsu_free_c1_clken = or(_T_19, io.clk_override) @[el2_lsu_clkdomain.scala 77:169]
node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:50]
node lsu_free_c2_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 78:72]
reg _T_21 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:60]
_T_21 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:60]
lsu_free_c1_clken_q <= _T_21 @[el2_lsu_clkdomain.scala 81:26]
reg _T_22 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:67]
_T_22 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:67]
lsu_c1_d_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 82:26]
reg _T_23 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:67]
_T_23 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:67]
lsu_c1_m_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 83:26]
reg _T_24 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:67]
_T_24 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:67]
lsu_c1_r_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 84:26]
node _T_25 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:59]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr.io.en <= _T_26 @[beh_lib.scala 343:14]
rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:27]
node _T_27 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:60]
inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 341:20]
rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr.io.en <= _T_25 @[el2_lib.scala 485:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:26]
node _T_26 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:59]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_1.io.en <= _T_27 @[beh_lib.scala 343:14]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:27]
node _T_28 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:60]
inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 341:20]
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_1.io.en <= _T_26 @[el2_lib.scala 485:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:26]
node _T_27 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:59]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_2.io.en <= _T_28 @[beh_lib.scala 343:14]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:27]
node _T_29 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:60]
inst rvclkhdr_3 of rvclkhdr_3 @[beh_lib.scala 341:20]
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_2.io.en <= _T_27 @[el2_lib.scala 485:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:26]
node _T_28 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:59]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_3.io.en <= _T_29 @[beh_lib.scala 343:14]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:27]
node _T_30 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:66]
inst rvclkhdr_4 of rvclkhdr_4 @[beh_lib.scala 341:20]
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_3.io.en <= _T_28 @[el2_lib.scala 485:16]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:26]
node _T_29 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:65]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_4.io.en <= _T_30 @[beh_lib.scala 343:14]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:27]
node _T_31 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:66]
inst rvclkhdr_5 of rvclkhdr_5 @[beh_lib.scala 341:20]
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_4.io.en <= _T_29 @[el2_lib.scala 485:16]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:26]
node _T_30 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:65]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_5.io.en <= _T_31 @[beh_lib.scala 343:14]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:27]
node _T_32 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:64]
inst rvclkhdr_6 of rvclkhdr_6 @[beh_lib.scala 341:20]
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_5.io.en <= _T_30 @[el2_lib.scala 485:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:26]
node _T_31 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:63]
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_6.io.en <= _T_32 @[beh_lib.scala 343:14]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:27]
node _T_33 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:67]
inst rvclkhdr_7 of rvclkhdr_7 @[beh_lib.scala 341:20]
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_6.io.en <= _T_31 @[el2_lib.scala 485:16]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:26]
node _T_32 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:66]
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_7.io.en <= _T_33 @[beh_lib.scala 343:14]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:27]
node _T_34 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:67]
inst rvclkhdr_8 of rvclkhdr_8 @[beh_lib.scala 341:20]
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_7.io.en <= _T_32 @[el2_lib.scala 485:16]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:26]
node _T_33 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:66]
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_8.io.en <= _T_34 @[beh_lib.scala 343:14]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:27]
node _T_35 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:66]
inst rvclkhdr_9 of rvclkhdr_9 @[beh_lib.scala 341:20]
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_8.io.en <= _T_33 @[el2_lib.scala 485:16]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:26]
node _T_34 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:65]
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_9.io.en <= _T_35 @[beh_lib.scala 343:14]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:27]
node _T_36 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:63]
inst rvclkhdr_10 of rvclkhdr_10 @[beh_lib.scala 341:20]
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_9.io.en <= _T_34 @[el2_lib.scala 485:16]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:26]
node _T_35 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:62]
inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 483:22]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_10.io.en <= _T_36 @[beh_lib.scala 343:14]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:27]
node _T_37 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:63]
inst rvclkhdr_11 of rvclkhdr_11 @[beh_lib.scala 341:20]
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_10.io.en <= _T_35 @[el2_lib.scala 485:16]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:26]
node _T_36 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:62]
inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 483:22]
rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[beh_lib.scala 342:15]
rvclkhdr_11.io.en <= _T_37 @[beh_lib.scala 343:14]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21]
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:27]
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_11.io.en <= _T_36 @[el2_lib.scala 485:16]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:26]

386
el2_lsu_clkdomain.v
View File

@ -4,20 +4,20 @@ module rvclkhdr(
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[beh_lib.scala 332:24]
wire clkhdr_CK; // @[beh_lib.scala 332:24]
wire clkhdr_EN; // @[beh_lib.scala 332:24]
wire clkhdr_SE; // @[beh_lib.scala 332:24]
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_lsu_clkdomain(
input clock,
@ -34,58 +34,58 @@ module el2_lsu_clkdomain(
input io_lsu_bus_buffer_empty_any,
input io_lsu_stbuf_empty_any,
input io_lsu_bus_clk_en,
input io_lsu_p_fast_int,
input io_lsu_p_by,
input io_lsu_p_half,
input io_lsu_p_word,
input io_lsu_p_dword,
input io_lsu_p_load,
input io_lsu_p_store,
input io_lsu_p_unsign,
input io_lsu_p_dma,
input io_lsu_p_store_data_bypass_d,
input io_lsu_p_load_ldst_bypass_d,
input io_lsu_p_store_data_bypass_m,
input io_lsu_p_valid,
input io_lsu_pkt_d_fast_int,
input io_lsu_pkt_d_by,
input io_lsu_pkt_d_half,
input io_lsu_pkt_d_word,
input io_lsu_pkt_d_dword,
input io_lsu_pkt_d_load,
input io_lsu_pkt_d_store,
input io_lsu_pkt_d_unsign,
input io_lsu_pkt_d_dma,
input io_lsu_pkt_d_store_data_bypass_d,
input io_lsu_pkt_d_load_ldst_bypass_d,
input io_lsu_pkt_d_store_data_bypass_m,
input io_lsu_p_bits_fast_int,
input io_lsu_p_bits_by,
input io_lsu_p_bits_half,
input io_lsu_p_bits_word,
input io_lsu_p_bits_dword,
input io_lsu_p_bits_load,
input io_lsu_p_bits_store,
input io_lsu_p_bits_unsign,
input io_lsu_p_bits_dma,
input io_lsu_p_bits_store_data_bypass_d,
input io_lsu_p_bits_load_ldst_bypass_d,
input io_lsu_p_bits_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_d_bits_fast_int,
input io_lsu_pkt_d_bits_by,
input io_lsu_pkt_d_bits_half,
input io_lsu_pkt_d_bits_word,
input io_lsu_pkt_d_bits_dword,
input io_lsu_pkt_d_bits_load,
input io_lsu_pkt_d_bits_store,
input io_lsu_pkt_d_bits_unsign,
input io_lsu_pkt_d_bits_dma,
input io_lsu_pkt_d_bits_store_data_bypass_d,
input io_lsu_pkt_d_bits_load_ldst_bypass_d,
input io_lsu_pkt_d_bits_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_r_fast_int,
input io_lsu_pkt_r_by,
input io_lsu_pkt_r_half,
input io_lsu_pkt_r_word,
input io_lsu_pkt_r_dword,
input io_lsu_pkt_r_load,
input io_lsu_pkt_r_store,
input io_lsu_pkt_r_unsign,
input io_lsu_pkt_r_dma,
input io_lsu_pkt_r_store_data_bypass_d,
input io_lsu_pkt_r_load_ldst_bypass_d,
input io_lsu_pkt_r_store_data_bypass_m,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_lsu_pkt_r_bits_fast_int,
input io_lsu_pkt_r_bits_by,
input io_lsu_pkt_r_bits_half,
input io_lsu_pkt_r_bits_word,
input io_lsu_pkt_r_bits_dword,
input io_lsu_pkt_r_bits_load,
input io_lsu_pkt_r_bits_store,
input io_lsu_pkt_r_bits_unsign,
input io_lsu_pkt_r_bits_dma,
input io_lsu_pkt_r_bits_store_data_bypass_d,
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
input io_lsu_pkt_r_bits_store_data_bypass_m,
output io_lsu_c1_m_clk,
output io_lsu_c1_r_clk,
output io_lsu_c2_m_clk,
@ -106,201 +106,201 @@ module el2_lsu_clkdomain(
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_1_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_2_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_2_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_3_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_3_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_3_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_3_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_4_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_4_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_4_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_4_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_5_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_5_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_5_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_5_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_6_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_6_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_6_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_6_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_7_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_7_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_7_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_7_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_8_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_8_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_8_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_8_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_9_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_9_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_9_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_9_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_10_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_10_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_10_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_10_io_scan_mode; // @[beh_lib.scala 341:20]
wire rvclkhdr_11_io_l1clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_11_io_clk; // @[beh_lib.scala 341:20]
wire rvclkhdr_11_io_en; // @[beh_lib.scala 341:20]
wire rvclkhdr_11_io_scan_mode; // @[beh_lib.scala 341:20]
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:52]
reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:68]
wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:52]
wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:71]
reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:68]
wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:52]
wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:71]
wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:48]
reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:68]
wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:48]
wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 70:50]
wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 71:50]
wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:56]
wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:78]
wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:62]
wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:80]
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:34]
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:63]
wire _T_14 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:49]
wire _T_15 = _T_14 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:70]
wire _T_16 = _T_15 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:91]
wire _T_18 = _T_16 | _T_11; // @[el2_lsu_clkdomain.scala 77:113]
wire _T_19 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:146]
wire _T_20 = _T_18 | _T_19; // @[el2_lsu_clkdomain.scala 77:144]
wire lsu_free_c1_clken = _T_20 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:170]
reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:61]
wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:51]
rvclkhdr rvclkhdr ( // @[beh_lib.scala 341:20]
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22]
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:51]
reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:67]
wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:51]
wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:70]
reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:67]
wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:51]
wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70]
wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:47]
reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:67]
wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:47]
wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[el2_lsu_clkdomain.scala 70:49]
wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[el2_lsu_clkdomain.scala 71:49]
wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:55]
wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:77]
wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:61]
wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:79]
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:32]
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:61]
wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:48]
wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:69]
wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:90]
wire _T_17 = _T_15 | _T_11; // @[el2_lsu_clkdomain.scala 77:112]
wire _T_18 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:145]
wire _T_19 = _T_17 | _T_18; // @[el2_lsu_clkdomain.scala 77:143]
wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:169]
reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:60]
wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:50]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
rvclkhdr rvclkhdr_6 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en),
.io_scan_mode(rvclkhdr_6_io_scan_mode)
);
rvclkhdr rvclkhdr_7 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en),
.io_scan_mode(rvclkhdr_7_io_scan_mode)
);
rvclkhdr rvclkhdr_8 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_8_io_l1clk),
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en),
.io_scan_mode(rvclkhdr_8_io_scan_mode)
);
rvclkhdr rvclkhdr_9 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_9_io_l1clk),
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode)
);
rvclkhdr rvclkhdr_10 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_10_io_l1clk),
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en),
.io_scan_mode(rvclkhdr_10_io_scan_mode)
);
rvclkhdr rvclkhdr_11 ( // @[beh_lib.scala 341:20]
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_11_io_l1clk),
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en),
.io_scan_mode(rvclkhdr_11_io_scan_mode)
);
assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:27]
assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:27]
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:27]
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:27]
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:27]
assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:27]
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:27]
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:27]
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:27]
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:27]
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:27]
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:27]
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_3_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_4_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_5_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_6_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_7_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_8_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[beh_lib.scala 343:14]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_9_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_10_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[beh_lib.scala 343:14]
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign rvclkhdr_11_io_clk = clock; // @[beh_lib.scala 342:15]
assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[beh_lib.scala 343:14]
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21]
assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:26]
assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:26]
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:26]
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:26]
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:26]
assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:26]
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:26]
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:26]
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:26]
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:26]
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:26]
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:26]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
@ -388,7 +388,7 @@ end // initial
if (reset) begin
lsu_free_c1_clken_q <= 1'h0;
end else begin
lsu_free_c1_clken_q <= _T_20 | io_clk_override;
lsu_free_c1_clken_q <= _T_19 | io_clk_override;
end
end
endmodule

398
el2_lsu_ecc.anno.json
View File

@ -1,68 +1,4 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_single_ecc_error_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r",
@ -72,8 +8,8 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
@ -84,10 +20,41 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
@ -101,117 +68,6 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_ecc_hi_r_ff",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_hi",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_r",
@ -227,10 +83,31 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
@ -242,8 +119,8 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
@ -254,10 +131,10 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
@ -269,8 +146,8 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
@ -285,10 +162,133 @@
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_ecc_hi_r_ff",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_hi",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_single_ecc_error_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
@ -330,8 +330,8 @@
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_ecc.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
"target":"el2_lsu_ecc.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",

3116
el2_lsu_ecc.fir
View File

File diff suppressed because it is too large Load Diff

756
el2_lsu_ecc.v
View File

@ -4,51 +4,51 @@ module rvclkhdr(
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[beh_lib.scala 332:24]
wire clkhdr_CK; // @[beh_lib.scala 332:24]
wire clkhdr_EN; // @[beh_lib.scala 332:24]
wire clkhdr_SE; // @[beh_lib.scala 332:24]
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_lsu_ecc(
input clock,
input reset,
input io_lsu_c2_r_clk,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_r_fast_int,
input io_lsu_pkt_r_by,
input io_lsu_pkt_r_half,
input io_lsu_pkt_r_word,
input io_lsu_pkt_r_dword,
input io_lsu_pkt_r_load,
input io_lsu_pkt_r_store,
input io_lsu_pkt_r_unsign,
input io_lsu_pkt_r_dma,
input io_lsu_pkt_r_store_data_bypass_d,
input io_lsu_pkt_r_load_ldst_bypass_d,
input io_lsu_pkt_r_store_data_bypass_m,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_lsu_pkt_r_bits_fast_int,
input io_lsu_pkt_r_bits_by,
input io_lsu_pkt_r_bits_half,
input io_lsu_pkt_r_bits_word,
input io_lsu_pkt_r_bits_dword,
input io_lsu_pkt_r_bits_load,
input io_lsu_pkt_r_bits_store,
input io_lsu_pkt_r_bits_unsign,
input io_lsu_pkt_r_bits_dma,
input io_lsu_pkt_r_bits_store_data_bypass_d,
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
input io_lsu_pkt_r_bits_store_data_bypass_m,
input [31:0] io_stbuf_data_any,
input io_dec_tlu_core_ecc_disable,
input io_lsu_dccm_rden_r,
@ -101,277 +101,411 @@ module el2_lsu_ecc(
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21]
wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21]
wire rvclkhdr_io_en; // @[beh_lib.scala 352:21]
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21]
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 352:21]
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 352:21]
wire rvclkhdr_1_io_en; // @[beh_lib.scala 352:21]
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 352:21]
wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 324:30]
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 324:44]
wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 324:35]
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 324:76]
wire _T_107 = ^_T_106; // @[el2_lib.scala 324:83]
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 324:71]
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 324:103]
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 324:103]
wire _T_124 = ^_T_123; // @[el2_lib.scala 324:110]
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 324:98]
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 324:130]
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 324:130]
wire _T_141 = ^_T_140; // @[el2_lib.scala 324:137]
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 324:125]
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 324:157]
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 324:157]
wire _T_161 = ^_T_160; // @[el2_lib.scala 324:164]
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 324:152]
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 324:184]
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 324:184]
wire _T_181 = ^_T_180; // @[el2_lib.scala 324:191]
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 324:179]
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 324:211]
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 324:211]
wire _T_201 = ^_T_200; // @[el2_lib.scala 324:218]
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 324:206]
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 333:30]
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 333:44]
wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 333:35]
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 333:76]
wire _T_107 = ^_T_106; // @[el2_lib.scala 333:83]
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 333:71]
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 333:103]
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 333:103]
wire _T_124 = ^_T_123; // @[el2_lib.scala 333:110]
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 333:98]
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 333:130]
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 333:130]
wire _T_141 = ^_T_140; // @[el2_lib.scala 333:137]
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 333:125]
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 333:157]
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 333:157]
wire _T_161 = ^_T_160; // @[el2_lib.scala 333:164]
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 333:152]
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:184]
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 333:184]
wire _T_181 = ^_T_180; // @[el2_lib.scala 333:191]
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 333:179]
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:211]
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 333:211]
wire _T_201 = ^_T_200; // @[el2_lib.scala 333:218]
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 333:206]
wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 325:44]
wire _T_1155 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:70]
wire _T_1162 = io_lsu_pkt_m_load | io_lsu_pkt_m_store; // @[el2_lsu_ecc.scala 125:60]
wire _T_1163 = io_lsu_pkt_m_valid & _T_1162; // @[el2_lsu_ecc.scala 125:39]
wire _T_1164 = _T_1163 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:82]
wire is_ldst_m = _T_1164 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:102]
wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 334:44]
wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:73]
wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[el2_lsu_ecc.scala 125:65]
wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[el2_lsu_ecc.scala 125:39]
wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:92]
wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:112]
wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[el2_lsu_ecc.scala 124:39]
wire _T_1168 = ldst_dual_m | io_lsu_pkt_m_dma; // @[el2_lsu_ecc.scala 127:48]
wire _T_1169 = is_ldst_m & _T_1168; // @[el2_lsu_ecc.scala 127:33]
wire is_ldst_hi_m = _T_1169 & _T_1155; // @[el2_lsu_ecc.scala 127:68]
wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 325:32]
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 325:53]
wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 326:55]
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 326:53]
wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 330:41]
wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 330:41]
wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 330:41]
wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 330:41]
wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 330:41]
wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 330:41]
wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 330:41]
wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 330:41]
wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 330:41]
wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 330:41]
wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 330:41]
wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 330:41]
wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 330:41]
wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 330:41]
wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 330:41]
wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 330:41]
wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 330:41]
wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 330:41]
wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 330:41]
wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 330:41]
wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 330:41]
wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 330:41]
wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 330:41]
wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 330:41]
wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 330:41]
wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 330:41]
wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 330:41]
wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 330:41]
wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 330:41]
wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 330:41]
wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 330:41]
wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 330:41]
wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 330:41]
wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 330:41]
wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 330:41]
wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 330:41]
wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 330:41]
wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 330:41]
wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 330:41]
wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[el2_lsu_ecc.scala 127:48]
wire _T_1145 = is_ldst_m & _T_1144; // @[el2_lsu_ecc.scala 127:33]
wire is_ldst_hi_m = _T_1145 & _T_1131; // @[el2_lsu_ecc.scala 127:73]
wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 334:32]
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 334:53]
wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 335:55]
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 335:53]
wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 339:41]
wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 339:41]
wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 339:41]
wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 339:41]
wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 339:41]
wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 339:41]
wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 339:41]
wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 339:41]
wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 339:41]
wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 339:41]
wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 339:41]
wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 339:41]
wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 339:41]
wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 339:41]
wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 339:41]
wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 339:41]
wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 339:41]
wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 339:41]
wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 339:41]
wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 339:41]
wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 339:41]
wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 339:41]
wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 339:41]
wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 339:41]
wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 339:41]
wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 339:41]
wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 339:41]
wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 339:41]
wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 339:41]
wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 339:41]
wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 339:41]
wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 339:41]
wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 339:41]
wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 339:41]
wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 339:41]
wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 339:41]
wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 339:41]
wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 339:41]
wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 339:41]
wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 333:69]
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 333:69]
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 333:69]
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 333:69]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 333:69]
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 333:76]
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 333:31]
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 342:69]
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 342:69]
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 342:69]
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 342:69]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 342:69]
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 342:76]
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 342:31]
wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 324:30]
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 324:44]
wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 324:35]
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 324:76]
wire _T_485 = ^_T_484; // @[el2_lib.scala 324:83]
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 324:71]
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 324:103]
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 324:103]
wire _T_502 = ^_T_501; // @[el2_lib.scala 324:110]
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 324:98]
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 324:130]
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 324:130]
wire _T_519 = ^_T_518; // @[el2_lib.scala 324:137]
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 324:125]
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 324:157]
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 324:157]
wire _T_539 = ^_T_538; // @[el2_lib.scala 324:164]
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 324:152]
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 324:184]
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 324:184]
wire _T_559 = ^_T_558; // @[el2_lib.scala 324:191]
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 324:179]
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 324:211]
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 324:211]
wire _T_579 = ^_T_578; // @[el2_lib.scala 324:218]
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 324:206]
wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 333:30]
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 333:44]
wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 333:35]
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 333:76]
wire _T_485 = ^_T_484; // @[el2_lib.scala 333:83]
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 333:71]
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 333:103]
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 333:103]
wire _T_502 = ^_T_501; // @[el2_lib.scala 333:110]
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 333:98]
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 333:130]
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 333:130]
wire _T_519 = ^_T_518; // @[el2_lib.scala 333:137]
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 333:125]
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 333:157]
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 333:157]
wire _T_539 = ^_T_538; // @[el2_lib.scala 333:164]
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 333:152]
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:184]
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 333:184]
wire _T_559 = ^_T_558; // @[el2_lib.scala 333:191]
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 333:179]
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:211]
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 333:211]
wire _T_579 = ^_T_578; // @[el2_lib.scala 333:218]
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 333:206]
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 325:44]
wire is_ldst_lo_m = is_ldst_m & _T_1155; // @[el2_lsu_ecc.scala 126:33]
wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 325:32]
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 325:53]
wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 326:55]
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 326:53]
wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 330:41]
wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 330:41]
wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 330:41]
wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 330:41]
wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 330:41]
wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 330:41]
wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 330:41]
wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 330:41]
wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 330:41]
wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 330:41]
wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 330:41]
wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 330:41]
wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 330:41]
wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 330:41]
wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 330:41]
wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 330:41]
wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 330:41]
wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 330:41]
wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 330:41]
wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 330:41]
wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 330:41]
wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 330:41]
wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 330:41]
wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 330:41]
wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 330:41]
wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 330:41]
wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 330:41]
wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 330:41]
wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 330:41]
wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 330:41]
wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 330:41]
wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 330:41]
wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 330:41]
wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 330:41]
wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 330:41]
wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 330:41]
wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 330:41]
wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 330:41]
wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 330:41]
wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 334:44]
wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[el2_lsu_ecc.scala 126:33]
wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 334:32]
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 334:53]
wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 335:55]
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 335:53]
wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 339:41]
wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 339:41]
wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 339:41]
wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 339:41]
wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 339:41]
wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 339:41]
wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 339:41]
wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 339:41]
wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 339:41]
wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 339:41]
wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 339:41]
wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 339:41]
wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 339:41]
wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 339:41]
wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 339:41]
wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 339:41]
wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 339:41]
wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 339:41]
wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 339:41]
wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 339:41]
wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 339:41]
wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 339:41]
wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 339:41]
wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 339:41]
wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 339:41]
wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 339:41]
wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 339:41]
wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 339:41]
wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 339:41]
wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 339:41]
wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 339:41]
wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 339:41]
wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 339:41]
wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 339:41]
wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 339:41]
wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 339:41]
wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 339:41]
wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 339:41]
wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 339:41]
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 333:69]
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 333:69]
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 333:69]
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 333:69]
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 333:69]
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 333:76]
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 333:31]
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 342:69]
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 342:69]
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 342:69]
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 342:69]
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 342:69]
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 342:76]
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 342:31]
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
wire [31:0] _T_1182 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:89]
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1182; // @[el2_lsu_ecc.scala 149:29]
wire [5:0] _T_856 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[26]}; // @[el2_lib.scala 287:22]
wire _T_857 = ^_T_856; // @[el2_lib.scala 287:29]
wire [6:0] _T_863 = {dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[11]}; // @[el2_lib.scala 287:39]
wire [14:0] _T_871 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_863}; // @[el2_lib.scala 287:39]
wire _T_872 = ^_T_871; // @[el2_lib.scala 287:46]
wire [6:0] _T_878 = {dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[4]}; // @[el2_lib.scala 287:56]
wire [14:0] _T_886 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_878}; // @[el2_lib.scala 287:56]
wire _T_887 = ^_T_886; // @[el2_lib.scala 287:63]
wire [8:0] _T_895 = {dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[1]}; // @[el2_lib.scala 287:73]
wire [17:0] _T_904 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_895}; // @[el2_lib.scala 287:73]
wire _T_905 = ^_T_904; // @[el2_lib.scala 287:80]
wire [8:0] _T_913 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 287:90]
wire [17:0] _T_922 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_913}; // @[el2_lib.scala 287:90]
wire _T_923 = ^_T_922; // @[el2_lib.scala 287:97]
wire [8:0] _T_931 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[11],dccm_wdata_lo_any[10],dccm_wdata_lo_any[8],dccm_wdata_lo_any[6],dccm_wdata_lo_any[4],dccm_wdata_lo_any[3],dccm_wdata_lo_any[1],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 287:107]
wire [17:0] _T_940 = {dccm_wdata_lo_any[30],dccm_wdata_lo_any[28],dccm_wdata_lo_any[26],dccm_wdata_lo_any[25],dccm_wdata_lo_any[23],dccm_wdata_lo_any[21],dccm_wdata_lo_any[19],dccm_wdata_lo_any[17],dccm_wdata_lo_any[15],_T_931}; // @[el2_lib.scala 287:107]
wire _T_941 = ^_T_940; // @[el2_lib.scala 287:114]
wire [5:0] _T_946 = {_T_857,_T_872,_T_887,_T_905,_T_923,_T_941}; // @[Cat.scala 29:58]
wire _T_947 = ^dccm_wdata_lo_any; // @[el2_lib.scala 288:27]
wire _T_948 = ^_T_946; // @[el2_lib.scala 288:37]
wire _T_949 = _T_947 ^ _T_948; // @[el2_lib.scala 288:32]
wire [31:0] _T_1186 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:89]
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1186; // @[el2_lsu_ecc.scala 150:29]
wire [5:0] _T_1050 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[26]}; // @[el2_lib.scala 287:22]
wire _T_1051 = ^_T_1050; // @[el2_lib.scala 287:29]
wire [6:0] _T_1057 = {dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[11]}; // @[el2_lib.scala 287:39]
wire [14:0] _T_1065 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1057}; // @[el2_lib.scala 287:39]
wire _T_1066 = ^_T_1065; // @[el2_lib.scala 287:46]
wire [6:0] _T_1072 = {dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[4]}; // @[el2_lib.scala 287:56]
wire [14:0] _T_1080 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1072}; // @[el2_lib.scala 287:56]
wire _T_1081 = ^_T_1080; // @[el2_lib.scala 287:63]
wire [8:0] _T_1089 = {dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[1]}; // @[el2_lib.scala 287:73]
wire [17:0] _T_1098 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1089}; // @[el2_lib.scala 287:73]
wire _T_1099 = ^_T_1098; // @[el2_lib.scala 287:80]
wire [8:0] _T_1107 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 287:90]
wire [17:0] _T_1116 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1107}; // @[el2_lib.scala 287:90]
wire _T_1117 = ^_T_1116; // @[el2_lib.scala 287:97]
wire [8:0] _T_1125 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[11],dccm_wdata_hi_any[10],dccm_wdata_hi_any[8],dccm_wdata_hi_any[6],dccm_wdata_hi_any[4],dccm_wdata_hi_any[3],dccm_wdata_hi_any[1],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 287:107]
wire [17:0] _T_1134 = {dccm_wdata_hi_any[30],dccm_wdata_hi_any[28],dccm_wdata_hi_any[26],dccm_wdata_hi_any[25],dccm_wdata_hi_any[23],dccm_wdata_hi_any[21],dccm_wdata_hi_any[19],dccm_wdata_hi_any[17],dccm_wdata_hi_any[15],_T_1125}; // @[el2_lib.scala 287:107]
wire _T_1135 = ^_T_1134; // @[el2_lib.scala 287:114]
wire [5:0] _T_1140 = {_T_1051,_T_1066,_T_1081,_T_1099,_T_1117,_T_1135}; // @[Cat.scala 29:58]
wire _T_1141 = ^dccm_wdata_hi_any; // @[el2_lib.scala 288:27]
wire _T_1142 = ^_T_1140; // @[el2_lib.scala 288:37]
wire _T_1143 = _T_1141 ^ _T_1142; // @[el2_lib.scala 288:32]
reg _T_1174; // @[el2_lsu_ecc.scala 141:72]
reg _T_1175; // @[el2_lsu_ecc.scala 142:72]
reg _T_1176; // @[el2_lsu_ecc.scala 143:72]
reg _T_1177; // @[el2_lsu_ecc.scala 144:72]
reg [31:0] _T_1178; // @[el2_lsu_ecc.scala 145:72]
reg [31:0] _T_1179; // @[el2_lsu_ecc.scala 146:72]
reg [31:0] _T_1188; // @[beh_lib.scala 358:14]
reg [31:0] _T_1189; // @[beh_lib.scala 358:14]
rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21]
wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:87]
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[el2_lsu_ecc.scala 149:27]
wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[el2_lib.scala 259:74]
wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74]
wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[el2_lib.scala 259:74]
wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74]
wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74]
wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[el2_lib.scala 259:74]
wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74]
wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74]
wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74]
wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[el2_lib.scala 259:74]
wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74]
wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74]
wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74]
wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74]
wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74]
wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74]
wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74]
wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74]
wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74]
wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74]
wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74]
wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74]
wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74]
wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74]
wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74]
wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74]
wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74]
wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74]
wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74]
wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74]
wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74]
wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74]
wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74]
wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74]
wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74]
wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74]
wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74]
wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74]
wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74]
wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74]
wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74]
wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74]
wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74]
wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74]
wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74]
wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74]
wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74]
wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74]
wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74]
wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74]
wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74]
wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74]
wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74]
wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74]
wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74]
wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74]
wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74]
wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74]
wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74]
wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74]
wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74]
wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74]
wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74]
wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74]
wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74]
wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58]
wire _T_935 = ^dccm_wdata_lo_any; // @[el2_lib.scala 267:13]
wire _T_936 = ^_T_934; // @[el2_lib.scala 267:23]
wire _T_937 = _T_935 ^ _T_936; // @[el2_lib.scala 267:18]
wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:87]
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[el2_lsu_ecc.scala 150:27]
wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[el2_lib.scala 259:74]
wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74]
wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[el2_lib.scala 259:74]
wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74]
wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74]
wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[el2_lib.scala 259:74]
wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74]
wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74]
wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74]
wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[el2_lib.scala 259:74]
wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74]
wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74]
wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74]
wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74]
wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74]
wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74]
wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74]
wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74]
wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74]
wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74]
wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74]
wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74]
wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74]
wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74]
wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74]
wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74]
wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74]
wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74]
wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74]
wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74]
wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74]
wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74]
wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74]
wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74]
wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74]
wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74]
wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74]
wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74]
wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74]
wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74]
wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74]
wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74]
wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74]
wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74]
wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74]
wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74]
wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74]
wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74]
wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74]
wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74]
wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74]
wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74]
wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74]
wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74]
wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74]
wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74]
wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74]
wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74]
wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74]
wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74]
wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74]
wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74]
wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74]
wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74]
wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74]
wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58]
wire _T_1117 = ^dccm_wdata_hi_any; // @[el2_lib.scala 267:13]
wire _T_1118 = ^_T_1116; // @[el2_lib.scala 267:23]
wire _T_1119 = _T_1117 ^ _T_1118; // @[el2_lib.scala 267:18]
reg _T_1150; // @[el2_lsu_ecc.scala 141:72]
reg _T_1151; // @[el2_lsu_ecc.scala 142:72]
reg _T_1152; // @[el2_lsu_ecc.scala 143:72]
reg _T_1153; // @[el2_lsu_ecc.scala 144:72]
reg [31:0] _T_1154; // @[el2_lsu_ecc.scala 145:72]
reg [31:0] _T_1155; // @[el2_lsu_ecc.scala 146:72]
reg [31:0] _T_1164; // @[el2_lib.scala 514:16]
reg [31:0] _T_1165; // @[el2_lib.scala 514:16]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 352:21]
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
assign io_sec_data_hi_r = _T_1178; // @[el2_lsu_ecc.scala 114:24 el2_lsu_ecc.scala 145:62]
assign io_sec_data_lo_r = _T_1179; // @[el2_lsu_ecc.scala 117:27 el2_lsu_ecc.scala 146:62]
assign io_sec_data_hi_r = _T_1154; // @[el2_lsu_ecc.scala 114:22 el2_lsu_ecc.scala 145:62]
assign io_sec_data_lo_r = _T_1155; // @[el2_lsu_ecc.scala 117:25 el2_lsu_ecc.scala 146:62]
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[el2_lsu_ecc.scala 90:32 el2_lsu_ecc.scala 134:27]
assign io_sec_data_lo_m = {_T_742,_T_740}; // @[el2_lsu_ecc.scala 91:32 el2_lsu_ecc.scala 136:27]
assign io_sec_data_hi_r_ff = _T_1188; // @[el2_lsu_ecc.scala 157:23]
assign io_sec_data_lo_r_ff = _T_1189; // @[el2_lsu_ecc.scala 158:23]
assign io_dma_dccm_wdata_ecc_hi = {_T_1143,_T_1140}; // @[el2_lsu_ecc.scala 154:30]
assign io_dma_dccm_wdata_ecc_lo = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 155:30]
assign io_stbuf_ecc_any = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 153:30]
assign io_sec_data_ecc_hi_r_ff = {_T_1143,_T_1140}; // @[el2_lsu_ecc.scala 151:30]
assign io_sec_data_ecc_lo_r_ff = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 152:30]
assign io_single_ecc_error_hi_r = _T_1177; // @[el2_lsu_ecc.scala 115:33 el2_lsu_ecc.scala 144:62]
assign io_single_ecc_error_lo_r = _T_1176; // @[el2_lsu_ecc.scala 118:33 el2_lsu_ecc.scala 143:62]
assign io_lsu_single_ecc_error_r = _T_1174; // @[el2_lsu_ecc.scala 120:33 el2_lsu_ecc.scala 141:62]
assign io_lsu_double_ecc_error_r = _T_1175; // @[el2_lsu_ecc.scala 121:33 el2_lsu_ecc.scala 142:62]
assign io_sec_data_hi_r_ff = _T_1164; // @[el2_lsu_ecc.scala 157:23]
assign io_sec_data_lo_r_ff = _T_1165; // @[el2_lsu_ecc.scala 158:23]
assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 154:28]
assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 155:28]
assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 153:28]
assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 151:28]
assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 152:28]
assign io_single_ecc_error_hi_r = _T_1153; // @[el2_lsu_ecc.scala 115:31 el2_lsu_ecc.scala 144:62]
assign io_single_ecc_error_lo_r = _T_1152; // @[el2_lsu_ecc.scala 118:31 el2_lsu_ecc.scala 143:62]
assign io_lsu_single_ecc_error_r = _T_1150; // @[el2_lsu_ecc.scala 120:31 el2_lsu_ecc.scala 141:62]
assign io_lsu_double_ecc_error_r = _T_1151; // @[el2_lsu_ecc.scala 121:31 el2_lsu_ecc.scala 142:62]
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 92:30 el2_lsu_ecc.scala 138:33]
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[el2_lsu_ecc.scala 93:30 el2_lsu_ecc.scala 139:33]
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16]
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 354:16]
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
@ -408,45 +542,45 @@ initial begin
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1174 = _RAND_0[0:0];
_T_1150 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
_T_1175 = _RAND_1[0:0];
_T_1151 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
_T_1176 = _RAND_2[0:0];
_T_1152 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
_T_1177 = _RAND_3[0:0];
_T_1153 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T_1178 = _RAND_4[31:0];
_T_1154 = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
_T_1179 = _RAND_5[31:0];
_T_1155 = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
_T_1188 = _RAND_6[31:0];
_T_1164 = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
_T_1189 = _RAND_7[31:0];
_T_1165 = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1174 = 1'h0;
_T_1150 = 1'h0;
end
if (reset) begin
_T_1175 = 1'h0;
_T_1151 = 1'h0;
end
if (reset) begin
_T_1176 = 1'h0;
_T_1152 = 1'h0;
end
if (reset) begin
_T_1177 = 1'h0;
_T_1153 = 1'h0;
end
if (reset) begin
_T_1178 = 32'h0;
_T_1154 = 32'h0;
end
if (reset) begin
_T_1179 = 32'h0;
_T_1155 = 32'h0;
end
if (reset) begin
_T_1188 = 32'h0;
_T_1164 = 32'h0;
end
if (reset) begin
_T_1189 = 32'h0;
_T_1165 = 32'h0;
end
`endif // RANDOMIZE
end // initial
@ -456,58 +590,58 @@ end // initial
`endif // SYNTHESIS
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1174 <= 1'h0;
_T_1150 <= 1'h0;
end else begin
_T_1174 <= io_lsu_single_ecc_error_m;
_T_1150 <= io_lsu_single_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1175 <= 1'h0;
_T_1151 <= 1'h0;
end else begin
_T_1175 <= io_lsu_double_ecc_error_m;
_T_1151 <= io_lsu_double_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1176 <= 1'h0;
_T_1152 <= 1'h0;
end else begin
_T_1176 <= _T_588 & _T_586[6];
_T_1152 <= _T_588 & _T_586[6];
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1177 <= 1'h0;
_T_1153 <= 1'h0;
end else begin
_T_1177 <= _T_210 & _T_208[6];
_T_1153 <= _T_210 & _T_208[6];
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1178 <= 32'h0;
_T_1154 <= 32'h0;
end else begin
_T_1178 <= io_sec_data_hi_m;
_T_1154 <= io_sec_data_hi_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1179 <= 32'h0;
_T_1155 <= 32'h0;
end else begin
_T_1179 <= io_sec_data_lo_m;
_T_1155 <= io_sec_data_lo_m;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_1188 <= 32'h0;
_T_1164 <= 32'h0;
end else begin
_T_1188 <= io_sec_data_hi_r;
_T_1164 <= io_sec_data_hi_r;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
_T_1189 <= 32'h0;
_T_1165 <= 32'h0;
end else begin
_T_1189 <= io_sec_data_lo_r;
_T_1165 <= io_sec_data_lo_r;
end
end
endmodule

420
el2_lsu_lsc_ctl.anno.json
View File

@ -1,59 +1,109 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_by",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_end_addr_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load"
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_fast_int",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write"
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_d",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store_data_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_unsign",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
@ -65,223 +115,173 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_dccm_req",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_m_up",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_store_data_bypass_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_end_addr_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_m",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store_data_bypass_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dma",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_fast_int",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_dccm_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_dccm_req",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_m_up",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},

496
el2_lsu_lsc_ctl.fir
View File

@ -3,7 +3,7 @@ circuit el2_lsu_lsc_ctl :
module el2_lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 496:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49]
@ -58,16 +58,16 @@ circuit el2_lsu_lsc_ctl :
node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62]
node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60]
node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137]
node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180]
node _T_32 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[el2_lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158]
node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69]
node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75]
node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51]
node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124]
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128]
node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106]
node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85]
node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138]
node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:74]
node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:80]
node _T_35 = and(io.lsu_pkt_d.bits.word, _T_34) @[el2_lsu_addrcheck.scala 62:56]
node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:134]
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:138]
node _T_38 = and(io.lsu_pkt_d.bits.half, _T_37) @[el2_lsu_addrcheck.scala 62:116]
node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_39, io.lsu_pkt_d.bits.by) @[el2_lsu_addrcheck.scala 62:148]
node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
@ -176,7 +176,7 @@ circuit el2_lsu_lsc_ctl :
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57]
node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70]
node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76]
node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92]
node _T_146 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92]
node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
@ -203,7 +203,7 @@ circuit el2_lsu_lsc_ctl :
node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70]
node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92]
node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118]
node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141]
node _T_166 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141]
node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21]
node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60]
@ -222,7 +222,7 @@ circuit el2_lsu_lsc_ctl :
node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90]
node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57]
node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113]
node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136]
node _T_181 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136]
node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25]
node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111]
@ -239,12 +239,12 @@ circuit el2_lsu_lsc_ctl :
node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118]
node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88]
node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142]
node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163]
node _T_195 = and(_T_194, io.lsu_pkt_d.bits.fast_int) @[el2_lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31]
node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66]
node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36]
node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95]
node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116]
node _T_199 = and(_T_198, io.lsu_pkt_d.bits.fast_int) @[el2_lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33]
reg _T_200 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
_T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60]
@ -253,19 +253,19 @@ circuit el2_lsu_lsc_ctl :
module el2_lsu_lsc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>}
output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
wire dma_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 96:29]
wire lsu_pkt_m_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 97:29]
wire lsu_pkt_r_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 98:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29]
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 96:29]
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 97:29]
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 98:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 99:29]
node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52]
node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28]
node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44]
node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node lsu_offset_d = and(_T_1, _T_3) @[el2_lsu_lsc_ctl.scala 102:51]
node _T_4 = bits(io.lsu_pkt_d.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:61]
node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:66]
node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[el2_lsu_lsc_ctl.scala 105:28]
node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 232:31]
node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
@ -305,17 +305,17 @@ circuit el2_lsu_lsc_ctl :
node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 234:61]
node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 236:22]
node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
node _T_42 = bits(io.lsu_pkt_d.half, 0, 0) @[Bitwise.scala 72:15]
node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_44 = and(_T_43, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 110:53]
node _T_45 = bits(io.lsu_pkt_d.word, 0, 0) @[Bitwise.scala 72:15]
node _T_44 = and(_T_43, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 110:58]
node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_47 = and(_T_46, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 111:35]
node _T_48 = or(_T_44, _T_47) @[el2_lsu_lsc_ctl.scala 110:65]
node _T_49 = bits(io.lsu_pkt_d.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = and(_T_46, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 111:40]
node _T_48 = or(_T_44, _T_47) @[el2_lsu_lsc_ctl.scala 110:70]
node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_51 = and(_T_50, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 112:35]
node addr_offset_d = or(_T_48, _T_51) @[el2_lsu_lsc_ctl.scala 111:47]
node _T_51 = and(_T_50, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 112:40]
node addr_offset_d = or(_T_48, _T_51) @[el2_lsu_lsc_ctl.scala 111:52]
node _T_52 = bits(lsu_offset_d, 11, 11) @[el2_lsu_lsc_ctl.scala 114:39]
node _T_53 = bits(lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 114:52]
node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58]
@ -339,19 +339,19 @@ circuit el2_lsu_lsc_ctl :
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[el2_lsu_lsc_ctl.scala 121:42]
addrcheck.io.start_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 123:42]
addrcheck.io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.lsu_pkt_d.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 125:42]
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu_lsc_ctl.scala 126:42]
node _T_66 = bits(rs1_d, 31, 28) @[el2_lsu_lsc_ctl.scala 127:50]
addrcheck.io.rs1_region_d <= _T_66 @[el2_lsu_lsc_ctl.scala 127:42]
@ -392,26 +392,26 @@ circuit el2_lsu_lsc_ctl :
io.lsu_exc_m <= _T_69 @[el2_lsu_lsc_ctl.scala 156:16]
node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 157:64]
node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[el2_lsu_lsc_ctl.scala 157:62]
node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_lsc_ctl.scala 157:111]
node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[el2_lsu_lsc_ctl.scala 157:111]
node _T_73 = and(_T_71, _T_72) @[el2_lsu_lsc_ctl.scala 157:92]
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:131]
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:136]
io.lsu_single_ecc_error_incr <= _T_74 @[el2_lsu_lsc_ctl.scala 157:32]
node _T_75 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 179:46]
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 179:67]
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 179:96]
node _T_78 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:119]
node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:119]
node _T_79 = and(_T_77, _T_78) @[el2_lsu_lsc_ctl.scala 179:117]
node _T_80 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:139]
node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:137]
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:164]
node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:162]
node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:144]
node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:142]
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:174]
node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:172]
lsu_error_pkt_m.valid <= _T_83 @[el2_lsu_lsc_ctl.scala 179:27]
node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:75]
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[el2_lsu_lsc_ctl.scala 180:73]
node _T_86 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:101]
node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:101]
node _T_87 = and(_T_85, _T_86) @[el2_lsu_lsc_ctl.scala 180:99]
lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[el2_lsu_lsc_ctl.scala 180:43]
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 181:43]
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[el2_lsu_lsc_ctl.scala 181:43]
node _T_88 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 182:46]
lsu_error_pkt_m.bits.exc_type <= _T_88 @[el2_lsu_lsc_ctl.scala 182:43]
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:80]
@ -426,20 +426,20 @@ circuit el2_lsu_lsc_ctl :
lsu_error_pkt_m.bits.addr <= _T_96 @[el2_lsu_lsc_ctl.scala 184:43]
node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:72]
node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:117]
node _T_99 = and(io.lsu_pkt_m.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:161]
node _T_100 = bits(_T_99, 0, 0) @[el2_lsu_lsc_ctl.scala 185:190]
node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:166]
node _T_100 = bits(_T_99, 0, 0) @[el2_lsu_lsc_ctl.scala 185:195]
node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[el2_lsu_lsc_ctl.scala 185:137]
node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92]
node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44]
lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38]
wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.addr <= UInt<32>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.mscause <= UInt<4>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
_T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75]
reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75]
_T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75]
_T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75]
_T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75]
@ -455,28 +455,28 @@ circuit el2_lsu_lsc_ctl :
reg _T_106 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 187:75]
_T_106 <= lsu_fir_error_m @[el2_lsu_lsc_ctl.scala 187:75]
io.lsu_fir_error <= _T_106 @[el2_lsu_lsc_ctl.scala 187:38]
dma_pkt_d.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 189:22]
dma_pkt_d.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 190:22]
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 189:27]
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 190:27]
dma_pkt_d.valid <= io.dma_dccm_req @[el2_lsu_lsc_ctl.scala 191:22]
dma_pkt_d.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 192:22]
dma_pkt_d.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 193:22]
node _T_107 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 194:25]
dma_pkt_d.load <= _T_107 @[el2_lsu_lsc_ctl.scala 194:22]
node _T_108 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 195:39]
node _T_109 = eq(_T_108, UInt<3>("h00")) @[el2_lsu_lsc_ctl.scala 195:45]
dma_pkt_d.by <= _T_109 @[el2_lsu_lsc_ctl.scala 195:22]
node _T_110 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 196:39]
node _T_111 = eq(_T_110, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 196:45]
dma_pkt_d.half <= _T_111 @[el2_lsu_lsc_ctl.scala 196:22]
node _T_112 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 197:39]
node _T_113 = eq(_T_112, UInt<3>("h02")) @[el2_lsu_lsc_ctl.scala 197:45]
dma_pkt_d.word <= _T_113 @[el2_lsu_lsc_ctl.scala 197:22]
node _T_114 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 198:39]
node _T_115 = eq(_T_114, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 198:45]
dma_pkt_d.dword <= _T_115 @[el2_lsu_lsc_ctl.scala 198:22]
dma_pkt_d.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 199:34]
dma_pkt_d.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 200:34]
dma_pkt_d.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 201:34]
dma_pkt_d.bits.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 192:27]
dma_pkt_d.bits.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 193:27]
node _T_107 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 194:30]
dma_pkt_d.bits.load <= _T_107 @[el2_lsu_lsc_ctl.scala 194:27]
node _T_108 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 195:44]
node _T_109 = eq(_T_108, UInt<3>("h00")) @[el2_lsu_lsc_ctl.scala 195:50]
dma_pkt_d.bits.by <= _T_109 @[el2_lsu_lsc_ctl.scala 195:27]
node _T_110 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 196:44]
node _T_111 = eq(_T_110, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 196:50]
dma_pkt_d.bits.half <= _T_111 @[el2_lsu_lsc_ctl.scala 196:27]
node _T_112 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 197:44]
node _T_113 = eq(_T_112, UInt<3>("h02")) @[el2_lsu_lsc_ctl.scala 197:50]
dma_pkt_d.bits.word <= _T_113 @[el2_lsu_lsc_ctl.scala 197:27]
node _T_114 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 198:44]
node _T_115 = eq(_T_114, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 198:50]
dma_pkt_d.bits.dword <= _T_115 @[el2_lsu_lsc_ctl.scala 198:27]
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 199:39]
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 200:39]
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 201:39]
wire lsu_ld_datafn_r : UInt<32>
lsu_ld_datafn_r <= UInt<32>("h00")
wire lsu_ld_datafn_corr_r : UInt<32>
@ -485,143 +485,143 @@ circuit el2_lsu_lsc_ctl :
lsu_ld_datafn_m <= UInt<32>("h00")
node _T_116 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 207:50]
node _T_117 = mux(_T_116, io.lsu_p, dma_pkt_d) @[el2_lsu_lsc_ctl.scala 207:26]
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_117.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_117.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_117.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.dma <= _T_117.bits.dma @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.unsign <= _T_117.bits.unsign @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.store <= _T_117.bits.store @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.load <= _T_117.bits.load @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.dword <= _T_117.bits.dword @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.word <= _T_117.bits.word @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.half <= _T_117.bits.half @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.by <= _T_117.bits.by @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.bits.fast_int <= _T_117.bits.fast_int @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.valid <= _T_117.valid @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.store_data_bypass_m <= _T_117.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.load_ldst_bypass_d <= _T_117.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.store_data_bypass_d <= _T_117.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.dma <= _T_117.dma @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.unsign <= _T_117.unsign @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.store <= _T_117.store @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.load <= _T_117.load @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.dword <= _T_117.dword @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.word <= _T_117.word @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.half <= _T_117.half @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.by <= _T_117.by @[el2_lsu_lsc_ctl.scala 207:20]
io.lsu_pkt_d.fast_int <= _T_117.fast_int @[el2_lsu_lsc_ctl.scala 207:20]
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_m_in.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 208:20]
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.dma <= io.lsu_pkt_m.dma @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.store <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.load <= io.lsu_pkt_m.load @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.dword <= io.lsu_pkt_m.dword @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.word <= io.lsu_pkt_m.word @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.half <= io.lsu_pkt_m.half @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.by <= io.lsu_pkt_m.by @[el2_lsu_lsc_ctl.scala 209:20]
lsu_pkt_r_in.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_lsc_ctl.scala 209:20]
node _T_118 = eq(io.lsu_p.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:64]
node _T_118 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:64]
node _T_119 = and(io.flush_m_up, _T_118) @[el2_lsu_lsc_ctl.scala 211:61]
node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:45]
node _T_121 = and(io.lsu_p.valid, _T_120) @[el2_lsu_lsc_ctl.scala 211:43]
node _T_122 = or(_T_121, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 211:85]
node _T_122 = or(_T_121, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 211:90]
io.lsu_pkt_d.valid <= _T_122 @[el2_lsu_lsc_ctl.scala 211:24]
node _T_123 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:68]
node _T_123 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:68]
node _T_124 = and(io.flush_m_up, _T_123) @[el2_lsu_lsc_ctl.scala 212:65]
node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:49]
node _T_126 = and(io.lsu_pkt_d.valid, _T_125) @[el2_lsu_lsc_ctl.scala 212:47]
lsu_pkt_m_in.valid <= _T_126 @[el2_lsu_lsc_ctl.scala 212:24]
node _T_127 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:68]
node _T_127 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:68]
node _T_128 = and(io.flush_m_up, _T_127) @[el2_lsu_lsc_ctl.scala 213:65]
node _T_129 = eq(_T_128, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:49]
node _T_130 = and(io.lsu_pkt_m.valid, _T_129) @[el2_lsu_lsc_ctl.scala 213:47]
lsu_pkt_r_in.valid <= _T_130 @[el2_lsu_lsc_ctl.scala 213:24]
wire _T_131 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 215:91]
wire _T_131 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.bits.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
_T_131.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91]
reg _T_132 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[el2_lsu_lsc_ctl.scala 215:65]
reg _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.dma <= lsu_pkt_m_in.bits.dma @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.unsign <= lsu_pkt_m_in.bits.unsign @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.store <= lsu_pkt_m_in.bits.store @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.load <= lsu_pkt_m_in.bits.load @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.dword <= lsu_pkt_m_in.bits.dword @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.word <= lsu_pkt_m_in.bits.word @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.half <= lsu_pkt_m_in.bits.half @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.by <= lsu_pkt_m_in.bits.by @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.valid <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.store_data_bypass_m <= lsu_pkt_m_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.load_ldst_bypass_d <= lsu_pkt_m_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.store_data_bypass_d <= lsu_pkt_m_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.dma <= lsu_pkt_m_in.dma @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.unsign <= lsu_pkt_m_in.unsign @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.store <= lsu_pkt_m_in.store @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.load <= lsu_pkt_m_in.load @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.dword <= lsu_pkt_m_in.dword @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.word <= lsu_pkt_m_in.word @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.half <= lsu_pkt_m_in.half @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.by <= lsu_pkt_m_in.by @[el2_lsu_lsc_ctl.scala 215:65]
_T_132.fast_int <= lsu_pkt_m_in.fast_int @[el2_lsu_lsc_ctl.scala 215:65]
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_132.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_132.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_132.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.dma <= _T_132.bits.dma @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.unsign <= _T_132.bits.unsign @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.store <= _T_132.bits.store @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.load <= _T_132.bits.load @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.dword <= _T_132.bits.dword @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.word <= _T_132.bits.word @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.half <= _T_132.bits.half @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.by <= _T_132.bits.by @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.bits.fast_int <= _T_132.bits.fast_int @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.valid <= _T_132.valid @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.store_data_bypass_m <= _T_132.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.load_ldst_bypass_d <= _T_132.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.store_data_bypass_d <= _T_132.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.dma <= _T_132.dma @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.unsign <= _T_132.unsign @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.store <= _T_132.store @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.load <= _T_132.load @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.dword <= _T_132.dword @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.word <= _T_132.word @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.half <= _T_132.half @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.by <= _T_132.by @[el2_lsu_lsc_ctl.scala 215:28]
io.lsu_pkt_m.fast_int <= _T_132.fast_int @[el2_lsu_lsc_ctl.scala 215:28]
wire _T_133 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 216:91]
wire _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.bits.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
_T_133.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91]
reg _T_134 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[el2_lsu_lsc_ctl.scala 216:65]
reg _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.dma <= lsu_pkt_r_in.bits.dma @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.unsign <= lsu_pkt_r_in.bits.unsign @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.store <= lsu_pkt_r_in.bits.store @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.load <= lsu_pkt_r_in.bits.load @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.dword <= lsu_pkt_r_in.bits.dword @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.word <= lsu_pkt_r_in.bits.word @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.half <= lsu_pkt_r_in.bits.half @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.by <= lsu_pkt_r_in.bits.by @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.valid <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.store_data_bypass_m <= lsu_pkt_r_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.load_ldst_bypass_d <= lsu_pkt_r_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.store_data_bypass_d <= lsu_pkt_r_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.dma <= lsu_pkt_r_in.dma @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.unsign <= lsu_pkt_r_in.unsign @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.store <= lsu_pkt_r_in.store @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.load <= lsu_pkt_r_in.load @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.dword <= lsu_pkt_r_in.dword @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.word <= lsu_pkt_r_in.word @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.half <= lsu_pkt_r_in.half @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.by <= lsu_pkt_r_in.by @[el2_lsu_lsc_ctl.scala 216:65]
_T_134.fast_int <= lsu_pkt_r_in.fast_int @[el2_lsu_lsc_ctl.scala 216:65]
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_134.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_134.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_134.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.dma <= _T_134.bits.dma @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.unsign <= _T_134.bits.unsign @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.store <= _T_134.bits.store @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.load <= _T_134.bits.load @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.dword <= _T_134.bits.dword @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.word <= _T_134.bits.word @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.half <= _T_134.bits.half @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.by <= _T_134.bits.by @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.bits.fast_int <= _T_134.bits.fast_int @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.valid <= _T_134.valid @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.store_data_bypass_m <= _T_134.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.load_ldst_bypass_d <= _T_134.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.store_data_bypass_d <= _T_134.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.dma <= _T_134.dma @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.unsign <= _T_134.unsign @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.store <= _T_134.store @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.load <= _T_134.load @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.dword <= _T_134.dword @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.word <= _T_134.word @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.half <= _T_134.half @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.by <= _T_134.by @[el2_lsu_lsc_ctl.scala 216:28]
io.lsu_pkt_r.fast_int <= _T_134.fast_int @[el2_lsu_lsc_ctl.scala 216:28]
reg _T_135 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 217:65]
_T_135 <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 217:65]
io.lsu_pkt_m.valid <= _T_135 @[el2_lsu_lsc_ctl.scala 217:28]
@ -636,9 +636,9 @@ circuit el2_lsu_lsc_ctl :
node _T_141 = bits(dma_mem_wdata_shifted, 31, 0) @[el2_lsu_lsc_ctl.scala 221:79]
node _T_142 = bits(io.exu_lsu_rs2_d, 31, 0) @[el2_lsu_lsc_ctl.scala 221:102]
node store_data_d = mux(_T_140, _T_141, _T_142) @[el2_lsu_lsc_ctl.scala 221:34]
node _T_143 = bits(io.lsu_pkt_d.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 222:68]
node _T_144 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 222:90]
node _T_145 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 222:109]
node _T_143 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 222:73]
node _T_144 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 222:95]
node _T_145 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 222:114]
node store_data_m_in = mux(_T_143, _T_144, _T_145) @[el2_lsu_lsc_ctl.scala 222:34]
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 224:72]
store_data_pre_m <= store_data_m_in @[el2_lsu_lsc_ctl.scala 224:72]
@ -676,19 +676,19 @@ circuit el2_lsu_lsc_ctl :
node _T_155 = bits(io.lsu_ld_data_corr_r, 31, 1) @[el2_lsu_lsc_ctl.scala 237:52]
io.lsu_fir_addr <= _T_155 @[el2_lsu_lsc_ctl.scala 237:28]
io.lsu_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 239:28]
node _T_156 = or(io.lsu_pkt_r.store, io.lsu_pkt_r.load) @[el2_lsu_lsc_ctl.scala 241:63]
node _T_156 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[el2_lsu_lsc_ctl.scala 241:68]
node _T_157 = and(io.lsu_pkt_r.valid, _T_156) @[el2_lsu_lsc_ctl.scala 241:41]
node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:86]
node _T_159 = and(_T_157, _T_158) @[el2_lsu_lsc_ctl.scala 241:84]
node _T_160 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:100]
node _T_161 = and(_T_159, _T_160) @[el2_lsu_lsc_ctl.scala 241:98]
node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:96]
node _T_159 = and(_T_157, _T_158) @[el2_lsu_lsc_ctl.scala 241:94]
node _T_160 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:110]
node _T_161 = and(_T_159, _T_160) @[el2_lsu_lsc_ctl.scala 241:108]
io.lsu_commit_r <= _T_161 @[el2_lsu_lsc_ctl.scala 241:19]
node _T_162 = bits(io.picm_mask_data_m, 31, 0) @[el2_lsu_lsc_ctl.scala 242:52]
node _T_163 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 242:69]
node _T_164 = bits(_T_163, 0, 0) @[Bitwise.scala 72:15]
node _T_165 = mux(_T_164, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_166 = or(_T_162, _T_165) @[el2_lsu_lsc_ctl.scala 242:59]
node _T_167 = bits(io.lsu_pkt_m.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 242:128]
node _T_167 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 242:133]
node _T_168 = mux(_T_167, io.lsu_result_m, store_data_pre_m) @[el2_lsu_lsc_ctl.scala 242:94]
node _T_169 = and(_T_166, _T_168) @[el2_lsu_lsc_ctl.scala 242:89]
io.store_data_m <= _T_169 @[el2_lsu_lsc_ctl.scala 242:29]
@ -698,86 +698,86 @@ circuit el2_lsu_lsc_ctl :
node _T_172 = eq(addr_external_r, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 264:49]
node _T_173 = mux(_T_172, bus_read_data_r, io.lsu_ld_data_corr_r) @[el2_lsu_lsc_ctl.scala 264:33]
lsu_ld_datafn_corr_r <= _T_173 @[el2_lsu_lsc_ctl.scala 264:27]
node _T_174 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 265:61]
node _T_174 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[el2_lsu_lsc_ctl.scala 265:66]
node _T_175 = bits(_T_174, 0, 0) @[Bitwise.scala 72:15]
node _T_176 = mux(_T_175, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 265:115]
node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 265:125]
node _T_178 = cat(UInt<24>("h00"), _T_177) @[Cat.scala 29:58]
node _T_179 = and(_T_176, _T_178) @[el2_lsu_lsc_ctl.scala 265:84]
node _T_180 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 266:38]
node _T_179 = and(_T_176, _T_178) @[el2_lsu_lsc_ctl.scala 265:94]
node _T_180 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[el2_lsu_lsc_ctl.scala 266:43]
node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15]
node _T_182 = mux(_T_181, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 266:92]
node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 266:102]
node _T_184 = cat(UInt<16>("h00"), _T_183) @[Cat.scala 29:58]
node _T_185 = and(_T_182, _T_184) @[el2_lsu_lsc_ctl.scala 266:61]
node _T_186 = or(_T_179, _T_185) @[el2_lsu_lsc_ctl.scala 265:123]
node _T_187 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 267:17]
node _T_188 = and(_T_187, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 267:38]
node _T_185 = and(_T_182, _T_184) @[el2_lsu_lsc_ctl.scala 266:71]
node _T_186 = or(_T_179, _T_185) @[el2_lsu_lsc_ctl.scala 265:133]
node _T_187 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 267:17]
node _T_188 = and(_T_187, io.lsu_pkt_m.bits.by) @[el2_lsu_lsc_ctl.scala 267:43]
node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15]
node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 267:92]
node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 267:102]
node _T_192 = bits(_T_191, 0, 0) @[Bitwise.scala 72:15]
node _T_193 = mux(_T_192, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 267:115]
node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 267:125]
node _T_195 = cat(_T_193, _T_194) @[Cat.scala 29:58]
node _T_196 = and(_T_190, _T_195) @[el2_lsu_lsc_ctl.scala 267:61]
node _T_197 = or(_T_186, _T_196) @[el2_lsu_lsc_ctl.scala 266:104]
node _T_198 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 268:17]
node _T_199 = and(_T_198, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 268:38]
node _T_196 = and(_T_190, _T_195) @[el2_lsu_lsc_ctl.scala 267:71]
node _T_197 = or(_T_186, _T_196) @[el2_lsu_lsc_ctl.scala 266:114]
node _T_198 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 268:17]
node _T_199 = and(_T_198, io.lsu_pkt_m.bits.half) @[el2_lsu_lsc_ctl.scala 268:43]
node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15]
node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 268:91]
node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 268:101]
node _T_203 = bits(_T_202, 0, 0) @[Bitwise.scala 72:15]
node _T_204 = mux(_T_203, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 268:115]
node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 268:125]
node _T_206 = cat(_T_204, _T_205) @[Cat.scala 29:58]
node _T_207 = and(_T_201, _T_206) @[el2_lsu_lsc_ctl.scala 268:61]
node _T_208 = or(_T_197, _T_207) @[el2_lsu_lsc_ctl.scala 267:124]
node _T_209 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15]
node _T_207 = and(_T_201, _T_206) @[el2_lsu_lsc_ctl.scala 268:71]
node _T_208 = or(_T_197, _T_207) @[el2_lsu_lsc_ctl.scala 267:134]
node _T_209 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 269:55]
node _T_212 = and(_T_210, _T_211) @[el2_lsu_lsc_ctl.scala 269:38]
node _T_213 = or(_T_208, _T_212) @[el2_lsu_lsc_ctl.scala 268:124]
node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 269:60]
node _T_212 = and(_T_210, _T_211) @[el2_lsu_lsc_ctl.scala 269:43]
node _T_213 = or(_T_208, _T_212) @[el2_lsu_lsc_ctl.scala 268:134]
io.lsu_result_m <= _T_213 @[el2_lsu_lsc_ctl.scala 265:27]
node _T_214 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 270:61]
node _T_214 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[el2_lsu_lsc_ctl.scala 270:66]
node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15]
node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 270:120]
node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 270:130]
node _T_218 = cat(UInt<24>("h00"), _T_217) @[Cat.scala 29:58]
node _T_219 = and(_T_216, _T_218) @[el2_lsu_lsc_ctl.scala 270:84]
node _T_220 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 271:38]
node _T_219 = and(_T_216, _T_218) @[el2_lsu_lsc_ctl.scala 270:94]
node _T_220 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[el2_lsu_lsc_ctl.scala 271:43]
node _T_221 = bits(_T_220, 0, 0) @[Bitwise.scala 72:15]
node _T_222 = mux(_T_221, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 271:97]
node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 271:107]
node _T_224 = cat(UInt<16>("h00"), _T_223) @[Cat.scala 29:58]
node _T_225 = and(_T_222, _T_224) @[el2_lsu_lsc_ctl.scala 271:61]
node _T_226 = or(_T_219, _T_225) @[el2_lsu_lsc_ctl.scala 270:128]
node _T_227 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 272:17]
node _T_228 = and(_T_227, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 272:38]
node _T_225 = and(_T_222, _T_224) @[el2_lsu_lsc_ctl.scala 271:71]
node _T_226 = or(_T_219, _T_225) @[el2_lsu_lsc_ctl.scala 270:138]
node _T_227 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 272:17]
node _T_228 = and(_T_227, io.lsu_pkt_r.bits.by) @[el2_lsu_lsc_ctl.scala 272:43]
node _T_229 = bits(_T_228, 0, 0) @[Bitwise.scala 72:15]
node _T_230 = mux(_T_229, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 272:97]
node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 272:107]
node _T_232 = bits(_T_231, 0, 0) @[Bitwise.scala 72:15]
node _T_233 = mux(_T_232, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 272:125]
node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 272:135]
node _T_235 = cat(_T_233, _T_234) @[Cat.scala 29:58]
node _T_236 = and(_T_230, _T_235) @[el2_lsu_lsc_ctl.scala 272:61]
node _T_237 = or(_T_226, _T_236) @[el2_lsu_lsc_ctl.scala 271:109]
node _T_238 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 273:17]
node _T_239 = and(_T_238, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 273:38]
node _T_236 = and(_T_230, _T_235) @[el2_lsu_lsc_ctl.scala 272:71]
node _T_237 = or(_T_226, _T_236) @[el2_lsu_lsc_ctl.scala 271:119]
node _T_238 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 273:17]
node _T_239 = and(_T_238, io.lsu_pkt_r.bits.half) @[el2_lsu_lsc_ctl.scala 273:43]
node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15]
node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 273:96]
node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 273:106]
node _T_243 = bits(_T_242, 0, 0) @[Bitwise.scala 72:15]
node _T_244 = mux(_T_243, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 273:125]
node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 273:135]
node _T_246 = cat(_T_244, _T_245) @[Cat.scala 29:58]
node _T_247 = and(_T_241, _T_246) @[el2_lsu_lsc_ctl.scala 273:61]
node _T_248 = or(_T_237, _T_247) @[el2_lsu_lsc_ctl.scala 272:134]
node _T_249 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15]
node _T_247 = and(_T_241, _T_246) @[el2_lsu_lsc_ctl.scala 273:71]
node _T_248 = or(_T_237, _T_247) @[el2_lsu_lsc_ctl.scala 272:144]
node _T_249 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 274:60]
node _T_252 = and(_T_250, _T_251) @[el2_lsu_lsc_ctl.scala 274:38]
node _T_253 = or(_T_248, _T_252) @[el2_lsu_lsc_ctl.scala 273:134]
node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 274:65]
node _T_252 = and(_T_250, _T_251) @[el2_lsu_lsc_ctl.scala 274:43]
node _T_253 = or(_T_248, _T_252) @[el2_lsu_lsc_ctl.scala 273:144]
io.lsu_result_corr_r <= _T_253 @[el2_lsu_lsc_ctl.scala 270:27]

627
el2_lsu_lsc_ctl.v
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File diff suppressed because it is too large Load Diff

132
el2_lsu_stbuf.anno.json
View File

@ -1,22 +1,4 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_stbuf_full_any",
@ -25,25 +7,13 @@
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_d",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_d",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_reqvld_any",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m"
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_store"
]
},
{
@ -54,6 +24,36 @@
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_reqvld_any",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwddata_lo_m",
@ -61,17 +61,35 @@
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
@ -81,35 +99,17 @@
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
@ -118,8 +118,8 @@
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_stbuf.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
"target":"el2_lsu_stbuf.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",

2972
el2_lsu_stbuf.fir
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1350
el2_lsu_stbuf.v
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18
el2_lsu_trigger.anno.json
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@ -4,12 +4,12 @@
"sink":"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_valid",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_dma",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_dma",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_store",
@ -20,17 +20,17 @@
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_pkt",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_pkt",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_pkt",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_pkt",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_addr_m",
"~el2_lsu_trigger|el2_lsu_trigger>io_store_data_m",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_word",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_half"
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_word",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_half"
]
},
{

2418
el2_lsu_trigger.fir
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1166
el2_lsu_trigger.v
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7360
el2_pic_ctrl.fir
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3054
el2_pic_ctrl.v
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4
firrtl_black_box_resource_files.f
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@ -1,3 +1 @@
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v

BIN
project/target/config-classes/$ec5cdbc4a1416f284ecb$.class → project/target/config-classes/$802a15ecf65c09cee93d$.class
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0
project/target/config-classes/$ec5cdbc4a1416f284ecb.cache → project/target/config-classes/$802a15ecf65c09cee93d.cache
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BIN
project/target/config-classes/$802a15ecf65c09cee93d.class Normal file
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BIN
project/target/config-classes/$ec5cdbc4a1416f284ecb.class
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52
src/main/scala/dbg/el2_dbg.scala
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@ -89,7 +89,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val sb_axi_rdata = Input(UInt(64.W))
val sb_axi_rresp = Input(UInt(2.W))
val dbg_bus_clk_en = Input(Bool())
val dbg_rst_l = Input(Bool())
val dbg_rst_l = Input(AsyncReset())
val clk_override = Input(Bool())
val scan_mode = Input(Bool())
})
@ -127,30 +127,30 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)
val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset()
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool()
val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en &
((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U)))
val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
val temp_sbcs_22 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
val temp_sbcs_22 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)
} // sbcs_sbbusyerror_reg
val temp_sbcs_21 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
val temp_sbcs_21 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)
} // sbcs_sbbusy_reg
val temp_sbcs_20 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
val temp_sbcs_20 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)
} // sbcs_sbreadonaddr_reg
val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
} // sbcs_misc_reg
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
} // sbcs_error_reg
sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
@ -175,11 +175,11 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
val sbdata0_reg = withReset(!dbg_dm_rst_l) {
val sbdata0_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) {
rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)
} // dbg_sbdata0_reg
val sbdata1_reg = withReset(!dbg_dm_rst_l) {
val sbdata1_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) {
rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)
} // dbg_sbdata1_reg
@ -187,7 +187,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
sbaddress0_reg := withReset(!dbg_dm_rst_l) {
sbaddress0_reg := withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) {
rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)
} // dbg_sbaddress0_reg
@ -195,7 +195,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val dm_temp = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
val dm_temp = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(
Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),
0.U, dmcontrol_wren)
@ -208,7 +208,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
dmcontrol_reg := temp
val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegNext(dmcontrol_wren, 0.U)
} // dmcontrol_wrenff
@ -221,15 +221,15 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val temp_rst = reset.asBool()
dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
dmstatus_resumeack := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
dmstatus_resumeack := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren)
} // dmstatus_resumeack_reg
dmstatus_halted := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
dmstatus_halted := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)
} // dmstatus_halted_reg
dmstatus_havereset := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
dmstatus_havereset := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren)
} // dmstatus_havereset_reg
@ -253,11 +253,11 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
(Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) |
(Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8))
val abs_temp_12 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
val abs_temp_12 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)
} // dmabstractcs_busy_reg
val abs_temp_10_8 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegNext(abstractcs_error_din(2, 0), 0.U)
} // dmabstractcs_error_reg
@ -265,8 +265,8 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
val command_reg = withReset(!dbg_dm_rst_l) {
RegEnable(command_din, 0.U, command_wren)
val command_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) {
rvdffe(command_din, command_wren, clock, io.scan_mode)
} // dmcommand_reg
val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted)
@ -274,13 +274,13 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
val data0_reg = withReset(!dbg_dm_rst_l) {
RegEnable(data0_din, 0.U, data0_reg_wren)
val data0_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) {
rvdffe(data0_din, data0_reg_wren, clock, io.scan_mode)
} // dbg_data0_reg
val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata
data1_reg := withReset(!dbg_dm_rst_l) {
data1_reg := withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) {
rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)
} // dbg_data1_reg
@ -343,12 +343,12 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
dbg_state := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l & temp_rst) {
dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool() & temp_rst).asAsyncReset()) {
RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
} // dbg_state_reg
io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
} // dmi_rddata_reg
@ -425,7 +425,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
sbaddress0_reg_wren1 := sbcs_reg(16)
}}
sb_state := withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
sb_state := withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) {
RegEnable(sb_nxtstate, 0.U, sb_state_en)
} // sb_state_reg
@ -476,5 +476,5 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
}
object debug extends App {
chisel3.Driver.emitVerilog(new el2_dbg)
println(chisel3.Driver.emitVerilog(new el2_dbg))
}

2
src/main/scala/dec/el2_dec_decode_ctl.scala
View File

@ -821,5 +821,5 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
}
object dec_decode extends App{
chisel3.Driver.emitVerilog(new el2_dec_decode_ctl)
println(chisel3.Driver.emitVerilog(new el2_dec_decode_ctl))
}

2
src/main/scala/dec/el2_dec_ib_ctl.scala
View File

@ -92,5 +92,5 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
}
object ib_gen extends App{
chisel3.Driver.emitVerilog(new el2_dec_ib_ctl)
println(chisel3.Driver.emitVerilog(new el2_dec_ib_ctl))
}

2
src/main/scala/dec/el2_dec_trigger.scala
View File

@ -16,5 +16,5 @@ class el2_dec_trigger extends Module with el2_lib {
}
object dec_trig extends App {
chisel3.Driver execute(args, () => new el2_dec_trigger())
println(chisel3.Driver.emitVerilog(new el2_dec_trigger))
}

6
src/main/scala/el2_dma_ctrl.scala
View File

@ -10,7 +10,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val clk_override = Input(Bool())
val scan_mode = Input(Bool())
// Debug signals
// Debug signals
val dbg_cmd_addr = Input(UInt(32.W))
val dbg_cmd_wrdata = Input(UInt(32.W))
val dbg_cmd_valid = Input(Bool())
@ -24,7 +24,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val dma_dbg_cmd_fail = Output(Bool())
val dma_dbg_rddata = Output(UInt(32.W))
// Core side signals
// Core side signals
val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set)
val dma_iccm_req = Output(Bool()) // DMA iccm request
val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number
@ -552,5 +552,5 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready))
}
object dma extends App{
chisel3.Driver.emitVerilog(new el2_dma_ctrl)
println(chisel3.Driver.emitVerilog(new el2_dma_ctrl))
}

252
src/main/scala/ifu/el2_ifu_mem_ctl.scala
View File

@ -130,7 +130,7 @@ class mem_ctl_bundle extends Bundle with el2_lib{
val scan_mode = Input(Bool())
}
class el2_ifu_mem_ctl extends Module with el2_lib {
class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new mem_ctl_bundle)
io.ifu_axi_wvalid := 0.U
io.ifu_axi_wdata := 0.U
@ -178,13 +178,12 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val bus_ifu_wr_en_ff = WireInit(Bool(), false.B)
val last_beat = WireInit(Bool(), false.B)
val last_data_recieved_ff = WireInit(Bool(), false.B)
//val flush_final_f = WireInit(Bool(), 0.U)
val stream_eol_f = WireInit(Bool(), false.B)
val ic_miss_under_miss_f = WireInit(Bool(), false.B)
val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B)
val ic_debug_rd_en_ff = WireInit(Bool(), false.B)
val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode)
val flush_final_f = RegNext(io.exu_flush_final, 0.U)
val flush_final_f = withClock(io.free_clk){RegNext(io.exu_flush_final, 0.U)}
val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en
val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
@ -210,8 +209,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
}
is (crit_wrd_rdy_C){
@ -242,7 +241,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
}
}
miss_state := RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)
miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)}
val crit_byp_hit_f = WireInit(Bool(), 0.U)
val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
@ -255,7 +254,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
miss_pending := miss_state =/= idle_C
val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
(miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
@ -296,17 +295,17 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))),
Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
val scnd_miss_req_q = WireInit(Bool(), false.B)
val reset_ic_ff = WireInit(Bool(), false.B)
val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
reset_ic_ff := RegNext(reset_ic_in)
val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U)
reset_ic_ff := withClock(io.free_clk){RegNext(reset_ic_in)}
val fetch_uncacheable_ff = withClock(io.active_clk){RegNext(io.ifc_fetch_uncacheable_bf, 0.U)}
ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)}
val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0)
uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)}
@ -320,7 +319,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)}
val stream_miss_f = WireInit(Bool(), 0.U)
val ifc_fetch_req_qual_bf = io.ifc_fetch_req_bf & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f
val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U)
val ifc_fetch_req_f_raw = withClock(io.active_clk){RegNext(ifc_fetch_req_qual_bf, 0.U)}
ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final
ifc_iccm_access_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)}
val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U)
@ -333,7 +332,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val reset_tag_valid_for_miss = WireInit(Bool(), false.B)
val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
!sel_mb_addr -> io.ifc_fetch_addr_bf))
!sel_mb_addr -> io.ifc_fetch_addr_bf))
val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B)
val sel_mb_status_addr = miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q
val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f)
@ -350,7 +349,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err
val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U)
val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U)
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
io.ic_debug_rd_data)
io.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)}
@ -400,8 +399,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W)))
for(i<- 0 until ICACHE_NUM_BEATS){
val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f)))
ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
@ -416,16 +415,16 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U
val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i)))
val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U)
val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0)
val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U)
@ -499,7 +498,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_tlu_force_halt
}
is(ecc_wff_C){
perr_nxtstate := Mux(((io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C)
perr_nxtstate := Mux(((!io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C)
perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt
}
is(dma_sb_err_C){
@ -516,7 +515,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val err_stop_nxtstate = WireInit(UInt(2.W), 0.U)
val err_stop_state_en = WireInit(Bool(), false.B)
io.iccm_correction_state := false.B
// val err_stop_fetch := WireInit(Bool(), false.B)
// val err_stop_fetch := WireInit(Bool(), false.B)
switch(err_stop_state){
is(err_stop_idle_C){
err_stop_nxtstate := err_fetch1_C
@ -547,8 +546,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
}
err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
bus_ifu_bus_clk_en := io.ifu_bus_clk_en
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode)
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode)
val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)}
@ -561,7 +560,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)}
val bus_cmd_sent = WireInit(Bool(), false.B)
val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_tlu_force_halt
bus_cmd_sent := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)}
// AXI Read-Channel
io.ifu_axi_arvalid := ifu_bus_cmd_valid
io.ifu_axi_arid := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid)
@ -604,8 +603,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
// Request Address Count
val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
// Command beat Count
val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_tlu_force_halt
@ -661,7 +660,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val iccm_dma_rvalid_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rvalid_in, false.B)} else 0.U
io.iccm_dma_rvalid := iccm_dma_rvalid_temp
val iccm_dma_ecc_error = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_ecc_error_in, false.B)} else 0.U
io.iccm_dma_ecc_error := iccm_dma_ecc_error_in
io.iccm_dma_ecc_error := iccm_dma_ecc_error
val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U
io.iccm_dma_rdata := iccm_dma_rdata_temp
val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
@ -699,106 +698,106 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
((miss_state===miss_wait_C) & !miss_state_en) |
((miss_state===crit_wrd_rdy_C) & !miss_state_en) |
((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) |
(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
reset_all_tags := withClock(io.active_clk){RegNext(io.dec_tlu_fence_i_wb, false.B)}
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
RegNext(ifu_status_wr_addr_w_debug, 0.U)
}
val way_status_wr_en = WireInit(Bool(), false.B)
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array)
val way_status_wr_en_ff = withClock(io.free_clk) {
RegNext(way_status_wr_en_w_debug, false.B)
}
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
val way_status_new_ff = withClock(io.free_clk) {
RegNext(way_status_new_w_debug, 0.U)
}
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
RegNext(ifu_status_wr_addr_w_debug, 0.U)
}
val way_status_wr_en = WireInit(Bool(), false.B)
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array)
val way_status_wr_en_ff = withClock(io.free_clk) {
RegNext(way_status_wr_en_w_debug, false.B)
}
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
val way_status_new_ff = withClock(io.free_clk) {
RegNext(way_status_new_w_debug, 0.U)
}
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
// io.test_way_status_out := test_way_status_out
// io.test_way_status_out := test_way_status_out
val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
//io.test_way_status_clken := test_way_status_clken
way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
}
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
val ifu_tag_wren_ff = withClock(io.free_clk) {
RegNext(ifu_tag_wren_w_debug, 0.U)
}
val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid)
val ic_valid_ff = withClock(io.free_clk) {
RegNext(ic_valid_w_debug, false.B)
}
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
reset_all_tags).reverse.reduce(Cat(_, _)))
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
}
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
val ifu_tag_wren_ff = withClock(io.free_clk) {
RegNext(ifu_tag_wren_w_debug, 0.U)
}
val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid)
val ic_valid_ff = withClock(io.free_clk) {
RegNext(ic_valid_w_debug, false.B)
}
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
reset_all_tags).reverse.reduce(Cat(_, _)))
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
// Making a sudo LRU
// val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool()))
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
if (ICACHE_NUM_WAYS == 4) {
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
// Making a sudo LRU
// val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool()))
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
if (ICACHE_NUM_WAYS == 4) {
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
(!tagv_mb_ff(1) & tagv_mb_ff(0))
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
}
else {
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
way_status_hit_new := io.ic_rd_hit(0)
way_status_rep_new := replace_way_mb_any(0)
}
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
}
else {
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
way_status_hit_new := io.ic_rd_hit(0)
way_status_rep_new := replace_way_mb_any(0)
}
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
if(!ICACHE_ENABLE){
@ -838,15 +837,15 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)}
io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)}
val ifc_region_acc_okay = Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR() |
INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U)) |
INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U)) |
INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U)) |
INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U)) |
INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U)) |
INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U)) |
INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U)) |
INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U))
val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) |
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |
(INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) |
(INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) |
(INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) |
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
@ -854,5 +853,4 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
}
object ifu_mem extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
}
}

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src/main/scala/lsu/el2_lsu.scala
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@ -241,7 +241,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_m_clk
dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_c2_r_clk
dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_free_c2_clk
dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_c1_r_clk
dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk
//dccm_ctl.io.clk := clock
dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m

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target/scala-2.12/classes/dbg/debug$.class
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target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class
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target/scala-2.12/classes/dbg/el2_dbg.class
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target/scala-2.12/classes/dec/dec_decode$.class
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target/scala-2.12/classes/dec/dec_trig$.class
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target/scala-2.12/classes/dec/ib_gen$.class
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target/scala-2.12/classes/dma$.class
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target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
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target/scala-2.12/classes/ifu/ifu_mem$.class
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target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class
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target/scala-2.12/classes/ifu/mem_ctl_bundle.class
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target/scala-2.12/classes/lsu/el2_lsu.class
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