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ALN 1st attempt

This commit is contained in:
waleed-lm 2020-10-01 14:49:02 +05:00
parent 11576a9414
commit 9f854c59ec
7 changed files with 777 additions and 779 deletions
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1316
el2_ifu_aln_ctl.fir
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239
el2_ifu_aln_ctl.v
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@ -511,7 +511,6 @@ module el2_ifu_aln_ctl(
input clock, input clock,
input reset, input reset,
input io_scan_mode, input io_scan_mode,
input io_free_clk,
input io_active_clk, input io_active_clk,
input io_ifu_async_error_start, input io_ifu_async_error_start,
input io_iccm_rd_ecc_double_err, input io_iccm_rd_ecc_double_err,
@ -576,30 +575,30 @@ module el2_ifu_aln_ctl(
reg [31:0] _RAND_16; reg [31:0] _RAND_16;
reg [31:0] _RAND_17; reg [31:0] _RAND_17;
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 100:28] wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 99:28]
wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 100:28] wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 99:28]
reg error_stall; // @[el2_ifu_aln_ctl.scala 90:54] reg error_stall; // @[el2_ifu_aln_ctl.scala 89:54]
reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 91:48] reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 90:48]
wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 92:34] wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 91:34]
wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 92:64] wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 91:64]
wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 92:62] wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 91:62]
wire _T_3 = ~error_stall; // @[el2_ifu_aln_ctl.scala 94:39] wire _T_3 = ~error_stall; // @[el2_ifu_aln_ctl.scala 93:39]
wire i0_shift = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 94:37] wire i0_shift = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 93:37]
wire _T_7 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 98:58] wire _T_7 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 97:58]
wire _T_9 = _T_7 & f0val[0]; // @[el2_ifu_aln_ctl.scala 98:68] wire _T_9 = _T_7 & f0val[0]; // @[el2_ifu_aln_ctl.scala 97:68]
reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 125:48] reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 124:48]
wire _T_252 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 179:32] wire _T_252 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 178:32]
reg q1off; // @[el2_ifu_aln_ctl.scala 132:48] reg q1off; // @[el2_ifu_aln_ctl.scala 131:48]
wire _T_255 = _T_252 & q1off; // @[Mux.scala 27:72] wire _T_255 = _T_252 & q1off; // @[Mux.scala 27:72]
wire _T_253 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 179:57] wire _T_253 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 178:57]
reg q2off; // @[el2_ifu_aln_ctl.scala 131:48] reg q2off; // @[el2_ifu_aln_ctl.scala 130:48]
wire _T_256 = _T_253 & q2off; // @[Mux.scala 27:72] wire _T_256 = _T_253 & q2off; // @[Mux.scala 27:72]
wire _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72] wire _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72]
wire _T_254 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 179:83] wire _T_254 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 178:83]
reg q0off; // @[el2_ifu_aln_ctl.scala 133:48] reg q0off; // @[el2_ifu_aln_ctl.scala 132:48]
wire _T_257 = _T_254 & q0off; // @[Mux.scala 27:72] wire _T_257 = _T_254 & q0off; // @[Mux.scala 27:72]
wire q1ptr = _T_258 | _T_257; // @[Mux.scala 27:72] wire q1ptr = _T_258 | _T_257; // @[Mux.scala 27:72]
wire _T_261 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 183:26] wire _T_261 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 182:26]
wire [1:0] q1sel = {q1ptr,_T_261}; // @[Cat.scala 29:58] wire [1:0] q1sel = {q1ptr,_T_261}; // @[Cat.scala 29:58]
wire [2:0] qren = {_T_254,_T_253,_T_252}; // @[Cat.scala 29:58] wire [2:0] qren = {_T_254,_T_253,_T_252}; // @[Cat.scala 29:58]
reg [31:0] q1; // @[Reg.scala 27:20] reg [31:0] q1; // @[Reg.scala 27:20]
@ -613,7 +612,7 @@ module el2_ifu_aln_ctl(
wire [63:0] _T_327 = {q0,q2}; // @[Cat.scala 29:58] wire [63:0] _T_327 = {q0,q2}; // @[Cat.scala 29:58]
wire [63:0] _T_330 = qren[2] ? _T_327 : 64'h0; // @[Mux.scala 27:72] wire [63:0] _T_330 = qren[2] ? _T_327 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] qeff = _T_331 | _T_330; // @[Mux.scala 27:72] wire [63:0] qeff = _T_331 | _T_330; // @[Mux.scala 27:72]
wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 226:29] wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 225:29]
wire [15:0] _T_527 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_527 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
wire [15:0] _T_528 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_528 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
wire [15:0] q1final = _T_527 | _T_528; // @[Mux.scala 27:72] wire [15:0] q1final = _T_527 | _T_528; // @[Mux.scala 27:72]
@ -622,111 +621,111 @@ module el2_ifu_aln_ctl(
wire _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72] wire _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72]
wire _T_249 = _T_254 & q2off; // @[Mux.scala 27:72] wire _T_249 = _T_254 & q2off; // @[Mux.scala 27:72]
wire q0ptr = _T_250 | _T_249; // @[Mux.scala 27:72] wire q0ptr = _T_250 | _T_249; // @[Mux.scala 27:72]
wire _T_260 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 181:26] wire _T_260 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 180:26]
wire [1:0] q0sel = {q0ptr,_T_260}; // @[Cat.scala 29:58] wire [1:0] q0sel = {q0ptr,_T_260}; // @[Cat.scala 29:58]
wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 226:42] wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 225:42]
wire [31:0] _T_517 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_517 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
wire [15:0] _T_518 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_518 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
wire [31:0] _GEN_12 = {{16'd0}, _T_518}; // @[Mux.scala 27:72] wire [31:0] _GEN_12 = {{16'd0}, _T_518}; // @[Mux.scala 27:72]
wire [31:0] _T_519 = _T_517 | _GEN_12; // @[Mux.scala 27:72] wire [31:0] _T_519 = _T_517 | _GEN_12; // @[Mux.scala 27:72]
wire [15:0] q0final = _T_519[15:0]; // @[el2_ifu_aln_ctl.scala 295:11] wire [15:0] q0final = _T_519[15:0]; // @[el2_ifu_aln_ctl.scala 294:11]
wire [31:0] _T_11 = {q1final,q0final}; // @[Cat.scala 29:58] wire [31:0] _T_11 = {q1final,q0final}; // @[Cat.scala 29:58]
wire [15:0] _T_12 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_12 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72]
wire [31:0] _T_13 = _T_9 ? _T_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_13 = _T_9 ? _T_11 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _GEN_13 = {{16'd0}, _T_12}; // @[Mux.scala 27:72] wire [31:0] _GEN_13 = {{16'd0}, _T_12}; // @[Mux.scala 27:72]
wire [31:0] aligndata = _GEN_13 | _T_13; // @[Mux.scala 27:72] wire [31:0] aligndata = _GEN_13 | _T_13; // @[Mux.scala 27:72]
reg [54:0] _T_768; // @[Reg.scala 27:20] reg [54:0] _T_768; // @[Reg.scala 27:20]
wire [53:0] misc1 = _T_768[53:0]; // @[el2_ifu_aln_ctl.scala 373:9] wire [53:0] misc1 = _T_768[53:0]; // @[el2_ifu_aln_ctl.scala 372:9]
reg [54:0] _T_770; // @[Reg.scala 27:20] reg [54:0] _T_770; // @[Reg.scala 27:20]
wire [53:0] misc0 = _T_770[53:0]; // @[el2_ifu_aln_ctl.scala 374:9] wire [53:0] misc0 = _T_770[53:0]; // @[el2_ifu_aln_ctl.scala 373:9]
wire [107:0] _T_269 = {misc1,misc0}; // @[Cat.scala 29:58] wire [107:0] _T_269 = {misc1,misc0}; // @[Cat.scala 29:58]
wire [107:0] _T_276 = qren[0] ? _T_269 : 108'h0; // @[Mux.scala 27:72] wire [107:0] _T_276 = qren[0] ? _T_269 : 108'h0; // @[Mux.scala 27:72]
reg [54:0] _T_766; // @[Reg.scala 27:20] reg [54:0] _T_766; // @[Reg.scala 27:20]
wire [53:0] misc2 = _T_766[53:0]; // @[el2_ifu_aln_ctl.scala 372:9] wire [53:0] misc2 = _T_766[53:0]; // @[el2_ifu_aln_ctl.scala 371:9]
wire [107:0] _T_272 = {misc2,misc1}; // @[Cat.scala 29:58] wire [107:0] _T_272 = {misc2,misc1}; // @[Cat.scala 29:58]
wire [107:0] _T_277 = qren[1] ? _T_272 : 108'h0; // @[Mux.scala 27:72] wire [107:0] _T_277 = qren[1] ? _T_272 : 108'h0; // @[Mux.scala 27:72]
wire [107:0] _T_279 = _T_276 | _T_277; // @[Mux.scala 27:72] wire [107:0] _T_279 = _T_276 | _T_277; // @[Mux.scala 27:72]
wire [107:0] _T_275 = {misc0,misc2}; // @[Cat.scala 29:58] wire [107:0] _T_275 = {misc0,misc2}; // @[Cat.scala 29:58]
wire [107:0] _T_278 = qren[2] ? _T_275 : 108'h0; // @[Mux.scala 27:72] wire [107:0] _T_278 = qren[2] ? _T_275 : 108'h0; // @[Mux.scala 27:72]
wire [107:0] misceff = _T_279 | _T_278; // @[Mux.scala 27:72] wire [107:0] misceff = _T_279 | _T_278; // @[Mux.scala 27:72]
wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 192:25] wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 191:25]
wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 196:21] wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 195:21]
wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 193:25] wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 192:25]
wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 203:21] wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 202:21]
wire [1:0] _T_23 = {f1icaf,f0icaf}; // @[Cat.scala 29:58] wire [1:0] _T_23 = {f1icaf,f0icaf}; // @[Cat.scala 29:58]
wire _T_24 = f0val[1] & f0icaf; // @[Mux.scala 27:72] wire _T_24 = f0val[1] & f0icaf; // @[Mux.scala 27:72]
wire [1:0] _T_25 = _T_9 ? _T_23 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_25 = _T_9 ? _T_23 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_14 = {{1'd0}, _T_24}; // @[Mux.scala 27:72] wire [1:0] _GEN_14 = {{1'd0}, _T_24}; // @[Mux.scala 27:72]
wire [1:0] alignicaf = _GEN_14 | _T_25; // @[Mux.scala 27:72] wire [1:0] alignicaf = _GEN_14 | _T_25; // @[Mux.scala 27:72]
wire [1:0] _T_539 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_539 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 128:48] reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 127:48]
wire [1:0] _T_538 = {f1val[0],1'h1}; // @[Cat.scala 29:58] wire [1:0] _T_538 = {f1val[0],1'h1}; // @[Cat.scala 29:58]
wire [1:0] _T_540 = _T_9 ? _T_538 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_540 = _T_9 ? _T_538 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] alignval = _T_539 | _T_540; // @[Mux.scala 27:72] wire [1:0] alignval = _T_539 | _T_540; // @[Mux.scala 27:72]
wire f0_shift_2B = i0_shift & f0val[0]; // @[Mux.scala 27:72] wire f0_shift_2B = i0_shift & f0val[0]; // @[Mux.scala 27:72]
reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 124:48] reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 123:48]
reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 127:48] reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 126:48]
wire _T_58 = ~f1val[0]; // @[el2_ifu_aln_ctl.scala 135:42] wire _T_58 = ~f1val[0]; // @[el2_ifu_aln_ctl.scala 134:42]
wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 247:20] wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 246:20]
wire _T_60 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 135:55] wire _T_60 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 134:55]
wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 257:30] wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 256:30]
wire _T_65 = _T_58 & f2_valid; // @[el2_ifu_aln_ctl.scala 136:53] wire _T_65 = _T_58 & f2_valid; // @[el2_ifu_aln_ctl.scala 135:53]
wire _T_66 = _T_65 & ifvalid; // @[el2_ifu_aln_ctl.scala 136:65] wire _T_66 = _T_65 & ifvalid; // @[el2_ifu_aln_ctl.scala 135:65]
wire _T_70 = f1val[0] & _T_60; // @[el2_ifu_aln_ctl.scala 137:53] wire _T_70 = f1val[0] & _T_60; // @[el2_ifu_aln_ctl.scala 136:53]
wire _T_71 = _T_70 & ifvalid; // @[el2_ifu_aln_ctl.scala 137:65] wire _T_71 = _T_70 & ifvalid; // @[el2_ifu_aln_ctl.scala 136:65]
wire fetch_to_f1 = _T_66 | _T_71; // @[el2_ifu_aln_ctl.scala 136:77] wire fetch_to_f1 = _T_66 | _T_71; // @[el2_ifu_aln_ctl.scala 135:77]
wire _T_80 = f1val[0] & f2_valid; // @[el2_ifu_aln_ctl.scala 140:53] wire _T_80 = f1val[0] & f2_valid; // @[el2_ifu_aln_ctl.scala 139:53]
wire f2_wr_en = _T_80 & ifvalid; // @[el2_ifu_aln_ctl.scala 140:65] wire f2_wr_en = _T_80 & ifvalid; // @[el2_ifu_aln_ctl.scala 139:65]
wire _T_94 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 148:24] wire _T_94 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 147:24]
wire _T_95 = _T_94 & ifvalid; // @[el2_ifu_aln_ctl.scala 148:32] wire _T_95 = _T_94 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:32]
wire _T_96 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 148:49] wire _T_96 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 147:49]
wire _T_97 = _T_96 & ifvalid; // @[el2_ifu_aln_ctl.scala 148:57] wire _T_97 = _T_96 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:57]
wire _T_98 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 148:74] wire _T_98 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 147:74]
wire _T_99 = _T_98 & ifvalid; // @[el2_ifu_aln_ctl.scala 148:82] wire _T_99 = _T_98 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:82]
wire [2:0] qwen = {_T_95,_T_97,_T_99}; // @[Cat.scala 29:58] wire [2:0] qwen = {_T_95,_T_97,_T_99}; // @[Cat.scala 29:58]
wire _T_153 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 158:34] wire _T_153 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 157:34]
wire _T_157 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 159:34] wire _T_157 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 158:34]
wire _T_163 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 161:26] wire _T_163 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 160:26]
wire _T_165 = _T_163 & _T_1; // @[el2_ifu_aln_ctl.scala 161:35] wire _T_165 = _T_163 & _T_1; // @[el2_ifu_aln_ctl.scala 160:35]
wire [1:0] _T_168 = _T_157 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_168 = _T_157 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_170 = _T_165 ? wrptr : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_170 = _T_165 ? wrptr : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_17 = {{1'd0}, _T_153}; // @[Mux.scala 27:72] wire [1:0] _GEN_17 = {{1'd0}, _T_153}; // @[Mux.scala 27:72]
wire [1:0] _T_171 = _GEN_17 | _T_168; // @[Mux.scala 27:72] wire [1:0] _T_171 = _GEN_17 | _T_168; // @[Mux.scala 27:72]
wire [1:0] wrptr_in = _T_171 | _T_170; // @[Mux.scala 27:72] wire [1:0] wrptr_in = _T_171 | _T_170; // @[Mux.scala 27:72]
wire _T_176 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 163:26] wire _T_176 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 162:26]
wire _T_178 = _T_176 & _T_254; // @[el2_ifu_aln_ctl.scala 163:35] wire _T_178 = _T_176 & _T_254; // @[el2_ifu_aln_ctl.scala 162:35]
wire _T_180 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 163:74] wire _T_180 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 162:74]
wire _T_184 = _T_176 & _T_253; // @[el2_ifu_aln_ctl.scala 164:35] wire _T_184 = _T_176 & _T_253; // @[el2_ifu_aln_ctl.scala 163:35]
wire _T_190 = _T_176 & _T_252; // @[el2_ifu_aln_ctl.scala 165:35] wire _T_190 = _T_176 & _T_252; // @[el2_ifu_aln_ctl.scala 164:35]
wire _T_192 = _T_178 & _T_180; // @[Mux.scala 27:72] wire _T_192 = _T_178 & _T_180; // @[Mux.scala 27:72]
wire _T_193 = _T_184 & q2off; // @[Mux.scala 27:72] wire _T_193 = _T_184 & q2off; // @[Mux.scala 27:72]
wire _T_194 = _T_190 & q2off; // @[Mux.scala 27:72] wire _T_194 = _T_190 & q2off; // @[Mux.scala 27:72]
wire _T_195 = _T_192 | _T_193; // @[Mux.scala 27:72] wire _T_195 = _T_192 | _T_193; // @[Mux.scala 27:72]
wire q2off_in = _T_195 | _T_194; // @[Mux.scala 27:72] wire q2off_in = _T_195 | _T_194; // @[Mux.scala 27:72]
wire _T_199 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 167:26] wire _T_199 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 166:26]
wire _T_201 = _T_199 & _T_253; // @[el2_ifu_aln_ctl.scala 167:35] wire _T_201 = _T_199 & _T_253; // @[el2_ifu_aln_ctl.scala 166:35]
wire _T_203 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 167:74] wire _T_203 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 166:74]
wire _T_207 = _T_199 & _T_252; // @[el2_ifu_aln_ctl.scala 168:35] wire _T_207 = _T_199 & _T_252; // @[el2_ifu_aln_ctl.scala 167:35]
wire _T_213 = _T_199 & _T_254; // @[el2_ifu_aln_ctl.scala 169:35] wire _T_213 = _T_199 & _T_254; // @[el2_ifu_aln_ctl.scala 168:35]
wire _T_215 = _T_201 & _T_203; // @[Mux.scala 27:72] wire _T_215 = _T_201 & _T_203; // @[Mux.scala 27:72]
wire _T_216 = _T_207 & q1off; // @[Mux.scala 27:72] wire _T_216 = _T_207 & q1off; // @[Mux.scala 27:72]
wire _T_217 = _T_213 & q1off; // @[Mux.scala 27:72] wire _T_217 = _T_213 & q1off; // @[Mux.scala 27:72]
wire _T_218 = _T_215 | _T_216; // @[Mux.scala 27:72] wire _T_218 = _T_215 | _T_216; // @[Mux.scala 27:72]
wire q1off_in = _T_218 | _T_217; // @[Mux.scala 27:72] wire q1off_in = _T_218 | _T_217; // @[Mux.scala 27:72]
wire _T_222 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 171:26] wire _T_222 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 170:26]
wire _T_224 = _T_222 & _T_252; // @[el2_ifu_aln_ctl.scala 171:35] wire _T_224 = _T_222 & _T_252; // @[el2_ifu_aln_ctl.scala 170:35]
wire _T_226 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 171:76] wire _T_226 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 170:76]
wire _T_230 = _T_222 & _T_254; // @[el2_ifu_aln_ctl.scala 172:35] wire _T_230 = _T_222 & _T_254; // @[el2_ifu_aln_ctl.scala 171:35]
wire _T_236 = _T_222 & _T_253; // @[el2_ifu_aln_ctl.scala 173:35] wire _T_236 = _T_222 & _T_253; // @[el2_ifu_aln_ctl.scala 172:35]
wire _T_238 = _T_224 & _T_226; // @[Mux.scala 27:72] wire _T_238 = _T_224 & _T_226; // @[Mux.scala 27:72]
wire _T_239 = _T_230 & q0off; // @[Mux.scala 27:72] wire _T_239 = _T_230 & q0off; // @[Mux.scala 27:72]
wire _T_240 = _T_236 & q0off; // @[Mux.scala 27:72] wire _T_240 = _T_236 & q0off; // @[Mux.scala 27:72]
wire _T_241 = _T_238 | _T_239; // @[Mux.scala 27:72] wire _T_241 = _T_238 | _T_239; // @[Mux.scala 27:72]
wire q0off_in = _T_241 | _T_240; // @[Mux.scala 27:72] wire q0off_in = _T_241 | _T_240; // @[Mux.scala 27:72]
wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58] wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 195:25] wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 194:25]
wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 202:25] wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 201:25]
wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 205:25] wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 204:25]
wire [5:0] _T_299 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58] wire [5:0] _T_299 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_299}; // @[Cat.scala 29:58] wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_299}; // @[Cat.scala 29:58]
reg [11:0] brdata1; // @[Reg.scala 27:20] reg [11:0] brdata1; // @[Reg.scala 27:20]
@ -740,8 +739,8 @@ module el2_ifu_aln_ctl(
wire [23:0] _T_316 = qren[2] ? _T_313 : 24'h0; // @[Mux.scala 27:72] wire [23:0] _T_316 = qren[2] ? _T_313 : 24'h0; // @[Mux.scala 27:72]
wire [23:0] _T_317 = _T_314 | _T_315; // @[Mux.scala 27:72] wire [23:0] _T_317 = _T_314 | _T_315; // @[Mux.scala 27:72]
wire [23:0] brdataeff = _T_317 | _T_316; // @[Mux.scala 27:72] wire [23:0] brdataeff = _T_317 | _T_316; // @[Mux.scala 27:72]
wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 217:43] wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 216:43]
wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 217:61] wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 216:61]
wire [11:0] _T_338 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_338 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72]
wire [5:0] _T_339 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72] wire [5:0] _T_339 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72]
wire [11:0] _GEN_18 = {{6'd0}, _T_339}; // @[Mux.scala 27:72] wire [11:0] _GEN_18 = {{6'd0}, _T_339}; // @[Mux.scala 27:72]
@ -762,32 +761,32 @@ module el2_ifu_aln_ctl(
wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58] wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58]
wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58] wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58]
wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58] wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58]
wire consume_fb1 = _T_58 & f1val[0]; // @[el2_ifu_aln_ctl.scala 252:32] wire consume_fb1 = _T_58 & f1val[0]; // @[el2_ifu_aln_ctl.scala 251:32]
wire _T_382 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 254:39] wire _T_382 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 253:39]
wire _T_383 = f0val[0] & _T_382; // @[el2_ifu_aln_ctl.scala 254:37] wire _T_383 = f0val[0] & _T_382; // @[el2_ifu_aln_ctl.scala 253:37]
wire _T_386 = f0val[0] & consume_fb1; // @[el2_ifu_aln_ctl.scala 255:37] wire _T_386 = f0val[0] & consume_fb1; // @[el2_ifu_aln_ctl.scala 254:37]
wire _T_409 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 272:28] wire _T_409 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 271:28]
wire _T_410 = ~_T_80; // @[el2_ifu_aln_ctl.scala 272:43] wire _T_410 = ~_T_80; // @[el2_ifu_aln_ctl.scala 271:43]
wire _T_411 = _T_409 & _T_410; // @[el2_ifu_aln_ctl.scala 272:41] wire _T_411 = _T_409 & _T_410; // @[el2_ifu_aln_ctl.scala 271:41]
wire _T_422 = ~_T_65; // @[el2_ifu_aln_ctl.scala 277:43] wire _T_422 = ~_T_65; // @[el2_ifu_aln_ctl.scala 276:43]
wire _T_435 = f2_wr_en & _T_1; // @[el2_ifu_aln_ctl.scala 279:38] wire _T_435 = f2_wr_en & _T_1; // @[el2_ifu_aln_ctl.scala 278:38]
wire _T_437 = ~f2_wr_en; // @[el2_ifu_aln_ctl.scala 280:6] wire _T_437 = ~f2_wr_en; // @[el2_ifu_aln_ctl.scala 279:6]
wire _T_439 = _T_437 & _T_410; // @[el2_ifu_aln_ctl.scala 280:19] wire _T_439 = _T_437 & _T_410; // @[el2_ifu_aln_ctl.scala 279:19]
wire _T_441 = _T_439 & _T_422; // @[el2_ifu_aln_ctl.scala 280:34] wire _T_441 = _T_439 & _T_422; // @[el2_ifu_aln_ctl.scala 279:34]
wire _T_443 = _T_441 & _T_1; // @[el2_ifu_aln_ctl.scala 280:49] wire _T_443 = _T_441 & _T_1; // @[el2_ifu_aln_ctl.scala 279:49]
wire [1:0] _T_445 = _T_435 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_445 = _T_435 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_446 = _T_443 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_446 = _T_443 ? f2val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] f2val_in = _T_445 | _T_446; // @[Mux.scala 27:72] wire [1:0] f2val_in = _T_445 | _T_446; // @[Mux.scala 27:72]
wire _T_458 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 284:38] wire _T_458 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 283:38]
wire _T_461 = _T_80 & _T_1; // @[el2_ifu_aln_ctl.scala 285:38] wire _T_461 = _T_80 & _T_1; // @[el2_ifu_aln_ctl.scala 284:38]
wire _T_467 = _T_411 & _T_58; // @[el2_ifu_aln_ctl.scala 286:54] wire _T_467 = _T_411 & _T_58; // @[el2_ifu_aln_ctl.scala 285:54]
wire _T_469 = _T_467 & _T_1; // @[el2_ifu_aln_ctl.scala 286:69] wire _T_469 = _T_467 & _T_1; // @[el2_ifu_aln_ctl.scala 285:69]
wire [1:0] _T_471 = _T_458 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_471 = _T_458 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_472 = _T_461 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_472 = _T_461 ? f2val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_473 = _T_469 ? f1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_473 = _T_469 ? f1val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_474 = _T_471 | _T_472; // @[Mux.scala 27:72] wire [1:0] _T_474 = _T_471 | _T_472; // @[Mux.scala 27:72]
wire [1:0] f1val_in = _T_474 | _T_473; // @[Mux.scala 27:72] wire [1:0] f1val_in = _T_474 | _T_473; // @[Mux.scala 27:72]
wire _T_479 = ~i0_shift; // @[el2_ifu_aln_ctl.scala 288:52] wire _T_479 = ~i0_shift; // @[el2_ifu_aln_ctl.scala 287:52]
wire _T_483 = i0_shift & f0val[1]; // @[Mux.scala 27:72] wire _T_483 = i0_shift & f0val[1]; // @[Mux.scala 27:72]
wire [1:0] _T_484 = _T_479 ? f0val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_484 = _T_479 ? f0val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_23 = {{1'd0}, _T_483}; // @[Mux.scala 27:72] wire [1:0] _GEN_23 = {{1'd0}, _T_483}; // @[Mux.scala 27:72]
@ -821,36 +820,36 @@ module el2_ifu_aln_ctl(
wire [1:0] _T_631 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_631 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_632 = _T_9 ? _T_630 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_632 = _T_9 ? _T_630 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] alignhist0 = _T_631 | _T_632; // @[Mux.scala 27:72] wire [1:0] alignhist0 = _T_631 | _T_632; // @[Mux.scala 27:72]
wire i0_brp_pc4 = alignpc4[0]; // @[el2_ifu_aln_ctl.scala 357:39] wire i0_brp_pc4 = alignpc4[0]; // @[el2_ifu_aln_ctl.scala 356:39]
el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 100:28] el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 99:28]
.io_din(decompressed_io_din), .io_din(decompressed_io_din),
.io_dout(decompressed_io_dout) .io_dout(decompressed_io_dout)
); );
assign io_ifu_i0_valid = alignval[0]; // @[el2_ifu_aln_ctl.scala 116:19] assign io_ifu_i0_valid = alignval[0]; // @[el2_ifu_aln_ctl.scala 115:19]
assign io_ifu_i0_icaf = alignicaf[0]; // @[el2_ifu_aln_ctl.scala 115:18] assign io_ifu_i0_icaf = alignicaf[0]; // @[el2_ifu_aln_ctl.scala 114:18]
assign io_ifu_i0_icaf_type = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 325:23] assign io_ifu_i0_icaf_type = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 324:23]
assign io_ifu_i0_icaf_f1 = 1'h0; // @[el2_ifu_aln_ctl.scala 329:21] assign io_ifu_i0_icaf_f1 = 1'h0; // @[el2_ifu_aln_ctl.scala 328:21]
assign io_ifu_i0_dbecc = aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 331:19] assign io_ifu_i0_dbecc = aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 330:19]
assign io_ifu_i0_instr = decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 104:20] assign io_ifu_i0_instr = decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 103:20]
assign io_ifu_i0_pc = 32'h0; // @[el2_ifu_aln_ctl.scala 321:16] assign io_ifu_i0_pc = 32'h0; // @[el2_ifu_aln_ctl.scala 320:16]
assign io_ifu_i0_pc4 = 1'h0; // @[el2_ifu_aln_ctl.scala 117:17] assign io_ifu_i0_pc4 = 1'h0; // @[el2_ifu_aln_ctl.scala 116:17]
assign io_ifu_fb_consume1 = _T_383 & _T_1; // @[el2_ifu_aln_ctl.scala 254:22] assign io_ifu_fb_consume1 = _T_383 & _T_1; // @[el2_ifu_aln_ctl.scala 253:22]
assign io_ifu_fb_consume2 = _T_386 & _T_1; // @[el2_ifu_aln_ctl.scala 255:22] assign io_ifu_fb_consume2 = _T_386 & _T_1; // @[el2_ifu_aln_ctl.scala 254:22]
assign io_ifu_i0_bp_index = 7'h0; // @[el2_ifu_aln_ctl.scala 362:22] assign io_ifu_i0_bp_index = 7'h0; // @[el2_ifu_aln_ctl.scala 361:22]
assign io_ifu_i0_bp_fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 364:21] assign io_ifu_i0_bp_fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 363:21]
assign io_ifu_i0_bp_btag = 5'h0; // @[el2_ifu_aln_ctl.scala 366:21] assign io_ifu_i0_bp_btag = 5'h0; // @[el2_ifu_aln_ctl.scala 365:21]
assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 96:28] assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 95:28]
assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 107:19] assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 106:19]
assign io_i0_brp_valid = alignbrend[0]; // @[el2_ifu_aln_ctl.scala 341:19] assign io_i0_brp_valid = alignbrend[0]; // @[el2_ifu_aln_ctl.scala 340:19]
assign io_i0_brp_toffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 349:21] assign io_i0_brp_toffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 348:21]
assign io_i0_brp_hist = {alignhist1[0],alignhist0[0]}; // @[el2_ifu_aln_ctl.scala 346:18] assign io_i0_brp_hist = {alignhist1[0],alignhist0[0]}; // @[el2_ifu_aln_ctl.scala 345:18]
assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 359:22] assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:22]
assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 353:29] assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 352:29]
assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 355:29] assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 354:29]
assign io_i0_brp_prett = {{1'd0}, f0prett}; // @[el2_ifu_aln_ctl.scala 351:19] assign io_i0_brp_prett = {{1'd0}, f0prett}; // @[el2_ifu_aln_ctl.scala 350:19]
assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 345:17] assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 344:17]
assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 343:17] assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 342:17]
assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 102:23] assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 101:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif

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src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -7,7 +7,6 @@ import include._
class el2_ifu_aln_ctl extends Module with el2_lib { class el2_ifu_aln_ctl extends Module with el2_lib {
val io = IO(new Bundle{ val io = IO(new Bundle{
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val free_clk = Input(Clock())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val ifu_async_error_start = Input(Bool()) val ifu_async_error_start = Input(Bool())
val iccm_rd_ecc_double_err = Input(Bool()) val iccm_rd_ecc_double_err = Input(Bool())

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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class
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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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target/scala-2.12/classes/ifu/ifu_aln$.class
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target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class
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