DECODE added

2020-12-17 11:01:49 +05:00 · 2020-12-17 11:01:49 +05:00 · a19d561a77
parent ff87a1341a
commit a19d561a77
13 changed files with 5520 additions and 5467 deletions
--- a/firrtl_black_box_resource_files.f
+++ b/firrtl_black_box_resource_files.f
@ -1 +1,3 @@
 /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv
+/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
+/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv
--- a/quasar_wrapper.fir
+++ b/quasar_wrapper.fir
--- a/quasar_wrapper.v
+++ b/quasar_wrapper.v
--- a/src/main/scala/dec/dec_tlu_ctl.scala
+++ b/src/main/scala/dec/dec_tlu_ctl.scala
@ -340,7 +340,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
 	val nmi_lsu_load_type_f		=withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)}
 	val nmi_lsu_store_type_f	=withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)}

-
+	io.tlu_bp.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
+	io.tlu_mem.dec_tlu_flush_lower_wb := io.tlu_bp.dec_tlu_flush_lower_wb
   // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared
 	val nmi_lsu_detected = ~mdseac_locked_f & (io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any)

--- a/target/scala-2.12/classes/dec/csr_tlu.class
+++ b/target/scala-2.12/classes/dec/csr_tlu.class
--- a/target/scala-2.12/classes/dec/dec.class
+++ b/target/scala-2.12/classes/dec/dec.class
--- a/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class
+++ b/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class
--- a/target/scala-2.12/classes/dec/dec_decode_ctl.class
+++ b/target/scala-2.12/classes/dec/dec_decode_ctl.class
--- a/target/scala-2.12/classes/dec/dec_main$.class
+++ b/target/scala-2.12/classes/dec/dec_main$.class
--- a/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class
+++ b/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class
--- a/target/scala-2.12/classes/dec/dec_main.class
+++ b/target/scala-2.12/classes/dec/dec_main.class
--- a/target/scala-2.12/classes/dec/dec_tlu_ctl.class
+++ b/target/scala-2.12/classes/dec/dec_tlu_ctl.class
--- a/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class
+++ b/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class