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Update el2_lsu_bus_intf.scala

This commit is contained in:
Jahanzaib Rasheed 2020-09-09 17:13:26 +05:00 committed by GitHub
parent 9feb32e9a5
commit a63562c44f
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1 changed files with 4 additions and 4 deletions
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src/main/scala/lsu/el2_lsu_bus_intf.scala
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@ -108,10 +108,10 @@ class el2_lsu_bus_intf extends Module
val lsu_axi_rready = Output(UInt(1.W)) val lsu_axi_rready = Output(UInt(1.W))
val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W)) val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W)) val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Intput(UInt(2.W)) val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rlast = Intput(UInt(1.W)) val lsu_axi_rlast = Input(UInt(1.W))
val lsu_bus_clk_en = Intput(UInt(1.W)) val lsu_bus_clk_en = Input(UInt(1.W))
}) })
val lsu_pkt_m = new el2_lsu_pkt_t() val lsu_pkt_m = new el2_lsu_pkt_t()
@ -180,4 +180,4 @@ class el2_lsu_bus_intf extends Module
} }
object busIntfMain extends App { object busIntfMain extends App {
println(chisel3.Driver.emitVerilog(new el2_lsu_bus_intf)) println(chisel3.Driver.emitVerilog(new el2_lsu_bus_intf))
} }