Bus Buffer Update

dbg.anno.json

@@ -0,0 +1,81 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_valid",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
+      "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
+    "sources":[
+      "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_addr",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_addr"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_dctl_dbg_cmd_wrdata",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_dctl_dbg_cmd_wrdata"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_type",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_type"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_write",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_resume_req",
+    "sources":[
+      "~dbg|dbg>io_dec_tlu_mpc_halted_only",
+      "~dbg|dbg>io_dec_tlu_debug_mode",
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
+      "~dbg|dbg>io_core_dbg_cmd_done",
+      "~dbg|dbg>io_dmi_reg_wr_en",
+      "~dbg|dbg>io_dmi_reg_en",
+      "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready",
+      "~dbg|dbg>io_dmi_reg_addr",
+      "~dbg|dbg>reset"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"dbg.gated_latch",
+    "resourceId":"/vsrc/gated_latch.v"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"dbg"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

src/main/scala/dbg/dbg.scala

@@ -449,4 +449,7 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_valid     := io.dbg_dec.dbg_ib.dbg_cmd_valid
   io.dbg_dma.dbg_ib.dbg_cmd_write     := io.dbg_dec.dbg_ib.dbg_cmd_write
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
+}
+object dbg_top extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
 }

src/main/scala/lsu/cipher.scala

@@ -0,0 +1,49 @@
+//package lsu
+//import chisel3._
+//import chisel3.util._
+//import chisel3.experimental.{ChiselEnum, chiselName}
+//import chisel3.util.ImplicitConversions.intToUInt
+//
+//
+//@chiselName
+//class aes extends Module{
+//  val io = IO (new Bundle {
+//    val byteIn = Input(UInt(8.W))
+//    val byteOut = Output(UInt(8.W))
+//  })
+//  def ROTL(x:Int,shift:Int) ={
+//    val y = (x << shift) | (x >> (8 - shift))
+//  y
+//  }
+//  io.byteOut := ROTL(io.byteIn,3)
+//  object aes extends App {
+//    println((new chisel3.stage.ChiselStage).emitVerilog(new aes()))
+//  }
+//// def aes_sbox () ={
+////
+////}
+///*#define ROTL8(x,shift) ((uint8_t) ((x) << (shift)) | ((x) >> (8 - (shift))))
+//
+//void initialize_aes_sbox(uint8_t sbox[256]) {
+//  uint8_t p = 1, q = 1;
+//
+//  /* loop invariant: p * q == 1 in the Galois field */
+//  do {
+//  /* multiply p by 3 */
+//  p = p ^ (p << 1) ^ (p & 0x80 ? 0x11B : 0);
+//
+//  /* divide q by 3 (equals multiplication by 0xf6) */
+//  q ^= q << 1;
+//  q ^= q << 2;
+//  q ^= q << 4;
+//  q ^= q & 0x80 ? 0x09 : 0;
+//
+//  /* compute the affine transformation */
+//  uint8_t xformed = q ^ ROTL8(q, 1) ^ ROTL8(q, 2) ^ ROTL8(q, 3) ^ ROTL8(q, 4);
+//
+//  sbox[p] = xformed ^ 0x63;
+//} while (p != 1);
+//
+//  /* 0 is a special case since it has no inverse */
+//  sbox[0] = 0x63;*/
+//}