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dec update

This commit is contained in:
​Laraib Khan 2020-11-24 17:21:01 +05:00
parent e4ec02558c
commit ab0b53b11f
9 changed files with 3563 additions and 3565 deletions
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6
el2_dec_decode_ctl.anno.json
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@ -1468,6 +1468,12 @@
"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_bits_hist" "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_bits_hist"
] ]
}, },
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

4529
el2_dec_decode_ctl.fir
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File diff suppressed because it is too large Load Diff

1657
el2_dec_decode_ctl.v
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File diff suppressed because it is too large Load Diff

478
el2_swerv_wrapper.fir
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@ -66855,11 +66855,11 @@ circuit el2_swerv_wrapper :
wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20]
wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17]
wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23]
wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17]
wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17]
wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17]
wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20]
wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17]
wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20]
wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28]
wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28]
@ -67287,14 +67287,14 @@ circuit el2_swerv_wrapper :
cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25]
node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54]
node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63]
node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48]
node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31]
node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116]
reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_90 : @[Reg.scala 28:19] when _T_90 : @[Reg.scala 28:19]
nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56]
node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45]
node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87]
@ -67328,17 +67328,17 @@ circuit el2_swerv_wrapper :
cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
skip @[el2_dec_decode_ctl.scala 329:28] skip @[el2_dec_decode_ctl.scala 329:28]
else : @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 334:131]
node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
node _T_103 = eq(r_d_in.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64]
node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:100] node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105]
node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44]
when _T_107 : @[el2_dec_decode_ctl.scala 334:126] when _T_107 : @[el2_dec_decode_ctl.scala 334:131]
cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
skip @[el2_dec_decode_ctl.scala 334:126] skip @[el2_dec_decode_ctl.scala 334:131]
else : @[el2_dec_decode_ctl.scala 336:16] else : @[el2_dec_decode_ctl.scala 336:16]
cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22]
cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22]
@ -67406,17 +67406,17 @@ circuit el2_swerv_wrapper :
cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
skip @[el2_dec_decode_ctl.scala 329:28] skip @[el2_dec_decode_ctl.scala 329:28]
else : @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 334:131]
node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
node _T_129 = eq(r_d_in.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64]
node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:100] node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105]
node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44]
when _T_133 : @[el2_dec_decode_ctl.scala 334:126] when _T_133 : @[el2_dec_decode_ctl.scala 334:131]
cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
skip @[el2_dec_decode_ctl.scala 334:126] skip @[el2_dec_decode_ctl.scala 334:131]
else : @[el2_dec_decode_ctl.scala 336:16] else : @[el2_dec_decode_ctl.scala 336:16]
cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22]
cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22]
@ -67484,17 +67484,17 @@ circuit el2_swerv_wrapper :
cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
skip @[el2_dec_decode_ctl.scala 329:28] skip @[el2_dec_decode_ctl.scala 329:28]
else : @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 334:131]
node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
node _T_155 = eq(r_d_in.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64]
node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:100] node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105]
node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44]
when _T_159 : @[el2_dec_decode_ctl.scala 334:126] when _T_159 : @[el2_dec_decode_ctl.scala 334:131]
cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
skip @[el2_dec_decode_ctl.scala 334:126] skip @[el2_dec_decode_ctl.scala 334:131]
else : @[el2_dec_decode_ctl.scala 336:16] else : @[el2_dec_decode_ctl.scala 336:16]
cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22]
cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22]
@ -67562,17 +67562,17 @@ circuit el2_swerv_wrapper :
cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
skip @[el2_dec_decode_ctl.scala 329:28] skip @[el2_dec_decode_ctl.scala 329:28]
else : @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 334:131]
node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
node _T_181 = eq(r_d_in.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85]
node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64]
node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123]
node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:100] node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105]
node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44]
when _T_185 : @[el2_dec_decode_ctl.scala 334:126] when _T_185 : @[el2_dec_decode_ctl.scala 334:131]
cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
skip @[el2_dec_decode_ctl.scala 334:126] skip @[el2_dec_decode_ctl.scala 334:131]
else : @[el2_dec_decode_ctl.scala 336:16] else : @[el2_dec_decode_ctl.scala 336:16]
cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22]
cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22]
@ -67608,8 +67608,8 @@ circuit el2_swerv_wrapper :
node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71]
nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28]
io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29]
node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49]
node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81]
node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95]
node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95]
node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95]
@ -67914,18 +67914,18 @@ circuit el2_swerv_wrapper :
io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24]
node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30]
io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24]
io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23]
node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39]
node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53]
node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51]
io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20]
node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50]
node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85]
node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64]
node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100]
node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118]
node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132]
node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130]
io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27]
reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52]
csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52]
@ -68072,11 +68072,11 @@ circuit el2_swerv_wrapper :
reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_429 <= write_csr_data_in @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16]
write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18]
node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49]
node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30]
io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24]
node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43]
node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63]
node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67]
node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48]
node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67]
@ -68196,8 +68196,8 @@ circuit el2_swerv_wrapper :
io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29]
node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46]
io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29]
node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41]
node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31]
node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37]
presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22]
reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53]
@ -68206,7 +68206,7 @@ circuit el2_swerv_wrapper :
node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56]
node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54]
node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39]
node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88]
node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69]
ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15]
node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50]
@ -68217,8 +68217,8 @@ circuit el2_swerv_wrapper :
mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16]
node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40]
div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16]
node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45]
node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43]
io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29]
d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26]
node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40]
@ -68355,7 +68355,7 @@ circuit el2_swerv_wrapper :
r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10]
r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10]
r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10]
node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61]
wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48]
_T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48]
_T_537[1] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48]
@ -68364,8 +68364,8 @@ circuit el2_swerv_wrapper :
node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58]
node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58]
node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58]
node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82]
node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105]
r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33]
r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33]
node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35]
@ -68402,7 +68402,7 @@ circuit el2_swerv_wrapper :
io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39]
io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39]
io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39]
node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58]
io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39]
reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52]
_T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52]
@ -68722,22 +68722,22 @@ circuit el2_swerv_wrapper :
io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27]
node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27]
d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34]
node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50]
d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34]
d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27]
node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50]
d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34]
node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50]
d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34]
node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50]
d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34]
node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61]
d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34]
node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58]
d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34]
node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40]
d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34]
node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34]
inst rvclkhdr_7 of rvclkhdr_668 @[el2_lib.scala 518:23] inst rvclkhdr_7 of rvclkhdr_668 @[el2_lib.scala 518:23]
rvclkhdr_7.clock <= clock rvclkhdr_7.clock <= clock
@ -68745,55 +68745,55 @@ circuit el2_swerv_wrapper :
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18]
rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33]
_T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
_T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
_T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16]
_T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16]
_T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16]
_T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16]
_T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16]
_T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16]
_T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16]
_T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16]
_T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16]
_T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] _T_731.valid <= d_d.valid @[el2_lib.scala 524:16]
x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7]
x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7]
x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7]
x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7]
x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7]
x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7]
x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7]
x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7]
x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7]
wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20]
x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10]
x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10]
x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10]
x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10]
x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10]
x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10]
x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10]
x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10]
x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10]
node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49]
node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47]
node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78]
node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76]
x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27]
node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35]
node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33]
node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64]
node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62]
x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20]
node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36]
inst rvclkhdr_8 of rvclkhdr_669 @[el2_lib.scala 518:23] inst rvclkhdr_8 of rvclkhdr_669 @[el2_lib.scala 518:23]
rvclkhdr_8.clock <= clock rvclkhdr_8.clock <= clock
@ -68801,57 +68801,57 @@ circuit el2_swerv_wrapper :
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18]
rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33]
_T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
_T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
_T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16]
_T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16]
_T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16]
_T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16]
_T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16]
_T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16]
_T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16]
_T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16]
_T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16]
_T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16]
r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7]
r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7]
r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7]
r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7]
r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7]
r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7]
r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7]
r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7]
r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7]
r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10]
r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10]
r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10]
r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22]
node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51]
node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49]
r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27]
node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37]
node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35]
r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20]
node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51]
node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49]
r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27]
node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51]
node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49]
r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27]
node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37]
inst rvclkhdr_9 of rvclkhdr_670 @[el2_lib.scala 518:23] inst rvclkhdr_9 of rvclkhdr_670 @[el2_lib.scala 518:23]
rvclkhdr_9.clock <= clock rvclkhdr_9.clock <= clock
@ -68859,43 +68859,43 @@ circuit el2_swerv_wrapper :
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18]
rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24]
wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33]
_T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33]
_T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33]
_T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33]
_T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33]
reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16]
_T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16]
_T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16]
_T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16]
_T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16]
_T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16]
_T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16]
_T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16]
_T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16]
_T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16]
wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7]
wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7]
wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7]
wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7]
wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7]
wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7]
wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7]
wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7]
wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7]
io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27]
node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47]
node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45]
i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25]
node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49]
node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47]
node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70]
node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68]
io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32]
io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26]
node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57]
@ -68907,13 +68907,13 @@ circuit el2_swerv_wrapper :
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16]
node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47]
node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66]
node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32]
i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26]
i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26]
node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42]
node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61]
node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27]
i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21]
node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54]
@ -68982,25 +68982,25 @@ circuit el2_swerv_wrapper :
reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_798 <= last_br_immed_d @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16]
last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19]
node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45]
node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76]
node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58]
node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48]
node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77]
node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60]
node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21]
node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33]
node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94]
node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21]
node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33]
node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60]
node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62]
node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51]
node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26]
node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24]
node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56]
node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39]
node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77]
node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65]
node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53]
io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29]
@ -69140,18 +69140,18 @@ circuit el2_swerv_wrapper :
node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51]
io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25]
node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48]
node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80]
node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63]
node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48]
node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80]
node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63]
node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48]
node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80]
node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63]
node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48]
node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80]
node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63]
node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44]
node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81]
wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109]

354
el2_swerv_wrapper.v
View File

@ -46421,8 +46421,8 @@ module el2_dec_decode_ctl(
wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54]
wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39]
reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53]
reg x_d_i0valid; // @[el2_lib.scala 524:16] reg x_d_valid; // @[el2_lib.scala 524:16]
wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88]
wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69]
wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32]
wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56]
@ -46565,34 +46565,34 @@ module el2_dec_decode_ctl(
wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72]
wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72]
wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72]
reg x_d_i0load; // @[el2_lib.scala 524:16] reg x_d_bits_i0load; // @[el2_lib.scala 524:16]
reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16]
wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31]
reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72]
wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58]
wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49]
wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53]
reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
reg r_d_i0load; // @[el2_lib.scala 524:16] reg r_d_bits_i0load; // @[el2_lib.scala 524:16]
wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56]
wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66]
wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66]
wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45]
wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87]
reg r_d_i0v; // @[el2_lib.scala 524:16] reg r_d_bits_i0v; // @[el2_lib.scala 524:16]
wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51]
wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49]
wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47]
wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45]
reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16]
reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_103 = r_d_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85]
wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64]
reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105]
wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44]
wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28]
wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28]
wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44]
@ -46602,13 +46602,13 @@ module el2_dec_decode_ctl(
wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45]
wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87]
reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_129 = r_d_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85]
wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64]
reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105]
wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44]
wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28]
wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28]
wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44]
@ -46618,13 +46618,13 @@ module el2_dec_decode_ctl(
wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45]
wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87]
reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_155 = r_d_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85]
wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64]
reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105]
wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44]
wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28]
wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28]
wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44]
@ -46634,20 +46634,20 @@ module el2_dec_decode_ctl(
wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45]
wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87]
reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_181 = r_d_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85]
wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64]
reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105]
wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44]
wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131]
wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28]
wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28]
wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44]
wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100]
wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71]
wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49]
wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81]
wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95]
wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95]
wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95]
@ -46734,13 +46734,13 @@ module el2_dec_decode_ctl(
reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] reg _T_339; // @[el2_dec_decode_ctl.scala 432:58]
wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40]
wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43]
reg x_d_i0v; // @[el2_lib.scala 524:16] reg x_d_bits_i0v; // @[el2_lib.scala 524:16]
wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48]
wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80]
wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63]
wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48]
wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80]
wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63]
wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63]
wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24]
wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58]
@ -46749,12 +46749,12 @@ module el2_dec_decode_ctl(
wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61]
wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24]
wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78]
wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48]
wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80]
wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63]
wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48]
wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80]
wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63]
wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63]
wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24]
wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43]
@ -46762,16 +46762,16 @@ module el2_dec_decode_ctl(
wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24]
wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63]
wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42]
reg r_d_csrwen; // @[el2_lib.scala 524:16] reg r_d_bits_csrwen; // @[el2_lib.scala 524:16]
reg r_d_i0valid; // @[el2_lib.scala 524:16] reg r_d_valid; // @[el2_lib.scala 524:16]
wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39]
reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16]
wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50]
wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85]
wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64]
wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100]
wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118]
wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132]
reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52]
reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51]
reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51]
@ -46801,14 +46801,14 @@ module el2_dec_decode_ctl(
wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46]
wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61]
wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75]
reg r_d_csrwonly; // @[el2_lib.scala 524:16] reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16]
wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42]
reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16]
wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27]
reg x_d_csrwonly; // @[el2_lib.scala 524:16] reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16]
wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43]
reg wbd_csrwonly; // @[el2_lib.scala 524:16] reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16]
wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63]
wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48]
wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40]
wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34]
@ -46825,8 +46825,8 @@ module el2_dec_decode_ctl(
wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95]
wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20]
wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45]
wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41]
wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31]
wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37]
wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62]
wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19]
@ -46882,13 +46882,13 @@ module el2_dec_decode_ctl(
reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16]
reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36]
reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37]
reg r_d_i0store; // @[el2_lib.scala 524:16] reg r_d_bits_i0store; // @[el2_lib.scala 524:16]
wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61]
wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58]
wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82]
wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105]
reg r_d_i0div; // @[el2_lib.scala 524:16] reg r_d_bits_i0div; // @[el2_lib.scala 524:16]
wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58]
wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49]
wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49]
wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48]
@ -46924,34 +46924,34 @@ module el2_dec_decode_ctl(
reg i0_r_c_alu; // @[Reg.scala 15:16] reg i0_r_c_alu; // @[Reg.scala 15:16]
wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49]
wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50]
reg x_d_i0store; // @[el2_lib.scala 524:16] reg x_d_bits_i0store; // @[el2_lib.scala 524:16]
reg x_d_i0div; // @[el2_lib.scala 524:16] reg x_d_bits_i0div; // @[el2_lib.scala 524:16]
reg x_d_csrwen; // @[el2_lib.scala 524:16] reg x_d_bits_csrwen; // @[el2_lib.scala 524:16]
reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16]
wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47]
wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33]
wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49]
wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47]
wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70]
wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47]
wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52]
wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16]
wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45]
wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58]
wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77]
wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60]
wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33]
wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94]
wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33]
wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60]
wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62]
wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51]
wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26]
wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24]
wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56]
wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39]
wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77]
wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65]
wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55]
wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62]
@ -47250,7 +47250,7 @@ module el2_dec_decode_ctl(
assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26]
assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31]
assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31]
assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27]
assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32]
assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26]
assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25]
@ -47282,10 +47282,10 @@ module el2_dec_decode_ctl(
assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24]
assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24]
assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20]
assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23]
assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24]
assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27]
assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29]
assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39]
assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39]
assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39]
@ -47294,7 +47294,7 @@ module el2_dec_decode_ctl(
assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39]
assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39]
assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39]
assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39]
assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39]
assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27]
assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23]
@ -47435,7 +47435,7 @@ initial begin
_RAND_6 = {1{`RANDOM}}; _RAND_6 = {1{`RANDOM}};
postsync_stall = _RAND_6[0:0]; postsync_stall = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}}; _RAND_7 = {1{`RANDOM}};
x_d_i0valid = _RAND_7[0:0]; x_d_valid = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}}; _RAND_8 = {1{`RANDOM}};
flush_final_r = _RAND_8[0:0]; flush_final_r = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}}; _RAND_9 = {1{`RANDOM}};
@ -47457,19 +47457,19 @@ initial begin
_RAND_17 = {1{`RANDOM}}; _RAND_17 = {1{`RANDOM}};
cam_raw_3_valid = _RAND_17[0:0]; cam_raw_3_valid = _RAND_17[0:0];
_RAND_18 = {1{`RANDOM}}; _RAND_18 = {1{`RANDOM}};
x_d_i0load = _RAND_18[0:0]; x_d_bits_i0load = _RAND_18[0:0];
_RAND_19 = {1{`RANDOM}}; _RAND_19 = {1{`RANDOM}};
x_d_i0rd = _RAND_19[4:0]; x_d_bits_i0rd = _RAND_19[4:0];
_RAND_20 = {1{`RANDOM}}; _RAND_20 = {1{`RANDOM}};
_T_701 = _RAND_20[2:0]; _T_701 = _RAND_20[2:0];
_RAND_21 = {1{`RANDOM}}; _RAND_21 = {1{`RANDOM}};
nonblock_load_valid_m_delay = _RAND_21[0:0]; nonblock_load_valid_m_delay = _RAND_21[0:0];
_RAND_22 = {1{`RANDOM}}; _RAND_22 = {1{`RANDOM}};
r_d_i0load = _RAND_22[0:0]; r_d_bits_i0load = _RAND_22[0:0];
_RAND_23 = {1{`RANDOM}}; _RAND_23 = {1{`RANDOM}};
r_d_i0v = _RAND_23[0:0]; r_d_bits_i0v = _RAND_23[0:0];
_RAND_24 = {1{`RANDOM}}; _RAND_24 = {1{`RANDOM}};
r_d_i0rd = _RAND_24[4:0]; r_d_bits_i0rd = _RAND_24[4:0];
_RAND_25 = {1{`RANDOM}}; _RAND_25 = {1{`RANDOM}};
cam_raw_0_bits_rd = _RAND_25[4:0]; cam_raw_0_bits_rd = _RAND_25[4:0];
_RAND_26 = {1{`RANDOM}}; _RAND_26 = {1{`RANDOM}};
@ -47491,17 +47491,17 @@ initial begin
_RAND_34 = {1{`RANDOM}}; _RAND_34 = {1{`RANDOM}};
_T_339 = _RAND_34[0:0]; _T_339 = _RAND_34[0:0];
_RAND_35 = {1{`RANDOM}}; _RAND_35 = {1{`RANDOM}};
x_d_i0v = _RAND_35[0:0]; x_d_bits_i0v = _RAND_35[0:0];
_RAND_36 = {1{`RANDOM}}; _RAND_36 = {1{`RANDOM}};
i0_x_c_load = _RAND_36[0:0]; i0_x_c_load = _RAND_36[0:0];
_RAND_37 = {1{`RANDOM}}; _RAND_37 = {1{`RANDOM}};
i0_r_c_load = _RAND_37[0:0]; i0_r_c_load = _RAND_37[0:0];
_RAND_38 = {1{`RANDOM}}; _RAND_38 = {1{`RANDOM}};
r_d_csrwen = _RAND_38[0:0]; r_d_bits_csrwen = _RAND_38[0:0];
_RAND_39 = {1{`RANDOM}}; _RAND_39 = {1{`RANDOM}};
r_d_i0valid = _RAND_39[0:0]; r_d_valid = _RAND_39[0:0];
_RAND_40 = {1{`RANDOM}}; _RAND_40 = {1{`RANDOM}};
r_d_csrwaddr = _RAND_40[11:0]; r_d_bits_csrwaddr = _RAND_40[11:0];
_RAND_41 = {1{`RANDOM}}; _RAND_41 = {1{`RANDOM}};
csr_read_x = _RAND_41[0:0]; csr_read_x = _RAND_41[0:0];
_RAND_42 = {1{`RANDOM}}; _RAND_42 = {1{`RANDOM}};
@ -47517,13 +47517,13 @@ initial begin
_RAND_47 = {1{`RANDOM}}; _RAND_47 = {1{`RANDOM}};
csr_rddata_x = _RAND_47[31:0]; csr_rddata_x = _RAND_47[31:0];
_RAND_48 = {1{`RANDOM}}; _RAND_48 = {1{`RANDOM}};
r_d_csrwonly = _RAND_48[0:0]; r_d_bits_csrwonly = _RAND_48[0:0];
_RAND_49 = {1{`RANDOM}}; _RAND_49 = {1{`RANDOM}};
i0_result_r_raw = _RAND_49[31:0]; i0_result_r_raw = _RAND_49[31:0];
_RAND_50 = {1{`RANDOM}}; _RAND_50 = {1{`RANDOM}};
x_d_csrwonly = _RAND_50[0:0]; x_d_bits_csrwonly = _RAND_50[0:0];
_RAND_51 = {1{`RANDOM}}; _RAND_51 = {1{`RANDOM}};
wbd_csrwonly = _RAND_51[0:0]; wbd_bits_csrwonly = _RAND_51[0:0];
_RAND_52 = {1{`RANDOM}}; _RAND_52 = {1{`RANDOM}};
_T_465 = _RAND_52[31:0]; _T_465 = _RAND_52[31:0];
_RAND_53 = {1{`RANDOM}}; _RAND_53 = {1{`RANDOM}};
@ -47563,9 +47563,9 @@ initial begin
_RAND_70 = {1{`RANDOM}}; _RAND_70 = {1{`RANDOM}};
lsu_pmu_misaligned_r = _RAND_70[0:0]; lsu_pmu_misaligned_r = _RAND_70[0:0];
_RAND_71 = {1{`RANDOM}}; _RAND_71 = {1{`RANDOM}};
r_d_i0store = _RAND_71[0:0]; r_d_bits_i0store = _RAND_71[0:0];
_RAND_72 = {1{`RANDOM}}; _RAND_72 = {1{`RANDOM}};
r_d_i0div = _RAND_72[0:0]; r_d_bits_i0div = _RAND_72[0:0];
_RAND_73 = {1{`RANDOM}}; _RAND_73 = {1{`RANDOM}};
i0_x_c_mul = _RAND_73[0:0]; i0_x_c_mul = _RAND_73[0:0];
_RAND_74 = {1{`RANDOM}}; _RAND_74 = {1{`RANDOM}};
@ -47575,13 +47575,13 @@ initial begin
_RAND_76 = {1{`RANDOM}}; _RAND_76 = {1{`RANDOM}};
i0_r_c_alu = _RAND_76[0:0]; i0_r_c_alu = _RAND_76[0:0];
_RAND_77 = {1{`RANDOM}}; _RAND_77 = {1{`RANDOM}};
x_d_i0store = _RAND_77[0:0]; x_d_bits_i0store = _RAND_77[0:0];
_RAND_78 = {1{`RANDOM}}; _RAND_78 = {1{`RANDOM}};
x_d_i0div = _RAND_78[0:0]; x_d_bits_i0div = _RAND_78[0:0];
_RAND_79 = {1{`RANDOM}}; _RAND_79 = {1{`RANDOM}};
x_d_csrwen = _RAND_79[0:0]; x_d_bits_csrwen = _RAND_79[0:0];
_RAND_80 = {1{`RANDOM}}; _RAND_80 = {1{`RANDOM}};
x_d_csrwaddr = _RAND_80[11:0]; x_d_bits_csrwaddr = _RAND_80[11:0];
_RAND_81 = {1{`RANDOM}}; _RAND_81 = {1{`RANDOM}};
last_br_immed_x = _RAND_81[11:0]; last_br_immed_x = _RAND_81[11:0];
_RAND_82 = {1{`RANDOM}}; _RAND_82 = {1{`RANDOM}};
@ -47625,7 +47625,7 @@ initial begin
postsync_stall = 1'h0; postsync_stall = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_i0valid = 1'h0; x_d_valid = 1'h0;
end end
if (reset) begin if (reset) begin
flush_final_r = 1'h0; flush_final_r = 1'h0;
@ -47658,10 +47658,10 @@ initial begin
cam_raw_3_valid = 1'h0; cam_raw_3_valid = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_i0load = 1'h0; x_d_bits_i0load = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_i0rd = 5'h0; x_d_bits_i0rd = 5'h0;
end end
if (reset) begin if (reset) begin
_T_701 = 3'h0; _T_701 = 3'h0;
@ -47670,13 +47670,13 @@ initial begin
nonblock_load_valid_m_delay = 1'h0; nonblock_load_valid_m_delay = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_i0load = 1'h0; r_d_bits_i0load = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_i0v = 1'h0; r_d_bits_i0v = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_i0rd = 5'h0; r_d_bits_i0rd = 5'h0;
end end
if (reset) begin if (reset) begin
cam_raw_0_bits_rd = 5'h0; cam_raw_0_bits_rd = 5'h0;
@ -47709,16 +47709,16 @@ initial begin
_T_339 = 1'h0; _T_339 = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_i0v = 1'h0; x_d_bits_i0v = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_csrwen = 1'h0; r_d_bits_csrwen = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_i0valid = 1'h0; r_d_valid = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_csrwaddr = 12'h0; r_d_bits_csrwaddr = 12'h0;
end end
if (reset) begin if (reset) begin
csr_read_x = 1'h0; csr_read_x = 1'h0;
@ -47742,16 +47742,16 @@ initial begin
csr_rddata_x = 32'h0; csr_rddata_x = 32'h0;
end end
if (reset) begin if (reset) begin
r_d_csrwonly = 1'h0; r_d_bits_csrwonly = 1'h0;
end end
if (reset) begin if (reset) begin
i0_result_r_raw = 32'h0; i0_result_r_raw = 32'h0;
end end
if (reset) begin if (reset) begin
x_d_csrwonly = 1'h0; x_d_bits_csrwonly = 1'h0;
end end
if (reset) begin if (reset) begin
wbd_csrwonly = 1'h0; wbd_bits_csrwonly = 1'h0;
end end
if (reset) begin if (reset) begin
_T_465 = 32'h0; _T_465 = 32'h0;
@ -47811,22 +47811,22 @@ initial begin
lsu_pmu_misaligned_r = 1'h0; lsu_pmu_misaligned_r = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_i0store = 1'h0; r_d_bits_i0store = 1'h0;
end end
if (reset) begin if (reset) begin
r_d_i0div = 1'h0; r_d_bits_i0div = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_i0store = 1'h0; x_d_bits_i0store = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_i0div = 1'h0; x_d_bits_i0div = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_csrwen = 1'h0; x_d_bits_csrwen = 1'h0;
end end
if (reset) begin if (reset) begin
x_d_csrwaddr = 12'h0; x_d_bits_csrwaddr = 12'h0;
end end
if (reset) begin if (reset) begin
last_br_immed_x = 12'h0; last_br_immed_x = 12'h0;
@ -47939,9 +47939,9 @@ end // initial
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_i0valid <= 1'h0; x_d_valid <= 1'h0;
end else begin end else begin
x_d_i0valid <= io_dec_i0_decode_d; x_d_valid <= io_dec_i0_decode_d;
end end
end end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
@ -48032,16 +48032,16 @@ end // initial
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_i0load <= 1'h0; x_d_bits_i0load <= 1'h0;
end else begin end else begin
x_d_i0load <= i0_dp_load & i0_legal_decode_d; x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d;
end end
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_i0rd <= 5'h0; x_d_bits_i0rd <= 5'h0;
end else begin end else begin
x_d_i0rd <= io_dec_i0_instr_d[11:7]; x_d_bits_i0rd <= io_dec_i0_instr_d[11:7];
end end
end end
always @(posedge io_active_clk or posedge reset) begin always @(posedge io_active_clk or posedge reset) begin
@ -48060,31 +48060,31 @@ end // initial
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_i0load <= 1'h0; r_d_bits_i0load <= 1'h0;
end else begin end else begin
r_d_i0load <= x_d_i0load; r_d_bits_i0load <= x_d_bits_i0load;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_i0v <= 1'h0; r_d_bits_i0v <= 1'h0;
end else begin end else begin
r_d_i0v <= _T_733 & _T_280; r_d_bits_i0v <= _T_733 & _T_280;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_i0rd <= 5'h0; r_d_bits_i0rd <= 5'h0;
end else begin end else begin
r_d_i0rd <= x_d_i0rd; r_d_bits_i0rd <= x_d_bits_i0rd;
end end
end end
always @(posedge io_free_clk or posedge reset) begin always @(posedge io_free_clk or posedge reset) begin
if (reset) begin if (reset) begin
cam_raw_0_bits_rd <= 5'h0; cam_raw_0_bits_rd <= 5'h0;
end else if (cam_wen[0]) begin end else if (cam_wen[0]) begin
if (x_d_i0load) begin if (x_d_bits_i0load) begin
cam_raw_0_bits_rd <= x_d_i0rd; cam_raw_0_bits_rd <= x_d_bits_i0rd;
end else begin end else begin
cam_raw_0_bits_rd <= 5'h0; cam_raw_0_bits_rd <= 5'h0;
end end
@ -48103,8 +48103,8 @@ end // initial
if (reset) begin if (reset) begin
cam_raw_1_bits_rd <= 5'h0; cam_raw_1_bits_rd <= 5'h0;
end else if (cam_wen[1]) begin end else if (cam_wen[1]) begin
if (x_d_i0load) begin if (x_d_bits_i0load) begin
cam_raw_1_bits_rd <= x_d_i0rd; cam_raw_1_bits_rd <= x_d_bits_i0rd;
end else begin end else begin
cam_raw_1_bits_rd <= 5'h0; cam_raw_1_bits_rd <= 5'h0;
end end
@ -48123,8 +48123,8 @@ end // initial
if (reset) begin if (reset) begin
cam_raw_2_bits_rd <= 5'h0; cam_raw_2_bits_rd <= 5'h0;
end else if (cam_wen[2]) begin end else if (cam_wen[2]) begin
if (x_d_i0load) begin if (x_d_bits_i0load) begin
cam_raw_2_bits_rd <= x_d_i0rd; cam_raw_2_bits_rd <= x_d_bits_i0rd;
end else begin end else begin
cam_raw_2_bits_rd <= 5'h0; cam_raw_2_bits_rd <= 5'h0;
end end
@ -48143,8 +48143,8 @@ end // initial
if (reset) begin if (reset) begin
cam_raw_3_bits_rd <= 5'h0; cam_raw_3_bits_rd <= 5'h0;
end else if (cam_wen[3]) begin end else if (cam_wen[3]) begin
if (x_d_i0load) begin if (x_d_bits_i0load) begin
cam_raw_3_bits_rd <= x_d_i0rd; cam_raw_3_bits_rd <= x_d_bits_i0rd;
end else begin end else begin
cam_raw_3_bits_rd <= 5'h0; cam_raw_3_bits_rd <= 5'h0;
end end
@ -48175,30 +48175,30 @@ end // initial
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_i0v <= 1'h0; x_d_bits_i0v <= 1'h0;
end else begin end else begin
x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_csrwen <= 1'h0; r_d_bits_csrwen <= 1'h0;
end else begin end else begin
r_d_csrwen <= x_d_csrwen; r_d_bits_csrwen <= x_d_bits_csrwen;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_i0valid <= 1'h0; r_d_valid <= 1'h0;
end else begin end else begin
r_d_i0valid <= _T_737 & _T_280; r_d_valid <= _T_737 & _T_280;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_csrwaddr <= 12'h0; r_d_bits_csrwaddr <= 12'h0;
end else begin end else begin
r_d_csrwaddr <= x_d_csrwaddr; r_d_bits_csrwaddr <= x_d_bits_csrwaddr;
end end
end end
always @(posedge io_active_clk or posedge reset) begin always @(posedge io_active_clk or posedge reset) begin
@ -48254,9 +48254,9 @@ end // initial
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_csrwonly <= 1'h0; r_d_bits_csrwonly <= 1'h0;
end else begin end else begin
r_d_csrwonly <= x_d_csrwonly; r_d_bits_csrwonly <= x_d_bits_csrwonly;
end end
end end
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
@ -48270,16 +48270,16 @@ end // initial
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_csrwonly <= 1'h0; x_d_bits_csrwonly <= 1'h0;
end else begin end else begin
x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d;
end end
end end
always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
wbd_csrwonly <= 1'h0; wbd_bits_csrwonly <= 1'h0;
end else begin end else begin
wbd_csrwonly <= r_d_csrwonly; wbd_bits_csrwonly <= r_d_bits_csrwonly;
end end
end end
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
@ -48419,44 +48419,44 @@ end // initial
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_i0store <= 1'h0; r_d_bits_i0store <= 1'h0;
end else begin end else begin
r_d_i0store <= x_d_i0store; r_d_bits_i0store <= x_d_bits_i0store;
end end
end end
always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
r_d_i0div <= 1'h0; r_d_bits_i0div <= 1'h0;
end else begin end else begin
r_d_i0div <= x_d_i0div; r_d_bits_i0div <= x_d_bits_i0div;
end end
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_i0store <= 1'h0; x_d_bits_i0store <= 1'h0;
end else begin end else begin
x_d_i0store <= i0_dp_store & i0_legal_decode_d; x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d;
end end
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_i0div <= 1'h0; x_d_bits_i0div <= 1'h0;
end else begin end else begin
x_d_i0div <= i0_dp_div & i0_legal_decode_d; x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d;
end end
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_csrwen <= 1'h0; x_d_bits_csrwen <= 1'h0;
end else begin end else begin
x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d;
end end
end end
always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
x_d_csrwaddr <= 12'h0; x_d_bits_csrwaddr <= 12'h0;
end else begin end else begin
x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20];
end end
end end
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin

102
src/main/scala/dec/el2_dec_decode_ctl.scala
View File

@ -133,11 +133,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val x_t_in = Wire(new el2_trap_pkt_t) val x_t_in = Wire(new el2_trap_pkt_t)
val r_t = Wire(new el2_trap_pkt_t) val r_t = Wire(new el2_trap_pkt_t)
val r_t_in = Wire(new el2_trap_pkt_t) val r_t_in = Wire(new el2_trap_pkt_t)
val d_d = Wire(new el2_dest_pkt_t) val d_d = Wire(Valid(new el2_dest_pkt_t))
val x_d = Wire(new el2_dest_pkt_t) val x_d = Wire(Valid(new el2_dest_pkt_t))
val r_d = Wire(new el2_dest_pkt_t) val r_d = Wire(Valid(new el2_dest_pkt_t))
val r_d_in = Wire(new el2_dest_pkt_t) val r_d_in = Wire(Valid(new el2_dest_pkt_t))
val wbd = Wire(new el2_dest_pkt_t) val wbd = Wire(Valid(new el2_dest_pkt_t))
val i0_d_c = Wire(new el2_class_pkt_t) val i0_d_c = Wire(new el2_class_pkt_t)
val i0_rs1_class_d = Wire(new el2_class_pkt_t) val i0_rs1_class_d = Wire(new el2_class_pkt_t)
val i0_rs2_class_d = Wire(new el2_class_pkt_t) val i0_rs2_class_d = Wire(new el2_class_pkt_t)
@ -311,12 +311,12 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error
val cam_data_reset_tag = io.lsu_nonblock_load_data_tag val cam_data_reset_tag = io.lsu_nonblock_load_data_tag
val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data
val load_data_tag = io.lsu_nonblock_load_data_tag val load_data_tag = io.lsu_nonblock_load_data_tag
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
// don't writeback a nonblock load // don't writeback a nonblock load
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load
for(i <- 0 until LSU_NUM_NBLOAD){ for(i <- 0 until LSU_NUM_NBLOAD){
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid
@ -331,7 +331,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
cam_in(i).bits.wb := 0.U(1.W) cam_in(i).bits.wb := 0.U(1.W)
cam_in(i).bits.tag := cam_write_tag cam_in(i).bits.tag := cam_write_tag
cam_in(i).bits.rd := nonblock_load_rd cam_in(i).bits.rd := nonblock_load_rd
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){
cam_in(i).valid := 0.U cam_in(i).valid := 0.U
}.otherwise{ }.otherwise{
cam_in(i) := cam(i) cam_in(i) := cam(i)
@ -350,7 +350,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_nonblock_load_waddr:=0.U(5.W) io.dec_nonblock_load_waddr:=0.U(5.W)
// cancel if any younger inst (including another nonblock) committing this cycle // cancel if any younger inst (including another nonblock) committing this cycle
val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d) val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d)
@ -464,14 +464,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
//dec_csr_wen_unq_d assigned as csr_write above //dec_csr_wen_unq_d assigned as csr_write above
io.dec_csr_rdaddr_d := i0(31,20) io.dec_csr_rdaddr_d := i0(31,20)
io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt io.dec_csr_wraddr_r := r_d.bits.csrwaddr //r_d is a el2_dest_pkt
// make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
// also use valid so it's flushable // also use valid so it's flushable
io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r; io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r;
// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb; io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb;
val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)}
val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)}
@ -511,9 +511,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val pause_stall = pause_state val pause_stall = pause_state
// for csr write only data is produced by the alu // for csr write only data is produced by the alu
io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data) io.dec_csr_wrdata_r := Mux(r_d.bits.csrwonly.asBool,i0_result_corr_r,write_csr_data)
val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly; val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly;
val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0) val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0)
val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1) val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1)
@ -559,8 +559,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_pmu_postsync_stall := postsync_stall.asBool io.dec_pmu_postsync_stall := postsync_stall.asBool
io.dec_pmu_presync_stall := presync_stall.asBool io.dec_pmu_presync_stall := presync_stall.asBool
val prior_inflight_x = x_d.i0valid val prior_inflight_x = x_d.valid
val prior_inflight_wb = r_d.i0valid val prior_inflight_wb = r_d.valid
val prior_inflight = prior_inflight_x | prior_inflight_wb val prior_inflight = prior_inflight_x | prior_inflight_wb
val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight)
@ -575,7 +575,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
div_decode_d := i0_exulegal_decode_d & i0_dp.div div_decode_d := i0_exulegal_decode_d & i0_dp.div
io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb
//traps for TLU (tlu stuff) //traps for TLU (tlu stuff)
d_t.legal := i0_legal_decode_d d_t.legal := i0_legal_decode_d
@ -604,13 +604,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
r_t_in := r_t r_t_in := r_t
r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage
when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) }
io.dec_tlu_packet_r := r_t_in io.dec_tlu_packet_r := r_t_in
io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid
// end tlu stuff // end tlu stuff
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)}
@ -662,52 +662,52 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
d_d.i0rd := i0r.rd d_d.bits.i0rd := i0r.rd
d_d.i0v := i0_rd_en_d & i0_legal_decode_d d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d
d_d.i0valid := io.dec_i0_decode_d // has flush_final_r d_d.valid := io.dec_i0_decode_d // has flush_final_r
d_d.i0load := i0_dp.load & i0_legal_decode_d d_d.bits.i0load := i0_dp.load & i0_legal_decode_d
d_d.i0store := i0_dp.store & i0_legal_decode_d d_d.bits.i0store := i0_dp.store & i0_legal_decode_d
d_d.i0div := i0_dp.div & i0_legal_decode_d d_d.bits.i0div := i0_dp.div & i0_legal_decode_d
d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
d_d.csrwaddr := i0(31,20) d_d.bits.csrwaddr := i0(31,20)
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
val x_d_in = Wire(new el2_dest_pkt_t) val x_d_in = Wire(Valid(new el2_dest_pkt_t))
x_d_in := x_d x_d_in := x_d
x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode) r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode)
r_d_in := r_d r_d_in := r_d
r_d_in.i0rd := r_d.i0rd r_d_in.bits.i0rd := r_d.bits.i0rd
r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb) r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb)
r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb) r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb)
r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb
r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb
wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode) wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode)
io.dec_i0_waddr_r := r_d_in.i0rd io.dec_i0_waddr_r := r_d_in.bits.i0rd
i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r
io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
io.dec_i0_wdata_r := i0_result_corr_r io.dec_i0_wdata_r := i0_result_corr_r
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
if ( LOAD_TO_USE_PLUS1 == 1 ) { if ( LOAD_TO_USE_PLUS1 == 1 ) {
i0_result_x := io.exu_i0_result_x i0_result_x := io.exu_i0_result_x
i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw) i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
} }
else { else {
i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x)
i0_result_r := i0_result_r_raw i0_result_r := i0_result_r_raw
} }
// correct lsu load data - don't use for bypass, do pass down the pipe // correct lsu load data - don't use for bypass, do pass down the pipe
i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
val last_br_immed_d = WireInit(UInt(12.W),0.U) val last_br_immed_d = WireInit(UInt(12.W),0.U)
last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
@ -716,16 +716,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
// divide stuff // divide stuff
val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid) val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid)
val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) | val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) |
(x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) | (x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) |
(r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) (r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
// cancel if any younger inst committing this cycle to same dest as nonblock divide // cancel if any younger inst committing this cycle to same dest as nonblock divide
val nonblock_div_cancel = (io.dec_div_active & div_flush) | val nonblock_div_cancel = (io.dec_div_active & div_flush) |
(io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r) (io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r)
io.dec_div_cancel := nonblock_div_cancel.asBool io.dec_div_cancel := nonblock_div_cancel.asBool
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
@ -765,11 +765,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
// scheduling logic for primary alu's // scheduling logic for primary alu's
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1) val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1)
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1) val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1)
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2) val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2)
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2) val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2)
// order the producers as follows: , i0_x, i0_r, i0_wb // order the producers as follows: , i0_x, i0_r, i0_wb
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))

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src/main/scala/include/el2_bundle.scala
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@ -107,7 +107,7 @@ class el2_dest_pkt_t extends Bundle {
val i0store = UInt(1.W) val i0store = UInt(1.W)
val i0div = UInt(1.W) val i0div = UInt(1.W)
val i0v = UInt(1.W) val i0v = UInt(1.W)
val i0valid = UInt(1.W) // val i0valid = UInt(1.W)
val csrwen = UInt(1.W) val csrwen = UInt(1.W)
val csrwonly = UInt(1.W) val csrwonly = UInt(1.W)
val csrwaddr = UInt(12.W) val csrwaddr = UInt(12.W)

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target/scala-2.12/classes/dec/el2_dec_decode_ctl.class
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target/scala-2.12/classes/include/el2_dest_pkt_t.class
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