colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Quasar 2.0 Final

This commit is contained in:
Laraib Khan 2021-04-09 09:56:05 +05:00 committed by GitHub
parent 38f826122f
commit b299d0b1aa
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
design/src/main/scala/lsu/lsu_bus_intf.scala
View File

@ -47,7 +47,6 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val lsu_bus_buffer_pend_any = Output(Bool()) val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool()) val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool()) val lsu_bus_buffer_empty_any = Output(Bool())
//val lsu_bus_idle_any = Output(Bool())
val bus_read_data_m = Output(UInt(32.W)) val bus_read_data_m = Output(UInt(32.W))
val lsu_nonblock_load_data = Output((UInt(32.W))) val lsu_nonblock_load_data = Output((UInt(32.W)))
val dctl_busbuff = new dctl_busbuff() val dctl_busbuff = new dctl_busbuff()
@ -135,7 +134,6 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
//io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
@ -202,4 +200,4 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
} }
object bus_intf extends App { object bus_intf extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
} }