IMC DONE

el2_ifu_mem_ctl.fir

@@ -3342,7 +3342,7 @@ circuit el2_ifu_mem_ctl :
     node _T_2458 = eq(_T_2457, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 470:60]
     node _T_2459 = and(_T_2456, _T_2458) @[el2_ifu_mem_ctl.scala 470:58]
     ic_rd_parity_final_err <= _T_2459 @[el2_ifu_mem_ctl.scala 470:26]
-    wire ifu_ic_rw_int_addr_ff : UInt<6>
+    wire ifu_ic_rw_int_addr_ff : UInt<7>
     ifu_ic_rw_int_addr_ff <= UInt<1>("h00")
     wire perr_sb_write_status : UInt<1>
     perr_sb_write_status <= UInt<1>("h00")

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -468,7 +468,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
 
 
   ic_rd_parity_final_err := io.ic_tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f)
-  val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO).W), 0.U)
+  val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U)
 
   val perr_sb_write_status = WireInit(Bool(), false.B)
   val perr_ic_index_ff = withClock(io.active_clk){RegEnable(ifu_ic_rw_int_addr_ff, 0.U, perr_sb_write_status)}