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This commit is contained in:
waleed-lm 2020-11-11 00:50:28 +05:00
parent da0c02368a
commit b3b060377a
126 changed files with 1 additions and 352083 deletions
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84
EL2_IC_DATA.anno.json
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@ -1,84 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_data",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_premux_data",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_sel_premux_data",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_data",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_eccerr",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_parerr",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"EL2_IC_DATA"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1784
EL2_IC_DATA.fir
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618
EL2_IC_DATA.v
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@ -1,618 +0,0 @@
module EL2_IC_DATA(
input clock,
input reset,
input io_clk_override,
input [11:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input io_ic_rd_en,
input [70:0] io_ic_wr_data_0,
input [70:0] io_ic_wr_data_1,
output [63:0] io_ic_rd_data,
input [70:0] io_ic_debug_wr_data,
output [70:0] io_ic_debug_rd_data,
output [1:0] io_ic_parerr,
output [1:0] io_ic_eccerr,
input [8:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
input [63:0] io_ic_premux_data,
input io_ic_sel_premux_data,
input [1:0] io_ic_rd_hit,
input io_scan_mode
);
`ifdef RANDOMIZE_MEM_INIT
reg [95:0] _RAND_0;
reg [95:0] _RAND_1;
reg [95:0] _RAND_2;
reg [95:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 192:70]
wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 192:68]
wire [1:0] _T_3 = _T_1 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 192:94]
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 193:68]
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 193:94]
wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 198:45]
wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58]
wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 198:25]
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 200:79]
wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 202:113]
wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 202:38]
wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 202:17]
wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 202:38]
wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 202:17]
wire [1:0] ic_debug_sel_sb = {io_ic_debug_addr[0],_T_14}; // @[Cat.scala 29:58]
wire _T_28 = ic_debug_sel_sb[0] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 204:80]
wire _T_31 = ic_debug_sel_sb[1] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 204:80]
wire _T_35 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 206:16]
wire _T_40 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 207:91]
wire _T_54 = ic_rw_addr_q[2] & _T_40; // @[Mux.scala 27:72]
wire _T_57 = _T_35 | _T_54; // @[Mux.scala 27:72]
wire _T_111 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 214:74]
wire _T_112 = ~_T_111; // @[el2_ifu_ic_mem.scala 214:61]
wire _T_113 = io_ic_debug_rd_en & _T_112; // @[el2_ifu_ic_mem.scala 214:58]
wire ic_rd_en_with_debug = io_ic_rd_en | _T_113; // @[el2_ifu_ic_mem.scala 214:38]
wire _T_61 = _T_57 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 209:117]
wire _T_85 = _T_35 & _T_40; // @[Mux.scala 27:72]
wire _T_88 = ic_rw_addr_q[2] | _T_85; // @[Mux.scala 27:72]
wire _T_90 = _T_88 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 209:117]
wire [1:0] ic_b_rden = {_T_90,_T_61}; // @[Cat.scala 29:58]
wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_96 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_98 = _T_96 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 212:43]
wire _T_100 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_102 = _T_100 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 212:43]
wire [1:0] ic_bank_way_clken_0 = {_T_98,_T_102}; // @[Cat.scala 29:58]
wire _T_104 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_106 = _T_104 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 212:43]
wire _T_108 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_110 = _T_108 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 212:43]
wire [1:0] ic_bank_way_clken_1 = {_T_106,_T_110}; // @[Cat.scala 29:58]
wire _T_119 = _T_54 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 216:86]
wire ic_rw_addr_wrap = _T_119 & _T_112; // @[el2_ifu_ic_mem.scala 216:108]
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 218:40]
wire [8:0] _T_127 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
reg [1:0] ic_b_rden_ff; // @[el2_ifu_ic_mem.scala 225:29]
reg [4:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 226:30]
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 227:38]
reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 228:34]
wire ic_cacheline_wrap_ff = ic_rw_addr_ff[4:2] == 3'h7; // @[el2_ifu_ic_mem.scala 230:84]
wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 242:36]
wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire [70:0] wb_dout_0_0 = _T_137 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 240:64]
wire _T_150 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_154 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_156 = _T_154 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 242:36]
wire [70:0] _GEN_17 = _T_156 ? data_mem_1_0__T_158_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire [70:0] wb_dout_0_1 = _T_150 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 240:64]
wire _T_163 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_167 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_169 = _T_167 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 242:36]
wire [70:0] _GEN_31 = _T_169 ? data_mem_0_1__T_171_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire [70:0] wb_dout_1_0 = _T_163 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 240:64]
wire _T_176 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_180 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_182 = _T_180 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 242:36]
wire [70:0] _GEN_45 = _T_182 ? data_mem_1_1__T_184_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire [70:0] wb_dout_1_1 = _T_176 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 240:64]
wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 246:24]
wire _T_187 = ~ic_rw_addr_ff[2]; // @[el2_ifu_ic_mem.scala 250:95]
wire [70:0] _T_192 = _T_187 ? wb_dout_0_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_193 = ic_rw_addr_ff[2] ? wb_dout_0_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_194 = _T_192 | _T_193; // @[Mux.scala 27:72]
wire _T_198 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 251:102]
wire _T_199 = ic_rw_addr_ff[2] == _T_198; // @[el2_ifu_ic_mem.scala 251:95]
wire [70:0] _T_206 = _T_199 ? wb_dout_0_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_207 = _T_187 ? wb_dout_0_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_208 = _T_206 | _T_207; // @[Mux.scala 27:72]
wire [141:0] wb_dout_way_pre_0 = {_T_194,_T_208}; // @[Cat.scala 29:58]
wire [70:0] _T_216 = _T_187 ? wb_dout_1_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_217 = ic_rw_addr_ff[2] ? wb_dout_1_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_218 = _T_216 | _T_217; // @[Mux.scala 27:72]
wire [70:0] _T_230 = _T_199 ? wb_dout_1_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_231 = _T_187 ? wb_dout_1_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_232 = _T_230 | _T_231; // @[Mux.scala 27:72]
wire [141:0] wb_dout_way_pre_1 = {_T_218,_T_232}; // @[Cat.scala 29:58]
wire _T_235 = ic_rw_addr_ff[1:0] == 2'h0; // @[el2_ifu_ic_mem.scala 253:83]
wire _T_239 = ic_rw_addr_ff[1:0] == 2'h1; // @[el2_ifu_ic_mem.scala 254:24]
wire [63:0] _T_243 = {wb_dout_way_pre_0[86:71],wb_dout_way_pre_0[63:16]}; // @[Cat.scala 29:58]
wire _T_245 = ic_rw_addr_ff[1:0] == 2'h2; // @[el2_ifu_ic_mem.scala 255:24]
wire [63:0] _T_249 = {wb_dout_way_pre_0[102:71],wb_dout_way_pre_0[63:32]}; // @[Cat.scala 29:58]
wire _T_251 = ic_rw_addr_ff[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 256:24]
wire [63:0] _T_255 = {wb_dout_way_pre_0[118:71],wb_dout_way_pre_0[63:48]}; // @[Cat.scala 29:58]
wire [63:0] _T_256 = _T_235 ? wb_dout_way_pre_0[63:0] : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_257 = _T_239 ? _T_243 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_258 = _T_245 ? _T_249 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_259 = _T_251 ? _T_255 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_260 = _T_256 | _T_257; // @[Mux.scala 27:72]
wire [63:0] _T_261 = _T_260 | _T_258; // @[Mux.scala 27:72]
wire [63:0] wb_dout_way_0 = _T_261 | _T_259; // @[Mux.scala 27:72]
wire [63:0] _T_272 = {wb_dout_way_pre_1[86:71],wb_dout_way_pre_1[63:16]}; // @[Cat.scala 29:58]
wire [63:0] _T_278 = {wb_dout_way_pre_1[102:71],wb_dout_way_pre_1[63:32]}; // @[Cat.scala 29:58]
wire [63:0] _T_284 = {wb_dout_way_pre_1[118:71],wb_dout_way_pre_1[63:48]}; // @[Cat.scala 29:58]
wire [63:0] _T_285 = _T_235 ? wb_dout_way_pre_1[63:0] : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_286 = _T_239 ? _T_272 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_287 = _T_245 ? _T_278 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_288 = _T_251 ? _T_284 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_289 = _T_285 | _T_286; // @[Mux.scala 27:72]
wire [63:0] _T_290 = _T_289 | _T_287; // @[Mux.scala 27:72]
wire [63:0] wb_dout_way_1 = _T_290 | _T_288; // @[Mux.scala 27:72]
wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 258:69]
wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 258:69]
wire _T_295 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 260:75]
wire _T_298 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 260:75]
wire [63:0] _T_300 = _T_295 ? wb_dout_way_with_premux_0 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_301 = _T_298 ? wb_dout_way_with_premux_1 : 64'h0; // @[Mux.scala 27:72]
wire [70:0] _T_310 = ic_rd_hit_q[0] ? wb_dout_way_pre_0[70:0] : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_311 = ic_rd_hit_q[1] ? wb_dout_way_pre_1[70:0] : 71'h0; // @[Mux.scala 27:72]
wire [141:0] _T_318 = ic_rd_hit_q[0] ? wb_dout_way_pre_0 : 142'h0; // @[Mux.scala 27:72]
wire [141:0] _T_319 = ic_rd_hit_q[1] ? wb_dout_way_pre_1 : 142'h0; // @[Mux.scala 27:72]
wire [141:0] wb_dout_ecc = _T_318 | _T_319; // @[Mux.scala 27:72]
wire _T_321 = |io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 264:75]
wire _T_322 = ~ic_cacheline_wrap_ff; // @[el2_ifu_ic_mem.scala 264:103]
wire _T_325 = ic_b_rden_ff == 2'h3; // @[el2_ifu_ic_mem.scala 264:163]
wire _T_326 = _T_322 & _T_325; // @[el2_ifu_ic_mem.scala 264:125]
wire bank_check_en_0 = _T_321 & _T_326; // @[el2_ifu_ic_mem.scala 264:79]
wire [70:0] wb_dout_ecc_bank_0 = wb_dout_ecc[70:0]; // @[el2_ifu_ic_mem.scala 265:72]
wire [70:0] wb_dout_ecc_bank_1 = wb_dout_ecc[141:71]; // @[el2_ifu_ic_mem.scala 265:72]
wire [6:0] _T_555 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[60],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[58],wb_dout_ecc_bank_0[57]}; // @[el2_lib.scala 380:41]
wire _T_556 = ^_T_555; // @[el2_lib.scala 380:48]
wire _T_557 = wb_dout_ecc_bank_0[70] ^ _T_556; // @[el2_lib.scala 380:36]
wire [6:0] _T_564 = {wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[31],wb_dout_ecc_bank_0[30],wb_dout_ecc_bank_0[29],wb_dout_ecc_bank_0[28],wb_dout_ecc_bank_0[27],wb_dout_ecc_bank_0[26]}; // @[el2_lib.scala 380:69]
wire [7:0] _T_571 = {wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[37],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[35],wb_dout_ecc_bank_0[34],wb_dout_ecc_bank_0[33]}; // @[el2_lib.scala 380:69]
wire [14:0] _T_572 = {wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[37],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[35],wb_dout_ecc_bank_0[34],wb_dout_ecc_bank_0[33],_T_564}; // @[el2_lib.scala 380:69]
wire [7:0] _T_579 = {wb_dout_ecc_bank_0[48],wb_dout_ecc_bank_0[47],wb_dout_ecc_bank_0[46],wb_dout_ecc_bank_0[45],wb_dout_ecc_bank_0[44],wb_dout_ecc_bank_0[43],wb_dout_ecc_bank_0[42],wb_dout_ecc_bank_0[41]}; // @[el2_lib.scala 380:69]
wire [30:0] _T_588 = {wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[49],_T_579,_T_572}; // @[el2_lib.scala 380:69]
wire _T_589 = ^_T_588; // @[el2_lib.scala 380:76]
wire _T_590 = wb_dout_ecc_bank_0[69] ^ _T_589; // @[el2_lib.scala 380:64]
wire [6:0] _T_597 = {wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[16],wb_dout_ecc_bank_0[15],wb_dout_ecc_bank_0[14],wb_dout_ecc_bank_0[13],wb_dout_ecc_bank_0[12],wb_dout_ecc_bank_0[11]}; // @[el2_lib.scala 380:96]
wire [14:0] _T_605 = {wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[22],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[20],wb_dout_ecc_bank_0[19],wb_dout_ecc_bank_0[18],_T_597}; // @[el2_lib.scala 380:96]
wire [30:0] _T_621 = {wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[49],_T_579,_T_605}; // @[el2_lib.scala 380:96]
wire _T_622 = ^_T_621; // @[el2_lib.scala 380:103]
wire _T_623 = wb_dout_ecc_bank_0[68] ^ _T_622; // @[el2_lib.scala 380:91]
wire [6:0] _T_630 = {wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[9],wb_dout_ecc_bank_0[8],wb_dout_ecc_bank_0[7],wb_dout_ecc_bank_0[6],wb_dout_ecc_bank_0[5],wb_dout_ecc_bank_0[4]}; // @[el2_lib.scala 380:123]
wire [14:0] _T_638 = {wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[22],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[20],wb_dout_ecc_bank_0[19],wb_dout_ecc_bank_0[18],_T_630}; // @[el2_lib.scala 380:123]
wire [30:0] _T_654 = {wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[49],_T_571,_T_638}; // @[el2_lib.scala 380:123]
wire _T_655 = ^_T_654; // @[el2_lib.scala 380:130]
wire _T_656 = wb_dout_ecc_bank_0[67] ^ _T_655; // @[el2_lib.scala 380:118]
wire [7:0] _T_664 = {wb_dout_ecc_bank_0[14],wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[9],wb_dout_ecc_bank_0[8],wb_dout_ecc_bank_0[7],wb_dout_ecc_bank_0[3],wb_dout_ecc_bank_0[2],wb_dout_ecc_bank_0[1]}; // @[el2_lib.scala 380:150]
wire [16:0] _T_673 = {wb_dout_ecc_bank_0[30],wb_dout_ecc_bank_0[29],wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[22],wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[16],wb_dout_ecc_bank_0[15],_T_664}; // @[el2_lib.scala 380:150]
wire [8:0] _T_681 = {wb_dout_ecc_bank_0[47],wb_dout_ecc_bank_0[46],wb_dout_ecc_bank_0[45],wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[37],wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[31]}; // @[el2_lib.scala 380:150]
wire [17:0] _T_690 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[60],wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[48],_T_681}; // @[el2_lib.scala 380:150]
wire [34:0] _T_691 = {_T_690,_T_673}; // @[el2_lib.scala 380:150]
wire _T_692 = ^_T_691; // @[el2_lib.scala 380:157]
wire _T_693 = wb_dout_ecc_bank_0[66] ^ _T_692; // @[el2_lib.scala 380:145]
wire [7:0] _T_701 = {wb_dout_ecc_bank_0[12],wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[9],wb_dout_ecc_bank_0[6],wb_dout_ecc_bank_0[5],wb_dout_ecc_bank_0[3],wb_dout_ecc_bank_0[2],wb_dout_ecc_bank_0[0]}; // @[el2_lib.scala 380:177]
wire [16:0] _T_710 = {wb_dout_ecc_bank_0[28],wb_dout_ecc_bank_0[27],wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[20],wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[16],wb_dout_ecc_bank_0[13],_T_701}; // @[el2_lib.scala 380:177]
wire [8:0] _T_718 = {wb_dout_ecc_bank_0[47],wb_dout_ecc_bank_0[44],wb_dout_ecc_bank_0[43],wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[35],wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[31]}; // @[el2_lib.scala 380:177]
wire [17:0] _T_727 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[58],wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[48],_T_718}; // @[el2_lib.scala 380:177]
wire [34:0] _T_728 = {_T_727,_T_710}; // @[el2_lib.scala 380:177]
wire _T_729 = ^_T_728; // @[el2_lib.scala 380:184]
wire _T_730 = wb_dout_ecc_bank_0[65] ^ _T_729; // @[el2_lib.scala 380:172]
wire [7:0] _T_738 = {wb_dout_ecc_bank_0[11],wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[8],wb_dout_ecc_bank_0[6],wb_dout_ecc_bank_0[4],wb_dout_ecc_bank_0[3],wb_dout_ecc_bank_0[1],wb_dout_ecc_bank_0[0]}; // @[el2_lib.scala 380:204]
wire [16:0] _T_747 = {wb_dout_ecc_bank_0[28],wb_dout_ecc_bank_0[26],wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[19],wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[15],wb_dout_ecc_bank_0[13],_T_738}; // @[el2_lib.scala 380:204]
wire [8:0] _T_755 = {wb_dout_ecc_bank_0[46],wb_dout_ecc_bank_0[44],wb_dout_ecc_bank_0[42],wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[34],wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[30]}; // @[el2_lib.scala 380:204]
wire [17:0] _T_764 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[57],wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[48],_T_755}; // @[el2_lib.scala 380:204]
wire [34:0] _T_765 = {_T_764,_T_747}; // @[el2_lib.scala 380:204]
wire _T_766 = ^_T_765; // @[el2_lib.scala 380:211]
wire _T_767 = wb_dout_ecc_bank_0[64] ^ _T_766; // @[el2_lib.scala 380:199]
wire [6:0] _T_773 = {_T_557,_T_590,_T_623,_T_656,_T_693,_T_730,_T_767}; // @[Cat.scala 29:58]
wire _T_775 = _T_773 != 7'h0; // @[el2_lib.scala 381:42]
wire _T_776 = bank_check_en_0 & _T_775; // @[el2_lib.scala 381:24]
wire [6:0] _T_997 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[62],wb_dout_ecc_bank_1[61],wb_dout_ecc_bank_1[60],wb_dout_ecc_bank_1[59],wb_dout_ecc_bank_1[58],wb_dout_ecc_bank_1[57]}; // @[el2_lib.scala 380:41]
wire _T_998 = ^_T_997; // @[el2_lib.scala 380:48]
wire _T_999 = wb_dout_ecc_bank_1[70] ^ _T_998; // @[el2_lib.scala 380:36]
wire [6:0] _T_1006 = {wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[31],wb_dout_ecc_bank_1[30],wb_dout_ecc_bank_1[29],wb_dout_ecc_bank_1[28],wb_dout_ecc_bank_1[27],wb_dout_ecc_bank_1[26]}; // @[el2_lib.scala 380:69]
wire [7:0] _T_1013 = {wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[37],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[35],wb_dout_ecc_bank_1[34],wb_dout_ecc_bank_1[33]}; // @[el2_lib.scala 380:69]
wire [14:0] _T_1014 = {wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[37],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[35],wb_dout_ecc_bank_1[34],wb_dout_ecc_bank_1[33],_T_1006}; // @[el2_lib.scala 380:69]
wire [7:0] _T_1021 = {wb_dout_ecc_bank_1[48],wb_dout_ecc_bank_1[47],wb_dout_ecc_bank_1[46],wb_dout_ecc_bank_1[45],wb_dout_ecc_bank_1[44],wb_dout_ecc_bank_1[43],wb_dout_ecc_bank_1[42],wb_dout_ecc_bank_1[41]}; // @[el2_lib.scala 380:69]
wire [30:0] _T_1030 = {wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[49],_T_1021,_T_1014}; // @[el2_lib.scala 380:69]
wire _T_1031 = ^_T_1030; // @[el2_lib.scala 380:76]
wire _T_1032 = wb_dout_ecc_bank_1[69] ^ _T_1031; // @[el2_lib.scala 380:64]
wire [6:0] _T_1039 = {wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[16],wb_dout_ecc_bank_1[15],wb_dout_ecc_bank_1[14],wb_dout_ecc_bank_1[13],wb_dout_ecc_bank_1[12],wb_dout_ecc_bank_1[11]}; // @[el2_lib.scala 380:96]
wire [14:0] _T_1047 = {wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[22],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[20],wb_dout_ecc_bank_1[19],wb_dout_ecc_bank_1[18],_T_1039}; // @[el2_lib.scala 380:96]
wire [30:0] _T_1063 = {wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[49],_T_1021,_T_1047}; // @[el2_lib.scala 380:96]
wire _T_1064 = ^_T_1063; // @[el2_lib.scala 380:103]
wire _T_1065 = wb_dout_ecc_bank_1[68] ^ _T_1064; // @[el2_lib.scala 380:91]
wire [6:0] _T_1072 = {wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[9],wb_dout_ecc_bank_1[8],wb_dout_ecc_bank_1[7],wb_dout_ecc_bank_1[6],wb_dout_ecc_bank_1[5],wb_dout_ecc_bank_1[4]}; // @[el2_lib.scala 380:123]
wire [14:0] _T_1080 = {wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[22],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[20],wb_dout_ecc_bank_1[19],wb_dout_ecc_bank_1[18],_T_1072}; // @[el2_lib.scala 380:123]
wire [30:0] _T_1096 = {wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[49],_T_1013,_T_1080}; // @[el2_lib.scala 380:123]
wire _T_1097 = ^_T_1096; // @[el2_lib.scala 380:130]
wire _T_1098 = wb_dout_ecc_bank_1[67] ^ _T_1097; // @[el2_lib.scala 380:118]
wire [7:0] _T_1106 = {wb_dout_ecc_bank_1[14],wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[9],wb_dout_ecc_bank_1[8],wb_dout_ecc_bank_1[7],wb_dout_ecc_bank_1[3],wb_dout_ecc_bank_1[2],wb_dout_ecc_bank_1[1]}; // @[el2_lib.scala 380:150]
wire [16:0] _T_1115 = {wb_dout_ecc_bank_1[30],wb_dout_ecc_bank_1[29],wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[22],wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[16],wb_dout_ecc_bank_1[15],_T_1106}; // @[el2_lib.scala 380:150]
wire [8:0] _T_1123 = {wb_dout_ecc_bank_1[47],wb_dout_ecc_bank_1[46],wb_dout_ecc_bank_1[45],wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[37],wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[31]}; // @[el2_lib.scala 380:150]
wire [17:0] _T_1132 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[62],wb_dout_ecc_bank_1[61],wb_dout_ecc_bank_1[60],wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[48],_T_1123}; // @[el2_lib.scala 380:150]
wire [34:0] _T_1133 = {_T_1132,_T_1115}; // @[el2_lib.scala 380:150]
wire _T_1134 = ^_T_1133; // @[el2_lib.scala 380:157]
wire _T_1135 = wb_dout_ecc_bank_1[66] ^ _T_1134; // @[el2_lib.scala 380:145]
wire [7:0] _T_1143 = {wb_dout_ecc_bank_1[12],wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[9],wb_dout_ecc_bank_1[6],wb_dout_ecc_bank_1[5],wb_dout_ecc_bank_1[3],wb_dout_ecc_bank_1[2],wb_dout_ecc_bank_1[0]}; // @[el2_lib.scala 380:177]
wire [16:0] _T_1152 = {wb_dout_ecc_bank_1[28],wb_dout_ecc_bank_1[27],wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[20],wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[16],wb_dout_ecc_bank_1[13],_T_1143}; // @[el2_lib.scala 380:177]
wire [8:0] _T_1160 = {wb_dout_ecc_bank_1[47],wb_dout_ecc_bank_1[44],wb_dout_ecc_bank_1[43],wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[35],wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[31]}; // @[el2_lib.scala 380:177]
wire [17:0] _T_1169 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[62],wb_dout_ecc_bank_1[59],wb_dout_ecc_bank_1[58],wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[48],_T_1160}; // @[el2_lib.scala 380:177]
wire [34:0] _T_1170 = {_T_1169,_T_1152}; // @[el2_lib.scala 380:177]
wire _T_1171 = ^_T_1170; // @[el2_lib.scala 380:184]
wire _T_1172 = wb_dout_ecc_bank_1[65] ^ _T_1171; // @[el2_lib.scala 380:172]
wire [7:0] _T_1180 = {wb_dout_ecc_bank_1[11],wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[8],wb_dout_ecc_bank_1[6],wb_dout_ecc_bank_1[4],wb_dout_ecc_bank_1[3],wb_dout_ecc_bank_1[1],wb_dout_ecc_bank_1[0]}; // @[el2_lib.scala 380:204]
wire [16:0] _T_1189 = {wb_dout_ecc_bank_1[28],wb_dout_ecc_bank_1[26],wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[19],wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[15],wb_dout_ecc_bank_1[13],_T_1180}; // @[el2_lib.scala 380:204]
wire [8:0] _T_1197 = {wb_dout_ecc_bank_1[46],wb_dout_ecc_bank_1[44],wb_dout_ecc_bank_1[42],wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[34],wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[30]}; // @[el2_lib.scala 380:204]
wire [17:0] _T_1206 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[61],wb_dout_ecc_bank_1[59],wb_dout_ecc_bank_1[57],wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[48],_T_1197}; // @[el2_lib.scala 380:204]
wire [34:0] _T_1207 = {_T_1206,_T_1189}; // @[el2_lib.scala 380:204]
wire _T_1208 = ^_T_1207; // @[el2_lib.scala 380:211]
wire _T_1209 = wb_dout_ecc_bank_1[64] ^ _T_1208; // @[el2_lib.scala 380:199]
wire [6:0] _T_1215 = {_T_999,_T_1032,_T_1065,_T_1098,_T_1135,_T_1172,_T_1209}; // @[Cat.scala 29:58]
wire _T_1217 = _T_1215 != 7'h0; // @[el2_lib.scala 381:42]
wire _T_1218 = bank_check_en_0 & _T_1217; // @[el2_lib.scala 381:24]
wire _T_1222 = ^wb_dout_ecc_bank_0[15:0]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_0 = _T_1222 ^ wb_dout_ecc_bank_0[64]; // @[el2_lib.scala 190:27]
wire _T_1226 = ^wb_dout_ecc_bank_0[31:16]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_1 = _T_1226 ^ wb_dout_ecc_bank_0[65]; // @[el2_lib.scala 190:27]
wire _T_1230 = ^wb_dout_ecc_bank_0[47:32]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_2 = _T_1230 ^ wb_dout_ecc_bank_0[66]; // @[el2_lib.scala 190:27]
wire _T_1234 = ^wb_dout_ecc_bank_0[63:48]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_3 = _T_1234 ^ wb_dout_ecc_bank_0[67]; // @[el2_lib.scala 190:27]
wire _T_1238 = ^wb_dout_ecc_bank_1[15:0]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_0 = _T_1238 ^ wb_dout_ecc_bank_1[64]; // @[el2_lib.scala 190:27]
wire _T_1242 = ^wb_dout_ecc_bank_1[31:16]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_1 = _T_1242 ^ wb_dout_ecc_bank_1[65]; // @[el2_lib.scala 190:27]
wire _T_1246 = ^wb_dout_ecc_bank_1[47:32]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_2 = _T_1246 ^ wb_dout_ecc_bank_1[66]; // @[el2_lib.scala 190:27]
wire _T_1250 = ^wb_dout_ecc_bank_1[63:48]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_3 = _T_1250 ^ wb_dout_ecc_bank_1[67]; // @[el2_lib.scala 190:27]
wire _T_1252 = ic_parerr_bank_0_0 | ic_parerr_bank_0_1; // @[el2_ifu_ic_mem.scala 272:49]
wire _T_1253 = _T_1252 | ic_parerr_bank_0_2; // @[el2_ifu_ic_mem.scala 272:49]
wire _T_1254 = _T_1253 | ic_parerr_bank_0_3; // @[el2_ifu_ic_mem.scala 272:49]
wire _T_1255 = _T_1254 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 272:53]
wire _T_1256 = ic_parerr_bank_1_0 | ic_parerr_bank_1_1; // @[el2_ifu_ic_mem.scala 272:99]
wire _T_1257 = _T_1256 | ic_parerr_bank_1_2; // @[el2_ifu_ic_mem.scala 272:99]
wire _T_1258 = _T_1257 | ic_parerr_bank_1_3; // @[el2_ifu_ic_mem.scala 272:99]
wire _T_1259 = _T_1258 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 272:103]
assign data_mem_0_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_171_data = data_mem_0_0[data_mem_0_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_184_data = data_mem_0_0[data_mem_0_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_139_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_0;
assign data_mem_0_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_139_mask = 1'h1;
assign data_mem_0_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_0_0__T_152_data = 71'h0;
assign data_mem_0_0__T_152_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_152_mask = 1'h0;
assign data_mem_0_0__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_0_0__T_165_data = 71'h0;
assign data_mem_0_0__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_165_mask = 1'h0;
assign data_mem_0_0__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_0_0__T_178_data = 71'h0;
assign data_mem_0_0__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_178_mask = 1'h0;
assign data_mem_0_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_0_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_171_data = data_mem_0_1[data_mem_0_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_184_data = data_mem_0_1[data_mem_0_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_139_data = 71'h0;
assign data_mem_0_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_139_mask = 1'h0;
assign data_mem_0_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_0_1__T_152_data = 71'h0;
assign data_mem_0_1__T_152_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_152_mask = 1'h0;
assign data_mem_0_1__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_0_1__T_165_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_0;
assign data_mem_0_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_165_mask = 1'h1;
assign data_mem_0_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_0_1__T_178_data = 71'h0;
assign data_mem_0_1__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_178_mask = 1'h0;
assign data_mem_0_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_1_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_171_data = data_mem_1_0[data_mem_1_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_184_data = data_mem_1_0[data_mem_1_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_139_data = 71'h0;
assign data_mem_1_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_139_mask = 1'h0;
assign data_mem_1_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_1_0__T_152_data = _T_31 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_1_0__T_152_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_152_mask = 1'h1;
assign data_mem_1_0__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_1_0__T_165_data = 71'h0;
assign data_mem_1_0__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_165_mask = 1'h0;
assign data_mem_1_0__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_1_0__T_178_data = 71'h0;
assign data_mem_1_0__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_178_mask = 1'h0;
assign data_mem_1_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_1_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_171_data = data_mem_1_1[data_mem_1_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_184_data = data_mem_1_1[data_mem_1_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_139_data = 71'h0;
assign data_mem_1_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_139_mask = 1'h0;
assign data_mem_1_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_1_1__T_152_data = 71'h0;
assign data_mem_1_1__T_152_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_152_mask = 1'h0;
assign data_mem_1_1__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_1_1__T_165_data = 71'h0;
assign data_mem_1_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_165_mask = 1'h0;
assign data_mem_1_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_1_1__T_178_data = _T_31 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_178_mask = 1'h1;
assign data_mem_1_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign io_ic_rd_data = _T_300 | _T_301; // @[el2_ifu_ic_mem.scala 260:17]
assign io_ic_debug_rd_data = _T_310 | _T_311; // @[el2_ifu_ic_mem.scala 261:23]
assign io_ic_parerr = {_T_1255,_T_1259}; // @[el2_ifu_ic_mem.scala 272:16]
assign io_ic_eccerr = {_T_1218,_T_776}; // @[el2_ifu_ic_mem.scala 268:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_0_0[initvar] = _RAND_0[70:0];
_RAND_1 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_0_1[initvar] = _RAND_1[70:0];
_RAND_2 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_0[initvar] = _RAND_2[70:0];
_RAND_3 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_1[initvar] = _RAND_3[70:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
ic_b_rden_ff = _RAND_4[1:0];
_RAND_5 = {1{`RANDOM}};
ic_rw_addr_ff = _RAND_5[4:0];
_RAND_6 = {1{`RANDOM}};
ic_debug_rd_way_en_ff = _RAND_6[1:0];
_RAND_7 = {1{`RANDOM}};
ic_debug_rd_en_ff = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin
data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_0__T_152_en & data_mem_0_0__T_152_mask) begin
data_mem_0_0[data_mem_0_0__T_152_addr] <= data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_0__T_165_en & data_mem_0_0__T_165_mask) begin
data_mem_0_0[data_mem_0_0__T_165_addr] <= data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_0__T_178_en & data_mem_0_0__T_178_mask) begin
data_mem_0_0[data_mem_0_0__T_178_addr] <= data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin
data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_1__T_152_en & data_mem_0_1__T_152_mask) begin
data_mem_0_1[data_mem_0_1__T_152_addr] <= data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_1__T_165_en & data_mem_0_1__T_165_mask) begin
data_mem_0_1[data_mem_0_1__T_165_addr] <= data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_0_1__T_178_en & data_mem_0_1__T_178_mask) begin
data_mem_0_1[data_mem_0_1__T_178_addr] <= data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin
data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_0__T_152_en & data_mem_1_0__T_152_mask) begin
data_mem_1_0[data_mem_1_0__T_152_addr] <= data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_0__T_165_en & data_mem_1_0__T_165_mask) begin
data_mem_1_0[data_mem_1_0__T_165_addr] <= data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_0__T_178_en & data_mem_1_0__T_178_mask) begin
data_mem_1_0[data_mem_1_0__T_178_addr] <= data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin
data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_1__T_152_en & data_mem_1_1__T_152_mask) begin
data_mem_1_1[data_mem_1_1__T_152_addr] <= data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_1__T_165_en & data_mem_1_1__T_165_mask) begin
data_mem_1_1[data_mem_1_1__T_165_addr] <= data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if(data_mem_1_1__T_178_en & data_mem_1_1__T_178_mask) begin
data_mem_1_1[data_mem_1_1__T_178_addr] <= data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if (reset) begin
ic_b_rden_ff <= 2'h0;
end else begin
ic_b_rden_ff <= ic_b_rden;
end
if (reset) begin
ic_rw_addr_ff <= 5'h0;
end else begin
ic_rw_addr_ff <= ic_rw_addr_q[4:0];
end
if (reset) begin
ic_debug_rd_way_en_ff <= 2'h0;
end else begin
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
end
if (reset) begin
ic_debug_rd_en_ff <= 1'h0;
end else begin
ic_debug_rd_en_ff <= io_ic_debug_rd_en;
end
end
endmodule

66
EL2_IC_TAG.anno.json
View File

@ -1,66 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ictag_debug_rd_data",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"EL2_IC_TAG"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1473
EL2_IC_TAG.fir
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File diff suppressed because it is too large Load Diff

276
EL2_IC_TAG.v
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@ -1,276 +0,0 @@
module EL2_IC_TAG(
input clock,
input reset,
input io_clk_override,
input io_dec_tlu_core_ecc_disable,
input [28:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input [1:0] io_ic_tag_valid,
input io_ic_rd_en,
input [9:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
output [25:0] io_ictag_debug_rd_data,
input [70:0] io_ic_debug_wr_data,
output [1:0] io_ic_rd_hit,
output io_ic_tag_perr,
input io_scan_mode
);
`ifdef RANDOMIZE_MEM_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
reg [25:0] tag_mem_0 [0:127]; // @[el2_ifu_ic_mem.scala 97:20]
wire [25:0] tag_mem_0__T_250_data; // @[el2_ifu_ic_mem.scala 97:20]
wire [6:0] tag_mem_0__T_250_addr; // @[el2_ifu_ic_mem.scala 97:20]
wire [25:0] tag_mem_0__T_254_data; // @[el2_ifu_ic_mem.scala 97:20]
wire [6:0] tag_mem_0__T_254_addr; // @[el2_ifu_ic_mem.scala 97:20]
wire [25:0] tag_mem_0__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
wire [6:0] tag_mem_0__T_238_addr; // @[el2_ifu_ic_mem.scala 97:20]
wire tag_mem_0__T_238_mask; // @[el2_ifu_ic_mem.scala 97:20]
wire tag_mem_0__T_238_en; // @[el2_ifu_ic_mem.scala 97:20]
reg [25:0] tag_mem_1 [0:127]; // @[el2_ifu_ic_mem.scala 97:20]
wire [25:0] tag_mem_1__T_250_data; // @[el2_ifu_ic_mem.scala 97:20]
wire [6:0] tag_mem_1__T_250_addr; // @[el2_ifu_ic_mem.scala 97:20]
wire [25:0] tag_mem_1__T_254_data; // @[el2_ifu_ic_mem.scala 97:20]
wire [6:0] tag_mem_1__T_254_addr; // @[el2_ifu_ic_mem.scala 97:20]
wire [25:0] tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
wire [6:0] tag_mem_1__T_238_addr; // @[el2_ifu_ic_mem.scala 97:20]
wire tag_mem_1__T_238_mask; // @[el2_ifu_ic_mem.scala 97:20]
wire tag_mem_1__T_238_en; // @[el2_ifu_ic_mem.scala 97:20]
wire _T_1 = io_ic_rw_addr[2:1] == 2'h1; // @[el2_ifu_ic_mem.scala 71:95]
wire [1:0] _T_3 = _T_1 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_tag_wren = io_ic_wr_en & _T_3; // @[el2_ifu_ic_mem.scala 71:33]
wire _T_4 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 72:55]
wire [1:0] _T_6 = _T_4 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_7 = _T_6 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 72:73]
wire _T_14 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 80:65]
wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_debug_wr_way_en = _T_16 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 80:90]
wire [1:0] _T_8 = _T_7 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 72:87]
wire _T_10 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 79:65]
wire [1:0] _T_12 = _T_10 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_debug_rd_way_en = _T_12 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 79:90]
wire [1:0] ic_tag_clken = _T_8 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 72:108]
reg ic_rd_en_ff; // @[el2_ifu_ic_mem.scala 74:28]
reg [18:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 75:30]
wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
wire [31:0] _T_20 = {13'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
wire [8:0] _T_124 = {_T_20[16],_T_20[14],_T_20[12],_T_20[10],_T_20[8],_T_20[6],_T_20[5],_T_20[3],_T_20[1]}; // @[el2_lib.scala 257:22]
wire [17:0] _T_133 = {_T_20[31],_T_20[30],_T_20[28],_T_20[27],_T_20[25],_T_20[23],_T_20[21],_T_20[20],_T_20[18],_T_124}; // @[el2_lib.scala 257:22]
wire _T_134 = ^_T_133; // @[el2_lib.scala 257:29]
wire [8:0] _T_142 = {_T_20[15],_T_20[14],_T_20[11],_T_20[10],_T_20[7],_T_20[6],_T_20[4],_T_20[3],_T_20[0]}; // @[el2_lib.scala 257:39]
wire [17:0] _T_151 = {_T_20[31],_T_20[29],_T_20[28],_T_20[26],_T_20[25],_T_20[22],_T_20[21],_T_20[19],_T_20[18],_T_142}; // @[el2_lib.scala 257:39]
wire _T_152 = ^_T_151; // @[el2_lib.scala 257:46]
wire [8:0] _T_160 = {_T_20[15],_T_20[14],_T_20[9],_T_20[8],_T_20[7],_T_20[6],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 257:56]
wire [17:0] _T_169 = {_T_20[30],_T_20[29],_T_20[28],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[17],_T_20[16],_T_160}; // @[el2_lib.scala 257:56]
wire _T_170 = ^_T_169; // @[el2_lib.scala 257:63]
wire [6:0] _T_176 = {_T_20[12],_T_20[11],_T_20[10],_T_20[9],_T_20[8],_T_20[7],_T_20[6]}; // @[el2_lib.scala 257:73]
wire [14:0] _T_184 = {_T_20[27],_T_20[26],_T_20[25],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[13],_T_176}; // @[el2_lib.scala 257:73]
wire _T_185 = ^_T_184; // @[el2_lib.scala 257:80]
wire [14:0] _T_199 = {_T_20[20],_T_20[19],_T_20[18],_T_20[17],_T_20[16],_T_20[15],_T_20[14],_T_20[13],_T_176}; // @[el2_lib.scala 257:90]
wire _T_200 = ^_T_199; // @[el2_lib.scala 257:97]
wire [5:0] _T_205 = {_T_20[5],_T_20[4],_T_20[3],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 257:107]
wire _T_206 = ^_T_205; // @[el2_lib.scala 257:114]
wire [5:0] _T_211 = {_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
wire _T_212 = ^_T_20; // @[el2_lib.scala 258:13]
wire _T_213 = ^_T_211; // @[el2_lib.scala 258:23]
wire _T_214 = _T_212 ^ _T_213; // @[el2_lib.scala 258:18]
wire [6:0] ic_tag_ecc = {_T_214,_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
wire [25:0] _T_221 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
wire [25:0] _T_226 = {ic_tag_ecc[4:0],2'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
wire _T_227 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 93:45]
wire [28:0] ic_rw_addr_q = _T_227 ? {{22'd0}, io_ic_debug_addr[9:3]} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 93:25]
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 95:38]
wire _T_240 = ~ic_tag_wren_q[0]; // @[el2_ifu_ic_mem.scala 102:59]
wire read_enable_0 = _T_240 & ic_tag_clken[0]; // @[el2_ifu_ic_mem.scala 102:77]
wire _T_244 = ~ic_tag_wren_q[1]; // @[el2_ifu_ic_mem.scala 102:59]
wire read_enable_1 = _T_244 & ic_tag_clken[1]; // @[el2_ifu_ic_mem.scala 102:77]
wire [25:0] _T_248 = read_enable_0 ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
wire [25:0] ic_tag_data_raw_0 = _T_248 & tag_mem_0__T_250_data; // @[el2_ifu_ic_mem.scala 103:87]
wire [25:0] _T_252 = read_enable_1 ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
wire [25:0] ic_tag_data_raw_1 = _T_252 & tag_mem_1__T_254_data; // @[el2_ifu_ic_mem.scala 103:87]
wire [23:0] w_tout_0 = {ic_tag_data_raw_0[25:21],ic_tag_data_raw_0[18:0]}; // @[Cat.scala 29:58]
wire [23:0] w_tout_1 = {ic_tag_data_raw_1[25:21],ic_tag_data_raw_1[18:0]}; // @[Cat.scala 29:58]
wire _T_261 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_ic_mem.scala 111:51]
wire _T_262 = _T_261 & ic_rd_en_ff; // @[el2_ifu_ic_mem.scala 111:80]
wire [31:0] _T_264 = {11'h0,ic_tag_data_raw_0[20:0]}; // @[Cat.scala 29:58]
wire [6:0] _T_266 = {2'h0,ic_tag_data_raw_0[25:21]}; // @[Cat.scala 29:58]
wire [5:0] _T_373 = {_T_264[31],_T_264[30],_T_264[29],_T_264[28],_T_264[27],_T_264[26]}; // @[el2_lib.scala 290:76]
wire _T_374 = ^_T_373; // @[el2_lib.scala 290:83]
wire _T_375 = _T_266[5] ^ _T_374; // @[el2_lib.scala 290:71]
wire [6:0] _T_382 = {_T_264[17],_T_264[16],_T_264[15],_T_264[14],_T_264[13],_T_264[12],_T_264[11]}; // @[el2_lib.scala 290:103]
wire [14:0] _T_390 = {_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[21],_T_264[20],_T_264[19],_T_264[18],_T_382}; // @[el2_lib.scala 290:103]
wire _T_391 = ^_T_390; // @[el2_lib.scala 290:110]
wire _T_392 = _T_266[4] ^ _T_391; // @[el2_lib.scala 290:98]
wire [6:0] _T_399 = {_T_264[10],_T_264[9],_T_264[8],_T_264[7],_T_264[6],_T_264[5],_T_264[4]}; // @[el2_lib.scala 290:130]
wire [14:0] _T_407 = {_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[21],_T_264[20],_T_264[19],_T_264[18],_T_399}; // @[el2_lib.scala 290:130]
wire _T_408 = ^_T_407; // @[el2_lib.scala 290:137]
wire _T_409 = _T_266[3] ^ _T_408; // @[el2_lib.scala 290:125]
wire [8:0] _T_418 = {_T_264[15],_T_264[14],_T_264[10],_T_264[9],_T_264[8],_T_264[7],_T_264[3],_T_264[2],_T_264[1]}; // @[el2_lib.scala 290:157]
wire [17:0] _T_427 = {_T_264[31],_T_264[30],_T_264[29],_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[17],_T_264[16],_T_418}; // @[el2_lib.scala 290:157]
wire _T_428 = ^_T_427; // @[el2_lib.scala 290:164]
wire _T_429 = _T_266[2] ^ _T_428; // @[el2_lib.scala 290:152]
wire [8:0] _T_438 = {_T_264[13],_T_264[12],_T_264[10],_T_264[9],_T_264[6],_T_264[5],_T_264[3],_T_264[2],_T_264[0]}; // @[el2_lib.scala 290:184]
wire [17:0] _T_447 = {_T_264[31],_T_264[28],_T_264[27],_T_264[25],_T_264[24],_T_264[21],_T_264[20],_T_264[17],_T_264[16],_T_438}; // @[el2_lib.scala 290:184]
wire _T_448 = ^_T_447; // @[el2_lib.scala 290:191]
wire _T_449 = _T_266[1] ^ _T_448; // @[el2_lib.scala 290:179]
wire [8:0] _T_458 = {_T_264[13],_T_264[11],_T_264[10],_T_264[8],_T_264[6],_T_264[4],_T_264[3],_T_264[1],_T_264[0]}; // @[el2_lib.scala 290:211]
wire [17:0] _T_467 = {_T_264[30],_T_264[28],_T_264[26],_T_264[25],_T_264[23],_T_264[21],_T_264[19],_T_264[17],_T_264[15],_T_458}; // @[el2_lib.scala 290:211]
wire _T_468 = ^_T_467; // @[el2_lib.scala 290:218]
wire _T_469 = _T_266[0] ^ _T_468; // @[el2_lib.scala 290:206]
wire [6:0] _T_475 = {1'h0,_T_375,_T_392,_T_409,_T_429,_T_449,_T_469}; // @[Cat.scala 29:58]
wire _T_476 = _T_475 != 7'h0; // @[el2_lib.scala 291:44]
wire _T_477 = _T_262 & _T_476; // @[el2_lib.scala 291:32]
wire ic_tag_single_ecc_error_0 = _T_477 & _T_475[6]; // @[el2_lib.scala 291:53]
wire _T_483 = ~_T_475[6]; // @[el2_lib.scala 292:55]
wire ic_tag_double_ecc_error_0 = _T_477 & _T_483; // @[el2_lib.scala 292:53]
wire [31:0] _T_652 = {11'h0,ic_tag_data_raw_1[20:0]}; // @[Cat.scala 29:58]
wire [6:0] _T_654 = {2'h0,ic_tag_data_raw_1[25:21]}; // @[Cat.scala 29:58]
wire [5:0] _T_761 = {_T_652[31],_T_652[30],_T_652[29],_T_652[28],_T_652[27],_T_652[26]}; // @[el2_lib.scala 290:76]
wire _T_762 = ^_T_761; // @[el2_lib.scala 290:83]
wire _T_763 = _T_654[5] ^ _T_762; // @[el2_lib.scala 290:71]
wire [6:0] _T_770 = {_T_652[17],_T_652[16],_T_652[15],_T_652[14],_T_652[13],_T_652[12],_T_652[11]}; // @[el2_lib.scala 290:103]
wire [14:0] _T_778 = {_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[21],_T_652[20],_T_652[19],_T_652[18],_T_770}; // @[el2_lib.scala 290:103]
wire _T_779 = ^_T_778; // @[el2_lib.scala 290:110]
wire _T_780 = _T_654[4] ^ _T_779; // @[el2_lib.scala 290:98]
wire [6:0] _T_787 = {_T_652[10],_T_652[9],_T_652[8],_T_652[7],_T_652[6],_T_652[5],_T_652[4]}; // @[el2_lib.scala 290:130]
wire [14:0] _T_795 = {_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[21],_T_652[20],_T_652[19],_T_652[18],_T_787}; // @[el2_lib.scala 290:130]
wire _T_796 = ^_T_795; // @[el2_lib.scala 290:137]
wire _T_797 = _T_654[3] ^ _T_796; // @[el2_lib.scala 290:125]
wire [8:0] _T_806 = {_T_652[15],_T_652[14],_T_652[10],_T_652[9],_T_652[8],_T_652[7],_T_652[3],_T_652[2],_T_652[1]}; // @[el2_lib.scala 290:157]
wire [17:0] _T_815 = {_T_652[31],_T_652[30],_T_652[29],_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[17],_T_652[16],_T_806}; // @[el2_lib.scala 290:157]
wire _T_816 = ^_T_815; // @[el2_lib.scala 290:164]
wire _T_817 = _T_654[2] ^ _T_816; // @[el2_lib.scala 290:152]
wire [8:0] _T_826 = {_T_652[13],_T_652[12],_T_652[10],_T_652[9],_T_652[6],_T_652[5],_T_652[3],_T_652[2],_T_652[0]}; // @[el2_lib.scala 290:184]
wire [17:0] _T_835 = {_T_652[31],_T_652[28],_T_652[27],_T_652[25],_T_652[24],_T_652[21],_T_652[20],_T_652[17],_T_652[16],_T_826}; // @[el2_lib.scala 290:184]
wire _T_836 = ^_T_835; // @[el2_lib.scala 290:191]
wire _T_837 = _T_654[1] ^ _T_836; // @[el2_lib.scala 290:179]
wire [8:0] _T_846 = {_T_652[13],_T_652[11],_T_652[10],_T_652[8],_T_652[6],_T_652[4],_T_652[3],_T_652[1],_T_652[0]}; // @[el2_lib.scala 290:211]
wire [17:0] _T_855 = {_T_652[30],_T_652[28],_T_652[26],_T_652[25],_T_652[23],_T_652[21],_T_652[19],_T_652[17],_T_652[15],_T_846}; // @[el2_lib.scala 290:211]
wire _T_856 = ^_T_855; // @[el2_lib.scala 290:218]
wire _T_857 = _T_654[0] ^ _T_856; // @[el2_lib.scala 290:206]
wire [6:0] _T_863 = {1'h0,_T_763,_T_780,_T_797,_T_817,_T_837,_T_857}; // @[Cat.scala 29:58]
wire _T_864 = _T_863 != 7'h0; // @[el2_lib.scala 291:44]
wire _T_865 = _T_262 & _T_864; // @[el2_lib.scala 291:32]
wire ic_tag_single_ecc_error_1 = _T_865 & _T_863[6]; // @[el2_lib.scala 291:53]
wire _T_871 = ~_T_863[6]; // @[el2_lib.scala 292:55]
wire ic_tag_double_ecc_error_1 = _T_865 & _T_871; // @[el2_lib.scala 292:53]
wire [1:0] _T_1037 = {ic_tag_single_ecc_error_1,ic_tag_single_ecc_error_0}; // @[Cat.scala 29:58]
wire [1:0] _T_1038 = {ic_tag_double_ecc_error_1,ic_tag_double_ecc_error_0}; // @[Cat.scala 29:58]
wire [1:0] ic_tag_way_perr = _T_1037 | _T_1038; // @[el2_ifu_ic_mem.scala 119:88]
wire [25:0] _T_1041 = ic_debug_rd_way_en_ff[0] ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
wire [25:0] _T_1042 = _T_1041 & ic_tag_data_raw_0; // @[el2_ifu_ic_mem.scala 123:112]
wire [25:0] _T_1045 = ic_debug_rd_way_en_ff[1] ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
wire [25:0] _T_1046 = _T_1045 & ic_tag_data_raw_1; // @[el2_ifu_ic_mem.scala 123:112]
wire _T_1049 = w_tout_0[18:0] == ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 124:83]
wire _T_1051 = _T_1049 & io_ic_tag_valid[0]; // @[el2_ifu_ic_mem.scala 124:100]
wire _T_1053 = w_tout_1[18:0] == ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 124:83]
wire _T_1055 = _T_1053 & io_ic_tag_valid[1]; // @[el2_ifu_ic_mem.scala 124:100]
wire [1:0] _T_1057 = ic_tag_way_perr & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 125:38]
assign tag_mem_0__T_250_addr = ic_rw_addr_q[6:0];
assign tag_mem_0__T_250_data = tag_mem_0[tag_mem_0__T_250_addr]; // @[el2_ifu_ic_mem.scala 97:20]
assign tag_mem_0__T_254_addr = ic_rw_addr_q[6:0];
assign tag_mem_0__T_254_data = tag_mem_0[tag_mem_0__T_254_addr]; // @[el2_ifu_ic_mem.scala 97:20]
assign tag_mem_0__T_238_data = _T_14 ? _T_221 : _T_226;
assign tag_mem_0__T_238_addr = ic_rw_addr_q[6:0];
assign tag_mem_0__T_238_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
assign tag_mem_0__T_238_en = 1'h1;
assign tag_mem_1__T_250_addr = ic_rw_addr_q[6:0];
assign tag_mem_1__T_250_data = tag_mem_1[tag_mem_1__T_250_addr]; // @[el2_ifu_ic_mem.scala 97:20]
assign tag_mem_1__T_254_addr = ic_rw_addr_q[6:0];
assign tag_mem_1__T_254_data = tag_mem_1[tag_mem_1__T_254_addr]; // @[el2_ifu_ic_mem.scala 97:20]
assign tag_mem_1__T_238_data = _T_14 ? _T_221 : _T_226;
assign tag_mem_1__T_238_addr = ic_rw_addr_q[6:0];
assign tag_mem_1__T_238_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
assign tag_mem_1__T_238_en = 1'h1;
assign io_ictag_debug_rd_data = _T_1042 | _T_1046; // @[el2_ifu_ic_mem.scala 64:26 el2_ifu_ic_mem.scala 123:26]
assign io_ic_rd_hit = {_T_1055,_T_1051}; // @[el2_ifu_ic_mem.scala 65:16 el2_ifu_ic_mem.scala 124:16]
assign io_ic_tag_perr = |_T_1057; // @[el2_ifu_ic_mem.scala 66:18 el2_ifu_ic_mem.scala 125:18]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {1{`RANDOM}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
tag_mem_0[initvar] = _RAND_0[25:0];
_RAND_1 = {1{`RANDOM}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
tag_mem_1[initvar] = _RAND_1[25:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
ic_rd_en_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
ic_rw_addr_ff = _RAND_3[18:0];
_RAND_4 = {1{`RANDOM}};
ic_debug_rd_way_en_ff = _RAND_4[1:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(tag_mem_0__T_238_en & tag_mem_0__T_238_mask) begin
tag_mem_0[tag_mem_0__T_238_addr] <= tag_mem_0__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
end
if(tag_mem_1__T_238_en & tag_mem_1__T_238_mask) begin
tag_mem_1[tag_mem_1__T_238_addr] <= tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
end
if (reset) begin
ic_rd_en_ff <= 1'h0;
end else begin
ic_rd_en_ff <= io_ic_rd_en;
end
if (reset) begin
ic_rw_addr_ff <= 19'h0;
end else begin
ic_rw_addr_ff <= io_ic_rw_addr[18:0];
end
if (reset) begin
ic_debug_rd_way_en_ff <= 2'h0;
end else begin
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
end
end
endmodule

9
InoutPort.v
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@ -1,9 +0,0 @@
module InoutPort( inout [15:0] a,
input [15:0] b,
input sel,
output [15:0] c);
assign a = sel ? 'bz : b;
assign c = sel ? a : 'bz;
endmodule

24
MakeInout.anno.json
View File

@ -1,24 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxInlineAnno",
"target":"MakeInout.rvdff",
"name":"rvdff.v",
"text":"\nmodule InoutPort( input [15:0] in,\n input clk,\n input reset,\n output [15:0] out);\n always@(posedge clk or negedge reset)\n begin\n if(reset == 0)\n out <= 0;\n else\n out <= in\n end\nendmodule\n "
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"MakeInout"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

26
MakeInout.fir
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@ -1,26 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit MakeInout :
extmodule rvdff :
input in : UInt<16>
input clk : Clock
input reset : UInt<1>
output out : UInt<16>
defname = rvdff
module MakeInout :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>}
inst m of rvdff @[GCD.scala 40:17]
m.out is invalid
m.reset is invalid
m.clk is invalid
m.in is invalid
io.out <= m.out @[GCD.scala 42:8]
m.reset <= io.reset @[GCD.scala 42:8]
m.clk <= io.clk @[GCD.scala 42:8]
m.in <= io.in @[GCD.scala 42:8]

23
MakeInout.v
View File

@ -1,23 +0,0 @@
module MakeInout(
input clock,
input reset,
input [15:0] io_in,
input io_clk,
input io_reset,
output [15:0] io_out
);
wire [15:0] m_in; // @[GCD.scala 40:17]
wire m_clk; // @[GCD.scala 40:17]
wire m_reset; // @[GCD.scala 40:17]
wire [15:0] m_out; // @[GCD.scala 40:17]
rvdff m ( // @[GCD.scala 40:17]
.in(m_in),
.clk(m_clk),
.reset(m_reset),
.out(m_out)
);
assign io_out = m_out; // @[GCD.scala 42:8]
assign m_in = io_in; // @[GCD.scala 42:8]
assign m_clk = io_clk; // @[GCD.scala 42:8]
assign m_reset = io_reset; // @[GCD.scala 42:8]
endmodule

60
RVCExpander.anno.json
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@ -1,60 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs2",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rd",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs1",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_bits",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_rvc",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs3",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"RVCExpander"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1193
RVCExpander.fir
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File diff suppressed because it is too large Load Diff

281
RVCExpander.v
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@ -1,281 +0,0 @@
module RVCExpander(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out_bits,
output [4:0] io_out_rd,
output [4:0] io_out_rs1,
output [4:0] io_out_rs2,
output [4:0] io_out_rs3,
output io_rvc
);
wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress.scala 49:29]
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 49:20]
wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58]
wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
wire [27:0] _T_78 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
wire [26:0] _T_109 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
wire [27:0] _T_136 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
wire [26:0] _T_167 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
wire [27:0] _T_194 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h23}; // @[Cat.scala 29:58]
wire [6:0] _T_205 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_207 = {_T_205,io_in[6:2]}; // @[Cat.scala 29:58]
wire [31:0] _T_213 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_221 = |io_in[11:7]; // @[el2_ifu_compress.scala 73:24]
wire [6:0] _T_222 = _T_221 ? 7'h1b : 7'h1f; // @[el2_ifu_compress.scala 73:20]
wire [31:0] _T_233 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],_T_222}; // @[Cat.scala 29:58]
wire [31:0] _T_249 = {_T_205,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_260 = |_T_207; // @[el2_ifu_compress.scala 86:29]
wire [6:0] _T_261 = _T_260 ? 7'h37 : 7'h3f; // @[el2_ifu_compress.scala 86:20]
wire [14:0] _T_264 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_267 = {_T_264,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_271 = {_T_267[31:12],io_in[11:7],_T_261}; // @[Cat.scala 29:58]
wire _T_279 = io_in[11:7] == 5'h0; // @[el2_ifu_compress.scala 88:14]
wire _T_281 = io_in[11:7] == 5'h2; // @[el2_ifu_compress.scala 88:27]
wire _T_282 = _T_279 | _T_281; // @[el2_ifu_compress.scala 88:21]
wire [6:0] _T_289 = _T_260 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 82:20]
wire [2:0] _T_292 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_307 = {_T_292,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_289}; // @[Cat.scala 29:58]
wire [31:0] _T_314_bits = _T_282 ? _T_307 : _T_271; // @[el2_ifu_compress.scala 88:10]
wire [4:0] _T_314_rd = _T_282 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 88:10]
wire [4:0] _T_314_rs2 = _T_282 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 88:10]
wire [4:0] _T_314_rs3 = _T_282 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 88:10]
wire [25:0] _T_325 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [30:0] _GEN_172 = {{5'd0}, _T_325}; // @[el2_ifu_compress.scala 95:23]
wire [30:0] _T_337 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress.scala 95:23]
wire [31:0] _T_350 = {_T_205,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [2:0] _T_354 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
wire _T_356 = io_in[6:5] == 2'h0; // @[el2_ifu_compress.scala 99:30]
wire [30:0] _T_357 = _T_356 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress.scala 99:22]
wire [6:0] _T_359 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress.scala 100:22]
wire [2:0] _GEN_1 = 3'h1 == _T_354 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
wire [2:0] _GEN_2 = 3'h2 == _T_354 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
wire [2:0] _GEN_3 = 3'h3 == _T_354 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
wire [2:0] _GEN_4 = 3'h4 == _T_354 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
wire [2:0] _GEN_5 = 3'h5 == _T_354 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
wire [2:0] _GEN_6 = 3'h6 == _T_354 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
wire [2:0] _GEN_7 = 3'h7 == _T_354 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
wire [24:0] _T_369 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_359}; // @[Cat.scala 29:58]
wire [30:0] _GEN_173 = {{6'd0}, _T_369}; // @[el2_ifu_compress.scala 101:43]
wire [30:0] _T_370 = _GEN_173 | _T_357; // @[el2_ifu_compress.scala 101:43]
wire [31:0] _T_371_0 = {{6'd0}, _T_325}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
wire [31:0] _T_371_1 = {{1'd0}, _T_337}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_371_1 : _T_371_0; // @[el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_350 : _GEN_9; // @[el2_ifu_compress.scala 18:14]
wire [31:0] _T_371_3 = {{1'd0}, _T_370}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19]
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_371_3 : _GEN_10; // @[el2_ifu_compress.scala 18:14]
wire [9:0] _T_383 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
wire [20:0] _T_398 = {_T_383,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_461 = {_T_398[20],_T_398[10:1],_T_398[11],_T_398[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
wire [4:0] _T_470 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
wire [12:0] _T_479 = {_T_470,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_528 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
wire [31:0] _T_595 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
wire [6:0] _T_602 = _T_221 ? 7'h3 : 7'h1f; // @[el2_ifu_compress.scala 109:23]
wire [25:0] _T_611 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [28:0] _T_627 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [27:0] _T_642 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
wire [28:0] _T_657 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
wire [24:0] _T_667 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_678 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_689 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
wire [24:0] _T_691 = {_T_689[24:7],7'h1f}; // @[Cat.scala 29:58]
wire [24:0] _T_694 = _T_221 ? _T_689 : _T_691; // @[el2_ifu_compress.scala 130:33]
wire _T_700 = |io_in[6:2]; // @[el2_ifu_compress.scala 131:27]
wire [31:0] _T_671_bits = {{7'd0}, _T_667}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _T_698_bits = {{7'd0}, _T_694}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _T_701_bits = _T_700 ? _T_671_bits : _T_698_bits; // @[el2_ifu_compress.scala 131:22]
wire [4:0] _T_701_rd = _T_700 ? io_in[11:7] : 5'h0; // @[el2_ifu_compress.scala 131:22]
wire [4:0] _T_701_rs1 = _T_700 ? 5'h0 : io_in[11:7]; // @[el2_ifu_compress.scala 131:22]
wire [4:0] _T_701_rs2 = _T_700 ? io_in[6:2] : io_in[6:2]; // @[el2_ifu_compress.scala 131:22]
wire [4:0] _T_701_rs3 = _T_700 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 131:22]
wire [24:0] _T_707 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
wire [24:0] _T_709 = {_T_689[24:7],7'h73}; // @[Cat.scala 29:58]
wire [24:0] _T_710 = _T_709 | 25'h100000; // @[el2_ifu_compress.scala 133:46]
wire [24:0] _T_713 = _T_221 ? _T_707 : _T_710; // @[el2_ifu_compress.scala 134:33]
wire [31:0] _T_683_bits = {{7'd0}, _T_678}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _T_717_bits = {{7'd0}, _T_713}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _T_720_bits = _T_700 ? _T_683_bits : _T_717_bits; // @[el2_ifu_compress.scala 135:25]
wire [4:0] _T_720_rd = _T_700 ? io_in[11:7] : 5'h1; // @[el2_ifu_compress.scala 135:25]
wire [4:0] _T_720_rs1 = _T_700 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 135:25]
wire [31:0] _T_722_bits = io_in[12] ? _T_720_bits : _T_701_bits; // @[el2_ifu_compress.scala 136:10]
wire [4:0] _T_722_rd = io_in[12] ? _T_720_rd : _T_701_rd; // @[el2_ifu_compress.scala 136:10]
wire [4:0] _T_722_rs1 = io_in[12] ? _T_720_rs1 : _T_701_rs1; // @[el2_ifu_compress.scala 136:10]
wire [4:0] _T_722_rs2 = io_in[12] ? _T_701_rs2 : _T_701_rs2; // @[el2_ifu_compress.scala 136:10]
wire [4:0] _T_722_rs3 = io_in[12] ? _T_701_rs3 : _T_701_rs3; // @[el2_ifu_compress.scala 136:10]
wire [8:0] _T_726 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [28:0] _T_738 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h27}; // @[Cat.scala 29:58]
wire [7:0] _T_746 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
wire [27:0] _T_758 = {_T_746[7:5],io_in[6:2],5'h2,3'h2,_T_746[4:0],7'h23}; // @[Cat.scala 29:58]
wire [28:0] _T_778 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h23}; // @[Cat.scala 29:58]
wire [4:0] _T_826 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_17 = 5'h1 == _T_826 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_18 = 5'h1 == _T_826 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_19 = 5'h1 == _T_826 ? _T_30 : 5'h2; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_21 = 5'h1 == _T_826 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_22 = 5'h2 == _T_826 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_23 = 5'h2 == _T_826 ? _T_14 : _GEN_18; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_24 = 5'h2 == _T_826 ? _T_30 : _GEN_19; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_26 = 5'h2 == _T_826 ? io_in[31:27] : _GEN_21; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_86_bits = {{4'd0}, _T_78}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_27 = 5'h3 == _T_826 ? _T_86_bits : _GEN_22; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_28 = 5'h3 == _T_826 ? _T_14 : _GEN_23; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_29 = 5'h3 == _T_826 ? _T_30 : _GEN_24; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_31 = 5'h3 == _T_826 ? io_in[31:27] : _GEN_26; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_117_bits = {{5'd0}, _T_109}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_32 = 5'h4 == _T_826 ? _T_117_bits : _GEN_27; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_33 = 5'h4 == _T_826 ? _T_14 : _GEN_28; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_34 = 5'h4 == _T_826 ? _T_30 : _GEN_29; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_36 = 5'h4 == _T_826 ? io_in[31:27] : _GEN_31; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_144_bits = {{4'd0}, _T_136}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_37 = 5'h5 == _T_826 ? _T_144_bits : _GEN_32; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_38 = 5'h5 == _T_826 ? _T_14 : _GEN_33; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_39 = 5'h5 == _T_826 ? _T_30 : _GEN_34; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_41 = 5'h5 == _T_826 ? io_in[31:27] : _GEN_36; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_175_bits = {{5'd0}, _T_167}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_42 = 5'h6 == _T_826 ? _T_175_bits : _GEN_37; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_43 = 5'h6 == _T_826 ? _T_14 : _GEN_38; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_44 = 5'h6 == _T_826 ? _T_30 : _GEN_39; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_46 = 5'h6 == _T_826 ? io_in[31:27] : _GEN_41; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_202_bits = {{4'd0}, _T_194}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_47 = 5'h7 == _T_826 ? _T_202_bits : _GEN_42; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_48 = 5'h7 == _T_826 ? _T_14 : _GEN_43; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_49 = 5'h7 == _T_826 ? _T_30 : _GEN_44; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_51 = 5'h7 == _T_826 ? io_in[31:27] : _GEN_46; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_52 = 5'h8 == _T_826 ? _T_213 : _GEN_47; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_53 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_48; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_54 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_49; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_55 = 5'h8 == _T_826 ? _T_14 : _GEN_48; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_56 = 5'h8 == _T_826 ? io_in[31:27] : _GEN_51; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_57 = 5'h9 == _T_826 ? _T_233 : _GEN_52; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_58 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_53; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_59 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_54; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_60 = 5'h9 == _T_826 ? _T_14 : _GEN_55; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_61 = 5'h9 == _T_826 ? io_in[31:27] : _GEN_56; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_62 = 5'ha == _T_826 ? _T_249 : _GEN_57; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_63 = 5'ha == _T_826 ? io_in[11:7] : _GEN_58; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_64 = 5'ha == _T_826 ? 5'h0 : _GEN_59; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_65 = 5'ha == _T_826 ? _T_14 : _GEN_60; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_66 = 5'ha == _T_826 ? io_in[31:27] : _GEN_61; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_67 = 5'hb == _T_826 ? _T_314_bits : _GEN_62; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_68 = 5'hb == _T_826 ? _T_314_rd : _GEN_63; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_69 = 5'hb == _T_826 ? _T_314_rd : _GEN_64; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_70 = 5'hb == _T_826 ? _T_314_rs2 : _GEN_65; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_71 = 5'hb == _T_826 ? _T_314_rs3 : _GEN_66; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_72 = 5'hc == _T_826 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_73 = 5'hc == _T_826 ? _T_30 : _GEN_68; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_74 = 5'hc == _T_826 ? _T_30 : _GEN_69; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_75 = 5'hc == _T_826 ? _T_14 : _GEN_70; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_76 = 5'hc == _T_826 ? io_in[31:27] : _GEN_71; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_77 = 5'hd == _T_826 ? _T_461 : _GEN_72; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_78 = 5'hd == _T_826 ? 5'h0 : _GEN_73; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_79 = 5'hd == _T_826 ? _T_30 : _GEN_74; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_80 = 5'hd == _T_826 ? _T_14 : _GEN_75; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_81 = 5'hd == _T_826 ? io_in[31:27] : _GEN_76; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_82 = 5'he == _T_826 ? _T_528 : _GEN_77; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_83 = 5'he == _T_826 ? _T_30 : _GEN_78; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_84 = 5'he == _T_826 ? _T_30 : _GEN_79; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_85 = 5'he == _T_826 ? 5'h0 : _GEN_80; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_86 = 5'he == _T_826 ? io_in[31:27] : _GEN_81; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_87 = 5'hf == _T_826 ? _T_595 : _GEN_82; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_88 = 5'hf == _T_826 ? 5'h0 : _GEN_83; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_89 = 5'hf == _T_826 ? _T_30 : _GEN_84; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_90 = 5'hf == _T_826 ? 5'h0 : _GEN_85; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_91 = 5'hf == _T_826 ? io_in[31:27] : _GEN_86; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_616_bits = {{6'd0}, _T_611}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_92 = 5'h10 == _T_826 ? _T_616_bits : _GEN_87; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_93 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_88; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_94 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_89; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_95 = 5'h10 == _T_826 ? io_in[6:2] : _GEN_90; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_96 = 5'h10 == _T_826 ? io_in[31:27] : _GEN_91; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_631_bits = {{3'd0}, _T_627}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_97 = 5'h11 == _T_826 ? _T_631_bits : _GEN_92; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_98 = 5'h11 == _T_826 ? io_in[11:7] : _GEN_93; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_99 = 5'h11 == _T_826 ? 5'h2 : _GEN_94; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_100 = 5'h11 == _T_826 ? io_in[6:2] : _GEN_95; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_101 = 5'h11 == _T_826 ? io_in[31:27] : _GEN_96; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_646_bits = {{4'd0}, _T_642}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_102 = 5'h12 == _T_826 ? _T_646_bits : _GEN_97; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_103 = 5'h12 == _T_826 ? io_in[11:7] : _GEN_98; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_104 = 5'h12 == _T_826 ? 5'h2 : _GEN_99; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_105 = 5'h12 == _T_826 ? io_in[6:2] : _GEN_100; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_106 = 5'h12 == _T_826 ? io_in[31:27] : _GEN_101; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_661_bits = {{3'd0}, _T_657}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_107 = 5'h13 == _T_826 ? _T_661_bits : _GEN_102; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_108 = 5'h13 == _T_826 ? io_in[11:7] : _GEN_103; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_109 = 5'h13 == _T_826 ? 5'h2 : _GEN_104; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_110 = 5'h13 == _T_826 ? io_in[6:2] : _GEN_105; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_111 = 5'h13 == _T_826 ? io_in[31:27] : _GEN_106; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_112 = 5'h14 == _T_826 ? _T_722_bits : _GEN_107; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_113 = 5'h14 == _T_826 ? _T_722_rd : _GEN_108; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_114 = 5'h14 == _T_826 ? _T_722_rs1 : _GEN_109; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_115 = 5'h14 == _T_826 ? _T_722_rs2 : _GEN_110; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_116 = 5'h14 == _T_826 ? _T_722_rs3 : _GEN_111; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_742_bits = {{3'd0}, _T_738}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_117 = 5'h15 == _T_826 ? _T_742_bits : _GEN_112; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_118 = 5'h15 == _T_826 ? io_in[11:7] : _GEN_113; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_119 = 5'h15 == _T_826 ? 5'h2 : _GEN_114; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_120 = 5'h15 == _T_826 ? io_in[6:2] : _GEN_115; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_121 = 5'h15 == _T_826 ? io_in[31:27] : _GEN_116; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_762_bits = {{4'd0}, _T_758}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_122 = 5'h16 == _T_826 ? _T_762_bits : _GEN_117; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_123 = 5'h16 == _T_826 ? io_in[11:7] : _GEN_118; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_124 = 5'h16 == _T_826 ? 5'h2 : _GEN_119; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_125 = 5'h16 == _T_826 ? io_in[6:2] : _GEN_120; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_126 = 5'h16 == _T_826 ? io_in[31:27] : _GEN_121; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _T_782_bits = {{3'd0}, _T_778}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14]
wire [31:0] _GEN_127 = 5'h17 == _T_826 ? _T_782_bits : _GEN_122; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_128 = 5'h17 == _T_826 ? io_in[11:7] : _GEN_123; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_129 = 5'h17 == _T_826 ? 5'h2 : _GEN_124; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_130 = 5'h17 == _T_826 ? io_in[6:2] : _GEN_125; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_131 = 5'h17 == _T_826 ? io_in[31:27] : _GEN_126; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_132 = 5'h18 == _T_826 ? io_in : _GEN_127; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_133 = 5'h18 == _T_826 ? io_in[11:7] : _GEN_128; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_134 = 5'h18 == _T_826 ? io_in[19:15] : _GEN_129; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_135 = 5'h18 == _T_826 ? io_in[24:20] : _GEN_130; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_136 = 5'h18 == _T_826 ? io_in[31:27] : _GEN_131; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_137 = 5'h19 == _T_826 ? io_in : _GEN_132; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_138 = 5'h19 == _T_826 ? io_in[11:7] : _GEN_133; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_139 = 5'h19 == _T_826 ? io_in[19:15] : _GEN_134; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_140 = 5'h19 == _T_826 ? io_in[24:20] : _GEN_135; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_141 = 5'h19 == _T_826 ? io_in[31:27] : _GEN_136; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_142 = 5'h1a == _T_826 ? io_in : _GEN_137; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_143 = 5'h1a == _T_826 ? io_in[11:7] : _GEN_138; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_144 = 5'h1a == _T_826 ? io_in[19:15] : _GEN_139; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_145 = 5'h1a == _T_826 ? io_in[24:20] : _GEN_140; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_146 = 5'h1a == _T_826 ? io_in[31:27] : _GEN_141; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_147 = 5'h1b == _T_826 ? io_in : _GEN_142; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_148 = 5'h1b == _T_826 ? io_in[11:7] : _GEN_143; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_149 = 5'h1b == _T_826 ? io_in[19:15] : _GEN_144; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_150 = 5'h1b == _T_826 ? io_in[24:20] : _GEN_145; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_151 = 5'h1b == _T_826 ? io_in[31:27] : _GEN_146; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_152 = 5'h1c == _T_826 ? io_in : _GEN_147; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_153 = 5'h1c == _T_826 ? io_in[11:7] : _GEN_148; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_154 = 5'h1c == _T_826 ? io_in[19:15] : _GEN_149; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_155 = 5'h1c == _T_826 ? io_in[24:20] : _GEN_150; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_156 = 5'h1c == _T_826 ? io_in[31:27] : _GEN_151; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_157 = 5'h1d == _T_826 ? io_in : _GEN_152; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_158 = 5'h1d == _T_826 ? io_in[11:7] : _GEN_153; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_159 = 5'h1d == _T_826 ? io_in[19:15] : _GEN_154; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_160 = 5'h1d == _T_826 ? io_in[24:20] : _GEN_155; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_161 = 5'h1d == _T_826 ? io_in[31:27] : _GEN_156; // @[el2_ifu_compress.scala 195:12]
wire [31:0] _GEN_162 = 5'h1e == _T_826 ? io_in : _GEN_157; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_163 = 5'h1e == _T_826 ? io_in[11:7] : _GEN_158; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_164 = 5'h1e == _T_826 ? io_in[19:15] : _GEN_159; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_165 = 5'h1e == _T_826 ? io_in[24:20] : _GEN_160; // @[el2_ifu_compress.scala 195:12]
wire [4:0] _GEN_166 = 5'h1e == _T_826 ? io_in[31:27] : _GEN_161; // @[el2_ifu_compress.scala 195:12]
assign io_out_bits = 5'h1f == _T_826 ? io_in : _GEN_162; // @[el2_ifu_compress.scala 195:12]
assign io_out_rd = 5'h1f == _T_826 ? io_in[11:7] : _GEN_163; // @[el2_ifu_compress.scala 195:12]
assign io_out_rs1 = 5'h1f == _T_826 ? io_in[19:15] : _GEN_164; // @[el2_ifu_compress.scala 195:12]
assign io_out_rs2 = 5'h1f == _T_826 ? io_in[24:20] : _GEN_165; // @[el2_ifu_compress.scala 195:12]
assign io_out_rs3 = 5'h1f == _T_826 ? io_in[31:27] : _GEN_166; // @[el2_ifu_compress.scala 195:12]
assign io_rvc = io_in[1:0] != 2'h3; // @[el2_ifu_compress.scala 193:12]
endmodule

14
TEC_RV_ICG.sv
View File

@ -1,14 +0,0 @@
module TEC_RV_ICG(
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

14
TEC_RV_ICG.v
View File

@ -1,14 +0,0 @@
module TEC_RV_ICG(
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

113
axi4_to_ahb.anno.json
View File

@ -1,113 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_araddr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arsize",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arprot"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1288
axi4_to_ahb.fir
View File

File diff suppressed because it is too large Load Diff

438
axi4_to_ahb.v
View File

@ -1,438 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module axi4_to_ahb(
input clock,
input reset,
input io_scan_mode,
input io_bus_clk_en,
input io_clk_override,
input io_axi_awvalid,
input io_axi_awid,
input [31:0] io_axi_awaddr,
input [2:0] io_axi_awsize,
input [2:0] io_axi_awprot,
input io_axi_wvalid,
input [63:0] io_axi_wdata,
input [7:0] io_axi_wstrb,
input io_axi_wlast,
input io_axi_bready,
input io_axi_arvalid,
input io_axi_arid,
input [31:0] io_axi_araddr,
input [2:0] io_axi_arsize,
input [2:0] io_axi_arprot,
input io_axi_rready,
input [63:0] io_ahb_hrdata,
input io_ahb_hready,
input io_ahb_hresp,
output io_axi_awready,
output io_axi_wready,
output io_axi_bvalid,
output [1:0] io_axi_bresp,
output io_axi_bid,
output io_axi_arready,
output io_axi_rvalid,
output io_axi_rid,
output [31:0] io_axi_rdata,
output [1:0] io_axi_rresp,
output io_axi_rlast,
output [31:0] io_ahb_haddr,
output [2:0] io_ahb_hburst,
output io_ahb_hmastlock,
output [3:0] io_ahb_hprot,
output [2:0] io_ahb_hsize,
output [1:0] io_ahb_htrans,
output io_ahb_hwrite,
output [63:0] io_ahb_hwdata
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [63:0] _RAND_6;
reg [63:0] _RAND_7;
reg [63:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 63:29]
wire wrbuf_en = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 216:11]
reg wrbuf_vld; // @[Reg.scala 27:20]
reg wrbuf_data_vld; // @[Reg.scala 27:20]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 193:27]
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 194:30]
wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 196:20]
wire [2:0] master_opc = {{1'd0}, _T_28}; // @[axi4_to_ahb.scala 196:14]
wire _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 252:89]
wire _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 252:70]
wire _T_151 = ~_T_150; // @[axi4_to_ahb.scala 252:55]
wire wrbuf_data_en = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34]
wire _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 186:33]
wire wrbuf_rst = _T_150 & _T_8; // @[axi4_to_ahb.scala 186:31]
wire _T_11 = wrbuf_vld & _T_151; // @[axi4_to_ahb.scala 188:33]
wire _T_15 = wrbuf_data_vld & _T_151; // @[axi4_to_ahb.scala 189:37]
reg [31:0] wrbuf_addr; // @[Reg.scala 27:20]
wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 197:21]
reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 198:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
wire buf_clk = rvclkhdr_2_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11]
reg [63:0] buf_data; // @[Reg.scala 27:20]
wire ahbm_data_clk = rvclkhdr_5_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 425:12]
wire _T_60 = wrbuf_en | wrbuf_data_en; // @[axi4_to_ahb.scala 214:74]
wire _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire buf_data_wr_en = master_valid & _T_69; // @[axi4_to_ahb.scala 230:38]
wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16]
wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16]
wire [2:0] _T_103 = wrbuf_byteen[4] ? 3'h4 : _T_102; // @[Mux.scala 98:16]
wire [2:0] _T_104 = wrbuf_byteen[3] ? 3'h3 : _T_103; // @[Mux.scala 98:16]
wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16]
wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16]
wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16]
wire [2:0] buf_cmd_byte_ptr = _T_149 ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
wire [1:0] _T_113 = master_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61]
reg [31:0] buf_addr; // @[Reg.scala 27:20]
wire _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 331:24]
wire _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 330:51]
wire _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 331:57]
wire _T_544 = _T_541 | _T_543; // @[axi4_to_ahb.scala 331:36]
wire _T_546 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 331:91]
wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 331:70]
wire _T_549 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 332:25]
wire _T_551 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 332:62]
wire _T_553 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 332:97]
wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 332:74]
wire _T_556 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 332:132]
wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 332:109]
wire _T_559 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 332:168]
wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 332:145]
wire _T_562 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 333:28]
wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 332:181]
wire _T_565 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 333:63]
wire _T_566 = _T_563 | _T_565; // @[axi4_to_ahb.scala 333:40]
wire _T_568 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 333:99]
wire _T_569 = _T_566 | _T_568; // @[axi4_to_ahb.scala 333:76]
wire _T_570 = _T_549 & _T_569; // @[axi4_to_ahb.scala 332:38]
wire buf_aligned_in = _T_547 | _T_570; // @[axi4_to_ahb.scala 331:104]
wire _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 325:55]
wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 325:38]
wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58]
wire _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 329:38]
wire _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 329:72]
wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 329:21]
wire [31:0] _T_575 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_578 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_582 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_536}; // @[axi4_to_ahb.scala 329:15]
wire [1:0] _T_584 = _T_582 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 336:80]
wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
wire _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 340:33]
wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20]
wire [31:0] buf_addr_in = _T_490[31:0]; // @[axi4_to_ahb.scala 325:15]
wire _T_652 = master_valid & io_bus_clk_en; // @[axi4_to_ahb.scala 379:61]
wire _T_664 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 391:66]
wire _T_688 = master_valid | io_clk_override; // @[axi4_to_ahb.scala 428:58]
wire _T_691 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54]
wire _T_692 = _T_691 | io_clk_override; // @[axi4_to_ahb.scala 429:74]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
assign io_axi_awready = ~_T_11; // @[axi4_to_ahb.scala 188:18]
assign io_axi_wready = ~_T_15; // @[axi4_to_ahb.scala 189:17]
assign io_axi_bvalid = 1'h0; // @[axi4_to_ahb.scala 203:17]
assign io_axi_bresp = 2'h0; // @[axi4_to_ahb.scala 204:16]
assign io_axi_bid = 1'h0; // @[axi4_to_ahb.scala 205:14]
assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18]
assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17]
assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14]
assign io_axi_rdata = ahb_hrdata_q[31:0]; // @[axi4_to_ahb.scala 210:16]
assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16]
assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 338:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 339:20]
assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 340:16]
assign io_ahb_hsize = master_valid ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16]
assign io_ahb_htrans = _T_113 & 2'h2; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
assign io_ahb_hwrite = master_valid ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 342:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = io_bus_clk_en & _T_688; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_4_io_en = io_bus_clk_en & _T_692; // @[el2_lib.scala 485:16]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_5_io_en = io_bus_clk_en & io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
buf_nxtstate = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wrbuf_vld = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
wrbuf_data_vld = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
wrbuf_addr = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
wrbuf_size = _RAND_4[2:0];
_RAND_5 = {1{`RANDOM}};
wrbuf_byteen = _RAND_5[7:0];
_RAND_6 = {2{`RANDOM}};
wrbuf_data = _RAND_6[63:0];
_RAND_7 = {2{`RANDOM}};
buf_data = _RAND_7[63:0];
_RAND_8 = {2{`RANDOM}};
ahb_hrdata_q = _RAND_8[63:0];
_RAND_9 = {1{`RANDOM}};
buf_addr = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
buf_write = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
buf_nxtstate = 3'h0;
end
if (reset) begin
wrbuf_vld = 1'h0;
end
if (reset) begin
wrbuf_data_vld = 1'h0;
end
if (reset) begin
wrbuf_addr = 32'h0;
end
if (reset) begin
wrbuf_size = 3'h0;
end
if (reset) begin
wrbuf_byteen = 8'h0;
end
if (reset) begin
wrbuf_data = 64'h0;
end
if (reset) begin
buf_data = 64'h0;
end
if (reset) begin
ahb_hrdata_q = 64'h0;
end
if (reset) begin
buf_addr = 32'h0;
end
if (reset) begin
buf_write = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_nxtstate <= 3'h0;
end else if (_T_149) begin
buf_nxtstate <= 3'h2;
end else begin
buf_nxtstate <= 3'h1;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_vld <= 1'h0;
end else if (wrbuf_en) begin
wrbuf_vld <= wrbuf_rst;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_data_vld <= 1'h0;
end else if (wrbuf_data_en) begin
wrbuf_data_vld <= wrbuf_rst;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wrbuf_addr <= 32'h0;
end else if (wrbuf_en) begin
wrbuf_addr <= io_axi_awaddr;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_size <= 3'h0;
end else if (wrbuf_en) begin
wrbuf_size <= io_axi_awsize;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_byteen <= 8'h0;
end else if (wrbuf_data_en) begin
wrbuf_byteen <= io_axi_wstrb;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wrbuf_data <= 64'h0;
end else if (wrbuf_data_en) begin
wrbuf_data <= io_axi_wdata;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_data <= 64'h0;
end else if (_T_664) begin
buf_data <= wrbuf_data;
end
end
always @(posedge ahbm_data_clk or posedge reset) begin
if (reset) begin
ahb_hrdata_q <= 64'h0;
end else begin
ahb_hrdata_q <= io_ahb_hrdata;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_addr <= 32'h0;
end else if (_T_652) begin
buf_addr <= buf_addr_in;
end
end
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
buf_write <= 1'h0;
end else if (master_valid) begin
buf_write <= _T_149;
end
end
endmodule

25
caller.anno.json
View File

@ -1,25 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~caller|caller>io_out",
"sources":[
"~caller|caller>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"caller"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

20
caller.fir
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@ -1,20 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit caller :
module rvdff :
input clock : Clock
input reset : Reset
output io : {flip in : UInt<32>, out : UInt}
io.out <= io.in @[GCD.scala 12:10]
module caller :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<32>, out : UInt}
inst u0 of rvdff @[GCD.scala 21:18]
u0.clock <= clock
u0.reset <= reset
io.out <= u0.io.out @[GCD.scala 22:6]
u0.io.in <= io.in @[GCD.scala 22:6]

21
caller.v
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@ -1,21 +0,0 @@
module rvdff(
input [31:0] io_in,
output [31:0] io_out
);
assign io_out = io_in; // @[GCD.scala 12:10]
endmodule
module caller(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out
);
wire [31:0] u0_io_in; // @[GCD.scala 21:18]
wire [31:0] u0_io_out; // @[GCD.scala 21:18]
rvdff u0 ( // @[GCD.scala 21:18]
.io_in(u0_io_in),
.io_out(u0_io_out)
);
assign io_out = u0_io_out; // @[GCD.scala 22:6]
assign u0_io_in = io_in; // @[GCD.scala 22:6]
endmodule

18
dmi_wrapper.anno.json
View File

@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_wrapper"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

349
dmi_wrapper.fir
View File

@ -1,349 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_wrapper :
module rvjtag_tap :
input clock : Clock
input reset : AsyncReset
output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>}
wire nsr : UInt<41>
nsr <= UInt<41>("h00")
reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55]
sr <= nsr @[rvjtag_tap.scala 32:55]
wire dr : UInt<41>
dr <= UInt<41>("h00")
wire nstate : UInt<4>
nstate <= UInt<4>("h00")
reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57]
state <= nstate @[rvjtag_tap.scala 39:57]
wire ir : UInt<5>
ir <= UInt<5>("h00")
wire jtag_reset : UInt<1>
jtag_reset <= UInt<1>("h00")
wire shift_dr : UInt<1>
shift_dr <= UInt<1>("h00")
wire pause_dr : UInt<1>
pause_dr <= UInt<1>("h00")
wire update_dr : UInt<1>
update_dr <= UInt<1>("h00")
wire capture_dr : UInt<1>
capture_dr <= UInt<1>("h00")
wire shift_ir : UInt<1>
shift_ir <= UInt<1>("h00")
wire pause_ir : UInt<1>
pause_ir <= UInt<1>("h00")
wire update_ir : UInt<1>
update_ir <= UInt<1>("h00")
wire capture_ir : UInt<1>
capture_ir <= UInt<1>("h00")
wire dr_en : UInt<2>
dr_en <= UInt<1>("h00")
wire devid_sel : UInt<1>
devid_sel <= UInt<1>("h00")
node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30]
when _T : @[Conditional.scala 40:58]
node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46]
nstate <= _T_1 @[rvjtag_tap.scala 55:40]
jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30]
when _T_2 : @[Conditional.scala 39:67]
node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47]
nstate <= _T_3 @[rvjtag_tap.scala 57:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30]
when _T_4 : @[Conditional.scala 39:67]
node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47]
nstate <= _T_5 @[rvjtag_tap.scala 58:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30]
when _T_6 : @[Conditional.scala 39:67]
node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47]
nstate <= _T_7 @[rvjtag_tap.scala 59:41]
capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30]
when _T_8 : @[Conditional.scala 39:67]
node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47]
nstate <= _T_9 @[rvjtag_tap.scala 61:41]
shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30]
when _T_10 : @[Conditional.scala 39:67]
node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47]
nstate <= _T_11 @[rvjtag_tap.scala 63:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30]
when _T_12 : @[Conditional.scala 39:67]
node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47]
nstate <= _T_13 @[rvjtag_tap.scala 64:41]
pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30]
when _T_14 : @[Conditional.scala 39:67]
node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47]
nstate <= _T_15 @[rvjtag_tap.scala 66:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30]
when _T_16 : @[Conditional.scala 39:67]
node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47]
nstate <= _T_17 @[rvjtag_tap.scala 67:41]
update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30]
when _T_18 : @[Conditional.scala 39:67]
node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47]
nstate <= _T_19 @[rvjtag_tap.scala 69:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30]
when _T_20 : @[Conditional.scala 39:67]
node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47]
nstate <= _T_21 @[rvjtag_tap.scala 70:41]
capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30]
when _T_22 : @[Conditional.scala 39:67]
node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47]
nstate <= _T_23 @[rvjtag_tap.scala 72:41]
shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30]
when _T_24 : @[Conditional.scala 39:67]
node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47]
nstate <= _T_25 @[rvjtag_tap.scala 74:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30]
when _T_26 : @[Conditional.scala 39:67]
node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47]
nstate <= _T_27 @[rvjtag_tap.scala 75:41]
pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30]
when _T_28 : @[Conditional.scala 39:67]
node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47]
nstate <= _T_29 @[rvjtag_tap.scala 77:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30]
when _T_30 : @[Conditional.scala 39:67]
node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47]
nstate <= _T_31 @[rvjtag_tap.scala 78:41]
update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17]
skip @[Conditional.scala 39:67]
node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28]
io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16]
node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93]
node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98]
node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106]
node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123]
node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89]
node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75]
node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56]
reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52]
_T_40 <= _T_39 @[rvjtag_tap.scala 85:52]
ir <= _T_40 @[rvjtag_tap.scala 85:6]
node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18]
devid_sel <= _T_41 @[rvjtag_tap.scala 86:13]
node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22]
node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32]
node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58]
dr_en <= _T_44 @[rvjtag_tap.scala 87:13]
node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16]
when _T_45 : @[rvjtag_tap.scala 92:23]
node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18]
when _T_47 : @[rvjtag_tap.scala 93:28]
node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49]
node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58]
nsr <= _T_49 @[rvjtag_tap.scala 93:33]
skip @[rvjtag_tap.scala 93:28]
else : @[rvjtag_tap.scala 94:54]
node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25]
node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44]
node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32]
when _T_53 : @[rvjtag_tap.scala 94:54]
node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106]
node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58]
node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58]
nsr <= _T_57 @[rvjtag_tap.scala 94:59]
skip @[rvjtag_tap.scala 94:54]
else : @[rvjtag_tap.scala 95:17]
node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58]
nsr <= _T_59 @[rvjtag_tap.scala 95:22]
skip @[rvjtag_tap.scala 95:17]
skip @[rvjtag_tap.scala 92:23]
else : @[rvjtag_tap.scala 97:33]
node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26]
when _T_60 : @[rvjtag_tap.scala 97:33]
node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17]
when _T_61 : @[rvjtag_tap.scala 98:21]
node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58]
node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58]
node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58]
node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58]
nsr <= _T_66 @[rvjtag_tap.scala 98:26]
skip @[rvjtag_tap.scala 98:21]
else : @[rvjtag_tap.scala 99:28]
node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24]
when _T_67 : @[rvjtag_tap.scala 99:28]
node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58]
node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58]
nsr <= _T_70 @[rvjtag_tap.scala 99:33]
skip @[rvjtag_tap.scala 99:28]
else : @[rvjtag_tap.scala 100:29]
when devid_sel : @[rvjtag_tap.scala 100:29]
node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58]
node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58]
nsr <= _T_73 @[rvjtag_tap.scala 100:34]
skip @[rvjtag_tap.scala 100:29]
skip @[rvjtag_tap.scala 97:33]
else : @[rvjtag_tap.scala 102:30]
node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23]
when _T_74 : @[rvjtag_tap.scala 102:30]
node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12]
node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78]
node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58]
node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
nsr <= _T_78 @[rvjtag_tap.scala 102:35]
skip @[rvjtag_tap.scala 102:30]
else : @[rvjtag_tap.scala 103:32]
node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25]
when _T_79 : @[rvjtag_tap.scala 103:32]
node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58]
nsr <= _T_81 @[rvjtag_tap.scala 103:37]
skip @[rvjtag_tap.scala 103:32]
node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40]
reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37]
_T_83 <= _T_82 @[rvjtag_tap.scala 106:37]
io.tdo <= _T_83 @[rvjtag_tap.scala 106:28]
node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89]
node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99]
node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82]
node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104]
node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71]
reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67]
_T_89 <= _T_88 @[rvjtag_tap.scala 108:67]
io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57]
node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84]
node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94]
node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77]
node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99]
node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66]
reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62]
_T_95 <= _T_94 @[rvjtag_tap.scala 109:62]
io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52]
node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74]
node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84]
node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67]
node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96]
node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56]
reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52]
_T_102 <= _T_101 @[rvjtag_tap.scala 111:52]
dr <= _T_102 @[rvjtag_tap.scala 111:42]
node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19]
io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14]
node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19]
io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14]
node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19]
io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14]
node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19]
io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14]
module dmi_jtag_to_core_sync :
input clock : Clock
input reset : AsyncReset
output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
wire c_rd_en : UInt<1>
c_rd_en <= UInt<1>("h00")
wire c_wr_en : UInt<1>
c_wr_en <= UInt<1>("h00")
wire rden : UInt<3>
rden <= UInt<3>("h00")
wire wren : UInt<3>
wren <= UInt<3>("h00")
node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 26:18]
rden <= _T_2 @[dmi_jtag_to_core_sync.scala 26:8]
node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 27:27]
node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 27:18]
_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 27:18]
wren <= _T_5 @[dmi_jtag_to_core_sync.scala 27:8]
node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:18]
node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:29]
node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:24]
node _T_9 = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:22]
c_rd_en <= _T_9 @[dmi_jtag_to_core_sync.scala 28:11]
node _T_10 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:18]
node _T_11 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:29]
node _T_12 = eq(_T_11, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:24]
node _T_13 = and(_T_10, _T_12) @[dmi_jtag_to_core_sync.scala 29:22]
c_wr_en <= _T_13 @[dmi_jtag_to_core_sync.scala 29:11]
node _T_14 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:28]
io.reg_en <= _T_14 @[dmi_jtag_to_core_sync.scala 31:17]
io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:17]
module dmi_wrapper :
input clock : Clock
input reset : AsyncReset
output io : {flip trst_n : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
wire rd_en : UInt<1>
rd_en <= UInt<1>("h00")
wire wr_en : UInt<1>
wr_en <= UInt<1>("h00")
wire dmireset : UInt<1>
dmireset <= UInt<1>("h00")
inst i_jtag_tap of rvjtag_tap @[dmi_wrapper.scala 35:27]
i_jtag_tap.clock <= clock
i_jtag_tap.reset <= reset
i_jtag_tap.io.trst <= io.trst_n @[dmi_wrapper.scala 36:27]
i_jtag_tap.io.tck <= io.tck @[dmi_wrapper.scala 37:27]
i_jtag_tap.io.tms <= io.tms @[dmi_wrapper.scala 38:27]
i_jtag_tap.io.tdi <= io.tdi @[dmi_wrapper.scala 39:27]
io.tdo <= i_jtag_tap.io.tdo @[dmi_wrapper.scala 40:27]
io.tdoEnable <= i_jtag_tap.io.tdoEnable @[dmi_wrapper.scala 41:27]
io.reg_wr_data <= i_jtag_tap.io.wr_data @[dmi_wrapper.scala 42:27]
io.reg_wr_addr <= i_jtag_tap.io.wr_addr @[dmi_wrapper.scala 43:27]
rd_en <= i_jtag_tap.io.rd_en @[dmi_wrapper.scala 44:27]
wr_en <= i_jtag_tap.io.wr_en @[dmi_wrapper.scala 45:27]
i_jtag_tap.io.rd_data <= io.rd_data @[dmi_wrapper.scala 46:27]
i_jtag_tap.io.rd_status <= UInt<2>("h00") @[dmi_wrapper.scala 47:27]
i_jtag_tap.io.idle <= UInt<3>("h00") @[dmi_wrapper.scala 48:27]
i_jtag_tap.io.dmi_stat <= UInt<2>("h00") @[dmi_wrapper.scala 49:27]
i_jtag_tap.io.version <= UInt<4>("h01") @[dmi_wrapper.scala 50:27]
i_jtag_tap.io.jtag_id <= io.jtag_id @[dmi_wrapper.scala 51:27]
io.dmi_hard_reset <= i_jtag_tap.io.dmi_hard_reset @[dmi_wrapper.scala 52:27]
dmireset <= i_jtag_tap.io.dmi_reset @[dmi_wrapper.scala 53:26]
inst i_dmi_jtag_to_core_sync of dmi_jtag_to_core_sync @[dmi_wrapper.scala 56:39]
i_dmi_jtag_to_core_sync.clock <= clock
i_dmi_jtag_to_core_sync.reset <= reset
i_dmi_jtag_to_core_sync.io.wr_en <= wr_en @[dmi_wrapper.scala 57:36]
i_dmi_jtag_to_core_sync.io.rd_en <= rd_en @[dmi_wrapper.scala 58:36]
io.reg_en <= i_dmi_jtag_to_core_sync.io.reg_en @[dmi_wrapper.scala 59:16]
io.reg_wr_en <= i_dmi_jtag_to_core_sync.io.reg_wr_en @[dmi_wrapper.scala 60:16]

525
dmi_wrapper.v
View File

@ -1,525 +0,0 @@
module rvjtag_tap(
input reset,
input io_trst,
input io_tck,
input io_tms,
input io_tdi,
output io_dmi_hard_reset,
input [30:0] io_jtag_id,
input [31:0] io_rd_data,
output io_tdo,
output io_tdoEnable,
output io_wr_en,
output io_rd_en,
output [31:0] io_wr_data
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [63:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
reg [40:0] sr; // @[rvjtag_tap.scala 32:55]
reg [3:0] state; // @[rvjtag_tap.scala 39:57]
wire jtag_reset = 4'h0 == state; // @[Conditional.scala 37:30]
wire _T_2 = 4'h1 == state; // @[Conditional.scala 37:30]
wire _T_4 = 4'h2 == state; // @[Conditional.scala 37:30]
wire _T_6 = 4'h3 == state; // @[Conditional.scala 37:30]
wire _T_8 = 4'h4 == state; // @[Conditional.scala 37:30]
wire _T_10 = 4'h5 == state; // @[Conditional.scala 37:30]
wire _T_12 = 4'h6 == state; // @[Conditional.scala 37:30]
wire _T_14 = 4'h7 == state; // @[Conditional.scala 37:30]
wire _T_16 = 4'h8 == state; // @[Conditional.scala 37:30]
wire _T_18 = 4'h9 == state; // @[Conditional.scala 37:30]
wire _T_20 = 4'ha == state; // @[Conditional.scala 37:30]
wire _T_22 = 4'hb == state; // @[Conditional.scala 37:30]
wire _T_24 = 4'hc == state; // @[Conditional.scala 37:30]
wire _T_26 = 4'hd == state; // @[Conditional.scala 37:30]
wire _T_28 = 4'he == state; // @[Conditional.scala 37:30]
wire _T_30 = 4'hf == state; // @[Conditional.scala 37:30]
wire _GEN_3 = _T_28 ? 1'h0 : _T_30; // @[Conditional.scala 39:67]
wire _GEN_6 = _T_26 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_24 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67]
wire _GEN_13 = _T_22 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_20 ? 1'h0 : _T_22; // @[Conditional.scala 39:67]
wire _GEN_18 = _T_20 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_18 ? 1'h0 : _T_20; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_18 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_23 = _T_18 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_16 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
wire _GEN_27 = _T_16 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire _GEN_29 = _T_16 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
wire _GEN_31 = _T_14 ? 1'h0 : _T_16; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_14 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_14 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_14 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
wire _GEN_38 = _T_12 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
wire _GEN_39 = _T_12 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
wire _GEN_40 = _T_12 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_42 = _T_12 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_10 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_10 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67]
wire _GEN_47 = _T_10 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_10 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
wire _GEN_53 = _T_8 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
wire _GEN_54 = _T_8 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
wire _GEN_55 = _T_8 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
wire _GEN_57 = _T_8 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67]
wire _GEN_60 = _T_6 ? 1'h0 : _T_8; // @[Conditional.scala 39:67]
wire _GEN_62 = _T_6 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_63 = _T_6 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
wire _GEN_64 = _T_6 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
wire _GEN_66 = _T_6 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
wire _GEN_68 = _T_4 ? 1'h0 : _T_6; // @[Conditional.scala 39:67]
wire _GEN_69 = _T_4 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_71 = _T_4 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_4 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_73 = _T_4 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
wire _GEN_75 = _T_4 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
wire _GEN_77 = _T_2 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
wire _GEN_78 = _T_2 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
wire _GEN_80 = _T_2 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
wire _GEN_81 = _T_2 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire _GEN_82 = _T_2 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_2 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
wire capture_dr = jtag_reset ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
wire shift_dr = jtag_reset ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58]
wire update_dr = jtag_reset ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58]
wire capture_ir = jtag_reset ? 1'h0 : _GEN_81; // @[Conditional.scala 40:58]
wire shift_ir = jtag_reset ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
wire update_ir = jtag_reset ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
wire _T_34 = sr[4:0] == 5'h0; // @[rvjtag_tap.scala 85:98]
reg [4:0] ir; // @[rvjtag_tap.scala 85:52]
wire devid_sel = ir == 5'h1; // @[rvjtag_tap.scala 86:18]
wire _T_42 = ir == 5'h11; // @[rvjtag_tap.scala 87:22]
wire _T_43 = ir == 5'h10; // @[rvjtag_tap.scala 87:32]
wire [1:0] dr_en = {_T_42,_T_43}; // @[Cat.scala 29:58]
wire [40:0] _T_49 = {io_tdi,sr[40:1]}; // @[Cat.scala 29:58]
wire _T_53 = dr_en[0] | devid_sel; // @[rvjtag_tap.scala 94:32]
wire [40:0] _T_57 = {9'h0,io_tdi,sr[31:1]}; // @[Cat.scala 29:58]
wire [40:0] _T_59 = {40'h0,io_tdi}; // @[Cat.scala 29:58]
wire [40:0] _T_70 = {7'h0,io_rd_data,2'h0}; // @[Cat.scala 29:58]
wire [40:0] _T_73 = {9'h0,io_jtag_id,1'h1}; // @[Cat.scala 29:58]
wire [40:0] _T_78 = {36'h0,io_tdi,sr[4:1]}; // @[Cat.scala 29:58]
reg _T_83; // @[rvjtag_tap.scala 106:37]
wire _T_86 = update_dr & dr_en[0]; // @[rvjtag_tap.scala 108:82]
reg _T_89; // @[rvjtag_tap.scala 108:67]
wire _T_98 = update_dr & dr_en[1]; // @[rvjtag_tap.scala 111:67]
reg [40:0] dr; // @[rvjtag_tap.scala 111:52]
wire [40:0] _T_100 = {dr[40:2],2'h0}; // @[Cat.scala 29:58]
assign io_dmi_hard_reset = _T_89; // @[rvjtag_tap.scala 108:57]
assign io_tdo = _T_83; // @[rvjtag_tap.scala 106:28]
assign io_tdoEnable = shift_dr | shift_ir; // @[rvjtag_tap.scala 81:16]
assign io_wr_en = dr[1]; // @[rvjtag_tap.scala 114:14]
assign io_rd_en = dr[0]; // @[rvjtag_tap.scala 113:14]
assign io_wr_data = dr[33:2]; // @[rvjtag_tap.scala 115:14]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
sr = _RAND_0[40:0];
_RAND_1 = {1{`RANDOM}};
state = _RAND_1[3:0];
_RAND_2 = {1{`RANDOM}};
ir = _RAND_2[4:0];
_RAND_3 = {1{`RANDOM}};
_T_83 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T_89 = _RAND_4[0:0];
_RAND_5 = {2{`RANDOM}};
dr = _RAND_5[40:0];
`endif // RANDOMIZE_REG_INIT
if (io_trst) begin
sr = 41'h0;
end
if (io_trst) begin
state = 4'h0;
end
if (io_trst) begin
ir = 5'h1;
end
if (reset) begin
_T_83 = 1'h0;
end
if (io_trst) begin
_T_89 = 1'h0;
end
if (io_trst) begin
dr = 41'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
sr <= 41'h0;
end else if (shift_dr) begin
if (dr_en[1]) begin
sr <= _T_49;
end else if (_T_53) begin
sr <= _T_57;
end else begin
sr <= _T_59;
end
end else if (capture_dr) begin
if (dr_en[0]) begin
sr <= 41'h71;
end else if (dr_en[1]) begin
sr <= _T_70;
end else if (devid_sel) begin
sr <= _T_73;
end else begin
sr <= 41'h0;
end
end else if (shift_ir) begin
sr <= _T_78;
end else if (capture_ir) begin
sr <= 41'h1;
end else begin
sr <= 41'h0;
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
state <= 4'h0;
end else if (jtag_reset) begin
if (io_tms) begin
state <= 4'h0;
end else begin
state <= 4'h1;
end
end else if (_T_2) begin
if (io_tms) begin
state <= 4'h2;
end else begin
state <= 4'h1;
end
end else if (_T_4) begin
if (io_tms) begin
state <= 4'h9;
end else begin
state <= 4'h3;
end
end else if (_T_6) begin
if (io_tms) begin
state <= 4'h5;
end else begin
state <= 4'h4;
end
end else if (_T_8) begin
if (io_tms) begin
state <= 4'h5;
end else begin
state <= 4'h4;
end
end else if (_T_10) begin
if (io_tms) begin
state <= 4'h8;
end else begin
state <= 4'h6;
end
end else if (_T_12) begin
if (io_tms) begin
state <= 4'h7;
end else begin
state <= 4'h6;
end
end else if (_T_14) begin
if (io_tms) begin
state <= 4'h8;
end else begin
state <= 4'h4;
end
end else if (_T_16) begin
if (io_tms) begin
state <= 4'h2;
end else begin
state <= 4'h1;
end
end else if (_T_18) begin
if (io_tms) begin
state <= 4'h0;
end else begin
state <= 4'ha;
end
end else if (_T_20) begin
if (io_tms) begin
state <= 4'hc;
end else begin
state <= 4'hb;
end
end else if (_T_22) begin
if (io_tms) begin
state <= 4'hc;
end else begin
state <= 4'hb;
end
end else if (_T_24) begin
if (io_tms) begin
state <= 4'hf;
end else begin
state <= 4'hd;
end
end else if (_T_26) begin
if (io_tms) begin
state <= 4'he;
end else begin
state <= 4'hd;
end
end else if (_T_28) begin
if (io_tms) begin
state <= 4'hf;
end else begin
state <= 4'hb;
end
end else if (_T_30) begin
if (io_tms) begin
state <= 4'h2;
end else begin
state <= 4'h1;
end
end else begin
state <= 4'h0;
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
ir <= 5'h1;
end else if (jtag_reset) begin
ir <= 5'h1;
end else if (update_ir) begin
if (_T_34) begin
ir <= 5'h1f;
end else begin
ir <= sr[4:0];
end
end else begin
ir <= 5'h0;
end
end
always @(posedge io_tck or posedge reset) begin
if (reset) begin
_T_83 <= 1'h0;
end else begin
_T_83 <= sr[0];
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
_T_89 <= 1'h0;
end else begin
_T_89 <= _T_86 & sr[17];
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
dr <= 41'h0;
end else if (_T_98) begin
dr <= sr;
end else begin
dr <= _T_100;
end
end
endmodule
module dmi_jtag_to_core_sync(
input clock,
input reset,
input io_rd_en,
input io_wr_en,
output io_reg_en,
output io_reg_wr_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 26:18]
reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 27:18]
wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:24]
wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:22]
wire _T_12 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:24]
wire c_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 29:22]
assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 31:17]
assign io_reg_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 32:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rden = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wren = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
rden = 3'h0;
end
if (reset) begin
wren = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
rden <= 3'h0;
end else begin
rden <= {rden[1:0],io_rd_en};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wren <= 3'h0;
end else begin
wren <= {wren[1:0],io_wr_en};
end
end
endmodule
module dmi_wrapper(
input clock,
input reset,
input io_trst_n,
input io_tck,
input io_tms,
input io_tdi,
output io_tdo,
output io_tdoEnable,
input [31:0] io_jtag_id,
input [31:0] io_rd_data,
output [31:0] io_reg_wr_data,
output [6:0] io_reg_wr_addr,
output io_reg_en,
output io_reg_wr_en,
output io_dmi_hard_reset
);
wire i_jtag_tap_reset; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_trst; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tck; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tms; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tdi; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_dmi_hard_reset; // @[dmi_wrapper.scala 35:27]
wire [30:0] i_jtag_tap_io_jtag_id; // @[dmi_wrapper.scala 35:27]
wire [31:0] i_jtag_tap_io_rd_data; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tdo; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tdoEnable; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_wr_en; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_rd_en; // @[dmi_wrapper.scala 35:27]
wire [31:0] i_jtag_tap_io_wr_data; // @[dmi_wrapper.scala 35:27]
wire i_dmi_jtag_to_core_sync_clock; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_reset; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_rd_en; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_wr_en; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 56:39]
rvjtag_tap i_jtag_tap ( // @[dmi_wrapper.scala 35:27]
.reset(i_jtag_tap_reset),
.io_trst(i_jtag_tap_io_trst),
.io_tck(i_jtag_tap_io_tck),
.io_tms(i_jtag_tap_io_tms),
.io_tdi(i_jtag_tap_io_tdi),
.io_dmi_hard_reset(i_jtag_tap_io_dmi_hard_reset),
.io_jtag_id(i_jtag_tap_io_jtag_id),
.io_rd_data(i_jtag_tap_io_rd_data),
.io_tdo(i_jtag_tap_io_tdo),
.io_tdoEnable(i_jtag_tap_io_tdoEnable),
.io_wr_en(i_jtag_tap_io_wr_en),
.io_rd_en(i_jtag_tap_io_rd_en),
.io_wr_data(i_jtag_tap_io_wr_data)
);
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync ( // @[dmi_wrapper.scala 56:39]
.clock(i_dmi_jtag_to_core_sync_clock),
.reset(i_dmi_jtag_to_core_sync_reset),
.io_rd_en(i_dmi_jtag_to_core_sync_io_rd_en),
.io_wr_en(i_dmi_jtag_to_core_sync_io_wr_en),
.io_reg_en(i_dmi_jtag_to_core_sync_io_reg_en),
.io_reg_wr_en(i_dmi_jtag_to_core_sync_io_reg_wr_en)
);
assign io_tdo = i_jtag_tap_io_tdo; // @[dmi_wrapper.scala 40:27]
assign io_tdoEnable = i_jtag_tap_io_tdoEnable; // @[dmi_wrapper.scala 41:27]
assign io_reg_wr_data = i_jtag_tap_io_wr_data; // @[dmi_wrapper.scala 42:27]
assign io_reg_wr_addr = 7'h0; // @[dmi_wrapper.scala 43:27]
assign io_reg_en = i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 59:16]
assign io_reg_wr_en = i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 60:16]
assign io_dmi_hard_reset = i_jtag_tap_io_dmi_hard_reset; // @[dmi_wrapper.scala 52:27]
assign i_jtag_tap_reset = reset;
assign i_jtag_tap_io_trst = io_trst_n; // @[dmi_wrapper.scala 36:27]
assign i_jtag_tap_io_tck = io_tck; // @[dmi_wrapper.scala 37:27]
assign i_jtag_tap_io_tms = io_tms; // @[dmi_wrapper.scala 38:27]
assign i_jtag_tap_io_tdi = io_tdi; // @[dmi_wrapper.scala 39:27]
assign i_jtag_tap_io_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 51:27]
assign i_jtag_tap_io_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:27]
assign i_dmi_jtag_to_core_sync_clock = clock;
assign i_dmi_jtag_to_core_sync_reset = reset;
assign i_dmi_jtag_to_core_sync_io_rd_en = i_jtag_tap_io_rd_en; // @[dmi_wrapper.scala 58:36]
assign i_dmi_jtag_to_core_sync_io_wr_en = i_jtag_tap_io_wr_en; // @[dmi_wrapper.scala 57:36]
endmodule

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el2_dbg.anno.json
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@ -1,51 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"sources":[
"~el2_dbg|el2_dbg>io_dma_dbg_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
"~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only",
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"~el2_dbg|el2_dbg>io_core_dbg_cmd_done",
"~el2_dbg|el2_dbg>io_dmi_reg_wr_en",
"~el2_dbg|el2_dbg>io_dmi_reg_en",
"~el2_dbg|el2_dbg>io_dma_dbg_ready",
"~el2_dbg|el2_dbg>io_dmi_reg_addr",
"~el2_dbg|el2_dbg>reset"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dbg.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dbg"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_dbg.fir
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el2_dbg.v
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el2_dec.anno.json
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el2_dec.fir
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el2_dec.v
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el2_dec_dec_ctl.anno.json
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@ -1,368 +0,0 @@
[
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]
},
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]
},
{
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]
},
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"sources":[
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]
},
{
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]
},
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},
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]
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{
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]
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]
},
{
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"sources":[
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]
},
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]
},
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"sources":[
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]
},
{
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]
},
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}
]

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el2_dec_dec_ctl.fir
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el2_dec_dec_ctl.v
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@ -1,704 +0,0 @@
module el2_dec_dec_ctl(
input clock,
input reset,
input [31:0] io_ins,
output io_out_alu,
output io_out_rs1,
output io_out_rs2,
output io_out_imm12,
output io_out_rd,
output io_out_shimm5,
output io_out_imm20,
output io_out_pc,
output io_out_load,
output io_out_store,
output io_out_lsu,
output io_out_add,
output io_out_sub,
output io_out_land,
output io_out_lor,
output io_out_lxor,
output io_out_sll,
output io_out_sra,
output io_out_srl,
output io_out_slt,
output io_out_unsign,
output io_out_condbr,
output io_out_beq,
output io_out_bne,
output io_out_bge,
output io_out_blt,
output io_out_jal,
output io_out_by,
output io_out_half,
output io_out_word,
output io_out_csr_read,
output io_out_csr_clr,
output io_out_csr_set,
output io_out_csr_write,
output io_out_csr_imm,
output io_out_presync,
output io_out_postsync,
output io_out_ebreak,
output io_out_ecall,
output io_out_mret,
output io_out_mul,
output io_out_rs1_sign,
output io_out_rs2_sign,
output io_out_low,
output io_out_div,
output io_out_rem,
output io_out_fence,
output io_out_fence_i,
output io_out_pm_alu,
output io_out_legal
);
wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27]
wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42]
wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53]
wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39]
wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68]
wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78]
wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51]
wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51]
wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90]
wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90]
wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55]
wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37]
wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37]
wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94]
wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76]
wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76]
wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41]
wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38]
wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38]
wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80]
wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76]
wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76]
wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42]
wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37]
wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37]
wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80]
wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75]
wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75]
wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41]
wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37]
wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37]
wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79]
wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75]
wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75]
wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41]
wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37]
wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37]
wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79]
wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71]
wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41]
wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106]
wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48]
wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48]
wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85]
wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85]
wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50]
wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90]
wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90]
wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90]
wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54]
wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40]
wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40]
wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40]
wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94]
wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81]
wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81]
wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81]
wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28]
wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55]
wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42]
wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58]
wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58]
wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58]
wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29]
wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53]
wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28]
wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41]
wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50]
wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49]
wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57]
wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57]
wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57]
wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61]
wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61]
wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109]
wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80]
wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80]
wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45]
wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94]
wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94]
wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94]
wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49]
wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34]
wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34]
wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98]
wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38]
wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44]
wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44]
wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44]
wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59]
wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59]
wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59]
wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99]
wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99]
wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99]
wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63]
wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37]
wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37]
wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103]
wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86]
wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41]
wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56]
wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56]
wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56]
wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55]
wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55]
wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55]
wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54]
wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54]
wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54]
wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55]
wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55]
wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55]
wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56]
wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56]
wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53]
wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53]
wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50]
wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52]
wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87]
wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87]
wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56]
wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34]
wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34]
wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91]
wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69]
wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69]
wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38]
wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105]
wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105]
wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73]
wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35]
wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35]
wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57]
wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57]
wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57]
wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99]
wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99]
wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99]
wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61]
wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41]
wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41]
wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41]
wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103]
wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81]
wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81]
wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81]
wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45]
wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39]
wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39]
wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39]
wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57]
wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55]
wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55]
wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94]
wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94]
wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94]
wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59]
wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38]
wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38]
wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38]
wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98]
wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77]
wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77]
wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77]
wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42]
wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38]
wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38]
wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38]
wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81]
wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77]
wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77]
wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77]
wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55]
wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55]
wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55]
wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95]
wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95]
wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95]
wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59]
wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39]
wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39]
wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39]
wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99]
wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43]
wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56]
wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56]
wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56]
wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62]
wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62]
wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62]
wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54]
wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54]
wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57]
wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57]
wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57]
wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47]
wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52]
wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52]
wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63]
wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37]
wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37]
wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96]
wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88]
wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88]
wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53]
wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38]
wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38]
wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92]
wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77]
wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77]
wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42]
wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81]
wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78]
wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78]
wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42]
wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39]
wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39]
wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82]
wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78]
wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78]
wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43]
wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38]
wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38]
wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82]
wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77]
wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77]
wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42]
wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38]
wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38]
wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38]
wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81]
wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77]
wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77]
wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57]
wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102]
wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42]
wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81]
wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42]
wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82]
wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43]
wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82]
wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42]
wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81]
wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148]
wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134]
wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131]
wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72]
wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81]
wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78]
wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70]
wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58]
wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52]
wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51]
wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103]
wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51]
wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146]
wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114]
wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55]
wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99]
wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50]
wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43]
assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14]
assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14]
assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14]
assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16]
assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13]
assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17]
assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16]
assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13]
assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15]
assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16]
assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14]
assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14]
assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14]
assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15]
assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14]
assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15]
assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14]
assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14]
assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14]
assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14]
assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17]
assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17]
assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14]
assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14]
assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14]
assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14]
assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14]
assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13]
assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15]
assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15]
assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19]
assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18]
assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18]
assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20]
assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18]
assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18]
assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19]
assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17]
assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16]
assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15]
assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14]
assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19]
assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19]
assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14]
assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14]
assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14]
assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16]
assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18]
assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17]
assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16]
endmodule

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el2_dec_gpr_ctl.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd1",
"sources":[
"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd0",
"sources":[
"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr0"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dec_gpr_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_gpr_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_dec_gpr_ctl.v
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183
el2_dec_ib_ctl.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_wdata_rs1_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid"
]
},
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71
el2_dec_ib_ctl.fir
View File

@ -1,71 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_dec_ib_ctl :
module el2_dec_ib_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31]
io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31]
io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31]
io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31]
io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31]
io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31]
io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31]
io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31]
io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31]
io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31]
node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60]
node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41]
node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38]
node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36]
node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36]
node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55]
node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37]
node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55]
node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37]
node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55]
node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37]
node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55]
node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37]
node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40]
node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40]
node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20]
node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21]
node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20]
node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21]
node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
ib0_debug_in <= _T_23 @[Mux.scala 27:72]
node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47]
io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28]
node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51]
node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43]
io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24]
node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41]
io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22]
node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41]
node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28]
io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22]

98
el2_dec_ib_ctl.v
View File

@ -1,98 +0,0 @@
module el2_dec_ib_ctl(
input clock,
input reset,
input io_dbg_cmd_valid,
input io_dbg_cmd_write,
input [1:0] io_dbg_cmd_type,
input [31:0] io_dbg_cmd_addr,
input io_i0_brp_valid,
input [11:0] io_i0_brp_toffset,
input [1:0] io_i0_brp_hist,
input io_i0_brp_br_error,
input io_i0_brp_br_start_error,
input io_i0_brp_bank,
input [30:0] io_i0_brp_prett,
input io_i0_brp_way,
input io_i0_brp_ret,
input [7:0] io_ifu_i0_bp_index,
input [7:0] io_ifu_i0_bp_fghr,
input [4:0] io_ifu_i0_bp_btag,
input io_ifu_i0_pc4,
input io_ifu_i0_valid,
input io_ifu_i0_icaf,
input [1:0] io_ifu_i0_icaf_type,
input io_ifu_i0_icaf_f1,
input io_ifu_i0_dbecc,
input [31:0] io_ifu_i0_instr,
input [30:0] io_ifu_i0_pc,
output io_dec_ib0_valid_d,
output [1:0] io_dec_i0_icaf_type_d,
output [31:0] io_dec_i0_instr_d,
output [30:0] io_dec_i0_pc_d,
output io_dec_i0_pc4_d,
output io_dec_i0_brp_valid,
output [11:0] io_dec_i0_brp_toffset,
output [1:0] io_dec_i0_brp_hist,
output io_dec_i0_brp_br_error,
output io_dec_i0_brp_br_start_error,
output io_dec_i0_brp_bank,
output [30:0] io_dec_i0_brp_prett,
output io_dec_i0_brp_way,
output io_dec_i0_brp_ret,
output [7:0] io_dec_i0_bp_index,
output [7:0] io_dec_i0_bp_fghr,
output [4:0] io_dec_i0_bp_btag,
output io_dec_i0_icaf_d,
output io_dec_i0_icaf_f1_d,
output io_dec_i0_dbecc_d,
output io_dec_debug_wdata_rs1_d,
output io_dec_debug_fence_d
);
wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60]
wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41]
wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38]
wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36]
wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36]
wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55]
wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37]
wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37]
wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55]
wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37]
wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37]
wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40]
wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40]
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58]
wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58]
wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58]
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72]
wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51]
assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22]
assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31]
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22]
assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31]
assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 47:31]
assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_bank = io_i0_brp_bank; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 49:31]
assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31]
assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31]
assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31]
assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31]
assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31]
assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31]
assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28]
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24]
endmodule

508
el2_dec_tlu_ctl.anno.json
View File

@ -1,508 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_hist",
"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
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]
},
{
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d",
"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
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]
},
{
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt1",
"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d",
"sources":[
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint",
"sources":[
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_middle",
"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
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"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_way",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt0",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_err_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_commit_cmt",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_valid",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_mp_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_pmu_i0_br_ataken"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dec_tlu_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_tlu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

8034
el2_dec_tlu_ctl.fir
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7181
el2_dec_tlu_ctl.v
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45
el2_dec_trigger.anno.json
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@ -1,45 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_trigger_match_d",
"sources":[
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_",
"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_trigger"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1457
el2_dec_trigger.fir
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613
el2_dec_trigger.v
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@ -1,613 +0,0 @@
module el2_dec_trigger(
input clock,
input reset,
input io_trigger_pkt_any_0_select,
input io_trigger_pkt_any_0_match_,
input io_trigger_pkt_any_0_store,
input io_trigger_pkt_any_0_load,
input io_trigger_pkt_any_0_execute,
input io_trigger_pkt_any_0_m,
input [31:0] io_trigger_pkt_any_0_tdata2,
input io_trigger_pkt_any_1_select,
input io_trigger_pkt_any_1_match_,
input io_trigger_pkt_any_1_store,
input io_trigger_pkt_any_1_load,
input io_trigger_pkt_any_1_execute,
input io_trigger_pkt_any_1_m,
input [31:0] io_trigger_pkt_any_1_tdata2,
input io_trigger_pkt_any_2_select,
input io_trigger_pkt_any_2_match_,
input io_trigger_pkt_any_2_store,
input io_trigger_pkt_any_2_load,
input io_trigger_pkt_any_2_execute,
input io_trigger_pkt_any_2_m,
input [31:0] io_trigger_pkt_any_2_tdata2,
input io_trigger_pkt_any_3_select,
input io_trigger_pkt_any_3_match_,
input io_trigger_pkt_any_3_store,
input io_trigger_pkt_any_3_load,
input io_trigger_pkt_any_3_execute,
input io_trigger_pkt_any_3_m,
input [31:0] io_trigger_pkt_any_3_tdata2,
input [30:0] io_dec_i0_pc_d,
output [3:0] io_dec_i0_trigger_match_d
);
wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63]
wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127]
wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63]
wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127]
wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63]
wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127]
wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63]
wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127]
wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83]
wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 232:45]
wire _T_152 = ~_T_151; // @[el2_lib.scala 232:39]
wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 232:37]
wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 233:52]
wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 233:41]
wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 235:36]
wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 235:41]
wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 235:78]
wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 235:23]
wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 235:36]
wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 235:41]
wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 235:78]
wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 235:23]
wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 235:36]
wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 235:41]
wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 235:78]
wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 235:23]
wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 235:36]
wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 235:41]
wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 235:78]
wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 235:23]
wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 235:36]
wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 235:41]
wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 235:78]
wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 235:23]
wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 235:36]
wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 235:41]
wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 235:78]
wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 235:23]
wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 235:36]
wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 235:41]
wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 235:78]
wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 235:23]
wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 235:36]
wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 235:41]
wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 235:78]
wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 235:23]
wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 235:36]
wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 235:41]
wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 235:78]
wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 235:23]
wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 235:36]
wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 235:41]
wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 235:78]
wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 235:23]
wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 235:36]
wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 235:41]
wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 235:78]
wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 235:23]
wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 235:36]
wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 235:41]
wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 235:78]
wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 235:23]
wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 235:36]
wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 235:41]
wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 235:78]
wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 235:23]
wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 235:36]
wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 235:41]
wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 235:78]
wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 235:23]
wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 235:36]
wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 235:41]
wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 235:78]
wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 235:23]
wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 235:36]
wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 235:41]
wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 235:78]
wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 235:23]
wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 235:36]
wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 235:41]
wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 235:78]
wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 235:23]
wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 235:36]
wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 235:41]
wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 235:78]
wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 235:23]
wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 235:36]
wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 235:41]
wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 235:78]
wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 235:23]
wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 235:36]
wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 235:41]
wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 235:78]
wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 235:23]
wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 235:36]
wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 235:41]
wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 235:78]
wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 235:23]
wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 235:36]
wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 235:41]
wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 235:78]
wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 235:23]
wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 235:36]
wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 235:41]
wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 235:78]
wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 235:23]
wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 235:36]
wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 235:41]
wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 235:78]
wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 235:23]
wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 235:36]
wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 235:41]
wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 235:78]
wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 235:23]
wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 235:36]
wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 235:41]
wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 235:78]
wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 235:23]
wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 235:36]
wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 235:41]
wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 235:78]
wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 235:23]
wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 235:36]
wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 235:41]
wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 235:78]
wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 235:23]
wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 235:36]
wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 235:41]
wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 235:78]
wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 235:23]
wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 235:36]
wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 235:41]
wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 235:78]
wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 235:23]
wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 235:36]
wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 235:41]
wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 235:78]
wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 235:23]
wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 236:14]
wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 236:14]
wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 236:14]
wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 236:14]
wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109]
wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83]
wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 232:45]
wire _T_411 = ~_T_410; // @[el2_lib.scala 232:39]
wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 232:37]
wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 233:52]
wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 233:41]
wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 235:36]
wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 235:41]
wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 235:78]
wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 235:23]
wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 235:36]
wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 235:41]
wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 235:78]
wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 235:23]
wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 235:36]
wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 235:41]
wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 235:78]
wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 235:23]
wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 235:36]
wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 235:41]
wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 235:78]
wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 235:23]
wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 235:36]
wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 235:41]
wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 235:78]
wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 235:23]
wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 235:36]
wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 235:41]
wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 235:78]
wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 235:23]
wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 235:36]
wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 235:41]
wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 235:78]
wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 235:23]
wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 235:36]
wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 235:41]
wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 235:78]
wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 235:23]
wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 235:36]
wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 235:41]
wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 235:78]
wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 235:23]
wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 235:36]
wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 235:41]
wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 235:78]
wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 235:23]
wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 235:36]
wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 235:41]
wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 235:78]
wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 235:23]
wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 235:36]
wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 235:41]
wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 235:78]
wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 235:23]
wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 235:36]
wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 235:41]
wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 235:78]
wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 235:23]
wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 235:36]
wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 235:41]
wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 235:78]
wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 235:23]
wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 235:36]
wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 235:41]
wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 235:78]
wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 235:23]
wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 235:36]
wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 235:41]
wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 235:78]
wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 235:23]
wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 235:36]
wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 235:41]
wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 235:78]
wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 235:23]
wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 235:36]
wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 235:41]
wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 235:78]
wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 235:23]
wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 235:36]
wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 235:41]
wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 235:78]
wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 235:23]
wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 235:36]
wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 235:41]
wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 235:78]
wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 235:23]
wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 235:36]
wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 235:41]
wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 235:78]
wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 235:23]
wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 235:36]
wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 235:41]
wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 235:78]
wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 235:23]
wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 235:36]
wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 235:41]
wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 235:78]
wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 235:23]
wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 235:36]
wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 235:41]
wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 235:78]
wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 235:23]
wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 235:36]
wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 235:41]
wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 235:78]
wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 235:23]
wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 235:36]
wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 235:41]
wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 235:78]
wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 235:23]
wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 235:36]
wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 235:41]
wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 235:78]
wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 235:23]
wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 235:36]
wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 235:41]
wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 235:78]
wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 235:23]
wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 235:36]
wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 235:41]
wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 235:78]
wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 235:23]
wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 235:36]
wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 235:41]
wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 235:78]
wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 235:23]
wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 235:36]
wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 235:41]
wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 235:78]
wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 235:23]
wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 236:14]
wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 236:14]
wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 236:14]
wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 236:14]
wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109]
wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83]
wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 232:45]
wire _T_670 = ~_T_669; // @[el2_lib.scala 232:39]
wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 232:37]
wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 233:52]
wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 233:41]
wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 235:36]
wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 235:41]
wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 235:78]
wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 235:23]
wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 235:36]
wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 235:41]
wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 235:78]
wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 235:23]
wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 235:36]
wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 235:41]
wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 235:78]
wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 235:23]
wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 235:36]
wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 235:41]
wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 235:78]
wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 235:23]
wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 235:36]
wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 235:41]
wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 235:78]
wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 235:23]
wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 235:36]
wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 235:41]
wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 235:78]
wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 235:23]
wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 235:36]
wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 235:41]
wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 235:78]
wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 235:23]
wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 235:36]
wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 235:41]
wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 235:78]
wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 235:23]
wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 235:36]
wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 235:41]
wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 235:78]
wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 235:23]
wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 235:36]
wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 235:41]
wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 235:78]
wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 235:23]
wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 235:36]
wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 235:41]
wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 235:78]
wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 235:23]
wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 235:36]
wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 235:41]
wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 235:78]
wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 235:23]
wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 235:36]
wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 235:41]
wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 235:78]
wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 235:23]
wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 235:36]
wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 235:41]
wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 235:78]
wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 235:23]
wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 235:36]
wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 235:41]
wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 235:78]
wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 235:23]
wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 235:36]
wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 235:41]
wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 235:78]
wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 235:23]
wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 235:36]
wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 235:41]
wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 235:78]
wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 235:23]
wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 235:36]
wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 235:41]
wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 235:78]
wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 235:23]
wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 235:36]
wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 235:41]
wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 235:78]
wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 235:23]
wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 235:36]
wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 235:41]
wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 235:78]
wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 235:23]
wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 235:36]
wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 235:41]
wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 235:78]
wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 235:23]
wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 235:36]
wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 235:41]
wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 235:78]
wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 235:23]
wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 235:36]
wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 235:41]
wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 235:78]
wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 235:23]
wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 235:36]
wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 235:41]
wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 235:78]
wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 235:23]
wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 235:36]
wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 235:41]
wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 235:78]
wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 235:23]
wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 235:36]
wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 235:41]
wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 235:78]
wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 235:23]
wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 235:36]
wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 235:41]
wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 235:78]
wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 235:23]
wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 235:36]
wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 235:41]
wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 235:78]
wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 235:23]
wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 235:36]
wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 235:41]
wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 235:78]
wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 235:23]
wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 235:36]
wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 235:41]
wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 235:78]
wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 235:23]
wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 235:36]
wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 235:41]
wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 235:78]
wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 235:23]
wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 236:14]
wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 236:14]
wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 236:14]
wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 236:14]
wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109]
wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83]
wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 232:45]
wire _T_929 = ~_T_928; // @[el2_lib.scala 232:39]
wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 232:37]
wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 233:52]
wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 233:41]
wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 235:36]
wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 235:41]
wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 235:78]
wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 235:23]
wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 235:36]
wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 235:41]
wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 235:78]
wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 235:23]
wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 235:36]
wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 235:41]
wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 235:78]
wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 235:23]
wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 235:36]
wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 235:41]
wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 235:78]
wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 235:23]
wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 235:36]
wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 235:41]
wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 235:78]
wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 235:23]
wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 235:36]
wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 235:41]
wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 235:78]
wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 235:23]
wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 235:36]
wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 235:41]
wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 235:78]
wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 235:23]
wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 235:36]
wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 235:41]
wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 235:78]
wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 235:23]
wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 235:36]
wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 235:41]
wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 235:78]
wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 235:23]
wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 235:36]
wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 235:78]
wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 235:23]
wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 235:36]
wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 235:78]
wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 235:23]
wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 235:36]
wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 235:78]
wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 235:23]
wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 235:36]
wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 235:78]
wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 235:23]
wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 235:36]
wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 235:78]
wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 235:23]
wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 235:36]
wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 235:78]
wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 235:23]
wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 235:36]
wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 235:78]
wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 235:23]
wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 235:36]
wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 235:78]
wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 235:23]
wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 235:36]
wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 235:78]
wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 235:23]
wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 235:36]
wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 235:78]
wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 235:23]
wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 235:36]
wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 235:78]
wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 235:23]
wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 235:36]
wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 235:78]
wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 235:23]
wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 235:36]
wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 235:78]
wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 235:23]
wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 235:36]
wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 235:78]
wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 235:23]
wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 235:36]
wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 235:78]
wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 235:23]
wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 235:36]
wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 235:78]
wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 235:23]
wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 235:36]
wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 235:78]
wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 235:23]
wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 235:36]
wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 235:78]
wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 235:23]
wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 235:36]
wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 235:78]
wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 235:23]
wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 235:36]
wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 235:78]
wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 235:23]
wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 235:36]
wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 235:78]
wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 235:23]
wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 235:36]
wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 235:41]
wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 235:78]
wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 235:23]
wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 236:14]
wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 236:14]
wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 236:14]
wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 236:14]
wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109]
wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58]
assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29]
endmodule

115
el2_dma_ctrl.anno.json
View File

@ -1,115 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dma_ctrl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dma_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_dma_ctrl.fir
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el2_dma_ctrl.v
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el2_exu.anno.json
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@ -1,131 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_div_wren",
"sources":[
"~el2_exu|el2_exu>io_dec_div_cancel"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_mp_fghr",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_lsu_rs1_d",
"sources":[
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"~el2_exu|el2_exu>io_dec_extint_stall",
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"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d"
]
},
{
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"sink":"~el2_exu|el2_exu>io_exu_flush_final",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
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},
{
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},
{
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},
{
"class":"firrtl.options.TargetDirAnnotation",
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{
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},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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}
]

3670
el2_exu.fir
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2605
el2_exu.v
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250
el2_exu_alu_ctl.anno.json
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@ -1,250 +0,0 @@
[
{
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},
{
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},
{
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]
},
{
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},
{
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},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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},
{
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]
},
{
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]
},
{
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},
{
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},
{
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pja",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_alu_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_alu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

568
el2_exu_alu_ctl.fir
View File

@ -1,568 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu_alu_ctl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
module el2_exu_alu_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}
node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 485:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18]
rvclkhdr.io.en <= io.enable @[el2_lib.scala 488:17]
rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 489:24]
reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16]
_T_1 <= io.pc_in @[el2_lib.scala 491:16]
io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12]
wire result : UInt<32>
result <= UInt<1>("h00")
node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 485:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18]
rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 488:17]
rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 489:24]
reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16]
_T_3 <= result @[el2_lib.scala 491:16]
io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16]
node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29]
node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37]
node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17]
wire aout : UInt<33>
aout <= UInt<1>("h00")
node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25]
node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58]
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70]
node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58]
node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55]
node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55]
node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80]
node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80]
node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58]
node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58]
node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58]
node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132]
node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132]
node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157]
node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157]
node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14]
aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8]
node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18]
node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22]
node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14]
node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32]
node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29]
node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27]
node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44]
node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37]
node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61]
node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71]
node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66]
node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83]
node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78]
node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76]
node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50]
node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50]
node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38]
node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29]
node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34]
node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30]
node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51]
node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44]
node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78]
node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76]
node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58]
node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29]
node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19]
node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50]
node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16]
node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50]
node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39]
node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39]
node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15]
node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50]
node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39]
node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39]
node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16]
node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50]
node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39]
node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39]
wire _T_58 : SInt<32> @[Mux.scala 27:72]
node _T_59 = asUInt(_T_45) @[Mux.scala 27:72]
node _T_60 = asSInt(_T_59) @[Mux.scala 27:72]
_T_58 <= _T_60 @[Mux.scala 27:72]
wire _T_61 : SInt<32> @[Mux.scala 27:72]
node _T_62 = asUInt(_T_49) @[Mux.scala 27:72]
node _T_63 = asSInt(_T_62) @[Mux.scala 27:72]
_T_61 <= _T_63 @[Mux.scala 27:72]
wire _T_64 : SInt<32> @[Mux.scala 27:72]
node _T_65 = asUInt(_T_53) @[Mux.scala 27:72]
node _T_66 = asSInt(_T_65) @[Mux.scala 27:72]
_T_64 <= _T_66 @[Mux.scala 27:72]
wire _T_67 : SInt<32> @[Mux.scala 27:72]
node _T_68 = asUInt(_T_57) @[Mux.scala 27:72]
node _T_69 = asSInt(_T_68) @[Mux.scala 27:72]
_T_67 <= _T_69 @[Mux.scala 27:72]
node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72]
node _T_75 = asSInt(_T_74) @[Mux.scala 27:72]
node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72]
node _T_77 = asSInt(_T_76) @[Mux.scala 27:72]
node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72]
node _T_79 = asSInt(_T_78) @[Mux.scala 27:72]
wire lout : SInt<32> @[Mux.scala 27:72]
node _T_80 = asUInt(_T_79) @[Mux.scala 27:72]
node _T_81 = asSInt(_T_80) @[Mux.scala 27:72]
lout <= _T_81 @[Mux.scala 27:72]
node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15]
node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60]
node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58]
node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38]
node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38]
node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15]
node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60]
node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58]
node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15]
node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60]
node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58]
node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72]
wire shift_amount : UInt<6> @[Mux.scala 27:72]
shift_amount <= _T_97 @[Mux.scala 27:72]
wire shift_mask : UInt<32>
shift_mask <= UInt<1>("h00")
wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48]
_T_98[0] <= io.ap.sll @[el2_lib.scala 161:48]
_T_98[1] <= io.ap.sll @[el2_lib.scala 161:48]
_T_98[2] <= io.ap.sll @[el2_lib.scala 161:48]
_T_98[3] <= io.ap.sll @[el2_lib.scala 161:48]
_T_98[4] <= io.ap.sll @[el2_lib.scala 161:48]
node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58]
node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58]
node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58]
node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58]
node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70]
node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61]
node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39]
shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14]
wire shift_extend : UInt<63>
shift_extend <= UInt<1>("h00")
wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48]
_T_106[0] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[1] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[2] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[3] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[4] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[5] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[6] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[7] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[8] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[9] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[10] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[11] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[12] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[13] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[14] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[15] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[16] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[17] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[18] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[19] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[20] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[21] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[22] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[23] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[24] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[25] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[26] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[27] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[28] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[29] <= io.ap.sra @[el2_lib.scala 161:48]
_T_106[30] <= io.ap.sra @[el2_lib.scala 161:48]
node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58]
node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58]
node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58]
node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58]
node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58]
node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58]
node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58]
node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58]
node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58]
node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58]
node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58]
node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58]
node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58]
node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58]
node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58]
node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58]
node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58]
node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58]
node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58]
node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58]
node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58]
node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58]
node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58]
node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58]
node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58]
node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58]
node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58]
node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58]
node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58]
node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58]
node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61]
wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48]
_T_138[0] <= _T_137 @[el2_lib.scala 161:48]
_T_138[1] <= _T_137 @[el2_lib.scala 161:48]
_T_138[2] <= _T_137 @[el2_lib.scala 161:48]
_T_138[3] <= _T_137 @[el2_lib.scala 161:48]
_T_138[4] <= _T_137 @[el2_lib.scala 161:48]
_T_138[5] <= _T_137 @[el2_lib.scala 161:48]
_T_138[6] <= _T_137 @[el2_lib.scala 161:48]
_T_138[7] <= _T_137 @[el2_lib.scala 161:48]
_T_138[8] <= _T_137 @[el2_lib.scala 161:48]
_T_138[9] <= _T_137 @[el2_lib.scala 161:48]
_T_138[10] <= _T_137 @[el2_lib.scala 161:48]
_T_138[11] <= _T_137 @[el2_lib.scala 161:48]
_T_138[12] <= _T_137 @[el2_lib.scala 161:48]
_T_138[13] <= _T_137 @[el2_lib.scala 161:48]
_T_138[14] <= _T_137 @[el2_lib.scala 161:48]
_T_138[15] <= _T_137 @[el2_lib.scala 161:48]
_T_138[16] <= _T_137 @[el2_lib.scala 161:48]
_T_138[17] <= _T_137 @[el2_lib.scala 161:48]
_T_138[18] <= _T_137 @[el2_lib.scala 161:48]
_T_138[19] <= _T_137 @[el2_lib.scala 161:48]
_T_138[20] <= _T_137 @[el2_lib.scala 161:48]
_T_138[21] <= _T_137 @[el2_lib.scala 161:48]
_T_138[22] <= _T_137 @[el2_lib.scala 161:48]
_T_138[23] <= _T_137 @[el2_lib.scala 161:48]
_T_138[24] <= _T_137 @[el2_lib.scala 161:48]
_T_138[25] <= _T_137 @[el2_lib.scala 161:48]
_T_138[26] <= _T_137 @[el2_lib.scala 161:48]
_T_138[27] <= _T_137 @[el2_lib.scala 161:48]
_T_138[28] <= _T_137 @[el2_lib.scala 161:48]
_T_138[29] <= _T_137 @[el2_lib.scala 161:48]
_T_138[30] <= _T_137 @[el2_lib.scala 161:48]
node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58]
node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58]
node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58]
node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58]
node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58]
node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58]
node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58]
node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58]
node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58]
node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58]
node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58]
node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58]
node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58]
node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58]
node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58]
node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58]
node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58]
node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58]
node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58]
node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58]
node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58]
node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58]
node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58]
node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58]
node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58]
node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58]
node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58]
node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58]
node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58]
node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58]
node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44]
wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48]
_T_170[0] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[1] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[2] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[3] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[4] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[5] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[6] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[7] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[8] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[9] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[10] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[11] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[12] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[13] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[14] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[15] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[16] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[17] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[18] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[19] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[20] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[21] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[22] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[23] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[24] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[25] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[26] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[27] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[28] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[29] <= io.ap.sll @[el2_lib.scala 161:48]
_T_170[30] <= io.ap.sll @[el2_lib.scala 161:48]
node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58]
node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58]
node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58]
node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58]
node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58]
node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58]
node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58]
node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58]
node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58]
node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58]
node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58]
node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58]
node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58]
node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58]
node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58]
node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58]
node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58]
node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58]
node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58]
node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58]
node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58]
node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58]
node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58]
node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58]
node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58]
node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58]
node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58]
node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58]
node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58]
node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58]
node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99]
node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90]
node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68]
node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58]
node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58]
shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16]
wire shift_long : UInt<63>
shift_long <= UInt<1>("h00")
node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47]
node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32]
shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14]
node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27]
node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46]
node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34]
node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41]
node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53]
node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41]
node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56]
node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54]
node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41]
node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58]
node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73]
node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47]
node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63]
node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32]
node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40]
node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 206:24]
node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 206:40]
node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 206:31]
node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 207:20]
node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 207:27]
node _T_224 = tail(_T_223, 1) @[el2_lib.scala 207:27]
node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 208:20]
node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 208:27]
node _T_227 = tail(_T_226, 1) @[el2_lib.scala 208:27]
node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 209:22]
node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 210:39]
node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 210:28]
node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 210:26]
node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 210:64]
node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 210:76]
node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 211:20]
node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 211:39]
node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 211:26]
node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 211:64]
node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39]
node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 212:28]
node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 212:26]
node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 212:64]
node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72]
node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72]
wire _T_247 : UInt<19> @[Mux.scala 27:72]
_T_247 <= _T_246 @[Mux.scala 27:72]
node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 212:94]
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24]
node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58]
node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31]
node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15]
node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41]
node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15]
node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41]
node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12]
node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21]
node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51]
node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72]
node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72]
node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72]
wire _T_267 : UInt<32> @[Mux.scala 27:72]
_T_267 <= _T_266 @[Mux.scala 27:72]
node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56]
result <= _T_268 @[el2_exu_alu_ctl.scala 88:16]
node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45]
node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20]
node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20]
node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40]
node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59]
node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46]
node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85]
node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72]
node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104]
node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91]
node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110]
node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42]
node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63]
node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61]
node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79]
node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77]
node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104]
node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123]
node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141]
node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139]
node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89]
io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26]
node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37]
node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49]
node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62]
node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28]
io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22]
node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47]
node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45]
node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82]
node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62]
node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70]
node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62]
node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44]
node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42]
node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60]
node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81]
node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97]
node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95]
node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119]
node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117]
io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26]
node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42]
node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60]
node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81]
node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97]
node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95]
node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117]
io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26]
wire newhist : UInt<2>
newhist <= UInt<1>("h00")
node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35]
node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55]
node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39]
node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77]
node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63]
node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81]
node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60]
node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20]
node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6]
node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26]
node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24]
node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58]
node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62]
node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42]
node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14]
io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30]
node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33]
node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53]
node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51]
node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90]
node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71]
io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30]
io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30]
io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30]

347
el2_exu_alu_ctl.v
View File

@ -1,347 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 465:26]
wire clkhdr_CK; // @[el2_lib.scala 465:26]
wire clkhdr_EN; // @[el2_lib.scala 465:26]
wire clkhdr_SE; // @[el2_lib.scala 465:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18]
endmodule
module el2_exu_alu_ctl(
input clock,
input reset,
input io_scan_mode,
input io_flush_upper_x,
input io_flush_lower_r,
input io_enable,
input io_valid_in,
input io_ap_land,
input io_ap_lor,
input io_ap_lxor,
input io_ap_sll,
input io_ap_srl,
input io_ap_sra,
input io_ap_beq,
input io_ap_bne,
input io_ap_blt,
input io_ap_bge,
input io_ap_add,
input io_ap_sub,
input io_ap_slt,
input io_ap_unsign,
input io_ap_jal,
input io_ap_predict_t,
input io_ap_predict_nt,
input io_ap_csr_write,
input io_ap_csr_imm,
input io_csr_ren_in,
input [31:0] io_a_in,
input [31:0] io_b_in,
input [30:0] io_pc_in,
input io_pp_in_misp,
input io_pp_in_ataken,
input io_pp_in_boffset,
input io_pp_in_pc4,
input [1:0] io_pp_in_hist,
input [11:0] io_pp_in_toffset,
input io_pp_in_valid,
input io_pp_in_br_error,
input io_pp_in_br_start_error,
input [30:0] io_pp_in_prett,
input io_pp_in_pcall,
input io_pp_in_pret,
input io_pp_in_pja,
input io_pp_in_way,
input [11:0] io_brimm_in,
output [31:0] io_result_ff,
output io_flush_upper_out,
output io_flush_final_out,
output [30:0] io_flush_path_out,
output [30:0] io_pc_ff,
output io_pred_correct_out,
output io_predict_p_out_misp,
output io_predict_p_out_ataken,
output io_predict_p_out_boffset,
output io_predict_p_out_pc4,
output [1:0] io_predict_p_out_hist,
output [11:0] io_predict_p_out_toffset,
output io_predict_p_out_valid,
output io_predict_p_out_br_error,
output io_predict_p_out_br_start_error,
output [30:0] io_predict_p_out_prett,
output io_predict_p_out_pcall,
output io_predict_p_out_pret,
output io_predict_p_out_pja,
output io_predict_p_out_way
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 485:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23]
reg [30:0] _T_1; // @[el2_lib.scala 491:16]
reg [31:0] _T_3; // @[el2_lib.scala 491:16]
wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37]
wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58]
wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55]
wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58]
wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80]
wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132]
wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157]
wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14]
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18]
wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14]
wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29]
wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27]
wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37]
wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66]
wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78]
wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76]
wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50]
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38]
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29]
wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30]
wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51]
wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44]
wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78]
wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76]
wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58]
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29]
wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72]
wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72]
wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38]
wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72]
wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61]
wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39]
wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44]
wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90]
wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68]
wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58]
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32]
wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34]
wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41]
wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53]
wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41]
wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56]
wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54]
wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41]
wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58]
wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73]
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40]
wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 206:31]
wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 207:27]
wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 208:27]
wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 210:28]
wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 210:26]
wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 211:20]
wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 211:26]
wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 212:26]
wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72]
wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24]
wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31]
wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51]
wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72]
wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72]
wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72]
wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40]
wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59]
wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46]
wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85]
wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72]
wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104]
wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91]
wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110]
wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42]
wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63]
wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61]
wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79]
wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77]
wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104]
wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123]
wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139]
wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45]
wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82]
wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62]
wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62]
wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44]
wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42]
wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60]
wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81]
wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97]
wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95]
wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119]
wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39]
wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63]
wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81]
wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60]
wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6]
wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24]
wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62]
wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42]
wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51]
wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16]
assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26]
assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22]
assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12]
assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26]
assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30]
assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30]
assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30]
assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18]
assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 488:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18]
assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 488:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1 = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
_T_3 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1 = 31'h0;
end
if (reset) begin
_T_3 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_1 <= 31'h0;
end else begin
_T_1 <= io_pc_in;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
_T_3 <= 32'h0;
end else begin
_T_3 <= _T_252 | _T_266;
end
end
endmodule

30
el2_exu_div_ctl.anno.json
View File

@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_ctl|el2_exu_div_ctl>io_finish_dly",
"sources":[
"~el2_exu_div_ctl|el2_exu_div_ctl>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_div_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_div_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1865
el2_exu_div_ctl.fir
View File

File diff suppressed because it is too large Load Diff

853
el2_exu_div_ctl.v
View File

@ -1,853 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 465:26]
wire clkhdr_CK; // @[el2_lib.scala 465:26]
wire clkhdr_EN; // @[el2_lib.scala 465:26]
wire clkhdr_SE; // @[el2_lib.scala 465:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18]
endmodule
module el2_exu_div_ctl(
input clock,
input reset,
input io_scan_mode,
input io_dp_valid,
input io_dp_unsign,
input io_dp_rem,
input [31:0] io_dividend,
input [31:0] io_divisor,
input io_cancel,
output [31:0] io_out,
output io_finish_dly
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 474:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 474:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 474:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 474:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23]
wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 54:30]
reg valid_ff_x; // @[el2_exu_div_ctl.scala 204:26]
wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 54:28]
reg [32:0] q_ff; // @[el2_lib.scala 491:16]
wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:34]
reg [32:0] m_ff; // @[el2_lib.scala 491:16]
wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:57]
wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 60:43]
wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 60:80]
wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 60:66]
reg rem_ff; // @[Reg.scala 27:20]
wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 60:91]
wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 60:89]
wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 60:99]
wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 61:18]
wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 61:27]
wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 61:50]
wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 61:60]
wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 60:110]
wire pat1 = q_ff[3]; // @[el2_exu_div_ctl.scala 64:57]
wire _T_22 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 65:69]
wire _T_24 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 65:69]
wire _T_26 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 65:69]
wire _T_27 = _T_22 & _T_24; // @[el2_exu_div_ctl.scala 65:94]
wire pat2 = _T_27 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_28 = pat1 & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_33 = pat1 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_35 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 72:32]
wire _T_36 = _T_33 & _T_35; // @[el2_exu_div_ctl.scala 72:30]
wire pat1_2 = q_ff[2]; // @[el2_exu_div_ctl.scala 64:57]
wire _T_44 = pat1_2 & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_45 = _T_36 | _T_44; // @[el2_exu_div_ctl.scala 72:41]
wire pat1_3 = pat1 & pat1_2; // @[el2_exu_div_ctl.scala 64:94]
wire _T_52 = pat1_3 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_53 = _T_45 | _T_52; // @[el2_exu_div_ctl.scala 72:73]
wire _T_58 = pat1_2 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_61 = _T_58 & _T_35; // @[el2_exu_div_ctl.scala 74:30]
wire pat1_5 = q_ff[1]; // @[el2_exu_div_ctl.scala 64:57]
wire _T_69 = pat1_5 & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_70 = _T_61 | _T_69; // @[el2_exu_div_ctl.scala 74:41]
wire pat2_6 = _T_22 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_75 = pat1 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_78 = _T_75 & _T_35; // @[el2_exu_div_ctl.scala 74:103]
wire _T_79 = _T_70 | _T_78; // @[el2_exu_div_ctl.scala 74:76]
wire _T_82 = ~pat1_2; // @[el2_exu_div_ctl.scala 64:69]
wire pat1_7 = pat1 & _T_82; // @[el2_exu_div_ctl.scala 64:94]
wire _T_90 = _T_27 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
wire pat2_7 = _T_90 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_91 = pat1_7 & pat2_7; // @[el2_exu_div_ctl.scala 66:10]
wire _T_92 = _T_79 | _T_91; // @[el2_exu_div_ctl.scala 74:114]
wire _T_94 = ~pat1; // @[el2_exu_div_ctl.scala 64:69]
wire _T_97 = _T_94 & pat1_2; // @[el2_exu_div_ctl.scala 64:94]
wire pat1_8 = _T_97 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_102 = pat1_8 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_103 = _T_92 | _T_102; // @[el2_exu_div_ctl.scala 75:43]
wire _T_107 = pat1_3 & _T_22; // @[el2_exu_div_ctl.scala 66:10]
wire _T_110 = _T_107 & _T_35; // @[el2_exu_div_ctl.scala 75:104]
wire _T_111 = _T_103 | _T_110; // @[el2_exu_div_ctl.scala 75:78]
wire _T_119 = _T_22 & m_ff[2]; // @[el2_exu_div_ctl.scala 65:94]
wire pat2_10 = _T_119 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_120 = pat1_3 & pat2_10; // @[el2_exu_div_ctl.scala 66:10]
wire _T_121 = _T_111 | _T_120; // @[el2_exu_div_ctl.scala 75:116]
wire pat1_11 = pat1 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_128 = pat1_11 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_129 = _T_121 | _T_128; // @[el2_exu_div_ctl.scala 76:43]
wire pat1_12 = pat1_3 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_137 = pat1_12 & _T_119; // @[el2_exu_div_ctl.scala 66:10]
wire _T_138 = _T_129 | _T_137; // @[el2_exu_div_ctl.scala 76:77]
wire _T_142 = pat1_2 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire pat1_13 = _T_142 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_147 = pat1_13 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire pat1_14 = pat1_7 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_157 = _T_22 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
wire pat2_14 = _T_157 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_158 = pat1_14 & pat2_14; // @[el2_exu_div_ctl.scala 66:10]
wire _T_159 = _T_147 | _T_158; // @[el2_exu_div_ctl.scala 78:44]
wire _T_164 = pat1_2 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_167 = _T_164 & _T_35; // @[el2_exu_div_ctl.scala 78:111]
wire _T_168 = _T_159 | _T_167; // @[el2_exu_div_ctl.scala 78:84]
wire _T_173 = pat1_5 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_176 = _T_173 & _T_35; // @[el2_exu_div_ctl.scala 79:32]
wire _T_177 = _T_168 | _T_176; // @[el2_exu_div_ctl.scala 78:126]
wire _T_185 = q_ff[0] & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_186 = _T_177 | _T_185; // @[el2_exu_div_ctl.scala 79:46]
wire _T_191 = ~pat1_5; // @[el2_exu_div_ctl.scala 64:69]
wire pat1_18 = _T_97 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
wire _T_201 = pat1_18 & pat2_7; // @[el2_exu_div_ctl.scala 66:10]
wire _T_202 = _T_186 | _T_201; // @[el2_exu_div_ctl.scala 79:86]
wire _T_209 = pat1_8 & _T_22; // @[el2_exu_div_ctl.scala 66:10]
wire _T_212 = _T_209 & _T_35; // @[el2_exu_div_ctl.scala 80:35]
wire _T_213 = _T_202 | _T_212; // @[el2_exu_div_ctl.scala 79:128]
wire pat2_20 = _T_24 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_218 = pat1 & pat2_20; // @[el2_exu_div_ctl.scala 66:10]
wire _T_221 = _T_218 & _T_35; // @[el2_exu_div_ctl.scala 80:74]
wire _T_222 = _T_213 | _T_221; // @[el2_exu_div_ctl.scala 80:46]
wire pat2_21 = _T_119 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_231 = pat1_7 & pat2_21; // @[el2_exu_div_ctl.scala 66:10]
wire _T_232 = _T_222 | _T_231; // @[el2_exu_div_ctl.scala 80:86]
wire _T_244 = pat1_8 & pat2_10; // @[el2_exu_div_ctl.scala 66:10]
wire _T_245 = _T_232 | _T_244; // @[el2_exu_div_ctl.scala 80:128]
wire pat1_23 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_255 = pat1_23 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_256 = _T_245 | _T_255; // @[el2_exu_div_ctl.scala 81:46]
wire pat1_24 = pat1_7 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
wire pat2_24 = _T_119 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_268 = pat1_24 & pat2_24; // @[el2_exu_div_ctl.scala 66:10]
wire _T_269 = _T_256 | _T_268; // @[el2_exu_div_ctl.scala 81:86]
wire _T_274 = _T_82 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire pat1_25 = _T_274 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_279 = pat1_25 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_280 = _T_269 | _T_279; // @[el2_exu_div_ctl.scala 81:128]
wire _T_284 = pat1_3 & _T_26; // @[el2_exu_div_ctl.scala 66:10]
wire _T_287 = _T_284 & _T_35; // @[el2_exu_div_ctl.scala 82:73]
wire _T_288 = _T_280 | _T_287; // @[el2_exu_div_ctl.scala 82:46]
wire pat1_27 = pat1_8 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_299 = pat1_27 & _T_119; // @[el2_exu_div_ctl.scala 66:10]
wire _T_300 = _T_288 | _T_299; // @[el2_exu_div_ctl.scala 82:86]
wire pat2_28 = m_ff[3] & _T_24; // @[el2_exu_div_ctl.scala 65:94]
wire _T_306 = pat1_3 & pat2_28; // @[el2_exu_div_ctl.scala 66:10]
wire _T_307 = _T_300 | _T_306; // @[el2_exu_div_ctl.scala 82:128]
wire pat2_29 = pat2_28 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_316 = pat1_11 & pat2_29; // @[el2_exu_div_ctl.scala 66:10]
wire _T_317 = _T_307 | _T_316; // @[el2_exu_div_ctl.scala 83:46]
wire pat1_30 = pat1 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_324 = pat1_30 & pat2_20; // @[el2_exu_div_ctl.scala 66:10]
wire _T_325 = _T_317 | _T_324; // @[el2_exu_div_ctl.scala 83:86]
wire pat1_31 = pat1 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
wire pat2_31 = pat2_21 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_336 = pat1_31 & pat2_31; // @[el2_exu_div_ctl.scala 66:10]
wire _T_337 = _T_325 | _T_336; // @[el2_exu_div_ctl.scala 83:128]
wire _T_342 = pat1_12 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
wire _T_345 = _T_342 & _T_35; // @[el2_exu_div_ctl.scala 84:75]
wire _T_346 = _T_337 | _T_345; // @[el2_exu_div_ctl.scala 84:46]
wire pat2_33 = m_ff[3] & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_354 = pat1_12 & pat2_33; // @[el2_exu_div_ctl.scala 66:10]
wire _T_355 = _T_346 | _T_354; // @[el2_exu_div_ctl.scala 84:86]
wire pat1_34 = pat1_3 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_363 = pat1_34 & pat2_33; // @[el2_exu_div_ctl.scala 66:10]
wire _T_364 = _T_355 | _T_363; // @[el2_exu_div_ctl.scala 84:128]
wire pat1_35 = pat1_7 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_373 = pat1_35 & _T_157; // @[el2_exu_div_ctl.scala 66:10]
wire _T_374 = _T_364 | _T_373; // @[el2_exu_div_ctl.scala 85:46]
wire pat1_36 = pat1_11 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_380 = pat1_36 & _T_24; // @[el2_exu_div_ctl.scala 66:10]
wire _T_381 = _T_374 | _T_380; // @[el2_exu_div_ctl.scala 85:86]
wire pat1_37 = pat1_12 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_388 = pat1_37 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
wire _T_389 = _T_381 | _T_388; // @[el2_exu_div_ctl.scala 85:128]
wire _T_393 = pat1_11 & _T_24; // @[el2_exu_div_ctl.scala 66:10]
wire _T_396 = _T_393 & _T_35; // @[el2_exu_div_ctl.scala 86:72]
wire _T_397 = _T_389 | _T_396; // @[el2_exu_div_ctl.scala 86:46]
wire [1:0] _T_398 = {_T_138,_T_397}; // @[Cat.scala 29:58]
wire [1:0] _T_399 = {_T_28,_T_53}; // @[Cat.scala 29:58]
reg sign_ff; // @[Reg.scala 27:20]
wire _T_401 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 96:34]
wire [32:0] short_dividend = {_T_401,q_ff[31:0]}; // @[Cat.scala 29:58]
wire _T_406 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 101:7]
wire _T_409 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 101:60]
wire _T_414 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 102:59]
wire _T_415 = _T_406 & _T_409; // @[Mux.scala 27:72]
wire _T_416 = short_dividend[32] & _T_414; // @[Mux.scala 27:72]
wire _T_417 = _T_415 | _T_416; // @[Mux.scala 27:72]
wire _T_424 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 105:60]
wire _T_429 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 106:59]
wire _T_430 = _T_406 & _T_424; // @[Mux.scala 27:72]
wire _T_431 = short_dividend[32] & _T_429; // @[Mux.scala 27:72]
wire _T_432 = _T_430 | _T_431; // @[Mux.scala 27:72]
wire _T_439 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 109:59]
wire _T_444 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 110:58]
wire _T_445 = _T_406 & _T_439; // @[Mux.scala 27:72]
wire _T_446 = short_dividend[32] & _T_444; // @[Mux.scala 27:72]
wire _T_447 = _T_445 | _T_446; // @[Mux.scala 27:72]
wire [2:0] a_cls = {_T_417,_T_432,_T_447}; // @[Cat.scala 29:58]
wire _T_452 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 115:7]
wire _T_455 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 115:40]
wire _T_460 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 116:39]
wire _T_461 = _T_452 & _T_455; // @[Mux.scala 27:72]
wire _T_462 = m_ff[32] & _T_460; // @[Mux.scala 27:72]
wire _T_463 = _T_461 | _T_462; // @[Mux.scala 27:72]
wire _T_470 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 119:40]
wire _T_475 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 120:39]
wire _T_476 = _T_452 & _T_470; // @[Mux.scala 27:72]
wire _T_477 = m_ff[32] & _T_475; // @[Mux.scala 27:72]
wire _T_478 = _T_476 | _T_477; // @[Mux.scala 27:72]
wire _T_485 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 123:39]
wire _T_490 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 124:38]
wire _T_491 = _T_452 & _T_485; // @[Mux.scala 27:72]
wire _T_492 = m_ff[32] & _T_490; // @[Mux.scala 27:72]
wire _T_493 = _T_491 | _T_492; // @[Mux.scala 27:72]
wire [2:0] b_cls = {_T_463,_T_478,_T_493}; // @[Cat.scala 29:58]
wire _T_497 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 128:19]
wire _T_500 = _T_497 & b_cls[2]; // @[el2_exu_div_ctl.scala 128:34]
wire _T_502 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 129:21]
wire _T_505 = _T_502 & b_cls[2]; // @[el2_exu_div_ctl.scala 129:36]
wire _T_506 = _T_500 | _T_505; // @[el2_exu_div_ctl.scala 128:65]
wire _T_508 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 130:21]
wire _T_511 = _T_508 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:36]
wire _T_512 = _T_506 | _T_511; // @[el2_exu_div_ctl.scala 129:67]
wire _T_516 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 131:50]
wire _T_517 = _T_502 & _T_516; // @[el2_exu_div_ctl.scala 131:36]
wire _T_518 = _T_512 | _T_517; // @[el2_exu_div_ctl.scala 130:67]
wire _T_523 = _T_508 & _T_516; // @[el2_exu_div_ctl.scala 132:36]
wire _T_524 = _T_518 | _T_523; // @[el2_exu_div_ctl.scala 131:67]
wire _T_528 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 133:50]
wire _T_529 = _T_508 & _T_528; // @[el2_exu_div_ctl.scala 133:36]
wire _T_530 = _T_524 | _T_529; // @[el2_exu_div_ctl.scala 132:67]
wire _T_535 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 135:34]
wire _T_540 = _T_497 & _T_516; // @[el2_exu_div_ctl.scala 136:36]
wire _T_541 = _T_535 | _T_540; // @[el2_exu_div_ctl.scala 135:65]
wire _T_546 = _T_502 & _T_528; // @[el2_exu_div_ctl.scala 137:36]
wire _T_547 = _T_541 | _T_546; // @[el2_exu_div_ctl.scala 136:67]
wire _T_551 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 138:50]
wire _T_552 = _T_508 & _T_551; // @[el2_exu_div_ctl.scala 138:36]
wire _T_553 = _T_547 | _T_552; // @[el2_exu_div_ctl.scala 137:67]
wire _T_558 = a_cls[2] & _T_516; // @[el2_exu_div_ctl.scala 140:34]
wire _T_563 = _T_497 & _T_528; // @[el2_exu_div_ctl.scala 141:36]
wire _T_564 = _T_558 | _T_563; // @[el2_exu_div_ctl.scala 140:65]
wire _T_569 = _T_502 & _T_551; // @[el2_exu_div_ctl.scala 142:36]
wire _T_570 = _T_564 | _T_569; // @[el2_exu_div_ctl.scala 141:67]
wire _T_575 = a_cls[2] & _T_528; // @[el2_exu_div_ctl.scala 144:34]
wire _T_580 = _T_497 & _T_551; // @[el2_exu_div_ctl.scala 145:36]
wire _T_581 = _T_575 | _T_580; // @[el2_exu_div_ctl.scala 144:65]
wire [3:0] shortq_raw = {_T_530,_T_553,_T_570,_T_581}; // @[Cat.scala 29:58]
wire _T_586 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 148:35]
wire _T_587 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 148:78]
wire shortq_enable = _T_586 & _T_587; // @[el2_exu_div_ctl.scala 148:64]
wire [3:0] _T_589 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
reg [3:0] shortq_shift_xx; // @[el2_exu_div_ctl.scala 215:31]
wire [4:0] _T_598 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_599 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_600 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [3:0] _T_601 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_602 = _T_598 | _T_599; // @[Mux.scala 27:72]
wire [4:0] _T_603 = _T_602 | _T_600; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_601}; // @[Mux.scala 27:72]
wire [4:0] shortq_shift_ff = _T_603 | _GEN_4; // @[Mux.scala 27:72]
reg [5:0] count; // @[el2_exu_div_ctl.scala 207:21]
wire _T_606 = count == 6'h20; // @[el2_exu_div_ctl.scala 159:55]
wire _T_607 = count == 6'h21; // @[el2_exu_div_ctl.scala 159:76]
wire _T_608 = _T_9 ? _T_606 : _T_607; // @[el2_exu_div_ctl.scala 159:39]
wire finish = smallnum_case | _T_608; // @[el2_exu_div_ctl.scala 159:34]
reg run_state; // @[el2_exu_div_ctl.scala 206:25]
wire _T_609 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 160:32]
wire _T_610 = _T_609 | finish; // @[el2_exu_div_ctl.scala 160:44]
reg finish_ff; // @[el2_exu_div_ctl.scala 205:25]
wire _T_612 = ~finish; // @[el2_exu_div_ctl.scala 161:48]
wire _T_613 = _T_609 & _T_612; // @[el2_exu_div_ctl.scala 161:46]
wire _T_616 = run_state & _T_612; // @[el2_exu_div_ctl.scala 162:35]
wire _T_618 = _T_616 & _T; // @[el2_exu_div_ctl.scala 162:45]
wire _T_619 = ~shortq_enable; // @[el2_exu_div_ctl.scala 162:60]
wire _T_620 = _T_618 & _T_619; // @[el2_exu_div_ctl.scala 162:58]
wire [5:0] _T_622 = _T_620 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [5:0] _T_623 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [5:0] _T_625 = count + _T_623; // @[el2_exu_div_ctl.scala 162:86]
wire [5:0] _T_627 = _T_625 + 6'h1; // @[el2_exu_div_ctl.scala 162:113]
wire _T_631 = ~io_dp_unsign; // @[el2_exu_div_ctl.scala 166:20]
wire _T_632 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 166:48]
wire sign_eff = _T_631 & _T_632; // @[el2_exu_div_ctl.scala 166:34]
wire _T_633 = ~run_state; // @[el2_exu_div_ctl.scala 170:6]
wire [32:0] _T_635 = {1'h0,io_dividend}; // @[Cat.scala 29:58]
reg shortq_enable_ff; // @[el2_exu_div_ctl.scala 214:32]
wire _T_636 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 171:30]
wire _T_637 = run_state & _T_636; // @[el2_exu_div_ctl.scala 171:16]
reg dividend_neg_ff; // @[Reg.scala 27:20]
wire _T_660 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 175:32]
wire _T_845 = |q_ff[30:0]; // @[el2_lib.scala 520:35]
wire _T_847 = ~q_ff[31]; // @[el2_lib.scala 520:40]
wire _T_849 = _T_845 ? _T_847 : q_ff[31]; // @[el2_lib.scala 520:23]
wire _T_839 = |q_ff[29:0]; // @[el2_lib.scala 520:35]
wire _T_841 = ~q_ff[30]; // @[el2_lib.scala 520:40]
wire _T_843 = _T_839 ? _T_841 : q_ff[30]; // @[el2_lib.scala 520:23]
wire _T_833 = |q_ff[28:0]; // @[el2_lib.scala 520:35]
wire _T_835 = ~q_ff[29]; // @[el2_lib.scala 520:40]
wire _T_837 = _T_833 ? _T_835 : q_ff[29]; // @[el2_lib.scala 520:23]
wire _T_827 = |q_ff[27:0]; // @[el2_lib.scala 520:35]
wire _T_829 = ~q_ff[28]; // @[el2_lib.scala 520:40]
wire _T_831 = _T_827 ? _T_829 : q_ff[28]; // @[el2_lib.scala 520:23]
wire _T_821 = |q_ff[26:0]; // @[el2_lib.scala 520:35]
wire _T_823 = ~q_ff[27]; // @[el2_lib.scala 520:40]
wire _T_825 = _T_821 ? _T_823 : q_ff[27]; // @[el2_lib.scala 520:23]
wire _T_815 = |q_ff[25:0]; // @[el2_lib.scala 520:35]
wire _T_817 = ~q_ff[26]; // @[el2_lib.scala 520:40]
wire _T_819 = _T_815 ? _T_817 : q_ff[26]; // @[el2_lib.scala 520:23]
wire _T_809 = |q_ff[24:0]; // @[el2_lib.scala 520:35]
wire _T_811 = ~q_ff[25]; // @[el2_lib.scala 520:40]
wire _T_813 = _T_809 ? _T_811 : q_ff[25]; // @[el2_lib.scala 520:23]
wire _T_803 = |q_ff[23:0]; // @[el2_lib.scala 520:35]
wire _T_805 = ~q_ff[24]; // @[el2_lib.scala 520:40]
wire _T_807 = _T_803 ? _T_805 : q_ff[24]; // @[el2_lib.scala 520:23]
wire _T_797 = |q_ff[22:0]; // @[el2_lib.scala 520:35]
wire _T_799 = ~q_ff[23]; // @[el2_lib.scala 520:40]
wire _T_801 = _T_797 ? _T_799 : q_ff[23]; // @[el2_lib.scala 520:23]
wire _T_791 = |q_ff[21:0]; // @[el2_lib.scala 520:35]
wire _T_793 = ~q_ff[22]; // @[el2_lib.scala 520:40]
wire _T_795 = _T_791 ? _T_793 : q_ff[22]; // @[el2_lib.scala 520:23]
wire _T_785 = |q_ff[20:0]; // @[el2_lib.scala 520:35]
wire _T_787 = ~q_ff[21]; // @[el2_lib.scala 520:40]
wire _T_789 = _T_785 ? _T_787 : q_ff[21]; // @[el2_lib.scala 520:23]
wire _T_779 = |q_ff[19:0]; // @[el2_lib.scala 520:35]
wire _T_781 = ~q_ff[20]; // @[el2_lib.scala 520:40]
wire _T_783 = _T_779 ? _T_781 : q_ff[20]; // @[el2_lib.scala 520:23]
wire _T_773 = |q_ff[18:0]; // @[el2_lib.scala 520:35]
wire _T_775 = ~q_ff[19]; // @[el2_lib.scala 520:40]
wire _T_777 = _T_773 ? _T_775 : q_ff[19]; // @[el2_lib.scala 520:23]
wire _T_767 = |q_ff[17:0]; // @[el2_lib.scala 520:35]
wire _T_769 = ~q_ff[18]; // @[el2_lib.scala 520:40]
wire _T_771 = _T_767 ? _T_769 : q_ff[18]; // @[el2_lib.scala 520:23]
wire _T_761 = |q_ff[16:0]; // @[el2_lib.scala 520:35]
wire _T_763 = ~q_ff[17]; // @[el2_lib.scala 520:40]
wire _T_765 = _T_761 ? _T_763 : q_ff[17]; // @[el2_lib.scala 520:23]
wire _T_755 = |q_ff[15:0]; // @[el2_lib.scala 520:35]
wire _T_757 = ~q_ff[16]; // @[el2_lib.scala 520:40]
wire _T_759 = _T_755 ? _T_757 : q_ff[16]; // @[el2_lib.scala 520:23]
wire [7:0] _T_870 = {_T_801,_T_795,_T_789,_T_783,_T_777,_T_771,_T_765,_T_759}; // @[el2_lib.scala 522:14]
wire _T_749 = |q_ff[14:0]; // @[el2_lib.scala 520:35]
wire _T_751 = ~q_ff[15]; // @[el2_lib.scala 520:40]
wire _T_753 = _T_749 ? _T_751 : q_ff[15]; // @[el2_lib.scala 520:23]
wire _T_743 = |q_ff[13:0]; // @[el2_lib.scala 520:35]
wire _T_745 = ~q_ff[14]; // @[el2_lib.scala 520:40]
wire _T_747 = _T_743 ? _T_745 : q_ff[14]; // @[el2_lib.scala 520:23]
wire _T_737 = |q_ff[12:0]; // @[el2_lib.scala 520:35]
wire _T_739 = ~q_ff[13]; // @[el2_lib.scala 520:40]
wire _T_741 = _T_737 ? _T_739 : q_ff[13]; // @[el2_lib.scala 520:23]
wire _T_731 = |q_ff[11:0]; // @[el2_lib.scala 520:35]
wire _T_733 = ~q_ff[12]; // @[el2_lib.scala 520:40]
wire _T_735 = _T_731 ? _T_733 : q_ff[12]; // @[el2_lib.scala 520:23]
wire _T_725 = |q_ff[10:0]; // @[el2_lib.scala 520:35]
wire _T_727 = ~q_ff[11]; // @[el2_lib.scala 520:40]
wire _T_729 = _T_725 ? _T_727 : q_ff[11]; // @[el2_lib.scala 520:23]
wire _T_719 = |q_ff[9:0]; // @[el2_lib.scala 520:35]
wire _T_721 = ~q_ff[10]; // @[el2_lib.scala 520:40]
wire _T_723 = _T_719 ? _T_721 : q_ff[10]; // @[el2_lib.scala 520:23]
wire _T_713 = |q_ff[8:0]; // @[el2_lib.scala 520:35]
wire _T_715 = ~q_ff[9]; // @[el2_lib.scala 520:40]
wire _T_717 = _T_713 ? _T_715 : q_ff[9]; // @[el2_lib.scala 520:23]
wire _T_707 = |q_ff[7:0]; // @[el2_lib.scala 520:35]
wire _T_709 = ~q_ff[8]; // @[el2_lib.scala 520:40]
wire _T_711 = _T_707 ? _T_709 : q_ff[8]; // @[el2_lib.scala 520:23]
wire _T_701 = |q_ff[6:0]; // @[el2_lib.scala 520:35]
wire _T_703 = ~q_ff[7]; // @[el2_lib.scala 520:40]
wire _T_705 = _T_701 ? _T_703 : q_ff[7]; // @[el2_lib.scala 520:23]
wire _T_695 = |q_ff[5:0]; // @[el2_lib.scala 520:35]
wire _T_697 = ~q_ff[6]; // @[el2_lib.scala 520:40]
wire _T_699 = _T_695 ? _T_697 : q_ff[6]; // @[el2_lib.scala 520:23]
wire _T_689 = |q_ff[4:0]; // @[el2_lib.scala 520:35]
wire _T_691 = ~q_ff[5]; // @[el2_lib.scala 520:40]
wire _T_693 = _T_689 ? _T_691 : q_ff[5]; // @[el2_lib.scala 520:23]
wire _T_683 = |q_ff[3:0]; // @[el2_lib.scala 520:35]
wire _T_685 = ~q_ff[4]; // @[el2_lib.scala 520:40]
wire _T_687 = _T_683 ? _T_685 : q_ff[4]; // @[el2_lib.scala 520:23]
wire _T_677 = |q_ff[2:0]; // @[el2_lib.scala 520:35]
wire _T_679 = ~q_ff[3]; // @[el2_lib.scala 520:40]
wire _T_681 = _T_677 ? _T_679 : q_ff[3]; // @[el2_lib.scala 520:23]
wire _T_671 = |q_ff[1:0]; // @[el2_lib.scala 520:35]
wire _T_673 = ~q_ff[2]; // @[el2_lib.scala 520:40]
wire _T_675 = _T_671 ? _T_673 : q_ff[2]; // @[el2_lib.scala 520:23]
wire _T_665 = |q_ff[0]; // @[el2_lib.scala 520:35]
wire _T_667 = ~q_ff[1]; // @[el2_lib.scala 520:40]
wire _T_669 = _T_665 ? _T_667 : q_ff[1]; // @[el2_lib.scala 520:23]
wire [6:0] _T_855 = {_T_705,_T_699,_T_693,_T_687,_T_681,_T_675,_T_669}; // @[el2_lib.scala 522:14]
wire [14:0] _T_863 = {_T_753,_T_747,_T_741,_T_735,_T_729,_T_723,_T_717,_T_711,_T_855}; // @[el2_lib.scala 522:14]
wire [30:0] _T_879 = {_T_849,_T_843,_T_837,_T_831,_T_825,_T_819,_T_813,_T_807,_T_870,_T_863}; // @[el2_lib.scala 522:14]
wire [31:0] _T_881 = {_T_879,q_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] dividend_eff = _T_660 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 175:22]
wire [32:0] _T_917 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
wire _T_929 = _T_607 & rem_ff; // @[el2_exu_div_ctl.scala 191:41]
reg [32:0] a_ff; // @[el2_lib.scala 491:16]
wire rem_correct = _T_929 & a_ff[32]; // @[el2_exu_div_ctl.scala 191:50]
wire [32:0] _T_902 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
wire _T_890 = ~rem_correct; // @[el2_exu_div_ctl.scala 182:6]
wire _T_891 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 182:21]
wire _T_892 = _T_890 & _T_891; // @[el2_exu_div_ctl.scala 182:19]
wire [32:0] _T_896 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
wire [32:0] _T_903 = _T_892 ? _T_896 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_905 = _T_902 | _T_903; // @[Mux.scala 27:72]
wire _T_898 = _T_890 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 183:19]
wire [55:0] _T_887 = {24'h0,dividend_eff}; // @[Cat.scala 29:58]
wire [86:0] _GEN_5 = {{31'd0}, _T_887}; // @[el2_exu_div_ctl.scala 179:47]
wire [86:0] _T_888 = _GEN_5 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 179:47]
wire [55:0] a_eff_shift = _T_888[55:0]; // @[el2_exu_div_ctl.scala 179:15]
wire [32:0] _T_901 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58]
wire [32:0] _T_904 = _T_898 ? _T_901 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] a_eff = _T_905 | _T_904; // @[Mux.scala 27:72]
wire [32:0] a_shift = _T_917 & a_eff; // @[el2_exu_div_ctl.scala 186:33]
wire _T_926 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 190:21]
reg divisor_neg_ff; // @[Reg.scala 27:20]
wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 188:48]
wire add = _T_926 ^ m_already_comp; // @[el2_exu_div_ctl.scala 190:36]
wire [32:0] _T_885 = ~m_ff; // @[el2_exu_div_ctl.scala 178:35]
wire [32:0] m_eff = add ? m_ff : _T_885; // @[el2_exu_div_ctl.scala 178:15]
wire [32:0] _T_919 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 187:41]
wire _T_920 = ~add; // @[el2_exu_div_ctl.scala 187:65]
wire [32:0] _T_921 = {32'h0,_T_920}; // @[Cat.scala 29:58]
wire [32:0] _T_923 = _T_919 + _T_921; // @[el2_exu_div_ctl.scala 187:49]
wire [32:0] a_in = _T_917 & _T_923; // @[el2_exu_div_ctl.scala 187:30]
wire _T_641 = ~a_in[32]; // @[el2_exu_div_ctl.scala 171:85]
wire [32:0] _T_642 = {dividend_eff,_T_641}; // @[Cat.scala 29:58]
wire [63:0] _GEN_6 = {{31'd0}, _T_642}; // @[el2_exu_div_ctl.scala 171:96]
wire [63:0] _T_643 = _GEN_6 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 171:96]
wire _T_645 = ~_T_636; // @[el2_exu_div_ctl.scala 172:18]
wire _T_646 = run_state & _T_645; // @[el2_exu_div_ctl.scala 172:16]
wire [32:0] _T_651 = {q_ff[31:0],_T_641}; // @[Cat.scala 29:58]
wire [32:0] _T_652 = _T_633 ? _T_635 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _T_653 = _T_637 ? _T_643 : 64'h0; // @[Mux.scala 27:72]
wire [32:0] _T_654 = _T_646 ? _T_651 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _GEN_7 = {{31'd0}, _T_652}; // @[Mux.scala 27:72]
wire [63:0] _T_655 = _GEN_7 | _T_653; // @[Mux.scala 27:72]
wire [63:0] _GEN_8 = {{31'd0}, _T_654}; // @[Mux.scala 27:72]
wire [63:0] _T_656 = _T_655 | _GEN_8; // @[Mux.scala 27:72]
wire _T_659 = run_state & _T_619; // @[el2_exu_div_ctl.scala 174:48]
wire _T_910 = count != 6'h21; // @[el2_exu_div_ctl.scala 185:73]
wire _T_911 = _T_659 & _T_910; // @[el2_exu_div_ctl.scala 185:64]
wire _T_912 = io_dp_valid | _T_911; // @[el2_exu_div_ctl.scala 185:34]
wire _T_932 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 192:50]
wire _T_933 = sign_ff & _T_932; // @[el2_exu_div_ctl.scala 192:31]
wire [31:0] q_ff_eff = _T_933 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 192:21]
wire _T_1161 = |a_ff[0]; // @[el2_lib.scala 520:35]
wire _T_1163 = ~a_ff[1]; // @[el2_lib.scala 520:40]
wire _T_1165 = _T_1161 ? _T_1163 : a_ff[1]; // @[el2_lib.scala 520:23]
wire _T_1167 = |a_ff[1:0]; // @[el2_lib.scala 520:35]
wire _T_1169 = ~a_ff[2]; // @[el2_lib.scala 520:40]
wire _T_1171 = _T_1167 ? _T_1169 : a_ff[2]; // @[el2_lib.scala 520:23]
wire _T_1173 = |a_ff[2:0]; // @[el2_lib.scala 520:35]
wire _T_1175 = ~a_ff[3]; // @[el2_lib.scala 520:40]
wire _T_1177 = _T_1173 ? _T_1175 : a_ff[3]; // @[el2_lib.scala 520:23]
wire _T_1179 = |a_ff[3:0]; // @[el2_lib.scala 520:35]
wire _T_1181 = ~a_ff[4]; // @[el2_lib.scala 520:40]
wire _T_1183 = _T_1179 ? _T_1181 : a_ff[4]; // @[el2_lib.scala 520:23]
wire _T_1185 = |a_ff[4:0]; // @[el2_lib.scala 520:35]
wire _T_1187 = ~a_ff[5]; // @[el2_lib.scala 520:40]
wire _T_1189 = _T_1185 ? _T_1187 : a_ff[5]; // @[el2_lib.scala 520:23]
wire _T_1191 = |a_ff[5:0]; // @[el2_lib.scala 520:35]
wire _T_1193 = ~a_ff[6]; // @[el2_lib.scala 520:40]
wire _T_1195 = _T_1191 ? _T_1193 : a_ff[6]; // @[el2_lib.scala 520:23]
wire _T_1197 = |a_ff[6:0]; // @[el2_lib.scala 520:35]
wire _T_1199 = ~a_ff[7]; // @[el2_lib.scala 520:40]
wire _T_1201 = _T_1197 ? _T_1199 : a_ff[7]; // @[el2_lib.scala 520:23]
wire _T_1203 = |a_ff[7:0]; // @[el2_lib.scala 520:35]
wire _T_1205 = ~a_ff[8]; // @[el2_lib.scala 520:40]
wire _T_1207 = _T_1203 ? _T_1205 : a_ff[8]; // @[el2_lib.scala 520:23]
wire _T_1209 = |a_ff[8:0]; // @[el2_lib.scala 520:35]
wire _T_1211 = ~a_ff[9]; // @[el2_lib.scala 520:40]
wire _T_1213 = _T_1209 ? _T_1211 : a_ff[9]; // @[el2_lib.scala 520:23]
wire _T_1215 = |a_ff[9:0]; // @[el2_lib.scala 520:35]
wire _T_1217 = ~a_ff[10]; // @[el2_lib.scala 520:40]
wire _T_1219 = _T_1215 ? _T_1217 : a_ff[10]; // @[el2_lib.scala 520:23]
wire _T_1221 = |a_ff[10:0]; // @[el2_lib.scala 520:35]
wire _T_1223 = ~a_ff[11]; // @[el2_lib.scala 520:40]
wire _T_1225 = _T_1221 ? _T_1223 : a_ff[11]; // @[el2_lib.scala 520:23]
wire _T_1227 = |a_ff[11:0]; // @[el2_lib.scala 520:35]
wire _T_1229 = ~a_ff[12]; // @[el2_lib.scala 520:40]
wire _T_1231 = _T_1227 ? _T_1229 : a_ff[12]; // @[el2_lib.scala 520:23]
wire _T_1233 = |a_ff[12:0]; // @[el2_lib.scala 520:35]
wire _T_1235 = ~a_ff[13]; // @[el2_lib.scala 520:40]
wire _T_1237 = _T_1233 ? _T_1235 : a_ff[13]; // @[el2_lib.scala 520:23]
wire _T_1239 = |a_ff[13:0]; // @[el2_lib.scala 520:35]
wire _T_1241 = ~a_ff[14]; // @[el2_lib.scala 520:40]
wire _T_1243 = _T_1239 ? _T_1241 : a_ff[14]; // @[el2_lib.scala 520:23]
wire _T_1245 = |a_ff[14:0]; // @[el2_lib.scala 520:35]
wire _T_1247 = ~a_ff[15]; // @[el2_lib.scala 520:40]
wire _T_1249 = _T_1245 ? _T_1247 : a_ff[15]; // @[el2_lib.scala 520:23]
wire _T_1251 = |a_ff[15:0]; // @[el2_lib.scala 520:35]
wire _T_1253 = ~a_ff[16]; // @[el2_lib.scala 520:40]
wire _T_1255 = _T_1251 ? _T_1253 : a_ff[16]; // @[el2_lib.scala 520:23]
wire _T_1257 = |a_ff[16:0]; // @[el2_lib.scala 520:35]
wire _T_1259 = ~a_ff[17]; // @[el2_lib.scala 520:40]
wire _T_1261 = _T_1257 ? _T_1259 : a_ff[17]; // @[el2_lib.scala 520:23]
wire _T_1263 = |a_ff[17:0]; // @[el2_lib.scala 520:35]
wire _T_1265 = ~a_ff[18]; // @[el2_lib.scala 520:40]
wire _T_1267 = _T_1263 ? _T_1265 : a_ff[18]; // @[el2_lib.scala 520:23]
wire _T_1269 = |a_ff[18:0]; // @[el2_lib.scala 520:35]
wire _T_1271 = ~a_ff[19]; // @[el2_lib.scala 520:40]
wire _T_1273 = _T_1269 ? _T_1271 : a_ff[19]; // @[el2_lib.scala 520:23]
wire _T_1275 = |a_ff[19:0]; // @[el2_lib.scala 520:35]
wire _T_1277 = ~a_ff[20]; // @[el2_lib.scala 520:40]
wire _T_1279 = _T_1275 ? _T_1277 : a_ff[20]; // @[el2_lib.scala 520:23]
wire _T_1281 = |a_ff[20:0]; // @[el2_lib.scala 520:35]
wire _T_1283 = ~a_ff[21]; // @[el2_lib.scala 520:40]
wire _T_1285 = _T_1281 ? _T_1283 : a_ff[21]; // @[el2_lib.scala 520:23]
wire _T_1287 = |a_ff[21:0]; // @[el2_lib.scala 520:35]
wire _T_1289 = ~a_ff[22]; // @[el2_lib.scala 520:40]
wire _T_1291 = _T_1287 ? _T_1289 : a_ff[22]; // @[el2_lib.scala 520:23]
wire _T_1293 = |a_ff[22:0]; // @[el2_lib.scala 520:35]
wire _T_1295 = ~a_ff[23]; // @[el2_lib.scala 520:40]
wire _T_1297 = _T_1293 ? _T_1295 : a_ff[23]; // @[el2_lib.scala 520:23]
wire _T_1299 = |a_ff[23:0]; // @[el2_lib.scala 520:35]
wire _T_1301 = ~a_ff[24]; // @[el2_lib.scala 520:40]
wire _T_1303 = _T_1299 ? _T_1301 : a_ff[24]; // @[el2_lib.scala 520:23]
wire _T_1305 = |a_ff[24:0]; // @[el2_lib.scala 520:35]
wire _T_1307 = ~a_ff[25]; // @[el2_lib.scala 520:40]
wire _T_1309 = _T_1305 ? _T_1307 : a_ff[25]; // @[el2_lib.scala 520:23]
wire _T_1311 = |a_ff[25:0]; // @[el2_lib.scala 520:35]
wire _T_1313 = ~a_ff[26]; // @[el2_lib.scala 520:40]
wire _T_1315 = _T_1311 ? _T_1313 : a_ff[26]; // @[el2_lib.scala 520:23]
wire _T_1317 = |a_ff[26:0]; // @[el2_lib.scala 520:35]
wire _T_1319 = ~a_ff[27]; // @[el2_lib.scala 520:40]
wire _T_1321 = _T_1317 ? _T_1319 : a_ff[27]; // @[el2_lib.scala 520:23]
wire _T_1323 = |a_ff[27:0]; // @[el2_lib.scala 520:35]
wire _T_1325 = ~a_ff[28]; // @[el2_lib.scala 520:40]
wire _T_1327 = _T_1323 ? _T_1325 : a_ff[28]; // @[el2_lib.scala 520:23]
wire _T_1329 = |a_ff[28:0]; // @[el2_lib.scala 520:35]
wire _T_1331 = ~a_ff[29]; // @[el2_lib.scala 520:40]
wire _T_1333 = _T_1329 ? _T_1331 : a_ff[29]; // @[el2_lib.scala 520:23]
wire _T_1335 = |a_ff[29:0]; // @[el2_lib.scala 520:35]
wire _T_1337 = ~a_ff[30]; // @[el2_lib.scala 520:40]
wire _T_1339 = _T_1335 ? _T_1337 : a_ff[30]; // @[el2_lib.scala 520:23]
wire _T_1341 = |a_ff[30:0]; // @[el2_lib.scala 520:35]
wire _T_1343 = ~a_ff[31]; // @[el2_lib.scala 520:40]
wire _T_1345 = _T_1341 ? _T_1343 : a_ff[31]; // @[el2_lib.scala 520:23]
wire [6:0] _T_1351 = {_T_1201,_T_1195,_T_1189,_T_1183,_T_1177,_T_1171,_T_1165}; // @[el2_lib.scala 522:14]
wire [14:0] _T_1359 = {_T_1249,_T_1243,_T_1237,_T_1231,_T_1225,_T_1219,_T_1213,_T_1207,_T_1351}; // @[el2_lib.scala 522:14]
wire [7:0] _T_1366 = {_T_1297,_T_1291,_T_1285,_T_1279,_T_1273,_T_1267,_T_1261,_T_1255}; // @[el2_lib.scala 522:14]
wire [30:0] _T_1375 = {_T_1345,_T_1339,_T_1333,_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1366,_T_1359}; // @[el2_lib.scala 522:14]
wire [31:0] _T_1377 = {_T_1375,a_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] a_ff_eff = _T_660 ? _T_1377 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 193:21]
reg smallnum_case_ff; // @[el2_exu_div_ctl.scala 212:32]
reg [3:0] smallnum_ff; // @[el2_exu_div_ctl.scala 213:27]
wire [31:0] _T_1380 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
wire _T_1382 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 198:6]
wire _T_1384 = _T_1382 & _T_9; // @[el2_exu_div_ctl.scala 198:24]
wire [31:0] _T_1386 = smallnum_case_ff ? _T_1380 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1387 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1388 = _T_1384 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1389 = _T_1386 | _T_1387; // @[Mux.scala 27:72]
wire _T_1421 = _T_631 & io_divisor[31]; // @[el2_exu_div_ctl.scala 219:36]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 474:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
assign io_out = _T_1389 | _T_1388; // @[el2_exu_div_ctl.scala 50:10 el2_exu_div_ctl.scala 195:10]
assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 51:17 el2_exu_div_ctl.scala 165:18]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 475:17]
assign rvclkhdr_io_en = _T_610 | finish_ff; // @[el2_lib.scala 476:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18]
assign rvclkhdr_1_io_en = io_dp_valid | _T_659; // @[el2_lib.scala 488:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18]
assign rvclkhdr_2_io_en = _T_912 | rem_correct; // @[el2_lib.scala 488:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18]
assign rvclkhdr_3_io_en = io_dp_valid; // @[el2_lib.scala 488:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
valid_ff_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
q_ff = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
m_ff = _RAND_2[32:0];
_RAND_3 = {1{`RANDOM}};
rem_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
sign_ff = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
shortq_shift_xx = _RAND_5[3:0];
_RAND_6 = {1{`RANDOM}};
count = _RAND_6[5:0];
_RAND_7 = {1{`RANDOM}};
run_state = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
finish_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
shortq_enable_ff = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
dividend_neg_ff = _RAND_10[0:0];
_RAND_11 = {2{`RANDOM}};
a_ff = _RAND_11[32:0];
_RAND_12 = {1{`RANDOM}};
divisor_neg_ff = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
smallnum_case_ff = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
smallnum_ff = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valid_ff_x = 1'h0;
end
if (reset) begin
q_ff = 33'h0;
end
if (reset) begin
m_ff = 33'h0;
end
if (reset) begin
rem_ff = 1'h0;
end
if (reset) begin
sign_ff = 1'h0;
end
if (reset) begin
shortq_shift_xx = 4'h0;
end
if (reset) begin
count = 6'h0;
end
if (reset) begin
run_state = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
dividend_neg_ff = 1'h0;
end
if (reset) begin
a_ff = 33'h0;
end
if (reset) begin
divisor_neg_ff = 1'h0;
end
if (reset) begin
smallnum_case_ff = 1'h0;
end
if (reset) begin
smallnum_ff = 4'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
valid_ff_x <= 1'h0;
end else begin
valid_ff_x <= io_dp_valid & _T;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
q_ff <= 33'h0;
end else begin
q_ff <= _T_656[32:0];
end
end
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin
m_ff <= 33'h0;
end else begin
m_ff <= {_T_1421,io_divisor};
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
rem_ff <= 1'h0;
end else if (io_dp_valid) begin
rem_ff <= io_dp_rem;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
sign_ff <= 1'h0;
end else if (io_dp_valid) begin
sign_ff <= sign_eff;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
shortq_shift_xx <= 4'h0;
end else begin
shortq_shift_xx <= _T_589 & shortq_raw;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
count <= 6'h0;
end else begin
count <= _T_622 & _T_627;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
run_state <= 1'h0;
end else begin
run_state <= _T_613 & _T;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else begin
finish_ff <= finish & _T;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else begin
shortq_enable_ff <= _T_586 & _T_587;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
dividend_neg_ff <= 1'h0;
end else if (io_dp_valid) begin
dividend_neg_ff <= io_dividend[31];
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
a_ff <= 33'h0;
end else begin
a_ff <= _T_917 & _T_923;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
divisor_neg_ff <= 1'h0;
end else if (io_dp_valid) begin
divisor_neg_ff <= io_divisor[31];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
smallnum_case_ff <= 1'h0;
end else begin
smallnum_case_ff <= _T_11 | _T_19;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
smallnum_ff <= 4'h0;
end else begin
smallnum_ff <= {_T_399,_T_398};
end
end
endmodule

23
el2_exu_mul_ctl.anno.json
View File

@ -1,23 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_mul_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_mul_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

145
el2_exu_mul_ctl.fir
View File

@ -1,145 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu_mul_ctl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
extmodule TEC_RV_ICG_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 465:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
module el2_exu_mul_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
wire rs1_ext_in : SInt<33>
rs1_ext_in <= asSInt(UInt<1>("h00"))
wire rs2_ext_in : SInt<33>
rs2_ext_in <= asSInt(UInt<1>("h00"))
wire rs1_x : SInt<33>
rs1_x <= asSInt(UInt<1>("h00"))
wire rs2_x : SInt<33>
rs2_x <= asSInt(UInt<1>("h00"))
wire prod_x : SInt<66>
prod_x <= asSInt(UInt<1>("h00"))
wire low_x : UInt<1>
low_x <= UInt<1>("h00")
node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:50]
node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:39]
node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:66]
rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14]
node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:50]
node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:39]
node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:66]
rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:47]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 485:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18]
rvclkhdr.io.en <= _T_8 @[el2_lib.scala 488:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24]
reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16]
_T_9 <= io.mul_p.low @[el2_lib.scala 491:16]
low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9]
node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 505:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 507:18]
rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 508:17]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 509:24]
reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 511:16]
_T_11 <= rs1_ext_in @[el2_lib.scala 511:16]
rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9]
node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 505:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 507:18]
rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 508:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 509:24]
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 511:16]
_T_13 <= rs2_ext_in @[el2_lib.scala 511:16]
rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9]
node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20]
prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10]
node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36]
node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29]
node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52]
node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67]
node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83]
node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
wire _T_23 : UInt<32> @[Mux.scala 27:72]
_T_23 <= _T_22 @[Mux.scala 27:72]
io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15]

181
el2_exu_mul_ctl.v
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@ -1,181 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 465:26]
wire clkhdr_CK; // @[el2_lib.scala 465:26]
wire clkhdr_EN; // @[el2_lib.scala 465:26]
wire clkhdr_SE; // @[el2_lib.scala 465:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18]
endmodule
module el2_exu_mul_ctl(
input clock,
input reset,
input io_scan_mode,
input io_mul_p_valid,
input io_mul_p_rs1_sign,
input io_mul_p_rs2_sign,
input io_mul_p_low,
input io_mul_p_bext,
input io_mul_p_bdep,
input io_mul_p_clmul,
input io_mul_p_clmulh,
input io_mul_p_clmulr,
input io_mul_p_grev,
input io_mul_p_shfl,
input io_mul_p_unshfl,
input io_mul_p_crc32_b,
input io_mul_p_crc32_h,
input io_mul_p_crc32_w,
input io_mul_p_crc32c_b,
input io_mul_p_crc32c_h,
input io_mul_p_crc32c_w,
input io_mul_p_bfp,
input [31:0] io_rs1_in,
input [31:0] io_rs2_in,
output [31:0] io_result_x
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 485:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 505:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 505:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 505:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 505:23]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 505:23]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 505:23]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 505:23]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 505:23]
wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:39]
wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:39]
reg low_x; // @[el2_lib.scala 491:16]
reg [32:0] rs1_x; // @[el2_lib.scala 511:16]
reg [32:0] rs2_x; // @[el2_lib.scala 511:16]
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20]
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29]
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 505:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 505:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18]
assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 488:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 507:18]
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 508:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 509:24]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 507:18]
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 508:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 509:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
low_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
rs1_x = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
rs2_x = _RAND_2[32:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
low_x = 1'h0;
end
if (reset) begin
rs1_x = 33'sh0;
end
if (reset) begin
rs2_x = 33'sh0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
low_x <= 1'h0;
end else begin
low_x <= io_mul_p_low;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
rs1_x <= 33'sh0;
end else begin
rs1_x <= {_T_1,io_rs1_in};
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
rs2_x <= 33'sh0;
end else begin
rs2_x <= {_T_5,io_rs2_in};
end
end
endmodule

339
el2_ifu.anno.json
View File

@ -1,339 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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},
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el2_ifu.fir
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el2_ifu.v
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el2_ifu_aln_ctl.anno.json
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@ -1,53 +0,0 @@
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el2_ifu_aln_ctl.fir
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el2_ifu_aln_ctl.sv
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el2_ifu_bp_ctl.anno.json
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@ -1,154 +0,0 @@
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{
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist0_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_way_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist1_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_poffset_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_valid_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_ret_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_inst_mask_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_bp_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_bp_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_ifu_bp_ctl.fir
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30834
el2_ifu_bp_ctl.v
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el2_ifu_compress.anno.json
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@ -1,60 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress|el2_ifu_compress>io_out_rs2",
"sources":[
"~el2_ifu_compress|el2_ifu_compress>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress|el2_ifu_compress>io_out_rd",
"sources":[
"~el2_ifu_compress|el2_ifu_compress>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress|el2_ifu_compress>io_out_rs1",
"sources":[
"~el2_ifu_compress|el2_ifu_compress>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress|el2_ifu_compress>io_out_bits",
"sources":[
"~el2_ifu_compress|el2_ifu_compress>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress|el2_ifu_compress>io_rvc",
"sources":[
"~el2_ifu_compress|el2_ifu_compress>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress|el2_ifu_compress>io_out_rs3",
"sources":[
"~el2_ifu_compress|el2_ifu_compress>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_compress"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1193
el2_ifu_compress.fir
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el2_ifu_compress.v
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@ -1,281 +0,0 @@
module el2_ifu_compress(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out_bits,
output [4:0] io_out_rd,
output [4:0] io_out_rs1,
output [4:0] io_out_rs2,
output [4:0] io_out_rs3,
output io_rvc
);
wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress.scala 48:29]
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 48:20]
wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58]
wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
wire [27:0] _T_78 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
wire [26:0] _T_109 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
wire [27:0] _T_136 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
wire [26:0] _T_167 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
wire [27:0] _T_194 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h23}; // @[Cat.scala 29:58]
wire [6:0] _T_205 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_207 = {_T_205,io_in[6:2]}; // @[Cat.scala 29:58]
wire [31:0] _T_213 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_221 = |io_in[11:7]; // @[el2_ifu_compress.scala 72:24]
wire [6:0] _T_222 = _T_221 ? 7'h1b : 7'h1f; // @[el2_ifu_compress.scala 72:20]
wire [31:0] _T_233 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],_T_222}; // @[Cat.scala 29:58]
wire [31:0] _T_249 = {_T_205,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_260 = |_T_207; // @[el2_ifu_compress.scala 85:29]
wire [6:0] _T_261 = _T_260 ? 7'h37 : 7'h3f; // @[el2_ifu_compress.scala 85:20]
wire [14:0] _T_264 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_267 = {_T_264,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_271 = {_T_267[31:12],io_in[11:7],_T_261}; // @[Cat.scala 29:58]
wire _T_279 = io_in[11:7] == 5'h0; // @[el2_ifu_compress.scala 87:14]
wire _T_281 = io_in[11:7] == 5'h2; // @[el2_ifu_compress.scala 87:27]
wire _T_282 = _T_279 | _T_281; // @[el2_ifu_compress.scala 87:21]
wire [6:0] _T_289 = _T_260 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 81:20]
wire [2:0] _T_292 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_307 = {_T_292,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_289}; // @[Cat.scala 29:58]
wire [31:0] _T_314_bits = _T_282 ? _T_307 : _T_271; // @[el2_ifu_compress.scala 87:10]
wire [4:0] _T_314_rd = _T_282 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 87:10]
wire [4:0] _T_314_rs2 = _T_282 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 87:10]
wire [4:0] _T_314_rs3 = _T_282 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 87:10]
wire [25:0] _T_325 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [30:0] _GEN_172 = {{5'd0}, _T_325}; // @[el2_ifu_compress.scala 94:23]
wire [30:0] _T_337 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress.scala 94:23]
wire [31:0] _T_350 = {_T_205,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [2:0] _T_354 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
wire _T_356 = io_in[6:5] == 2'h0; // @[el2_ifu_compress.scala 98:30]
wire [30:0] _T_357 = _T_356 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress.scala 98:22]
wire [6:0] _T_359 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress.scala 99:22]
wire [2:0] _GEN_1 = 3'h1 == _T_354 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
wire [2:0] _GEN_2 = 3'h2 == _T_354 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
wire [2:0] _GEN_3 = 3'h3 == _T_354 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
wire [2:0] _GEN_4 = 3'h4 == _T_354 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
wire [2:0] _GEN_5 = 3'h5 == _T_354 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
wire [2:0] _GEN_6 = 3'h6 == _T_354 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
wire [2:0] _GEN_7 = 3'h7 == _T_354 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
wire [24:0] _T_369 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_359}; // @[Cat.scala 29:58]
wire [30:0] _GEN_173 = {{6'd0}, _T_369}; // @[el2_ifu_compress.scala 100:43]
wire [30:0] _T_370 = _GEN_173 | _T_357; // @[el2_ifu_compress.scala 100:43]
wire [31:0] _T_371_0 = {{6'd0}, _T_325}; // @[el2_ifu_compress.scala 102:19 el2_ifu_compress.scala 102:19]
wire [31:0] _T_371_1 = {{1'd0}, _T_337}; // @[el2_ifu_compress.scala 102:19 el2_ifu_compress.scala 102:19]
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_371_1 : _T_371_0; // @[el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_350 : _GEN_9; // @[el2_ifu_compress.scala 17:14]
wire [31:0] _T_371_3 = {{1'd0}, _T_370}; // @[el2_ifu_compress.scala 102:19 el2_ifu_compress.scala 102:19]
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_371_3 : _GEN_10; // @[el2_ifu_compress.scala 17:14]
wire [9:0] _T_383 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
wire [20:0] _T_398 = {_T_383,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_461 = {_T_398[20],_T_398[10:1],_T_398[11],_T_398[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
wire [4:0] _T_470 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
wire [12:0] _T_479 = {_T_470,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_528 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
wire [31:0] _T_595 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
wire [6:0] _T_602 = _T_221 ? 7'h3 : 7'h1f; // @[el2_ifu_compress.scala 108:23]
wire [25:0] _T_611 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [28:0] _T_627 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [27:0] _T_642 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
wire [28:0] _T_657 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
wire [24:0] _T_667 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_678 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_689 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
wire [24:0] _T_691 = {_T_689[24:7],7'h1f}; // @[Cat.scala 29:58]
wire [24:0] _T_694 = _T_221 ? _T_689 : _T_691; // @[el2_ifu_compress.scala 129:33]
wire _T_700 = |io_in[6:2]; // @[el2_ifu_compress.scala 130:27]
wire [31:0] _T_671_bits = {{7'd0}, _T_667}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_698_bits = {{7'd0}, _T_694}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_701_bits = _T_700 ? _T_671_bits : _T_698_bits; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rd = _T_700 ? io_in[11:7] : 5'h0; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rs1 = _T_700 ? 5'h0 : io_in[11:7]; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rs2 = _T_700 ? io_in[6:2] : io_in[6:2]; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rs3 = _T_700 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 130:22]
wire [24:0] _T_707 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
wire [24:0] _T_709 = {_T_689[24:7],7'h73}; // @[Cat.scala 29:58]
wire [24:0] _T_710 = _T_709 | 25'h100000; // @[el2_ifu_compress.scala 132:46]
wire [24:0] _T_713 = _T_221 ? _T_707 : _T_710; // @[el2_ifu_compress.scala 133:33]
wire [31:0] _T_683_bits = {{7'd0}, _T_678}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_717_bits = {{7'd0}, _T_713}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_720_bits = _T_700 ? _T_683_bits : _T_717_bits; // @[el2_ifu_compress.scala 134:25]
wire [4:0] _T_720_rd = _T_700 ? io_in[11:7] : 5'h1; // @[el2_ifu_compress.scala 134:25]
wire [4:0] _T_720_rs1 = _T_700 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 134:25]
wire [31:0] _T_722_bits = io_in[12] ? _T_720_bits : _T_701_bits; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rd = io_in[12] ? _T_720_rd : _T_701_rd; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rs1 = io_in[12] ? _T_720_rs1 : _T_701_rs1; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rs2 = io_in[12] ? _T_701_rs2 : _T_701_rs2; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rs3 = io_in[12] ? _T_701_rs3 : _T_701_rs3; // @[el2_ifu_compress.scala 135:10]
wire [8:0] _T_726 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [28:0] _T_738 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h27}; // @[Cat.scala 29:58]
wire [7:0] _T_746 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
wire [27:0] _T_758 = {_T_746[7:5],io_in[6:2],5'h2,3'h2,_T_746[4:0],7'h23}; // @[Cat.scala 29:58]
wire [28:0] _T_778 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h23}; // @[Cat.scala 29:58]
wire [4:0] _T_826 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_17 = 5'h1 == _T_826 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_18 = 5'h1 == _T_826 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_19 = 5'h1 == _T_826 ? _T_30 : 5'h2; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_21 = 5'h1 == _T_826 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_22 = 5'h2 == _T_826 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_23 = 5'h2 == _T_826 ? _T_14 : _GEN_18; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_24 = 5'h2 == _T_826 ? _T_30 : _GEN_19; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_26 = 5'h2 == _T_826 ? io_in[31:27] : _GEN_21; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_86_bits = {{4'd0}, _T_78}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_27 = 5'h3 == _T_826 ? _T_86_bits : _GEN_22; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_28 = 5'h3 == _T_826 ? _T_14 : _GEN_23; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_29 = 5'h3 == _T_826 ? _T_30 : _GEN_24; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_31 = 5'h3 == _T_826 ? io_in[31:27] : _GEN_26; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_117_bits = {{5'd0}, _T_109}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_32 = 5'h4 == _T_826 ? _T_117_bits : _GEN_27; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_33 = 5'h4 == _T_826 ? _T_14 : _GEN_28; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_34 = 5'h4 == _T_826 ? _T_30 : _GEN_29; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_36 = 5'h4 == _T_826 ? io_in[31:27] : _GEN_31; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_144_bits = {{4'd0}, _T_136}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_37 = 5'h5 == _T_826 ? _T_144_bits : _GEN_32; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_38 = 5'h5 == _T_826 ? _T_14 : _GEN_33; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_39 = 5'h5 == _T_826 ? _T_30 : _GEN_34; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_41 = 5'h5 == _T_826 ? io_in[31:27] : _GEN_36; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_175_bits = {{5'd0}, _T_167}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_42 = 5'h6 == _T_826 ? _T_175_bits : _GEN_37; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_43 = 5'h6 == _T_826 ? _T_14 : _GEN_38; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_44 = 5'h6 == _T_826 ? _T_30 : _GEN_39; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_46 = 5'h6 == _T_826 ? io_in[31:27] : _GEN_41; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_202_bits = {{4'd0}, _T_194}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_47 = 5'h7 == _T_826 ? _T_202_bits : _GEN_42; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_48 = 5'h7 == _T_826 ? _T_14 : _GEN_43; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_49 = 5'h7 == _T_826 ? _T_30 : _GEN_44; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_51 = 5'h7 == _T_826 ? io_in[31:27] : _GEN_46; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_52 = 5'h8 == _T_826 ? _T_213 : _GEN_47; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_53 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_48; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_54 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_49; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_55 = 5'h8 == _T_826 ? _T_14 : _GEN_48; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_56 = 5'h8 == _T_826 ? io_in[31:27] : _GEN_51; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_57 = 5'h9 == _T_826 ? _T_233 : _GEN_52; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_58 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_53; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_59 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_54; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_60 = 5'h9 == _T_826 ? _T_14 : _GEN_55; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_61 = 5'h9 == _T_826 ? io_in[31:27] : _GEN_56; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_62 = 5'ha == _T_826 ? _T_249 : _GEN_57; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_63 = 5'ha == _T_826 ? io_in[11:7] : _GEN_58; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_64 = 5'ha == _T_826 ? 5'h0 : _GEN_59; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_65 = 5'ha == _T_826 ? _T_14 : _GEN_60; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_66 = 5'ha == _T_826 ? io_in[31:27] : _GEN_61; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_67 = 5'hb == _T_826 ? _T_314_bits : _GEN_62; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_68 = 5'hb == _T_826 ? _T_314_rd : _GEN_63; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_69 = 5'hb == _T_826 ? _T_314_rd : _GEN_64; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_70 = 5'hb == _T_826 ? _T_314_rs2 : _GEN_65; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_71 = 5'hb == _T_826 ? _T_314_rs3 : _GEN_66; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_72 = 5'hc == _T_826 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_73 = 5'hc == _T_826 ? _T_30 : _GEN_68; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_74 = 5'hc == _T_826 ? _T_30 : _GEN_69; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_75 = 5'hc == _T_826 ? _T_14 : _GEN_70; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_76 = 5'hc == _T_826 ? io_in[31:27] : _GEN_71; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_77 = 5'hd == _T_826 ? _T_461 : _GEN_72; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_78 = 5'hd == _T_826 ? 5'h0 : _GEN_73; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_79 = 5'hd == _T_826 ? _T_30 : _GEN_74; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_80 = 5'hd == _T_826 ? _T_14 : _GEN_75; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_81 = 5'hd == _T_826 ? io_in[31:27] : _GEN_76; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_82 = 5'he == _T_826 ? _T_528 : _GEN_77; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_83 = 5'he == _T_826 ? _T_30 : _GEN_78; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_84 = 5'he == _T_826 ? _T_30 : _GEN_79; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_85 = 5'he == _T_826 ? 5'h0 : _GEN_80; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_86 = 5'he == _T_826 ? io_in[31:27] : _GEN_81; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_87 = 5'hf == _T_826 ? _T_595 : _GEN_82; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_88 = 5'hf == _T_826 ? 5'h0 : _GEN_83; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_89 = 5'hf == _T_826 ? _T_30 : _GEN_84; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_90 = 5'hf == _T_826 ? 5'h0 : _GEN_85; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_91 = 5'hf == _T_826 ? io_in[31:27] : _GEN_86; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_616_bits = {{6'd0}, _T_611}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_92 = 5'h10 == _T_826 ? _T_616_bits : _GEN_87; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_93 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_88; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_94 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_89; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_95 = 5'h10 == _T_826 ? io_in[6:2] : _GEN_90; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_96 = 5'h10 == _T_826 ? io_in[31:27] : _GEN_91; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_631_bits = {{3'd0}, _T_627}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_97 = 5'h11 == _T_826 ? _T_631_bits : _GEN_92; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_98 = 5'h11 == _T_826 ? io_in[11:7] : _GEN_93; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_99 = 5'h11 == _T_826 ? 5'h2 : _GEN_94; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_100 = 5'h11 == _T_826 ? io_in[6:2] : _GEN_95; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_101 = 5'h11 == _T_826 ? io_in[31:27] : _GEN_96; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_646_bits = {{4'd0}, _T_642}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_102 = 5'h12 == _T_826 ? _T_646_bits : _GEN_97; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_103 = 5'h12 == _T_826 ? io_in[11:7] : _GEN_98; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_104 = 5'h12 == _T_826 ? 5'h2 : _GEN_99; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_105 = 5'h12 == _T_826 ? io_in[6:2] : _GEN_100; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_106 = 5'h12 == _T_826 ? io_in[31:27] : _GEN_101; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_661_bits = {{3'd0}, _T_657}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_107 = 5'h13 == _T_826 ? _T_661_bits : _GEN_102; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_108 = 5'h13 == _T_826 ? io_in[11:7] : _GEN_103; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_109 = 5'h13 == _T_826 ? 5'h2 : _GEN_104; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_110 = 5'h13 == _T_826 ? io_in[6:2] : _GEN_105; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_111 = 5'h13 == _T_826 ? io_in[31:27] : _GEN_106; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_112 = 5'h14 == _T_826 ? _T_722_bits : _GEN_107; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_113 = 5'h14 == _T_826 ? _T_722_rd : _GEN_108; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_114 = 5'h14 == _T_826 ? _T_722_rs1 : _GEN_109; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_115 = 5'h14 == _T_826 ? _T_722_rs2 : _GEN_110; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_116 = 5'h14 == _T_826 ? _T_722_rs3 : _GEN_111; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_742_bits = {{3'd0}, _T_738}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_117 = 5'h15 == _T_826 ? _T_742_bits : _GEN_112; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_118 = 5'h15 == _T_826 ? io_in[11:7] : _GEN_113; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_119 = 5'h15 == _T_826 ? 5'h2 : _GEN_114; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_120 = 5'h15 == _T_826 ? io_in[6:2] : _GEN_115; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_121 = 5'h15 == _T_826 ? io_in[31:27] : _GEN_116; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_762_bits = {{4'd0}, _T_758}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_122 = 5'h16 == _T_826 ? _T_762_bits : _GEN_117; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_123 = 5'h16 == _T_826 ? io_in[11:7] : _GEN_118; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_124 = 5'h16 == _T_826 ? 5'h2 : _GEN_119; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_125 = 5'h16 == _T_826 ? io_in[6:2] : _GEN_120; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_126 = 5'h16 == _T_826 ? io_in[31:27] : _GEN_121; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_782_bits = {{3'd0}, _T_778}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_127 = 5'h17 == _T_826 ? _T_782_bits : _GEN_122; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_128 = 5'h17 == _T_826 ? io_in[11:7] : _GEN_123; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_129 = 5'h17 == _T_826 ? 5'h2 : _GEN_124; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_130 = 5'h17 == _T_826 ? io_in[6:2] : _GEN_125; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_131 = 5'h17 == _T_826 ? io_in[31:27] : _GEN_126; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_132 = 5'h18 == _T_826 ? io_in : _GEN_127; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_133 = 5'h18 == _T_826 ? io_in[11:7] : _GEN_128; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_134 = 5'h18 == _T_826 ? io_in[19:15] : _GEN_129; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_135 = 5'h18 == _T_826 ? io_in[24:20] : _GEN_130; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_136 = 5'h18 == _T_826 ? io_in[31:27] : _GEN_131; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_137 = 5'h19 == _T_826 ? io_in : _GEN_132; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_138 = 5'h19 == _T_826 ? io_in[11:7] : _GEN_133; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_139 = 5'h19 == _T_826 ? io_in[19:15] : _GEN_134; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_140 = 5'h19 == _T_826 ? io_in[24:20] : _GEN_135; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_141 = 5'h19 == _T_826 ? io_in[31:27] : _GEN_136; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_142 = 5'h1a == _T_826 ? io_in : _GEN_137; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_143 = 5'h1a == _T_826 ? io_in[11:7] : _GEN_138; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_144 = 5'h1a == _T_826 ? io_in[19:15] : _GEN_139; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_145 = 5'h1a == _T_826 ? io_in[24:20] : _GEN_140; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_146 = 5'h1a == _T_826 ? io_in[31:27] : _GEN_141; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_147 = 5'h1b == _T_826 ? io_in : _GEN_142; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_148 = 5'h1b == _T_826 ? io_in[11:7] : _GEN_143; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_149 = 5'h1b == _T_826 ? io_in[19:15] : _GEN_144; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_150 = 5'h1b == _T_826 ? io_in[24:20] : _GEN_145; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_151 = 5'h1b == _T_826 ? io_in[31:27] : _GEN_146; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_152 = 5'h1c == _T_826 ? io_in : _GEN_147; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_153 = 5'h1c == _T_826 ? io_in[11:7] : _GEN_148; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_154 = 5'h1c == _T_826 ? io_in[19:15] : _GEN_149; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_155 = 5'h1c == _T_826 ? io_in[24:20] : _GEN_150; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_156 = 5'h1c == _T_826 ? io_in[31:27] : _GEN_151; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_157 = 5'h1d == _T_826 ? io_in : _GEN_152; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_158 = 5'h1d == _T_826 ? io_in[11:7] : _GEN_153; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_159 = 5'h1d == _T_826 ? io_in[19:15] : _GEN_154; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_160 = 5'h1d == _T_826 ? io_in[24:20] : _GEN_155; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_161 = 5'h1d == _T_826 ? io_in[31:27] : _GEN_156; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_162 = 5'h1e == _T_826 ? io_in : _GEN_157; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_163 = 5'h1e == _T_826 ? io_in[11:7] : _GEN_158; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_164 = 5'h1e == _T_826 ? io_in[19:15] : _GEN_159; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_165 = 5'h1e == _T_826 ? io_in[24:20] : _GEN_160; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_166 = 5'h1e == _T_826 ? io_in[31:27] : _GEN_161; // @[el2_ifu_compress.scala 194:12]
assign io_out_bits = 5'h1f == _T_826 ? io_in : _GEN_162; // @[el2_ifu_compress.scala 194:12]
assign io_out_rd = 5'h1f == _T_826 ? io_in[11:7] : _GEN_163; // @[el2_ifu_compress.scala 194:12]
assign io_out_rs1 = 5'h1f == _T_826 ? io_in[19:15] : _GEN_164; // @[el2_ifu_compress.scala 194:12]
assign io_out_rs2 = 5'h1f == _T_826 ? io_in[24:20] : _GEN_165; // @[el2_ifu_compress.scala 194:12]
assign io_out_rs3 = 5'h1f == _T_826 ? io_in[31:27] : _GEN_166; // @[el2_ifu_compress.scala 194:12]
assign io_rvc = io_in[1:0] != 2'h3; // @[el2_ifu_compress.scala 192:12]
endmodule

25
el2_ifu_compress_ctl.anno.json
View File

@ -1,25 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout",
"sources":[
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_compress_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1995
el2_ifu_compress_ctl.fir
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File diff suppressed because it is too large Load Diff

511
el2_ifu_compress_ctl.v
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@ -1,511 +0,0 @@
module el2_ifu_compress_ctl(
input clock,
input reset,
input [15:0] io_din,
output [31:0] io_dout
);
wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 17:53]
wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 21:46]
wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 21:80]
wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 21:113]
wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 23:50]
wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 23:101]
wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 23:99]
wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 23:86]
wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 25:47]
wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 25:81]
wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 25:115]
wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 26:26]
wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 28:53]
wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 28:67]
wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 28:88]
wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 30:24]
wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 30:39]
wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 30:63]
wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 30:83]
wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 30:102]
wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 31:22]
wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 31:42]
wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 31:62]
wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 31:83]
wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 33:50]
wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 33:87]
wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 33:65]
wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 34:23]
wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 33:102]
wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 34:38]
wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 34:82]
wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 34:62]
wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 35:23]
wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 34:97]
wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 35:58]
wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 35:38]
wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 35:93]
wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 35:73]
wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 35:108]
wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 40:59]
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 40:107]
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_454 = _T_453 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 41:50]
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_478 = _T_477 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 41:94]
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_501 = _T_500 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 42:94]
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 42:49]
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 42:109]
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 43:26]
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 43:48]
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 43:70]
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 43:93]
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 44:26]
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 50:20]
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 51:19]
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 55:33]
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 55:58]
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 55:79]
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 55:104]
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 56:24]
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 56:48]
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 56:69]
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 56:94]
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 57:22]
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 57:46]
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 57:65]
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 59:38]
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 59:63]
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 59:87]
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 60:27]
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_706 = _T_705 & _T_50; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 60:51]
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 60:89]
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 61:27]
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 61:51]
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 61:75]
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 61:99]
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 62:27]
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 62:54]
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 64:34]
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 64:54]
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 64:74]
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 64:94]
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 64:114]
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 68:36]
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 12:83]
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 68:76]
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 68:57]
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 70:66]
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 70:47]
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 72:33]
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 74:34]
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 76:39]
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_899 = _T_898 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_900 = _T_899 & _T_40; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 12:110]
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 84:42]
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 86:53]
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 86:71]
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 92:45]
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 96:44]
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 96:70]
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 96:95]
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 96:121]
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 98:45]
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1194 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1195 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1196 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1197 = _T_1192 | _T_1193; // @[Mux.scala 27:72]
wire [4:0] _T_1198 = _T_1197 | _T_1194; // @[Mux.scala 27:72]
wire [4:0] _T_1199 = _T_1198 | _T_1195; // @[Mux.scala 27:72]
wire [4:0] l1_11 = _T_1199 | _T_1196; // @[Mux.scala 27:72]
wire [4:0] _T_1210 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1211 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1212 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1213 = _T_1210 | _T_1211; // @[Mux.scala 27:72]
wire [4:0] l1_19 = _T_1213 | _T_1212; // @[Mux.scala 27:72]
wire [4:0] _T_1219 = {3'h0,1'h0,out_20}; // @[Cat.scala 29:58]
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 114:67]
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
wire [10:0] sjald_1 = {io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
wire [19:0] sjald = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],sjald_1}; // @[Cat.scala 29:58]
wire [9:0] _T_1296 = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12]}; // @[Cat.scala 29:58]
wire [19:0] sluimmd = {_T_1296,io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],rs2d}; // @[Cat.scala 29:58]
wire [11:0] _T_1314 = {simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[4:0]}; // @[Cat.scala 29:58]
wire [11:0] _T_1317 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1325 = {simm9d[5],simm9d[5],simm9d[5],simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1328 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1331 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1333 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
wire [11:0] _T_1339 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
wire [11:0] _T_1342 = simm5_0 ? _T_1314 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1343 = uimm9_2 ? _T_1317 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1344 = rdeq2 ? _T_1325 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1345 = ulwimm6_2 ? _T_1328 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1346 = ulwspimm7_2 ? _T_1331 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1347 = uimm5_0 ? _T_1333 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1348 = _T_228 ? _T_1339 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1349 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1350 = _T_1342 | _T_1343; // @[Mux.scala 27:72]
wire [11:0] _T_1351 = _T_1350 | _T_1344; // @[Mux.scala 27:72]
wire [11:0] _T_1352 = _T_1351 | _T_1345; // @[Mux.scala 27:72]
wire [11:0] _T_1353 = _T_1352 | _T_1346; // @[Mux.scala 27:72]
wire [11:0] _T_1354 = _T_1353 | _T_1347; // @[Mux.scala 27:72]
wire [11:0] _T_1355 = _T_1354 | _T_1348; // @[Mux.scala 27:72]
wire [11:0] _T_1356 = _T_1355 | _T_1349; // @[Mux.scala 27:72]
wire [11:0] l2_31 = l1[31:20] | _T_1356; // @[el2_ifu_compress_ctl.scala 133:25]
wire [7:0] _T_1363 = _T_228 ? sjald[19:12] : 8'h0; // @[Mux.scala 27:72]
wire [7:0] _T_1364 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
wire [7:0] _T_1365 = _T_1363 | _T_1364; // @[Mux.scala 27:72]
wire [7:0] l2_19 = l1[19:12] | _T_1365; // @[el2_ifu_compress_ctl.scala 143:25]
wire [31:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
wire [6:0] _T_1400 = {sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[7:5]}; // @[Cat.scala 29:58]
wire [6:0] _T_1403 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
wire [6:0] _T_1406 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
wire [6:0] _T_1407 = _T_234 ? _T_1400 : 7'h0; // @[Mux.scala 27:72]
wire [6:0] _T_1408 = _T_854 ? _T_1403 : 7'h0; // @[Mux.scala 27:72]
wire [6:0] _T_1409 = _T_807 ? _T_1406 : 7'h0; // @[Mux.scala 27:72]
wire [6:0] _T_1410 = _T_1407 | _T_1408; // @[Mux.scala 27:72]
wire [6:0] _T_1411 = _T_1410 | _T_1409; // @[Mux.scala 27:72]
wire [6:0] l3_31 = l2[31:25] | _T_1411; // @[el2_ifu_compress_ctl.scala 151:25]
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 154:17]
wire [4:0] _T_1417 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
wire [4:0] _T_1422 = _T_234 ? _T_1417 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1423 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1424 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1425 = _T_1422 | _T_1423; // @[Mux.scala 27:72]
wire [4:0] _T_1426 = _T_1425 | _T_1424; // @[Mux.scala 27:72]
wire [4:0] l3_11 = l2[11:7] | _T_1426; // @[el2_ifu_compress_ctl.scala 156:24]
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
wire _T_1437 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1438 = _T_1437 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1439 = _T_1438 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1442 = _T_1439 & _T_147; // @[el2_ifu_compress_ctl.scala 162:39]
wire _T_1450 = _T_1437 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1451 = _T_1450 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1454 = _T_1451 & _T_147; // @[el2_ifu_compress_ctl.scala 162:79]
wire _T_1455 = _T_1442 | _T_1454; // @[el2_ifu_compress_ctl.scala 162:54]
wire _T_1464 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1465 = _T_1464 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1466 = _T_1455 | _T_1465; // @[el2_ifu_compress_ctl.scala 162:94]
wire _T_1474 = _T_1437 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1475 = _T_1474 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1478 = _T_1475 & _T_147; // @[el2_ifu_compress_ctl.scala 163:55]
wire _T_1479 = _T_1466 | _T_1478; // @[el2_ifu_compress_ctl.scala 163:30]
wire _T_1487 = _T_1437 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1488 = _T_1487 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1491 = _T_1488 & _T_147; // @[el2_ifu_compress_ctl.scala 163:96]
wire _T_1492 = _T_1479 | _T_1491; // @[el2_ifu_compress_ctl.scala 163:70]
wire _T_1501 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1502 = _T_1501 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1503 = _T_1492 | _T_1502; // @[el2_ifu_compress_ctl.scala 163:111]
wire _T_1510 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1511 = _T_1510 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1512 = _T_1511 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1513 = _T_1503 | _T_1512; // @[el2_ifu_compress_ctl.scala 164:29]
wire _T_1521 = _T_1437 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1522 = _T_1521 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1525 = _T_1522 & _T_147; // @[el2_ifu_compress_ctl.scala 164:79]
wire _T_1526 = _T_1513 | _T_1525; // @[el2_ifu_compress_ctl.scala 164:54]
wire _T_1533 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1534 = _T_1533 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1535 = _T_1534 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1536 = _T_1526 | _T_1535; // @[el2_ifu_compress_ctl.scala 164:94]
wire _T_1545 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1546 = _T_1545 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1547 = _T_1536 | _T_1546; // @[el2_ifu_compress_ctl.scala 164:118]
wire _T_1555 = _T_1437 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1556 = _T_1555 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1559 = _T_1556 & _T_147; // @[el2_ifu_compress_ctl.scala 165:28]
wire _T_1560 = _T_1547 | _T_1559; // @[el2_ifu_compress_ctl.scala 164:144]
wire _T_1567 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1568 = _T_1567 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1569 = _T_1568 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1570 = _T_1560 | _T_1569; // @[el2_ifu_compress_ctl.scala 165:43]
wire _T_1579 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1580 = _T_1579 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1581 = _T_1570 | _T_1580; // @[el2_ifu_compress_ctl.scala 165:67]
wire _T_1589 = _T_1437 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1590 = _T_1589 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1593 = _T_1590 & _T_147; // @[el2_ifu_compress_ctl.scala 166:28]
wire _T_1594 = _T_1581 | _T_1593; // @[el2_ifu_compress_ctl.scala 165:94]
wire _T_1602 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1603 = _T_1602 & _T_38; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1604 = _T_1603 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1605 = _T_1604 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1606 = _T_1594 | _T_1605; // @[el2_ifu_compress_ctl.scala 166:43]
wire _T_1615 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1616 = _T_1615 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1617 = _T_1606 | _T_1616; // @[el2_ifu_compress_ctl.scala 166:71]
wire _T_1625 = _T_1437 & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1626 = _T_1625 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1629 = _T_1626 & _T_147; // @[el2_ifu_compress_ctl.scala 167:28]
wire _T_1630 = _T_1617 | _T_1629; // @[el2_ifu_compress_ctl.scala 166:97]
wire _T_1636 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1637 = _T_1636 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1638 = _T_1637 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1639 = _T_1630 | _T_1638; // @[el2_ifu_compress_ctl.scala 167:43]
wire _T_1648 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1649 = _T_1648 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1650 = _T_1639 | _T_1649; // @[el2_ifu_compress_ctl.scala 167:67]
wire _T_1658 = _T_1437 & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1659 = _T_1658 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1662 = _T_1659 & _T_147; // @[el2_ifu_compress_ctl.scala 168:28]
wire _T_1663 = _T_1650 | _T_1662; // @[el2_ifu_compress_ctl.scala 167:93]
wire _T_1669 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1670 = _T_1669 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1671 = _T_1670 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1672 = _T_1663 | _T_1671; // @[el2_ifu_compress_ctl.scala 168:43]
wire _T_1680 = _T_1437 & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1681 = _T_1680 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1684 = _T_1681 & _T_147; // @[el2_ifu_compress_ctl.scala 168:91]
wire _T_1685 = _T_1672 | _T_1684; // @[el2_ifu_compress_ctl.scala 168:66]
wire _T_1694 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1695 = _T_1694 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1696 = _T_1685 | _T_1695; // @[el2_ifu_compress_ctl.scala 168:106]
wire _T_1702 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1703 = _T_1702 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1704 = _T_1703 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1705 = _T_1696 | _T_1704; // @[el2_ifu_compress_ctl.scala 169:29]
wire _T_1711 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1712 = _T_1711 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1713 = _T_1712 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1714 = _T_1705 | _T_1713; // @[el2_ifu_compress_ctl.scala 169:52]
wire _T_1720 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1721 = _T_1720 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1722 = _T_1714 | _T_1721; // @[el2_ifu_compress_ctl.scala 169:75]
wire _T_1731 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1732 = _T_1731 & io_din[0]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1733 = _T_1722 | _T_1732; // @[el2_ifu_compress_ctl.scala 169:98]
wire _T_1740 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1741 = _T_1740 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1744 = _T_1741 & _T_147; // @[el2_ifu_compress_ctl.scala 170:54]
wire _T_1745 = _T_1733 | _T_1744; // @[el2_ifu_compress_ctl.scala 170:29]
wire _T_1754 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1755 = _T_1754 & io_din[1]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1758 = _T_1755 & _T_147; // @[el2_ifu_compress_ctl.scala 170:96]
wire _T_1759 = _T_1745 | _T_1758; // @[el2_ifu_compress_ctl.scala 170:69]
wire _T_1768 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1769 = _T_1768 & _T_830; // @[el2_ifu_compress_ctl.scala 12:110]
wire _T_1770 = _T_1759 | _T_1769; // @[el2_ifu_compress_ctl.scala 170:111]
wire _T_1777 = _T_1720 & _T_147; // @[el2_ifu_compress_ctl.scala 171:50]
wire legal = _T_1770 | _T_1777; // @[el2_ifu_compress_ctl.scala 171:30]
wire [9:0] _T_1787 = {legal,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
wire [18:0] _T_1796 = {_T_1787,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
wire [27:0] _T_1805 = {_T_1796,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
wire [31:0] _T_1809 = {_T_1805,legal,legal,legal,legal}; // @[Cat.scala 29:58]
assign io_dout = l3 & _T_1809; // @[el2_ifu_compress_ctl.scala 173:10]
endmodule

136
el2_ifu_ic_mem.anno.json
View File

@ -1,136 +0,0 @@
[
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit",
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"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override",
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"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en",
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]
},
{
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"sources":[
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en",
"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_ic_mem"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

3308
el2_ifu_ic_mem.fir
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1039
el2_ifu_ic_mem.v
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18
el2_ifu_iccm_mem.anno.json
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@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_iccm_mem"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

640
el2_ifu_iccm_mem.fir
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@ -1,640 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_iccm_mem :
module el2_ifu_iccm_mem :
input clock : Clock
input reset : AsyncReset
output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>}
io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
node _T = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 24:38]
node _T_1 = eq(_T, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 24:43]
node _T_2 = bits(_T_1, 0, 0) @[el2_ifu_iccm_mem.scala 24:51]
node addr_inc = mux(_T_2, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_iccm_mem.scala 24:21]
node _T_3 = bits(io.iccm_rw_addr, 14, 0) @[el2_ifu_iccm_mem.scala 25:38]
node _T_4 = add(_T_3, addr_inc) @[el2_ifu_iccm_mem.scala 25:54]
node addr_bank_inc = tail(_T_4, 1) @[el2_ifu_iccm_mem.scala 25:54]
wire iccm_bank_wr_data : UInt<39>[4] @[el2_ifu_iccm_mem.scala 27:35]
node _T_5 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
iccm_bank_wr_data[0] <= _T_5 @[el2_ifu_iccm_mem.scala 29:32]
node _T_6 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
iccm_bank_wr_data[1] <= _T_6 @[el2_ifu_iccm_mem.scala 30:36]
node _T_7 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32]
node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36]
node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_11 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_13 = or(_T_10, _T_12) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_0 = and(io.iccm_wren, _T_13) @[el2_ifu_iccm_mem.scala 33:64]
node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_16 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_18 = or(_T_15, _T_17) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_1 = and(io.iccm_wren, _T_18) @[el2_ifu_iccm_mem.scala 33:64]
node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_21 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_22 = eq(_T_21, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_23 = or(_T_20, _T_22) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_2 = and(io.iccm_wren, _T_23) @[el2_ifu_iccm_mem.scala 33:64]
node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_26 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64]
node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99]
node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64]
node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139]
node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106]
node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99]
node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64]
node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139]
node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106]
node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99]
node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64]
node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139]
node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106]
node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99]
node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64]
node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139]
node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106]
node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72]
node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72]
node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72]
node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72]
node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
wire addr_bank : UInt<12>[4] @[el2_ifu_iccm_mem.scala 38:23]
node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 40:41]
node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 40:8]
node _T_60 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 39:54]
addr_bank[0] <= _T_60 @[el2_ifu_iccm_mem.scala 39:48]
node _T_61 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
node _T_62 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
node _T_63 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
node _T_64 = eq(_T_63, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 40:41]
node _T_65 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
node _T_66 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
node _T_67 = mux(_T_64, _T_65, _T_66) @[el2_ifu_iccm_mem.scala 40:8]
node _T_68 = mux(_T_61, _T_62, _T_67) @[el2_ifu_iccm_mem.scala 39:54]
addr_bank[1] <= _T_68 @[el2_ifu_iccm_mem.scala 39:48]
node _T_69 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
node _T_70 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
node _T_71 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
node _T_72 = eq(_T_71, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 40:41]
node _T_73 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
node _T_74 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
node _T_75 = mux(_T_72, _T_73, _T_74) @[el2_ifu_iccm_mem.scala 40:8]
node _T_76 = mux(_T_69, _T_70, _T_75) @[el2_ifu_iccm_mem.scala 39:54]
addr_bank[2] <= _T_76 @[el2_ifu_iccm_mem.scala 39:48]
node _T_77 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
node _T_78 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
node _T_79 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
node _T_80 = eq(_T_79, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 40:41]
node _T_81 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
node _T_82 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
node _T_83 = mux(_T_80, _T_81, _T_82) @[el2_ifu_iccm_mem.scala 40:8]
node _T_84 = mux(_T_77, _T_78, _T_83) @[el2_ifu_iccm_mem.scala 39:54]
addr_bank[3] <= _T_84 @[el2_ifu_iccm_mem.scala 39:48]
smem _T_85 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
smem _T_86 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
smem _T_87 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
smem _T_88 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
node _T_89 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 47:68]
node _T_90 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 47:68]
node _T_91 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 47:68]
node _T_92 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 47:68]
wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 47:51]
write_vec[0] <= _T_89 @[el2_ifu_iccm_mem.scala 47:51]
write_vec[1] <= _T_90 @[el2_ifu_iccm_mem.scala 47:51]
write_vec[2] <= _T_91 @[el2_ifu_iccm_mem.scala 47:51]
write_vec[3] <= _T_92 @[el2_ifu_iccm_mem.scala 47:51]
node _T_93 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
node _T_94 = and(iccm_clken_0, _T_93) @[el2_ifu_iccm_mem.scala 48:70]
node _T_95 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
node _T_96 = and(iccm_clken_1, _T_95) @[el2_ifu_iccm_mem.scala 48:70]
node _T_97 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
node _T_98 = and(iccm_clken_2, _T_97) @[el2_ifu_iccm_mem.scala 48:70]
node _T_99 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
node _T_100 = and(iccm_clken_3, _T_99) @[el2_ifu_iccm_mem.scala 48:70]
wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 48:53]
read_enable[0] <= _T_94 @[el2_ifu_iccm_mem.scala 48:53]
read_enable[1] <= _T_96 @[el2_ifu_iccm_mem.scala 48:53]
read_enable[2] <= _T_98 @[el2_ifu_iccm_mem.scala 48:53]
read_enable[3] <= _T_100 @[el2_ifu_iccm_mem.scala 48:53]
wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 50:28]
when write_vec[0] : @[el2_ifu_iccm_mem.scala 54:54]
infer mport _T_101 = _T_85[addr_bank[0]], clock @[el2_ifu_iccm_mem.scala 54:66]
_T_101 <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 54:81]
skip @[el2_ifu_iccm_mem.scala 54:54]
when write_vec[1] : @[el2_ifu_iccm_mem.scala 54:54]
infer mport _T_102 = _T_86[addr_bank[1]], clock @[el2_ifu_iccm_mem.scala 54:66]
_T_102 <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 54:81]
skip @[el2_ifu_iccm_mem.scala 54:54]
when write_vec[2] : @[el2_ifu_iccm_mem.scala 54:54]
infer mport _T_103 = _T_87[addr_bank[2]], clock @[el2_ifu_iccm_mem.scala 54:66]
_T_103 <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 54:81]
skip @[el2_ifu_iccm_mem.scala 54:54]
when write_vec[3] : @[el2_ifu_iccm_mem.scala 54:54]
infer mport _T_104 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 54:66]
_T_104 <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 54:81]
skip @[el2_ifu_iccm_mem.scala 54:54]
infer mport _T_105 = _T_85[addr_bank[0]], clock @[el2_ifu_iccm_mem.scala 56:77]
reg _T_106 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when read_enable[0] : @[Reg.scala 28:19]
_T_106 <= _T_105 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
iccm_bank_dout[0] <= _T_106 @[el2_ifu_iccm_mem.scala 56:53]
infer mport _T_107 = _T_86[addr_bank[1]], clock @[el2_ifu_iccm_mem.scala 56:77]
reg _T_108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when read_enable[1] : @[Reg.scala 28:19]
_T_108 <= _T_107 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
iccm_bank_dout[1] <= _T_108 @[el2_ifu_iccm_mem.scala 56:53]
infer mport _T_109 = _T_87[addr_bank[2]], clock @[el2_ifu_iccm_mem.scala 56:77]
reg _T_110 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when read_enable[2] : @[Reg.scala 28:19]
_T_110 <= _T_109 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
iccm_bank_dout[2] <= _T_110 @[el2_ifu_iccm_mem.scala 56:53]
infer mport _T_111 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 56:77]
reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when read_enable[3] : @[Reg.scala 28:19]
_T_112 <= _T_111 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
iccm_bank_dout[3] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53]
wire redundant_valid : UInt<2>
redundant_valid <= UInt<1>("h00")
wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 62:31]
redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 65:105]
node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 65:145]
node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 65:71]
node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 66:37]
node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 66:77]
node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 65:179]
node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 65:105]
node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 65:145]
node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 65:71]
node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 66:37]
node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 66:77]
node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 65:179]
node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 65:105]
node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 65:145]
node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 65:71]
node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 66:37]
node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 66:77]
node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 65:179]
node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 65:105]
node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 65:145]
node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 65:71]
node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 66:37]
node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 66:77]
node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 65:179]
node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58]
node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58]
node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58]
node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 67:105]
node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 67:145]
node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 67:71]
node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 68:37]
node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 68:77]
node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 67:179]
node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 67:105]
node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 67:145]
node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 67:71]
node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 68:37]
node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 68:77]
node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 67:179]
node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 67:105]
node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 67:145]
node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 67:71]
node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 68:37]
node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 68:77]
node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 67:179]
node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 67:105]
node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 67:145]
node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 67:71]
node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 68:37]
node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 68:77]
node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 67:179]
node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58]
node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58]
node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58]
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 70:27]
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 70:27]
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 71:27]
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 71:27]
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 72:28]
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47]
node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 76:47]
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:47]
node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 77:36]
node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:64]
node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 77:53]
node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 77:51]
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72]
node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72]
node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47]
node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 76:47]
node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:47]
node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 77:36]
node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:64]
node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 77:53]
node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 77:51]
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72]
node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72]
node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47]
node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 76:47]
node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:47]
node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 77:36]
node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:64]
node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 77:53]
node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 77:51]
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72]
node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72]
node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47]
node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 76:47]
node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:47]
node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 77:36]
node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:64]
node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 77:53]
node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 77:51]
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = or(_T_292, _T_293) @[Mux.scala 27:72]
node _T_296 = or(_T_295, _T_294) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72]
wire redundant_lru : UInt<1>
redundant_lru <= UInt<1>("h00")
node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 79:20]
node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 79:35]
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 80:35]
node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 81:63]
node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 81:78]
node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 81:67]
node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 81:83]
node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 81:98]
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 81:50]
node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:55]
node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 82:84]
node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:74]
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 82:29]
reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when redundant_lru_en : @[Reg.scala 28:19]
_T_306 <= redundant_lru_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 83:17]
node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 84:52]
reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when r0_addr_en : @[Reg.scala 28:19]
_T_308 <= _T_307 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 84:24]
node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 85:52]
node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 85:85]
reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_310 : @[Reg.scala 28:19]
_T_311 <= _T_309 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 85:24]
node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 86:57]
reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_312 : @[Reg.scala 28:19]
_T_313 <= UInt<1>("h01") @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when r0_addr_en : @[Reg.scala 28:19]
_T_314 <= UInt<1>("h01") @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58]
redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 86:19]
node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 88:45]
node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 88:85]
node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 88:61]
node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:22]
node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:48]
node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 89:26]
node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:70]
node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:75]
node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 89:52]
node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 88:102]
node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 89:101]
node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 89:84]
node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 89:105]
node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 90:6]
node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 90:21]
node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 89:121]
node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 91:49]
node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:73]
node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 91:52]
node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:100]
node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 91:122]
node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 91:127]
node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 91:104]
node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 91:78]
node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 91:137]
node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 92:20]
node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 92:44]
node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 91:31]
node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 93:78]
reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_342 : @[Reg.scala 28:19]
_T_343 <= redundant_data0_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 93:21]
node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 95:45]
node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 95:85]
node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 95:61]
node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:22]
node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:48]
node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 96:26]
node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:70]
node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:75]
node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 96:52]
node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 95:102]
node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 96:101]
node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 96:84]
node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 96:105]
node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:6]
node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 97:21]
node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 96:121]
node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 98:49]
node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:73]
node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 98:52]
node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:100]
node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 98:122]
node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 98:127]
node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 98:104]
node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 98:78]
node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 98:137]
node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 99:20]
node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 99:44]
node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 98:31]
node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 100:78]
reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_370 : @[Reg.scala 28:19]
_T_371 <= redundant_data1_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21]
node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:60]
reg _T_373 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when UInt<1>("h01") : @[Reg.scala 28:19]
_T_373 <= _T_372 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
iccm_rd_addr_lo_q <= _T_373 @[el2_ifu_iccm_mem.scala 102:34]
node _T_374 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
iccm_rd_addr_hi_q <= _T_374 @[el2_ifu_iccm_mem.scala 103:34]
node _T_375 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:104]
node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
node _T_378 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
node _T_379 = eq(_T_378, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:104]
node _T_380 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
node _T_381 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
node _T_382 = eq(_T_381, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:104]
node _T_383 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
node _T_384 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
node _T_385 = eq(_T_384, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:104]
node _T_386 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
node _T_387 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_388 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_389 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_390 = mux(_T_385, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_391 = or(_T_387, _T_388) @[Mux.scala 27:72]
node _T_392 = or(_T_391, _T_389) @[Mux.scala 27:72]
node _T_393 = or(_T_392, _T_390) @[Mux.scala 27:72]
wire _T_394 : UInt<32> @[Mux.scala 27:72]
_T_394 <= _T_393 @[Mux.scala 27:72]
node _T_395 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_397 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_398 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_399 = eq(_T_398, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_400 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_401 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_402 = eq(_T_401, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_403 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_404 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
node _T_405 = eq(_T_404, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_406 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_407 = mux(_T_396, _T_397, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_408 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_409 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_410 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_411 = or(_T_407, _T_408) @[Mux.scala 27:72]
node _T_412 = or(_T_411, _T_409) @[Mux.scala 27:72]
node _T_413 = or(_T_412, _T_410) @[Mux.scala 27:72]
wire _T_414 : UInt<32> @[Mux.scala 27:72]
_T_414 <= _T_413 @[Mux.scala 27:72]
node iccm_rd_data_pre = cat(_T_394, _T_414) @[Cat.scala 29:58]
node _T_415 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 108:43]
node _T_416 = bits(_T_415, 0, 0) @[el2_ifu_iccm_mem.scala 108:53]
node _T_417 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_418 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 108:89]
node _T_419 = cat(_T_417, _T_418) @[Cat.scala 29:58]
node _T_420 = mux(_T_416, _T_419, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 108:25]
io.iccm_rd_data <= _T_420 @[el2_ifu_iccm_mem.scala 108:19]
node _T_421 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_422 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_423 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_424 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_425 = mux(_T_421, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_426 = mux(_T_422, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_427 = mux(_T_423, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_428 = mux(_T_424, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_429 = or(_T_425, _T_426) @[Mux.scala 27:72]
node _T_430 = or(_T_429, _T_427) @[Mux.scala 27:72]
node _T_431 = or(_T_430, _T_428) @[Mux.scala 27:72]
wire _T_432 : UInt<39> @[Mux.scala 27:72]
_T_432 <= _T_431 @[Mux.scala 27:72]
node _T_433 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_434 = eq(_T_433, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_435 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_436 = eq(_T_435, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_437 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_438 = eq(_T_437, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_439 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_440 = eq(_T_439, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_441 = mux(_T_434, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_442 = mux(_T_436, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_443 = mux(_T_438, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_444 = mux(_T_440, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_445 = or(_T_441, _T_442) @[Mux.scala 27:72]
node _T_446 = or(_T_445, _T_443) @[Mux.scala 27:72]
node _T_447 = or(_T_446, _T_444) @[Mux.scala 27:72]
wire _T_448 : UInt<39> @[Mux.scala 27:72]
_T_448 <= _T_447 @[Mux.scala 27:72]
node _T_449 = cat(_T_432, _T_448) @[Cat.scala 29:58]
io.iccm_rd_data_ecc <= _T_449 @[el2_ifu_iccm_mem.scala 109:23]
node _T_450 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:104]
node _T_452 = bits(iccm_bank_dout_fn_1, 38, 0) @[el2_ifu_iccm_mem.scala 111:151]
node _T_453 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
node _T_454 = eq(_T_453, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:104]
node _T_455 = bits(iccm_bank_dout_fn_2, 38, 0) @[el2_ifu_iccm_mem.scala 111:151]
node _T_456 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
node _T_457 = eq(_T_456, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:104]
node _T_458 = bits(iccm_bank_dout_fn_3, 38, 0) @[el2_ifu_iccm_mem.scala 111:151]
node _T_459 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
node _T_460 = eq(_T_459, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:104]
node _T_461 = bits(iccm_bank_dout_fn_0, 38, 0) @[el2_ifu_iccm_mem.scala 111:151]
node _T_462 = mux(_T_451, _T_452, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_463 = mux(_T_454, _T_455, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_464 = mux(_T_457, _T_458, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_465 = mux(_T_460, _T_461, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_466 = or(_T_462, _T_463) @[Mux.scala 27:72]
node _T_467 = or(_T_466, _T_464) @[Mux.scala 27:72]
node _T_468 = or(_T_467, _T_465) @[Mux.scala 27:72]
wire _T_469 : UInt<39> @[Mux.scala 27:72]
_T_469 <= _T_468 @[Mux.scala 27:72]
node _T_470 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 112:79]
node _T_472 = bits(iccm_bank_dout_fn_0, 38, 0) @[el2_ifu_iccm_mem.scala 112:108]
node _T_473 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
node _T_474 = eq(_T_473, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 112:79]
node _T_475 = bits(iccm_bank_dout_fn_1, 38, 0) @[el2_ifu_iccm_mem.scala 112:108]
node _T_476 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
node _T_477 = eq(_T_476, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 112:79]
node _T_478 = bits(iccm_bank_dout_fn_2, 38, 0) @[el2_ifu_iccm_mem.scala 112:108]
node _T_479 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
node _T_480 = eq(_T_479, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 112:79]
node _T_481 = bits(iccm_bank_dout_fn_3, 38, 0) @[el2_ifu_iccm_mem.scala 112:108]
node _T_482 = mux(_T_471, _T_472, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_483 = mux(_T_474, _T_475, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_484 = mux(_T_477, _T_478, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_485 = mux(_T_480, _T_481, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_486 = or(_T_482, _T_483) @[Mux.scala 27:72]
node _T_487 = or(_T_486, _T_484) @[Mux.scala 27:72]
node _T_488 = or(_T_487, _T_485) @[Mux.scala 27:72]
wire _T_489 : UInt<39> @[Mux.scala 27:72]
_T_489 <= _T_488 @[Mux.scala 27:72]
node _T_490 = cat(_T_469, _T_489) @[Cat.scala 29:58]
io.iccm_rd_data_ecc <= _T_490 @[el2_ifu_iccm_mem.scala 111:23]

598
el2_ifu_iccm_mem.v
View File

@ -1,598 +0,0 @@
module el2_ifu_iccm_mem(
input clock,
input reset,
input io_clk_override,
input io_iccm_wren,
input io_iccm_rden,
input [14:0] io_iccm_rw_addr,
input io_iccm_buf_correct_ecc,
input io_iccm_correction_state,
input [2:0] io_iccm_wr_size,
input [77:0] io_iccm_wr_data,
output [63:0] io_iccm_rd_data,
output [77:0] io_iccm_rd_data_ecc,
input io_scan_mode
);
`ifdef RANDOMIZE_MEM_INIT
reg [63:0] _RAND_0;
reg [63:0] _RAND_2;
reg [63:0] _RAND_4;
reg [63:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_1;
reg [31:0] _RAND_3;
reg [31:0] _RAND_5;
reg [31:0] _RAND_7;
reg [63:0] _RAND_8;
reg [63:0] _RAND_9;
reg [63:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_15;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [63:0] _RAND_18;
reg [63:0] _RAND_19;
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
reg [38:0] _T_85 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_85__T_105_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_85__T_105_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_85__T_101_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_85__T_101_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_85__T_101_mask; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_85__T_101_en; // @[el2_ifu_iccm_mem.scala 43:59]
reg [11:0] _T_85__T_105_addr_pipe_0;
reg [38:0] _T_86 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_86__T_107_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_86__T_107_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_86__T_102_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_86__T_102_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_86__T_102_mask; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_86__T_102_en; // @[el2_ifu_iccm_mem.scala 43:59]
reg [11:0] _T_86__T_107_addr_pipe_0;
reg [38:0] _T_87 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_87__T_109_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_87__T_109_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_87__T_103_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_87__T_103_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_87__T_103_mask; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_87__T_103_en; // @[el2_ifu_iccm_mem.scala 43:59]
reg [11:0] _T_87__T_109_addr_pipe_0;
reg [38:0] _T_88 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_88__T_111_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_88__T_111_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire [38:0] _T_88__T_104_data; // @[el2_ifu_iccm_mem.scala 43:59]
wire [11:0] _T_88__T_104_addr; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_88__T_104_mask; // @[el2_ifu_iccm_mem.scala 43:59]
wire _T_88__T_104_en; // @[el2_ifu_iccm_mem.scala 43:59]
reg [11:0] _T_88__T_111_addr_pipe_0;
wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
wire [14:0] _GEN_32 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_32; // @[el2_ifu_iccm_mem.scala 25:54]
wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_12 = addr_bank_inc[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_13 = _T_10 | _T_12; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_0 = io_iccm_wren & _T_13; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_15 = io_iccm_rw_addr[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_17 = addr_bank_inc[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_18 = _T_15 | _T_17; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_1 = io_iccm_wren & _T_18; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_20 = io_iccm_rw_addr[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_22 = addr_bank_inc[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_23 = _T_20 | _T_22; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_2 = io_iccm_wren & _T_23; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_25 = io_iccm_rw_addr[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_27 = addr_bank_inc[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_28 = _T_25 | _T_27; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_3 = io_iccm_wren & _T_28; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 35:64]
wire rden_bank_0 = _T_31 | _T_12; // @[el2_ifu_iccm_mem.scala 35:106]
wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 35:64]
wire rden_bank_1 = _T_36 | _T_17; // @[el2_ifu_iccm_mem.scala 35:106]
wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 35:64]
wire rden_bank_2 = _T_41 | _T_22; // @[el2_ifu_iccm_mem.scala 35:106]
wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 35:64]
wire rden_bank_3 = _T_46 | _T_27; // @[el2_ifu_iccm_mem.scala 35:106]
wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 36:72]
wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 36:72]
wire iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
wire _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 36:72]
wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 36:72]
wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
wire [11:0] _T_59 = _T_12 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
wire [11:0] _T_67 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
wire [11:0] _T_75 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
wire [11:0] _T_83 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
wire _T_93 = ~wren_bank_0; // @[el2_ifu_iccm_mem.scala 48:72]
wire read_enable_0 = iccm_clken_0 & _T_93; // @[el2_ifu_iccm_mem.scala 48:70]
wire _T_95 = ~wren_bank_1; // @[el2_ifu_iccm_mem.scala 48:72]
wire read_enable_1 = iccm_clken_1 & _T_95; // @[el2_ifu_iccm_mem.scala 48:70]
wire _T_97 = ~wren_bank_2; // @[el2_ifu_iccm_mem.scala 48:72]
wire read_enable_2 = iccm_clken_2 & _T_97; // @[el2_ifu_iccm_mem.scala 48:70]
wire _T_99 = ~wren_bank_3; // @[el2_ifu_iccm_mem.scala 48:72]
wire read_enable_3 = iccm_clken_3 & _T_99; // @[el2_ifu_iccm_mem.scala 48:70]
reg [38:0] iccm_bank_dout_0; // @[Reg.scala 27:20]
reg [38:0] iccm_bank_dout_1; // @[Reg.scala 27:20]
reg [38:0] iccm_bank_dout_2; // @[Reg.scala 27:20]
reg [38:0] iccm_bank_dout_3; // @[Reg.scala 27:20]
reg _T_313; // @[Reg.scala 27:20]
reg _T_314; // @[Reg.scala 27:20]
wire [1:0] redundant_valid = {_T_313,_T_314}; // @[Cat.scala 29:58]
reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
wire _T_116 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 65:105]
wire _T_119 = _T_116 & _T_10; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_123 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 66:37]
wire _T_126 = _T_123 & _T_12; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 65:179]
wire _T_134 = _T_116 & _T_15; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_141 = _T_123 & _T_17; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 65:179]
wire _T_149 = _T_116 & _T_20; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_156 = _T_123 & _T_22; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 65:179]
wire _T_164 = _T_116 & _T_25; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_165 = redundant_valid[1] & _T_164; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_171 = _T_123 & _T_27; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_172 = _T_165 | _T_171; // @[el2_ifu_iccm_mem.scala 65:179]
wire [2:0] _T_174 = {_T_172,_T_157,_T_142}; // @[Cat.scala 29:58]
wire [3:0] sel_red1 = {_T_172,_T_157,_T_142,_T_127}; // @[Cat.scala 29:58]
reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
wire _T_178 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 67:105]
wire _T_181 = _T_178 & _T_10; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_185 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 68:37]
wire _T_188 = _T_185 & _T_12; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 67:179]
wire _T_196 = _T_178 & _T_15; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_203 = _T_185 & _T_17; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 67:179]
wire _T_211 = _T_178 & _T_20; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_218 = _T_185 & _T_22; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 67:179]
wire _T_226 = _T_178 & _T_25; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_227 = redundant_valid[0] & _T_226; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_233 = _T_185 & _T_27; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_234 = _T_227 | _T_233; // @[el2_ifu_iccm_mem.scala 67:179]
wire [2:0] _T_236 = {_T_234,_T_219,_T_204}; // @[Cat.scala 29:58]
wire [3:0] sel_red0 = {_T_234,_T_219,_T_204,_T_189}; // @[Cat.scala 29:58]
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 70:27]
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 71:27]
wire _T_242 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_244 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 77:51]
reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
wire [38:0] _T_247 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
wire [38:0] _T_248 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_0 = _T_250 | _T_249; // @[Mux.scala 27:72]
wire _T_257 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_259 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 77:51]
wire [38:0] _T_262 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_263 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_1 = _T_265 | _T_264; // @[Mux.scala 27:72]
wire _T_272 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_274 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 77:51]
wire [38:0] _T_277 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_278 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_2 = _T_280 | _T_279; // @[Mux.scala 27:72]
wire _T_287 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_289 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_290 = _T_287 & _T_289; // @[el2_ifu_iccm_mem.scala 77:51]
wire [38:0] _T_292 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_293 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_294 = _T_290 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_295 = _T_292 | _T_293; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_3 = _T_295 | _T_294; // @[Mux.scala 27:72]
reg redundant_lru; // @[Reg.scala 27:20]
wire _T_297 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 79:20]
wire r0_addr_en = _T_297 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 79:35]
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 80:35]
wire _T_298 = |sel_red0; // @[el2_ifu_iccm_mem.scala 81:63]
wire _T_299 = |sel_red1; // @[el2_ifu_iccm_mem.scala 81:78]
wire _T_300 = _T_298 | _T_299; // @[el2_ifu_iccm_mem.scala 81:67]
wire _T_301 = _T_300 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 81:83]
wire _T_302 = _T_301 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 81:98]
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_302; // @[el2_ifu_iccm_mem.scala 81:50]
wire _T_318 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 88:61]
wire _T_321 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 89:26]
wire _T_324 = _T_321 | _T_1; // @[el2_ifu_iccm_mem.scala 89:52]
wire _T_325 = _T_318 & _T_324; // @[el2_ifu_iccm_mem.scala 88:102]
wire _T_327 = _T_325 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 89:84]
wire _T_328 = _T_327 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 89:105]
wire redundant_data0_en = _T_328 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 89:121]
wire _T_337 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 91:104]
wire _T_338 = _T_321 | _T_337; // @[el2_ifu_iccm_mem.scala 91:78]
wire _T_346 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 95:61]
wire _T_349 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 96:26]
wire _T_352 = _T_349 | _T_1; // @[el2_ifu_iccm_mem.scala 96:52]
wire _T_353 = _T_346 & _T_352; // @[el2_ifu_iccm_mem.scala 95:102]
wire _T_355 = _T_353 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 96:84]
wire _T_356 = _T_355 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 96:105]
wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121]
wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104]
wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78]
reg [2:0] _T_373; // @[Reg.scala 27:20]
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
wire _T_376 = iccm_rd_addr_lo_q[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 105:104]
wire _T_379 = iccm_rd_addr_lo_q[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 105:104]
wire _T_382 = iccm_rd_addr_lo_q[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 105:104]
wire _T_385 = iccm_rd_addr_lo_q[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 105:104]
wire [31:0] _T_387 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_388 = _T_379 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_389 = _T_382 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_390 = _T_385 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_391 = _T_387 | _T_388; // @[Mux.scala 27:72]
wire [31:0] _T_392 = _T_391 | _T_389; // @[Mux.scala 27:72]
wire [31:0] _T_393 = _T_392 | _T_390; // @[Mux.scala 27:72]
wire [31:0] _T_407 = _T_376 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_408 = _T_379 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_409 = _T_382 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_410 = _T_385 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_411 = _T_407 | _T_408; // @[Mux.scala 27:72]
wire [31:0] _T_412 = _T_411 | _T_409; // @[Mux.scala 27:72]
wire [31:0] _T_413 = _T_412 | _T_410; // @[Mux.scala 27:72]
wire [63:0] iccm_rd_data_pre = {_T_393,_T_413}; // @[Cat.scala 29:58]
wire [63:0] _T_419 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
wire [38:0] _T_462 = _T_376 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_463 = _T_379 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_464 = _T_382 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_465 = _T_385 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_466 = _T_462 | _T_463; // @[Mux.scala 27:72]
wire [38:0] _T_467 = _T_466 | _T_464; // @[Mux.scala 27:72]
wire [38:0] _T_468 = _T_467 | _T_465; // @[Mux.scala 27:72]
wire [38:0] _T_482 = _T_376 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_483 = _T_379 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_484 = _T_382 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_485 = _T_385 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_486 = _T_482 | _T_483; // @[Mux.scala 27:72]
wire [38:0] _T_487 = _T_486 | _T_484; // @[Mux.scala 27:72]
wire [38:0] _T_488 = _T_487 | _T_485; // @[Mux.scala 27:72]
assign _T_85__T_105_addr = _T_85__T_105_addr_pipe_0;
assign _T_85__T_105_data = _T_85[_T_85__T_105_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
assign _T_85__T_101_data = io_iccm_wr_data[38:0];
assign _T_85__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
assign _T_85__T_101_mask = 1'h1;
assign _T_85__T_101_en = iccm_clken_0 & wren_bank_0;
assign _T_86__T_107_addr = _T_86__T_107_addr_pipe_0;
assign _T_86__T_107_data = _T_86[_T_86__T_107_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
assign _T_86__T_102_data = io_iccm_wr_data[77:39];
assign _T_86__T_102_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_67;
assign _T_86__T_102_mask = 1'h1;
assign _T_86__T_102_en = iccm_clken_1 & wren_bank_1;
assign _T_87__T_109_addr = _T_87__T_109_addr_pipe_0;
assign _T_87__T_109_data = _T_87[_T_87__T_109_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
assign _T_87__T_103_data = io_iccm_wr_data[38:0];
assign _T_87__T_103_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_75;
assign _T_87__T_103_mask = 1'h1;
assign _T_87__T_103_en = iccm_clken_2 & wren_bank_2;
assign _T_88__T_111_addr = _T_88__T_111_addr_pipe_0;
assign _T_88__T_111_data = _T_88[_T_88__T_111_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
assign _T_88__T_104_data = io_iccm_wr_data[77:39];
assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83;
assign _T_88__T_104_mask = 1'h1;
assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3;
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_419 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
assign io_iccm_rd_data_ecc = {_T_468,_T_488}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23 el2_ifu_iccm_mem.scala 111:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {2{`RANDOM}};
for (initvar = 0; initvar < 4096; initvar = initvar+1)
_T_85[initvar] = _RAND_0[38:0];
_RAND_2 = {2{`RANDOM}};
for (initvar = 0; initvar < 4096; initvar = initvar+1)
_T_86[initvar] = _RAND_2[38:0];
_RAND_4 = {2{`RANDOM}};
for (initvar = 0; initvar < 4096; initvar = initvar+1)
_T_87[initvar] = _RAND_4[38:0];
_RAND_6 = {2{`RANDOM}};
for (initvar = 0; initvar < 4096; initvar = initvar+1)
_T_88[initvar] = _RAND_6[38:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_85__T_105_addr_pipe_0 = _RAND_1[11:0];
_RAND_3 = {1{`RANDOM}};
_T_86__T_107_addr_pipe_0 = _RAND_3[11:0];
_RAND_5 = {1{`RANDOM}};
_T_87__T_109_addr_pipe_0 = _RAND_5[11:0];
_RAND_7 = {1{`RANDOM}};
_T_88__T_111_addr_pipe_0 = _RAND_7[11:0];
_RAND_8 = {2{`RANDOM}};
iccm_bank_dout_0 = _RAND_8[38:0];
_RAND_9 = {2{`RANDOM}};
iccm_bank_dout_1 = _RAND_9[38:0];
_RAND_10 = {2{`RANDOM}};
iccm_bank_dout_2 = _RAND_10[38:0];
_RAND_11 = {2{`RANDOM}};
iccm_bank_dout_3 = _RAND_11[38:0];
_RAND_12 = {1{`RANDOM}};
_T_313 = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
_T_314 = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
redundant_address_1 = _RAND_14[13:0];
_RAND_15 = {1{`RANDOM}};
redundant_address_0 = _RAND_15[13:0];
_RAND_16 = {1{`RANDOM}};
sel_red0_q = _RAND_16[3:0];
_RAND_17 = {1{`RANDOM}};
sel_red1_q = _RAND_17[3:0];
_RAND_18 = {2{`RANDOM}};
redundant_data_1 = _RAND_18[38:0];
_RAND_19 = {2{`RANDOM}};
redundant_data_0 = _RAND_19[38:0];
_RAND_20 = {1{`RANDOM}};
redundant_lru = _RAND_20[0:0];
_RAND_21 = {1{`RANDOM}};
_T_373 = _RAND_21[2:0];
_RAND_22 = {1{`RANDOM}};
iccm_rd_addr_lo_q = _RAND_22[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
iccm_bank_dout_0 = 39'h0;
end
if (reset) begin
iccm_bank_dout_1 = 39'h0;
end
if (reset) begin
iccm_bank_dout_2 = 39'h0;
end
if (reset) begin
iccm_bank_dout_3 = 39'h0;
end
if (reset) begin
_T_313 = 1'h0;
end
if (reset) begin
_T_314 = 1'h0;
end
if (reset) begin
redundant_address_1 = 14'h0;
end
if (reset) begin
redundant_address_0 = 14'h0;
end
if (reset) begin
sel_red0_q = 4'h0;
end
if (reset) begin
sel_red1_q = 4'h0;
end
if (reset) begin
redundant_data_1 = 39'h0;
end
if (reset) begin
redundant_data_0 = 39'h0;
end
if (reset) begin
redundant_lru = 1'h0;
end
if (reset) begin
_T_373 = 3'h0;
end
if (reset) begin
iccm_rd_addr_lo_q = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(_T_85__T_101_en & _T_85__T_101_mask) begin
_T_85[_T_85__T_101_addr] <= _T_85__T_101_data; // @[el2_ifu_iccm_mem.scala 43:59]
end
if (wren_bank_0) begin
_T_85__T_105_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end else if (_T_12) begin
_T_85__T_105_addr_pipe_0 <= addr_bank_inc[14:3];
end else begin
_T_85__T_105_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end
if(_T_86__T_102_en & _T_86__T_102_mask) begin
_T_86[_T_86__T_102_addr] <= _T_86__T_102_data; // @[el2_ifu_iccm_mem.scala 43:59]
end
if (wren_bank_1) begin
_T_86__T_107_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end else if (_T_17) begin
_T_86__T_107_addr_pipe_0 <= addr_bank_inc[14:3];
end else begin
_T_86__T_107_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end
if(_T_87__T_103_en & _T_87__T_103_mask) begin
_T_87[_T_87__T_103_addr] <= _T_87__T_103_data; // @[el2_ifu_iccm_mem.scala 43:59]
end
if (wren_bank_2) begin
_T_87__T_109_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end else if (_T_22) begin
_T_87__T_109_addr_pipe_0 <= addr_bank_inc[14:3];
end else begin
_T_87__T_109_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end
if(_T_88__T_104_en & _T_88__T_104_mask) begin
_T_88[_T_88__T_104_addr] <= _T_88__T_104_data; // @[el2_ifu_iccm_mem.scala 43:59]
end
if (wren_bank_3) begin
_T_88__T_111_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end else if (_T_27) begin
_T_88__T_111_addr_pipe_0 <= addr_bank_inc[14:3];
end else begin
_T_88__T_111_addr_pipe_0 <= io_iccm_rw_addr[14:3];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
iccm_bank_dout_0 <= 39'h0;
end else if (read_enable_0) begin
iccm_bank_dout_0 <= _T_85__T_105_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
iccm_bank_dout_1 <= 39'h0;
end else if (read_enable_1) begin
iccm_bank_dout_1 <= _T_86__T_107_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
iccm_bank_dout_2 <= 39'h0;
end else if (read_enable_2) begin
iccm_bank_dout_2 <= _T_87__T_109_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
iccm_bank_dout_3 <= 39'h0;
end else if (read_enable_3) begin
iccm_bank_dout_3 <= _T_88__T_111_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_313 <= 1'h0;
end else begin
_T_313 <= r1_addr_en | _T_313;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_314 <= 1'h0;
end else begin
_T_314 <= r0_addr_en | _T_314;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
redundant_address_1 <= 14'h0;
end else if (r1_addr_en) begin
redundant_address_1 <= io_iccm_rw_addr[14:1];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
redundant_address_0 <= 14'h0;
end else if (r0_addr_en) begin
redundant_address_0 <= io_iccm_rw_addr[14:1];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sel_red0_q <= 4'h0;
end else begin
sel_red0_q <= {_T_236,_T_189};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sel_red1_q <= 4'h0;
end else begin
sel_red1_q <= {_T_174,_T_127};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
redundant_data_1 <= 39'h0;
end else if (redundant_data1_en) begin
if (_T_366) begin
redundant_data_1 <= iccm_bank_wr_data_1;
end else begin
redundant_data_1 <= iccm_bank_wr_data_0;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
redundant_data_0 <= 39'h0;
end else if (redundant_data0_en) begin
if (_T_338) begin
redundant_data_0 <= iccm_bank_wr_data_1;
end else begin
redundant_data_0 <= iccm_bank_wr_data_0;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
redundant_lru <= 1'h0;
end else if (redundant_lru_en) begin
if (io_iccm_buf_correct_ecc) begin
redundant_lru <= _T_297;
end else begin
redundant_lru <= _T_298;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_373 <= 3'h0;
end else begin
_T_373 <= io_iccm_rw_addr[2:0];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
iccm_rd_addr_lo_q <= 3'h0;
end else begin
iccm_rd_addr_lo_q <= _T_373;
end
end
endmodule

127
el2_ifu_ifc_ctl.anno.json
View File

@ -1,127 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_dma_access_ok",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
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"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_mrac_ff",
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"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
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{
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{
"class":"firrtl.options.TargetDirAnnotation",
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]

295
el2_ifu_ifc_ctl.fir
View File

@ -1,295 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ifc_ctl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 452:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14]
clkhdr.CK <= io.clk @[el2_lib.scala 454:18]
clkhdr.EN <= io.en @[el2_lib.scala 455:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18]
module el2_ifu_ifc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<31>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next_0 : UInt<1>
fetch_addr_next_0 <= UInt<1>("h00")
wire fetch_addr_next : UInt<31>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<31> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24]
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39]
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:45]
_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:45]
state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
wire _T_130 : UInt<4> @[Mux.scala 27:72]
_T_130 <= _T_129 @[Mux.scala 27:72]
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 119:17]
idle <= _T_131 @[el2_ifu_ifc_ctl.scala 119:8]
node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 120:16]
wfm <= _T_132 @[el2_ifu_ifc_ctl.scala 120:7]
node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 122:30]
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctl.scala 122:16]
reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 123:52]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 123:52]
reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 124:50]
_T_134 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 124:50]
fb_write_f <= _T_134 @[el2_ifu_ifc_ctl.scala 124:14]
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 127:40]
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 127:61]
node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 127:19]
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctl.scala 127:17]
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctl.scala 127:84]
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctl.scala 126:60]
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctl.scala 126:33]
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctl.scala 126:26]
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 219:25]
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 219:47]
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 222:14]
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 222:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 132:25]
node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 133:30]
node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 134:39]
node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 134:18]
node _T_148 = and(fb_full_f, _T_147) @[el2_ifu_ifc_ctl.scala 134:16]
node _T_149 = or(_T_145, _T_148) @[el2_ifu_ifc_ctl.scala 133:53]
node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:13]
node _T_151 = and(wfm, _T_150) @[el2_ifu_ifc_ctl.scala 135:11]
node _T_152 = or(_T_149, _T_151) @[el2_ifu_ifc_ctl.scala 134:62]
node _T_153 = or(_T_152, idle) @[el2_ifu_ifc_ctl.scala 135:35]
node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:46]
node _T_155 = and(_T_153, _T_154) @[el2_ifu_ifc_ctl.scala 135:44]
node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 135:67]
io.ifc_dma_access_ok <= _T_156 @[el2_ifu_ifc_ctl.scala 133:24]
node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:33]
node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 137:55]
io.ifc_region_acc_fault_bf <= _T_158 @[el2_ifu_ifc_ctl.scala 137:30]
node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 138:78]
node _T_160 = cat(_T_159, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_161 = dshr(io.dec_tlu_mrac_ff, _T_160) @[el2_ifu_ifc_ctl.scala 138:53]
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_ifc_ctl.scala 138:53]
node _T_163 = not(_T_162) @[el2_ifu_ifc_ctl.scala 138:34]
io.ifc_fetch_uncacheable_bf <= _T_163 @[el2_ifu_ifc_ctl.scala 138:31]
reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 140:57]
_T_164 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 140:57]
io.ifc_fetch_req_f <= _T_164 @[el2_ifu_ifc_ctl.scala 140:22]
node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:73]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 472:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 474:18]
rvclkhdr.io.en <= _T_165 @[el2_lib.scala 475:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24]
reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16]
_T_166 <= io.ifc_fetch_addr_bf @[el2_lib.scala 478:16]
io.ifc_fetch_addr_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:23]

327
el2_ifu_ifc_ctl.v
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@ -1,327 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 452:26]
wire clkhdr_CK; // @[el2_lib.scala 452:26]
wire clkhdr_EN; // @[el2_lib.scala 452:26]
wire clkhdr_SE; // @[el2_lib.scala 452:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 452:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 453:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 454:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 455:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 456:18]
endmodule
module el2_ifu_ifc_ctl(
input clock,
input reset,
input io_free_clk,
input io_active_clk,
input io_scan_mode,
input io_ic_hit_f,
input io_ifu_ic_mb_empty,
input io_ifu_fb_consume1,
input io_ifu_fb_consume2,
input io_dec_tlu_flush_noredir_wb,
input io_exu_flush_final,
input [30:0] io_exu_flush_path_final,
input io_ifu_bp_hit_taken_f,
input [30:0] io_ifu_bp_btb_target_f,
input io_ic_dma_active,
input io_ic_write_stall,
input io_dma_iccm_stall_any,
input [31:0] io_dec_tlu_mrac_ff,
output [30:0] io_ifc_fetch_addr_f,
output [30:0] io_ifc_fetch_addr_bf,
output io_ifc_fetch_req_f,
output io_ifu_pmu_fetch_stall,
output io_ifc_fetch_uncacheable_bf,
output io_ifc_fetch_req_bf,
output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 472:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 472:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 472:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 472:23]
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:45]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 119:17]
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 124:50]
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 122:30]
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 120:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 123:52]
wire _T_136 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 127:61]
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctl.scala 127:19]
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctl.scala 127:17]
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84]
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60]
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 219:47]
wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 222:29]
wire _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30]
wire _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16]
wire _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53]
wire _T_150 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 135:13]
wire _T_151 = wfm & _T_150; // @[el2_ifu_ifc_ctl.scala 135:11]
wire _T_152 = _T_149 | _T_151; // @[el2_ifu_ifc_ctl.scala 134:62]
wire _T_153 = _T_152 | idle; // @[el2_ifu_ifc_ctl.scala 135:35]
wire _T_155 = _T_153 & _T_2; // @[el2_ifu_ifc_ctl.scala 135:44]
wire _T_157 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 137:33]
wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53]
reg _T_164; // @[el2_ifu_ifc_ctl.scala 140:57]
reg [30:0] _T_166; // @[el2_lib.scala 478:16]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 472:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23]
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctl.scala 126:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[el2_ifu_ifc_ctl.scala 138:31]
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25]
assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30]
assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 474:18]
assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 475:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
dma_iccm_stall_any_f = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
miss_a = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
state = _RAND_2[1:0];
_RAND_3 = {1{`RANDOM}};
fb_write_f = _RAND_3[3:0];
_RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_164 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_166 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
dma_iccm_stall_any_f = 1'h0;
end
if (reset) begin
miss_a = 1'h0;
end
if (reset) begin
state = 2'h0;
end
if (reset) begin
fb_write_f = 4'h0;
end
if (reset) begin
fb_full_f = 1'h0;
end
if (reset) begin
_T_164 = 1'h0;
end
if (reset) begin
_T_166 = 31'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
dma_iccm_stall_any_f <= 1'h0;
end else begin
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
miss_a <= 1'h0;
end else begin
miss_a <= _T_48 & _T_2;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
state <= 2'h0;
end else begin
state <= {next_state_1,next_state_0};
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
fb_write_f <= 4'h0;
end else begin
fb_write_f <= _T_128 | _T_125;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
fb_full_f <= 1'h0;
end else begin
fb_full_f <= fb_write_ns[3];
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
_T_164 <= 1'h0;
end else begin
_T_164 <= io_ifc_fetch_req_bf;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_166 <= 31'h0;
end else begin
_T_166 <= io_ifc_fetch_addr_bf;
end
end
endmodule

122
el2_ifu_ifc_ctrl.anno.json
View File

@ -1,122 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_dma_access_ok",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_write_stall",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_write_stall",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_region_acc_fault_bf",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_ifc_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

266
el2_ifu_ifc_ctrl.fir
View File

@ -1,266 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ifc_ctrl :
module el2_ifu_ifc_ctrl :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<32>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next : UInt<32>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 61:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 62:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 62:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 62:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 64:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 64:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 64:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 66:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 66:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 67:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 67:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 71:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 72:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:22]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<32> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 71:24]
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctl.scala 78:13]
node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctl.scala 79:47]
node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 79:75]
node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctl.scala 79:30]
node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 80:45]
node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 80:51]
node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctl.scala 80:51]
node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58]
fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_31 = not(idle) @[el2_ifu_ifc_ctl.scala 83:30]
io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctl.scala 83:27]
node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 85:91]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:70]
node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctl.scala 85:68]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:53]
node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctl.scala 85:51]
node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:5]
node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctl.scala 85:114]
node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:18]
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 86:16]
node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:39]
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 86:37]
io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctl.scala 85:23]
node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 88:37]
fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctl.scala 88:15]
node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:34]
node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctl.scala 90:32]
node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:49]
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctl.scala 90:47]
miss_f <= _T_47 @[el2_ifu_ifc_ctl.scala 90:10]
node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 92:39]
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:63]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 92:61]
node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:76]
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 92:74]
node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:86]
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 92:84]
mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctl.scala 92:16]
node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 94:35]
goto_idle <= _T_55 @[el2_ifu_ifc_ctl.scala 94:13]
node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 96:38]
node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctl.scala 96:36]
node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctl.scala 96:67]
leave_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 96:14]
node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:29]
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:23]
node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 98:40]
node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctl.scala 98:44]
node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:55]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 98:53]
node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 99:11]
node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:17]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 99:15]
node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:33]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 99:31]
node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctl.scala 98:67]
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:23]
node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctl.scala 101:34]
node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 101:56]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:62]
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctl.scala 101:60]
node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctl.scala 101:48]
node _T_76 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 103:19]
_T_77 <= _T_76 @[el2_ifu_ifc_ctl.scala 103:19]
state <= _T_77 @[el2_ifu_ifc_ctl.scala 103:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 105:12]
node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:38]
node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctl.scala 107:36]
node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:61]
node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctl.scala 107:81]
node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctl.scala 107:58]
node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 108:25]
node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctl.scala 107:92]
fb_right <= _T_84 @[el2_ifu_ifc_ctl.scala 107:12]
node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 110:39]
node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctl.scala 110:59]
node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctl.scala 110:36]
fb_right2 <= _T_87 @[el2_ifu_ifc_ctl.scala 110:13]
node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 111:56]
node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:35]
node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctl.scala 111:33]
node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:80]
node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctl.scala 111:78]
fb_left <= _T_92 @[el2_ifu_ifc_ctl.scala 111:11]
node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 113:37]
node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctl.scala 114:28]
node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 114:62]
node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58]
node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctl.scala 115:29]
node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 115:63]
node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58]
node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctl.scala 116:27]
node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 116:51]
node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:6]
node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:18]
node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctl.scala 117:16]
node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:30]
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 117:28]
node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:43]
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 117:41]
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctl.scala 117:53]
node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 117:73]
node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = mux(_T_106, _T_108, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_116, _T_117, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = or(_T_118, _T_119) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_120) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
wire _T_127 : UInt<4> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
fb_write_ns <= _T_127 @[el2_ifu_ifc_ctl.scala 113:15]
node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 120:38]
reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 120:26]
_T_129 <= _T_128 @[el2_ifu_ifc_ctl.scala 120:26]
fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 120:16]
node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 122:17]
idle <= _T_130 @[el2_ifu_ifc_ctl.scala 122:8]
node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 123:16]
wfm <= _T_131 @[el2_ifu_ifc_ctl.scala 123:7]
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 125:30]
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 125:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 126:26]
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 127:24]
_T_133 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 127:24]
fb_write_f <= _T_133 @[el2_ifu_ifc_ctl.scala 127:14]
node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 130:40]
node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 130:61]
node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 130:19]
node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctl.scala 130:17]
node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctl.scala 130:84]
node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctl.scala 129:60]
node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctl.scala 129:33]
io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctl.scala 129:26]
node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 211:25]
node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 211:47]
node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 214:14]
node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 135:25]
node _T_144 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:30]
node _T_145 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 137:39]
node _T_146 = eq(_T_145, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:18]
node _T_147 = and(fb_full_f, _T_146) @[el2_ifu_ifc_ctl.scala 137:16]
node _T_148 = or(_T_144, _T_147) @[el2_ifu_ifc_ctl.scala 136:53]
node _T_149 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:13]
node _T_150 = and(wfm, _T_149) @[el2_ifu_ifc_ctl.scala 138:11]
node _T_151 = or(_T_148, _T_150) @[el2_ifu_ifc_ctl.scala 137:62]
node _T_152 = or(_T_151, idle) @[el2_ifu_ifc_ctl.scala 138:35]
node _T_153 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:46]
node _T_154 = and(_T_152, _T_153) @[el2_ifu_ifc_ctl.scala 138:44]
node _T_155 = or(_T_154, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 138:67]
io.ifc_dma_access_ok <= _T_155 @[el2_ifu_ifc_ctl.scala 136:24]
node _T_156 = not(iccm_acc_in_range_bf) @[el2_ifu_ifc_ctl.scala 140:33]
node _T_157 = and(_T_156, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 140:55]
io.ifc_region_acc_fault_bf <= _T_157 @[el2_ifu_ifc_ctl.scala 140:30]
node _T_158 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 141:78]
node _T_159 = cat(_T_158, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_160 = dshr(io.dec_tlu_mrac_ff, _T_159) @[el2_ifu_ifc_ctl.scala 141:53]
node _T_161 = bits(_T_160, 0, 0) @[el2_ifu_ifc_ctl.scala 141:53]
node _T_162 = not(_T_161) @[el2_ifu_ifc_ctl.scala 141:34]
io.ifc_fetch_uncacheable_bf <= _T_162 @[el2_ifu_ifc_ctl.scala 141:31]
reg _T_163 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 143:32]
_T_163 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 143:32]
io.ifc_fetch_req_f <= _T_163 @[el2_ifu_ifc_ctl.scala 143:22]
node _T_164 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 145:88]
reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_165 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_165 @[el2_ifu_ifc_ctl.scala 145:23]

294
el2_ifu_ifc_ctrl.v
View File

@ -1,294 +0,0 @@
module el2_ifu_ifc_ctrl(
input clock,
input reset,
input io_free_clk,
input io_active_clk,
input io_scan_mode,
input io_ic_hit_f,
input io_ifu_ic_mb_empty,
input io_ifu_fb_consume1,
input io_ifu_fb_consume2,
input io_dec_tlu_flush_noredir_wb,
input io_exu_flush_final,
input [30:0] io_exu_flush_path_final,
input io_ifu_bp_hit_taken_f,
input [30:0] io_ifu_bp_btb_target_f,
input io_ic_dma_active,
input io_ic_write_stall,
input io_dma_iccm_stall_any,
input [31:0] io_dec_tlu_mrac_ff,
output [30:0] io_ifc_fetch_addr_f,
output [30:0] io_ifc_fetch_addr_bf,
output io_ifc_fetch_req_f,
output io_ifu_pmu_fetch_stall,
output io_ifc_fetch_uncacheable_bf,
output io_ifc_fetch_req_bf,
output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 61:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 64:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 66:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 66:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 66:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 66:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 66:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 67:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] _T_29 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 80:51]
wire [30:0] _T_30 = {_T_29,1'h0}; // @[Cat.scala 29:58]
wire [31:0] fetch_addr_next = {{1'd0}, _T_30}; // @[el2_ifu_ifc_ctl.scala 80:19]
wire [31:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
wire [31:0] _GEN_1 = {{1'd0}, _T_22}; // @[Mux.scala 27:72]
wire [31:0] _T_23 = _GEN_1 | _T_20; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 103:19]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 122:17]
wire _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 85:91]
wire _T_33 = ~_T_32; // @[el2_ifu_ifc_ctl.scala 85:70]
wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 107:38]
wire _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctl.scala 107:36]
wire _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 90:32]
wire miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctl.scala 90:47]
wire _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 107:81]
wire _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctl.scala 107:58]
wire _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 108:25]
wire fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctl.scala 107:92]
wire _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 114:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 127:24]
wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctl.scala 110:36]
wire _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72]
wire _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 111:56]
wire _T_89 = ~_T_88; // @[el2_ifu_ifc_ctl.scala 111:35]
wire _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctl.scala 111:33]
wire _T_91 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 111:80]
wire fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctl.scala 111:78]
wire _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 116:16]
wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
wire _T_110 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 117:18]
wire _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctl.scala 117:16]
wire _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 117:30]
wire _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctl.scala 117:28]
wire _T_114 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 117:43]
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 117:41]
wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 125:30]
wire _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctl.scala 85:68]
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 85:53]
wire _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctl.scala 85:51]
wire _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 86:5]
wire _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctl.scala 85:114]
wire _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 86:18]
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 86:16]
wire _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 86:39]
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 88:37]
wire _T_48 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 92:39]
wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctl.scala 92:61]
wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctl.scala 92:74]
wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 92:86]
wire mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctl.scala 92:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 94:35]
wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctl.scala 96:36]
wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctl.scala 96:67]
wire _T_60 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 98:23]
wire _T_62 = _T_60 & state[0]; // @[el2_ifu_ifc_ctl.scala 98:33]
wire _T_63 = _T_62 & miss_f; // @[el2_ifu_ifc_ctl.scala 98:44]
wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 98:55]
wire _T_65 = _T_63 & _T_64; // @[el2_ifu_ifc_ctl.scala 98:53]
wire _T_67 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 99:17]
wire _T_68 = state[1] & _T_67; // @[el2_ifu_ifc_ctl.scala 99:15]
wire _T_70 = _T_68 & _T_64; // @[el2_ifu_ifc_ctl.scala 99:31]
wire next_state_1 = _T_65 | _T_70; // @[el2_ifu_ifc_ctl.scala 98:67]
wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctl.scala 101:34]
wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctl.scala 101:60]
wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctl.scala 101:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 123:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 126:26]
wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 130:61]
wire _T_136 = ~_T_135; // @[el2_ifu_ifc_ctl.scala 130:19]
wire _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctl.scala 130:17]
wire _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctl.scala 130:84]
wire _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctl.scala 129:60]
wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_141[31:28] == 4'he; // @[el2_lib.scala 211:47]
wire iccm_acc_in_range_bf = _T_141[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
wire _T_144 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 136:30]
wire _T_147 = fb_full_f & _T_33; // @[el2_ifu_ifc_ctl.scala 137:16]
wire _T_148 = _T_144 | _T_147; // @[el2_ifu_ifc_ctl.scala 136:53]
wire _T_149 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 138:13]
wire _T_150 = wfm & _T_149; // @[el2_ifu_ifc_ctl.scala 138:11]
wire _T_151 = _T_148 | _T_150; // @[el2_ifu_ifc_ctl.scala 137:62]
wire _T_152 = _T_151 | idle; // @[el2_ifu_ifc_ctl.scala 138:35]
wire _T_154 = _T_152 & _T_2; // @[el2_ifu_ifc_ctl.scala 138:44]
wire _T_156 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 140:33]
wire [4:0] _T_159 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_160 = io_dec_tlu_mrac_ff >> _T_159; // @[el2_ifu_ifc_ctl.scala 141:53]
reg _T_163; // @[el2_ifu_ifc_ctl.scala 143:32]
reg [30:0] _T_165; // @[Reg.scala 27:20]
assign io_ifc_fetch_addr_f = _T_165; // @[el2_ifu_ifc_ctl.scala 145:23]
assign io_ifc_fetch_addr_bf = _T_23[30:0]; // @[el2_ifu_ifc_ctl.scala 71:24]
assign io_ifc_fetch_req_f = _T_163; // @[el2_ifu_ifc_ctl.scala 143:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctl.scala 129:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_160[0]; // @[el2_ifu_ifc_ctl.scala 141:31]
assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 83:27]
assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 135:25]
assign io_ifc_region_acc_fault_bf = _T_156 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 140:30]
assign io_ifc_dma_access_ok = _T_154 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 136:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
dma_iccm_stall_any_f = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
miss_a = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
state = _RAND_2[1:0];
_RAND_3 = {1{`RANDOM}};
fb_write_f = _RAND_3[3:0];
_RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_163 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_165 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
dma_iccm_stall_any_f = 1'h0;
end
if (reset) begin
miss_a = 1'h0;
end
if (reset) begin
state = 2'h0;
end
if (reset) begin
fb_write_f = 4'h0;
end
if (reset) begin
fb_full_f = 1'h0;
end
if (reset) begin
_T_163 = 1'h0;
end
if (reset) begin
_T_165 = 31'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
dma_iccm_stall_any_f <= 1'h0;
end else begin
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
miss_a <= 1'h0;
end else begin
miss_a <= _T_45 & _T_2;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
state <= 2'h0;
end else begin
state <= {next_state_1,next_state_0};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
fb_write_f <= 4'h0;
end else begin
fb_write_f <= _T_125 | _T_122;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
fb_full_f <= 1'h0;
end else begin
fb_full_f <= fb_write_ns[3];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_163 <= 1'h0;
end else begin
_T_163 <= io_ifc_fetch_req_bf;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_165 <= 31'h0;
end else if (fetch_bf_en) begin
_T_165 <= io_ifc_fetch_addr_bf;
end
end
endmodule

370
el2_ifu_mem_ctl.anno.json
View File

@ -1,370 +0,0 @@
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
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]
},
{
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]
},
{
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]
},
{
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},
{
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]
},
{
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]
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{
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
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]
},
{
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
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]
},
{
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},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]

15680
el2_ifu_mem_ctl.fir
View File

File diff suppressed because it is too large Load Diff

9604
el2_ifu_mem_ctl.v
View File

File diff suppressed because it is too large Load Diff

494
el2_lsu.anno.json
View File

@ -1,494 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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]
},
{
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wren",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
"sources":[
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_fastint_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wr_data",
"sources":[
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_inv_r",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

15840
el2_lsu.fir
View File

File diff suppressed because it is too large Load Diff

11709
el2_lsu.v
View File

File diff suppressed because it is too large Load Diff

105
el2_lsu_addrcheck.anno.json
View File

@ -1,105 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_exc_mscause_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_dccm_access_error_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_nondccm_access_error_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_access_fault_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_addrcheck"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

280
el2_lsu_addrcheck.fir
View File

@ -1,280 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_addrcheck :
module rvrangecheck :
input clock : Clock
input reset : Reset
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
wire start_addr : UInt<32> @[beh_lib.scala 139:25]
start_addr <= UInt<6>("h020") @[beh_lib.scala 140:15]
node region = bits(start_addr, 31, 28) @[beh_lib.scala 141:27]
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 143:28]
node _T_1 = bits(region, 3, 0) @[beh_lib.scala 143:60]
node _T_2 = eq(_T, _T_1) @[beh_lib.scala 143:50]
io.in_region <= _T_2 @[beh_lib.scala 143:17]
node _T_3 = bits(io.addr, 31, 15) @[beh_lib.scala 147:28]
node _T_4 = bits(start_addr, 31, 15) @[beh_lib.scala 147:57]
node _T_5 = eq(_T_3, _T_4) @[beh_lib.scala 147:43]
io.in_range <= _T_5 @[beh_lib.scala 147:17]
module rvrangecheck_1 :
input clock : Clock
input reset : Reset
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
wire start_addr : UInt<32> @[beh_lib.scala 139:25]
start_addr <= UInt<6>("h020") @[beh_lib.scala 140:15]
node region = bits(start_addr, 31, 28) @[beh_lib.scala 141:27]
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 143:28]
node _T_1 = bits(region, 3, 0) @[beh_lib.scala 143:60]
node _T_2 = eq(_T, _T_1) @[beh_lib.scala 143:50]
io.in_region <= _T_2 @[beh_lib.scala 143:17]
node _T_3 = bits(io.addr, 31, 15) @[beh_lib.scala 147:28]
node _T_4 = bits(start_addr, 31, 15) @[beh_lib.scala 147:57]
node _T_5 = eq(_T_3, _T_4) @[beh_lib.scala 147:43]
io.in_range <= _T_5 @[beh_lib.scala 147:17]
module el2_lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
wire start_addr_in_dccm_d : UInt<1>
start_addr_in_dccm_d <= UInt<1>("h00")
wire start_addr_in_dccm_region_d : UInt<1>
start_addr_in_dccm_region_d <= UInt<1>("h00")
wire end_addr_in_dccm_d : UInt<1>
end_addr_in_dccm_d <= UInt<1>("h00")
wire end_addr_in_dccm_region_d : UInt<1>
end_addr_in_dccm_region_d <= UInt<1>("h00")
start_addr_in_dccm_d <= UInt<1>("h00") @[w.scala 61:36]
start_addr_in_dccm_region_d <= UInt<1>("h00") @[w.scala 62:36]
end_addr_in_dccm_d <= UInt<1>("h00") @[w.scala 63:36]
end_addr_in_dccm_region_d <= UInt<1>("h00") @[w.scala 64:36]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
addr_in_iccm <= UInt<1>("h01") @[w.scala 72:18]
inst start_addr_pic_rangecheck of rvrangecheck @[w.scala 78:41]
start_addr_pic_rangecheck.clock <= clock
start_addr_pic_rangecheck.reset <= reset
node _T = bits(io.start_addr_d, 31, 0) @[w.scala 79:55]
start_addr_pic_rangecheck.io.addr <= _T @[w.scala 79:37]
inst end_addr_pic_rangecheck of rvrangecheck_1 @[w.scala 84:39]
end_addr_pic_rangecheck.clock <= clock
end_addr_pic_rangecheck.reset <= reset
node _T_1 = bits(io.end_addr_d, 31, 0) @[w.scala 85:51]
end_addr_pic_rangecheck.io.addr <= _T_1 @[w.scala 85:35]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 89:60]
node _T_2 = bits(io.rs1_region_d, 3, 0) @[w.scala 90:48]
node _T_3 = eq(_T_2, UInt<4>("h0f")) @[w.scala 90:54]
node _T_4 = bits(io.rs1_region_d, 3, 0) @[w.scala 90:91]
node _T_5 = eq(_T_4, UInt<4>("h0f")) @[w.scala 90:97]
node base_reg_dccm_or_pic = or(_T_3, _T_5) @[w.scala 90:73]
node _T_6 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[w.scala 91:57]
io.addr_in_dccm_d <= _T_6 @[w.scala 91:32]
node _T_7 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[w.scala 92:56]
io.addr_in_pic_d <= _T_7 @[w.scala 92:32]
node _T_8 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 94:63]
node _T_9 = not(_T_8) @[w.scala 94:33]
io.addr_external_d <= _T_9 @[w.scala 94:30]
node _T_10 = bits(io.start_addr_d, 31, 28) @[w.scala 95:51]
node csr_idx = cat(_T_10, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_11 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[w.scala 96:50]
node _T_12 = bits(_T_11, 0, 0) @[w.scala 96:50]
node _T_13 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 96:92]
node _T_14 = or(_T_13, addr_in_iccm) @[w.scala 96:121]
node _T_15 = not(_T_14) @[w.scala 96:62]
node _T_16 = and(_T_12, _T_15) @[w.scala 96:60]
node _T_17 = and(_T_16, io.lsu_pkt_d.valid) @[w.scala 96:137]
node _T_18 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[w.scala 96:180]
node is_sideeffects_d = and(_T_17, _T_18) @[w.scala 96:158]
node _T_19 = bits(io.start_addr_d, 1, 0) @[w.scala 97:69]
node _T_20 = eq(_T_19, UInt<1>("h00")) @[w.scala 97:75]
node _T_21 = and(io.lsu_pkt_d.word, _T_20) @[w.scala 97:51]
node _T_22 = bits(io.start_addr_d, 0, 0) @[w.scala 97:124]
node _T_23 = eq(_T_22, UInt<1>("h00")) @[w.scala 97:128]
node _T_24 = and(io.lsu_pkt_d.half, _T_23) @[w.scala 97:106]
node _T_25 = or(_T_21, _T_24) @[w.scala 97:85]
node is_aligned_d = or(_T_25, io.lsu_pkt_d.by) @[w.scala 97:138]
node _T_26 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_27 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_28 = cat(_T_27, _T_26) @[Cat.scala 29:58]
node _T_29 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_30 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_31 = cat(_T_30, _T_29) @[Cat.scala 29:58]
node _T_32 = cat(_T_31, _T_28) @[Cat.scala 29:58]
node _T_33 = orr(_T_32) @[w.scala 101:98]
node _T_34 = not(_T_33) @[w.scala 100:33]
node _T_35 = bits(io.start_addr_d, 31, 0) @[w.scala 102:49]
node _T_36 = or(_T_35, UInt<31>("h07fffffff")) @[w.scala 102:56]
node _T_37 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[w.scala 102:105]
node _T_38 = eq(_T_36, _T_37) @[w.scala 102:80]
node _T_39 = and(UInt<1>("h01"), _T_38) @[w.scala 102:30]
node _T_40 = bits(io.start_addr_d, 31, 0) @[w.scala 103:49]
node _T_41 = or(_T_40, UInt<30>("h03fffffff")) @[w.scala 103:56]
node _T_42 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[w.scala 103:105]
node _T_43 = eq(_T_41, _T_42) @[w.scala 103:80]
node _T_44 = and(UInt<1>("h01"), _T_43) @[w.scala 103:30]
node _T_45 = or(_T_39, _T_44) @[w.scala 102:129]
node _T_46 = bits(io.start_addr_d, 31, 0) @[w.scala 104:49]
node _T_47 = or(_T_46, UInt<29>("h01fffffff")) @[w.scala 104:56]
node _T_48 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[w.scala 104:105]
node _T_49 = eq(_T_47, _T_48) @[w.scala 104:80]
node _T_50 = and(UInt<1>("h01"), _T_49) @[w.scala 104:30]
node _T_51 = or(_T_45, _T_50) @[w.scala 103:129]
node _T_52 = bits(io.start_addr_d, 31, 0) @[w.scala 105:49]
node _T_53 = or(_T_52, UInt<28>("h0fffffff")) @[w.scala 105:56]
node _T_54 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[w.scala 105:105]
node _T_55 = eq(_T_53, _T_54) @[w.scala 105:80]
node _T_56 = and(UInt<1>("h01"), _T_55) @[w.scala 105:30]
node _T_57 = or(_T_51, _T_56) @[w.scala 104:129]
node _T_58 = bits(io.start_addr_d, 31, 0) @[w.scala 106:49]
node _T_59 = or(_T_58, UInt<32>("h0ffffffff")) @[w.scala 106:56]
node _T_60 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 106:105]
node _T_61 = eq(_T_59, _T_60) @[w.scala 106:80]
node _T_62 = and(UInt<1>("h00"), _T_61) @[w.scala 106:30]
node _T_63 = or(_T_57, _T_62) @[w.scala 105:129]
node _T_64 = bits(io.start_addr_d, 31, 0) @[w.scala 107:49]
node _T_65 = or(_T_64, UInt<32>("h0ffffffff")) @[w.scala 107:56]
node _T_66 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 107:105]
node _T_67 = eq(_T_65, _T_66) @[w.scala 107:80]
node _T_68 = and(UInt<1>("h00"), _T_67) @[w.scala 107:30]
node _T_69 = or(_T_63, _T_68) @[w.scala 106:129]
node _T_70 = bits(io.start_addr_d, 31, 0) @[w.scala 108:49]
node _T_71 = or(_T_70, UInt<32>("h0ffffffff")) @[w.scala 108:56]
node _T_72 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 108:105]
node _T_73 = eq(_T_71, _T_72) @[w.scala 108:80]
node _T_74 = and(UInt<1>("h00"), _T_73) @[w.scala 108:30]
node _T_75 = or(_T_69, _T_74) @[w.scala 107:129]
node _T_76 = bits(io.start_addr_d, 31, 0) @[w.scala 109:49]
node _T_77 = or(_T_76, UInt<32>("h0ffffffff")) @[w.scala 109:56]
node _T_78 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 109:105]
node _T_79 = eq(_T_77, _T_78) @[w.scala 109:80]
node _T_80 = and(UInt<1>("h00"), _T_79) @[w.scala 109:30]
node _T_81 = or(_T_75, _T_80) @[w.scala 108:129]
node _T_82 = bits(io.end_addr_d, 31, 0) @[w.scala 111:48]
node _T_83 = or(_T_82, UInt<31>("h07fffffff")) @[w.scala 111:57]
node _T_84 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[w.scala 111:106]
node _T_85 = eq(_T_83, _T_84) @[w.scala 111:81]
node _T_86 = and(UInt<1>("h01"), _T_85) @[w.scala 111:31]
node _T_87 = bits(io.end_addr_d, 31, 0) @[w.scala 112:49]
node _T_88 = or(_T_87, UInt<30>("h03fffffff")) @[w.scala 112:58]
node _T_89 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[w.scala 112:107]
node _T_90 = eq(_T_88, _T_89) @[w.scala 112:82]
node _T_91 = and(UInt<1>("h01"), _T_90) @[w.scala 112:32]
node _T_92 = or(_T_86, _T_91) @[w.scala 111:130]
node _T_93 = bits(io.end_addr_d, 31, 0) @[w.scala 113:49]
node _T_94 = or(_T_93, UInt<29>("h01fffffff")) @[w.scala 113:58]
node _T_95 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[w.scala 113:107]
node _T_96 = eq(_T_94, _T_95) @[w.scala 113:82]
node _T_97 = and(UInt<1>("h01"), _T_96) @[w.scala 113:32]
node _T_98 = or(_T_92, _T_97) @[w.scala 112:131]
node _T_99 = bits(io.end_addr_d, 31, 0) @[w.scala 114:49]
node _T_100 = or(_T_99, UInt<28>("h0fffffff")) @[w.scala 114:58]
node _T_101 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[w.scala 114:107]
node _T_102 = eq(_T_100, _T_101) @[w.scala 114:82]
node _T_103 = and(UInt<1>("h01"), _T_102) @[w.scala 114:32]
node _T_104 = or(_T_98, _T_103) @[w.scala 113:131]
node _T_105 = bits(io.end_addr_d, 31, 0) @[w.scala 115:49]
node _T_106 = or(_T_105, UInt<32>("h0ffffffff")) @[w.scala 115:58]
node _T_107 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 115:107]
node _T_108 = eq(_T_106, _T_107) @[w.scala 115:82]
node _T_109 = and(UInt<1>("h00"), _T_108) @[w.scala 115:32]
node _T_110 = or(_T_104, _T_109) @[w.scala 114:131]
node _T_111 = bits(io.end_addr_d, 31, 0) @[w.scala 116:49]
node _T_112 = or(_T_111, UInt<32>("h0ffffffff")) @[w.scala 116:58]
node _T_113 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 116:107]
node _T_114 = eq(_T_112, _T_113) @[w.scala 116:82]
node _T_115 = and(UInt<1>("h00"), _T_114) @[w.scala 116:32]
node _T_116 = or(_T_110, _T_115) @[w.scala 115:131]
node _T_117 = bits(io.end_addr_d, 31, 0) @[w.scala 117:49]
node _T_118 = or(_T_117, UInt<32>("h0ffffffff")) @[w.scala 117:58]
node _T_119 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 117:107]
node _T_120 = eq(_T_118, _T_119) @[w.scala 117:82]
node _T_121 = and(UInt<1>("h00"), _T_120) @[w.scala 117:32]
node _T_122 = or(_T_116, _T_121) @[w.scala 116:131]
node _T_123 = bits(io.end_addr_d, 31, 0) @[w.scala 118:49]
node _T_124 = or(_T_123, UInt<32>("h0ffffffff")) @[w.scala 118:58]
node _T_125 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 118:107]
node _T_126 = eq(_T_124, _T_125) @[w.scala 118:82]
node _T_127 = and(UInt<1>("h00"), _T_126) @[w.scala 118:32]
node _T_128 = or(_T_122, _T_127) @[w.scala 117:131]
node _T_129 = and(_T_81, _T_128) @[w.scala 110:7]
node non_dccm_access_ok = or(_T_34, _T_129) @[w.scala 101:103]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[w.scala 120:57]
node _T_130 = bits(io.start_addr_d, 1, 0) @[w.scala 121:70]
node _T_131 = neq(_T_130, UInt<2>("h00")) @[w.scala 121:76]
node _T_132 = not(io.lsu_pkt_d.word) @[w.scala 121:92]
node _T_133 = or(_T_131, _T_132) @[w.scala 121:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_133) @[w.scala 121:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_134 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[w.scala 126:87]
node _T_135 = not(_T_134) @[w.scala 126:64]
node _T_136 = and(start_addr_in_dccm_region_d, _T_135) @[w.scala 126:62]
node _T_137 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[w.scala 128:57]
node _T_138 = not(_T_137) @[w.scala 128:36]
node _T_139 = and(end_addr_in_dccm_region_d, _T_138) @[w.scala 128:34]
node _T_140 = or(_T_136, _T_139) @[w.scala 126:112]
node _T_141 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[w.scala 130:29]
node _T_142 = or(_T_140, _T_141) @[w.scala 128:85]
node _T_143 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[w.scala 132:29]
node _T_144 = or(_T_142, _T_143) @[w.scala 130:85]
unmapped_access_fault_d <= _T_144 @[w.scala 126:29]
node _T_145 = not(start_addr_in_dccm_region_d) @[w.scala 134:33]
node _T_146 = not(non_dccm_access_ok) @[w.scala 134:64]
node _T_147 = and(_T_145, _T_146) @[w.scala 134:62]
mpu_access_fault_d <= _T_147 @[w.scala 134:29]
node _T_148 = or(unmapped_access_fault_d, mpu_access_fault_d) @[w.scala 146:49]
node _T_149 = or(_T_148, picm_access_fault_d) @[w.scala 146:70]
node _T_150 = or(_T_149, regpred_access_fault_d) @[w.scala 146:92]
node _T_151 = and(_T_150, io.lsu_pkt_d.valid) @[w.scala 146:118]
node _T_152 = not(io.lsu_pkt_d.dma) @[w.scala 146:141]
node _T_153 = and(_T_151, _T_152) @[w.scala 146:139]
io.access_fault_d <= _T_153 @[w.scala 146:21]
node _T_154 = bits(unmapped_access_fault_d, 0, 0) @[w.scala 147:60]
node _T_155 = bits(mpu_access_fault_d, 0, 0) @[w.scala 147:100]
node _T_156 = bits(regpred_access_fault_d, 0, 0) @[w.scala 147:144]
node _T_157 = bits(picm_access_fault_d, 0, 0) @[w.scala 147:185]
node _T_158 = mux(_T_157, UInt<4>("h06"), UInt<4>("h00")) @[w.scala 147:164]
node _T_159 = mux(_T_156, UInt<4>("h05"), _T_158) @[w.scala 147:120]
node _T_160 = mux(_T_155, UInt<4>("h03"), _T_159) @[w.scala 147:80]
node access_fault_mscause_d = mux(_T_154, UInt<4>("h02"), _T_160) @[w.scala 147:35]
node _T_161 = bits(io.start_addr_d, 31, 28) @[w.scala 148:53]
node _T_162 = bits(io.end_addr_d, 31, 28) @[w.scala 148:78]
node regcross_misaligned_fault_d = neq(_T_161, _T_162) @[w.scala 148:61]
node _T_163 = not(is_aligned_d) @[w.scala 149:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_163) @[w.scala 149:57]
node _T_164 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[w.scala 150:90]
node _T_165 = or(regcross_misaligned_fault_d, _T_164) @[w.scala 150:57]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[w.scala 150:113]
node _T_167 = not(io.lsu_pkt_d.dma) @[w.scala 150:136]
node _T_168 = and(_T_166, _T_167) @[w.scala 150:134]
io.misaligned_fault_d <= _T_168 @[w.scala 150:25]
node _T_169 = bits(sideeffect_misaligned_fault_d, 0, 0) @[w.scala 151:111]
node _T_170 = mux(_T_169, UInt<4>("h01"), UInt<4>("h00")) @[w.scala 151:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_170) @[w.scala 151:39]
node _T_171 = bits(io.misaligned_fault_d, 0, 0) @[w.scala 152:50]
node _T_172 = bits(misaligned_fault_mscause_d, 3, 0) @[w.scala 152:84]
node _T_173 = bits(access_fault_mscause_d, 3, 0) @[w.scala 152:113]
node _T_174 = mux(_T_171, _T_172, _T_173) @[w.scala 152:27]
io.exc_mscause_d <= _T_174 @[w.scala 152:21]
node _T_175 = not(start_addr_in_dccm_d) @[w.scala 153:66]
node _T_176 = and(start_addr_in_dccm_region_d, _T_175) @[w.scala 153:64]
node _T_177 = not(end_addr_in_dccm_d) @[w.scala 153:120]
node _T_178 = and(end_addr_in_dccm_region_d, _T_177) @[w.scala 153:118]
node _T_179 = or(_T_176, _T_178) @[w.scala 153:88]
node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[w.scala 153:142]
node _T_181 = and(_T_180, io.lsu_pkt_d.fast_int) @[w.scala 153:163]
io.fir_dccm_access_error_d <= _T_181 @[w.scala 153:31]
node _T_182 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[w.scala 154:66]
node _T_183 = not(_T_182) @[w.scala 154:36]
node _T_184 = and(_T_183, io.lsu_pkt_d.valid) @[w.scala 154:95]
node _T_185 = and(_T_184, io.lsu_pkt_d.fast_int) @[w.scala 154:116]
io.fir_nondccm_access_error_d <= _T_185 @[w.scala 154:33]
reg _T_186 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[w.scala 156:60]
_T_186 <= is_sideeffects_d @[w.scala 156:60]
io.is_sideeffects_m <= _T_186 @[w.scala 156:50]

111
el2_lsu_addrcheck.v
View File

@ -1,111 +0,0 @@
module rvrangecheck(
input [31:0] io_addr,
output io_in_range,
output io_in_region
);
assign io_in_range = io_addr[31:15] == 17'h0; // @[beh_lib.scala 147:17]
assign io_in_region = io_addr[31:28] == 4'h0; // @[beh_lib.scala 143:17]
endmodule
module el2_lsu_addrcheck(
input clock,
input reset,
input io_lsu_c2_m_clk,
input [31:0] io_start_addr_d,
input [31:0] io_end_addr_d,
input io_lsu_pkt_d_fast_int,
input io_lsu_pkt_d_by,
input io_lsu_pkt_d_half,
input io_lsu_pkt_d_word,
input io_lsu_pkt_d_dword,
input io_lsu_pkt_d_load,
input io_lsu_pkt_d_store,
input io_lsu_pkt_d_unsign,
input io_lsu_pkt_d_dma,
input io_lsu_pkt_d_store_data_bypass_d,
input io_lsu_pkt_d_load_ldst_bypass_d,
input io_lsu_pkt_d_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input [31:0] io_dec_tlu_mrac_ff,
input [3:0] io_rs1_region_d,
input [31:0] io_rs1_d,
output io_is_sideeffects_m,
output io_addr_in_dccm_d,
output io_addr_in_pic_d,
output io_addr_external_d,
output io_access_fault_d,
output io_misaligned_fault_d,
output [3:0] io_exc_mscause_d,
output io_fir_dccm_access_error_d,
output io_fir_nondccm_access_error_d,
input io_scan_mode
);
wire [31:0] start_addr_pic_rangecheck_io_addr; // @[w.scala 78:41]
wire start_addr_pic_rangecheck_io_in_range; // @[w.scala 78:41]
wire start_addr_pic_rangecheck_io_in_region; // @[w.scala 78:41]
wire [31:0] end_addr_pic_rangecheck_io_addr; // @[w.scala 84:39]
wire end_addr_pic_rangecheck_io_in_range; // @[w.scala 84:39]
wire end_addr_pic_rangecheck_io_in_region; // @[w.scala 84:39]
wire start_addr_dccm_or_pic = start_addr_pic_rangecheck_io_in_region; // @[w.scala 89:60]
wire _T_3 = io_rs1_region_d == 4'hf; // @[w.scala 90:54]
wire base_reg_dccm_or_pic = _T_3 | _T_3; // @[w.scala 90:73]
wire [31:0] _T_36 = io_start_addr_d | 32'h7fffffff; // @[w.scala 102:56]
wire _T_38 = _T_36 == 32'h7fffffff; // @[w.scala 102:80]
wire [31:0] _T_41 = io_start_addr_d | 32'h3fffffff; // @[w.scala 103:56]
wire _T_43 = _T_41 == 32'hffffffff; // @[w.scala 103:80]
wire _T_45 = _T_38 | _T_43; // @[w.scala 102:129]
wire [31:0] _T_47 = io_start_addr_d | 32'h1fffffff; // @[w.scala 104:56]
wire _T_49 = _T_47 == 32'hbfffffff; // @[w.scala 104:80]
wire _T_51 = _T_45 | _T_49; // @[w.scala 103:129]
wire [31:0] _T_53 = io_start_addr_d | 32'hfffffff; // @[w.scala 105:56]
wire _T_55 = _T_53 == 32'h8fffffff; // @[w.scala 105:80]
wire _T_57 = _T_51 | _T_55; // @[w.scala 104:129]
wire [31:0] _T_83 = io_end_addr_d | 32'h7fffffff; // @[w.scala 111:57]
wire _T_85 = _T_83 == 32'h7fffffff; // @[w.scala 111:81]
wire [31:0] _T_88 = io_end_addr_d | 32'h3fffffff; // @[w.scala 112:58]
wire _T_90 = _T_88 == 32'hffffffff; // @[w.scala 112:82]
wire _T_92 = _T_85 | _T_90; // @[w.scala 111:130]
wire [31:0] _T_94 = io_end_addr_d | 32'h1fffffff; // @[w.scala 113:58]
wire _T_96 = _T_94 == 32'hbfffffff; // @[w.scala 113:82]
wire _T_98 = _T_92 | _T_96; // @[w.scala 112:131]
wire [31:0] _T_100 = io_end_addr_d | 32'hfffffff; // @[w.scala 114:58]
wire _T_102 = _T_100 == 32'h8fffffff; // @[w.scala 114:82]
wire _T_104 = _T_98 | _T_102; // @[w.scala 113:131]
wire non_dccm_access_ok = _T_57 & _T_104; // @[w.scala 110:7]
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[w.scala 120:57]
wire _T_131 = io_start_addr_d[1:0] != 2'h0; // @[w.scala 121:76]
wire _T_132 = ~io_lsu_pkt_d_word; // @[w.scala 121:92]
wire _T_133 = _T_131 | _T_132; // @[w.scala 121:90]
wire picm_access_fault_d = io_addr_in_pic_d & _T_133; // @[w.scala 121:51]
wire mpu_access_fault_d = ~non_dccm_access_ok; // @[w.scala 134:64]
wire _T_149 = mpu_access_fault_d | picm_access_fault_d; // @[w.scala 146:70]
wire _T_150 = _T_149 | regpred_access_fault_d; // @[w.scala 146:92]
wire _T_151 = _T_150 & io_lsu_pkt_d_valid; // @[w.scala 146:118]
wire _T_152 = ~io_lsu_pkt_d_dma; // @[w.scala 146:141]
wire [3:0] _T_158 = picm_access_fault_d ? 4'h6 : 4'h0; // @[w.scala 147:164]
wire [3:0] _T_159 = regpred_access_fault_d ? 4'h5 : _T_158; // @[w.scala 147:120]
wire [3:0] access_fault_mscause_d = mpu_access_fault_d ? 4'h3 : _T_159; // @[w.scala 147:80]
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[w.scala 148:61]
wire _T_166 = regcross_misaligned_fault_d & io_lsu_pkt_d_valid; // @[w.scala 150:113]
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : 4'h0; // @[w.scala 151:39]
rvrangecheck start_addr_pic_rangecheck ( // @[w.scala 78:41]
.io_addr(start_addr_pic_rangecheck_io_addr),
.io_in_range(start_addr_pic_rangecheck_io_in_range),
.io_in_region(start_addr_pic_rangecheck_io_in_region)
);
rvrangecheck end_addr_pic_rangecheck ( // @[w.scala 84:39]
.io_addr(end_addr_pic_rangecheck_io_addr),
.io_in_range(end_addr_pic_rangecheck_io_in_range),
.io_in_region(end_addr_pic_rangecheck_io_in_region)
);
assign io_is_sideeffects_m = 1'h0; // @[w.scala 156:50]
assign io_addr_in_dccm_d = 1'h0; // @[w.scala 91:32]
assign io_addr_in_pic_d = start_addr_pic_rangecheck_io_in_range & end_addr_pic_rangecheck_io_in_range; // @[w.scala 92:32]
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[w.scala 94:30]
assign io_access_fault_d = _T_151 & _T_152; // @[w.scala 146:21]
assign io_misaligned_fault_d = _T_166 & _T_152; // @[w.scala 150:25]
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[w.scala 152:21]
assign io_fir_dccm_access_error_d = 1'h0; // @[w.scala 153:31]
assign io_fir_nondccm_access_error_d = io_lsu_pkt_d_valid & io_lsu_pkt_d_fast_int; // @[w.scala 154:33]
assign start_addr_pic_rangecheck_io_addr = io_start_addr_d; // @[w.scala 79:37]
assign end_addr_pic_rangecheck_io_addr = io_end_addr_d; // @[w.scala 85:35]
endmodule

179
el2_lsu_bus_buffer.anno.json
View File

@ -1,179 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_full_hit_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_load",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_flush_m_up",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_valid",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_inv_r",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_misaligned",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_error",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_bus_buffer.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_bus_buffer"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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