Memory connection updated
This commit is contained in:
Laraib Khan
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["lsu.buffer","lsu.bus_intf","lsu.clkdomain","lsu.dccm_ctl","lsu.lsc_ctl","lsu.lsu_main","lsu.stbuf"]
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["DMA","QUASAR","QUASAR_Wrp","dbg.debug","dec.dec_dec","dec.dec_main","dec.tlu","exu.div_main","exu.exu_main","exu.mul","ifu.ifu_top","lib.axi4_to_ahb","lsu.buffer","lsu.bus_intf","lsu.clkdomain","lsu.dccm_ctl","lsu.lsc_ctl","lsu.lsu_main","lsu.stbuf","pic"]
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[0m[[0m[33mwarn[0m] [0m[0mthere were 337 feature warnings; re-run with -feature for details[0m
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[0m[[0m[33mwarn[0m] [0m[0mone warning found[0m
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[0m[[0m[33mwarn[0m] [0m[0m/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive.[0m
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[0m[[0m[33mwarn[0m] [0m[0mIt would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _)[0m
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[0m[[0m[33mwarn[0m] [0m[0m (ICACHE_WAYPACK, ICACHE_ECC) match{[0m
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[0m[[0m[33mwarn[0m] [0m[0m ^[0m
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[0m[[0m[33mwarn[0m] [0m[0m/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar.scala:326:8: Generated class QUASAR differs only in case from quasar.[0m
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[0m[[0m[33mwarn[0m] [0m[0m Such classes will overwrite one another on case-insensitive filesystems.[0m
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[0m[[0m[33mwarn[0m] [0m[0mobject QUASAR extends App {[0m
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[0m[[0m[33mwarn[0m] [0m[0m ^[0m
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[0m[[0m[33mwarn[0m] [0m[0mthere were 5450 feature warnings; re-run with -feature for details[0m
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[0m[[0m[0mdebug[0m] [0m[0mJar uptodate: /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/quasar_2.12-3.3.0.jar[0m
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[0m[[0m[0mdebug[0m] [0m[0mPackaging /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/quasar_2.12-3.3.0.jar ...[0m
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[0m[[0m[0mdebug[0m] [0m[0mInput file mappings:[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_addrcheck.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_addrcheck.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_dccm_ctl$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/clkdomain$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/bus_intf.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_buffer$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/dccm_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_trigger.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_trigger.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/dccm_ctl$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/buffer.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/bus_intf$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/stbuf.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_ecc.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_ecc.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/buffer$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/bus_intf$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/stbuf$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_stbuf$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_main$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_intf$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/stbuf$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_main.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_ecc$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/dccm_ctl$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_buffer.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_buffer.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsc_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/lsc_ctl$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/clkdomain.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lsu/buffer$.class[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer$.class[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_main$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main$.class[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_lsc_ctl.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_dccm_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_addrcheck$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/clkdomain$delayedInit$body.class[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_trigger$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_clkdomain.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_clkdomain.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_intf.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_intf.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_lsc_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsc_ctl$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_stbuf.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_stbuf.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_clkdomain$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m DMA.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/DMA.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m pic_ctrl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic_ctrl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$gated_latch$$anon$4.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffiee$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffiee$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffpcie$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffpcie$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdff_fpga$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdff_fpga$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$gated_latch.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$gated_latch.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvclkhdr$$anon$5.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/param.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/param.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvoclkhdr$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvoclkhdr$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode_64$$anon$3.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdfflie$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdfflie$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvclkhdr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvclkhdr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/ahb_to_axi4$$anon$1$$anon$2.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class[0m
|
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|
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|
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|
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|
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[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb_IO.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/ahb_to_axi4$$anon$1.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffsc_fpga$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvsyncss_fpga$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvsyncss_fpga$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvsyncss$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvsyncss$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/ahb_to_axi4.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/ahb_to_axi4.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$$anon$1.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$$anon$1.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffppe$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffppe$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode_64.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffie$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffie$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffs_fpga$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/int_exc$$anon$3.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/int_exc$$anon$3.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/dec_main$delayedInit$body.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_timer_ctl_IO.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec_ctl.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_csr_read_IO.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_mux_and_flops.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/perf_mux_and_flops.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/tlu$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/tlu$.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/CSRs.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/CSRs.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m dec/dec_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/int_exc.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/int_exc.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_ib_ctl.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_ib_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_mux_and_flops$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/perf_mux_and_flops$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/CSR_VAL.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/CSR_VAL.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/tlu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/tlu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_timer_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_timer_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_csr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/perf_csr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_tlu_ctl_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_gpr_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_gpr_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/csr_tlu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/csr_tlu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_main.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_main.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_main$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_main$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_trigger.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trigger.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_tlu_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_tlu_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_gpr_ctl_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_csr_read.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_csr_read.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/CSR_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/CSR_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_trigger$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_csr$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/perf_csr$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/tlu$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/tlu$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_ib_ctl_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/mem_lib.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_lib.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/ifu_iccm_mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/ifu_ic_mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/dmi_jtag_to_core_sync.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/gated_latch.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/gated_latch.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/mem_mod.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_mod.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/beh_lib.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/beh_lib.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/lsu_dccm_mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/dmi_wrapper.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_wrapper.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m vsrc/rvjtag_tap.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/rvjtag_tap.sv[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m QUASAR$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/QUASAR$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m quasar_wrapper$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/quasar_wrapper$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_top$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_top$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_top$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_top$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_aln_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_compress_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_compress_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_mem_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_mem_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/mem_ctl_io.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/mem_ctl_io.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_top.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_top.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_ifc_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_bp_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_bp_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_bp_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_compress_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_aln_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_aln_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_ifc_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m pic$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m pic.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dmi[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper_module.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper_module.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper_module$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dma_ctrl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dma_ctrl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m QUASAR_Wrp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/QUASAR_Wrp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m QUASAR_Wrp$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/QUASAR_Wrp$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m quasar_bundle$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/quasar_bundle$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem/quasar$mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/quasar$mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem/blackbox_mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/blackbox_mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem/Mem_bundle.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/Mem_bundle.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem/quasar.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/quasar.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem/quasar$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/quasar$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m mem/mem_lsu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/mem_lsu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_ifc.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_ifc.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/reg_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/reg_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ic_mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ic_mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_bp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_bp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/predict_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/predict_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_mem_ctrl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_mem_ctrl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/class_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/class_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_out.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_out.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/br_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/br_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/cache_debug_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/cache_debug_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_alu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_alu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/decode_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/decode_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dccm_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_aln.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_aln.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dma_mem_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_mem_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/write_resp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_resp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/tlu_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/tlu_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/tlu_busbuff.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/tlu_busbuff.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/read_addr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_addr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/exu_ifu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/exu_ifu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/write_data.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_data.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dma_dccm_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_dccm_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dctl_busbuff.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dctl_busbuff.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dma_lsc_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_lsc_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/mul_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/mul_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/div_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/div_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_tlu_csr_pkt.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ib_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ib_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dctl_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dctl_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dma_ifc.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_ifc.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/write_addr$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_addr$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/aln_dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/aln_dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_tlu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_tlu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/read_addr$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_addr$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/gpr_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/gpr_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_error_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_error_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_channel.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_channel.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/aln_ib.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/aln_ib.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_in.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_in.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/iccm_mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/iccm_mem.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/inst_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/inst_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/write_addr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_addr.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dbg_ib.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dbg_ib.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/alu_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/alu_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_div.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_div.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dbg_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dbg_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ic_data_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/br_tlu_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/br_tlu_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/exu_bp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/exu_bp.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dest_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dest_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/tlu_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/tlu_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ic_tag_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/rets_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/rets_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/trap_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/trap_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/trace_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/trace_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ccm_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/axi_channels$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/axi_channels$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ifu_dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ifu_dec.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_out_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_out_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_pic.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_pic.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_pic.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_pic.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/read_data.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_data.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dec_dbg.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_dbg.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/ifu_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ifu_dma.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/load_cam_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/load_cam_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/axi_channels.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/axi_channels.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/read_data$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_data$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/dbg_dctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dbg_dctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/trigger_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/trigger_pkt_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m include/inst_pkt_t$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/inst_pkt_t$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m QUASAR_Wrp$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/debug.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/debug.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/state_t$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/state_t$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/dbg.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/dbg.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/sb_state_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/sb_state_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/dbg$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/dbg$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/debug$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/debug$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/state_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/state_t.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/sb_state_t$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/sb_state_t$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dbg/debug$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/debug$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m DMA$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/DMA$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m QUASAR$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/QUASAR$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m pic$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m quasar_bundle.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/quasar_bundle.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m quasar.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/quasar.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m dma_ctrl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dma_ctrl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m DMA$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/DMA$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m .vscode[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/.vscode[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m .vscode/settings.json[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/.vscode/settings.json[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m pic_ctrl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic_ctrl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m quasar_wrapper.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/quasar_wrapper.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m QUASAR.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/QUASAR.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/mul$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/mul$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/mul$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/mul$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_4bit_fullshortq.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_3bit_fullshortq$$anon$5.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq$$anon$5.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_main$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_existing_1bit_cheapshortq.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/div_main$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/div_main$.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_mul_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_cls.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_cls.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/div_main$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/div_main$delayedInit$body.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_alu_ctl$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_mul_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_2bit_fullshortq$$anon$4.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq$$anon$4.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_1bit_fullshortq$$anon$3.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_main$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_main$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_1bit_fullshortq.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_2bit_fullshortq.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_4bit_fullshortq$$anon$6.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_ctl.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_3bit_fullshortq.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m exu/div_main.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/div_main.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_cls$$anon$7.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m exu/exu$$anon$1.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu$$anon$1.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_existing_1bit_cheapshortq$$anon$2.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq$$anon$2.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_alu_ctl.class[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_alu_ctl.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0mDone packaging.[0m
|
||||
|
|
|
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Loading…
Reference in New Issue