colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Modify RAM and ROM to WIDTH=12 4K Byte.

This commit is contained in:
colin 2022-03-20 09:04:32 +00:00
parent cdd2f57902
commit b6a916aca4
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
demo/link.ld
View File

@ -8,8 +8,8 @@ SECTIONS
.text_init : { *(.text_init*) } .text_init : { *(.text_init*) }
.text : { *(.text*) } .text : { *(.text*) }
_end = .; _end = .;
. = 0x80004000; . = 0xf0040000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; } .data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
.bss : { *(.bss) } .bss : { *(.bss) }
. = 0xd0580000; . = 0xd0580000;
.data.io : { *(.data.io) } .data.io : { *(.data.io) }

4
demo/link_pro.ld
View File

@ -8,8 +8,8 @@ SECTIONS
.text_init : { *(.text_init*) } .text_init : { *(.text_init*) }
.text : { *(.text*) } .text : { *(.text*) }
_end = .; _end = .;
. = 0x4000; . = 0x800;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; } .data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
.bss : { *(.bss) } .bss : { *(.bss) }
. = 0xd0580000; . = 0xd0580000;
.data.io : { *(.data.io) } .data.io : { *(.data.io) }

2
soc/ahb_sif.sv
View File

@ -53,7 +53,7 @@ module axi_slv #(
output reg [TAGW-1:0] bid output reg [TAGW-1:0] bid
); );
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k parameter MEM_DEPTH = 12; // memory size = 0x8000 = 32k WIDTH=15
bit [7:0] mem[(1<<MEM_DEPTH)-1:0]; bit [7:0] mem[(1<<MEM_DEPTH)-1:0];