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lsu with newer release

This commit is contained in:
​Laraib Khan 2020-12-22 15:24:39 +05:00
parent 9f30e1773b
commit b8b042faa8
63 changed files with 68701 additions and 160 deletions
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2
firrtl_black_box_resource_files.f
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/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv

547
lsu.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_mken",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_single_ecc_error_incr",
"sources":[
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_trigger_match_m",
"sources":[
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"~lsu|lsu>io_trigger_pkt_any_1_store",
"~lsu|lsu>io_trigger_pkt_any_3_m",
"~lsu|lsu>io_trigger_pkt_any_0_load",
"~lsu|lsu>io_trigger_pkt_any_0_select",
"~lsu|lsu>io_trigger_pkt_any_3_store",
"~lsu|lsu>io_trigger_pkt_any_2_store",
"~lsu|lsu>io_trigger_pkt_any_1_load",
"~lsu|lsu>io_trigger_pkt_any_1_select",
"~lsu|lsu>io_trigger_pkt_any_2_m",
"~lsu|lsu>io_trigger_pkt_any_3_load",
"~lsu|lsu>io_trigger_pkt_any_3_select",
"~lsu|lsu>io_trigger_pkt_any_2_load",
"~lsu|lsu>io_trigger_pkt_any_2_select",
"~lsu|lsu>io_trigger_pkt_any_0_m",
"~lsu|lsu>io_trigger_pkt_any_1_m",
"~lsu|lsu>io_trigger_pkt_any_0_tdata2",
"~lsu|lsu>io_trigger_pkt_any_0_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_1_tdata2",
"~lsu|lsu>io_trigger_pkt_any_1_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_3_tdata2",
"~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_2_tdata2",
"~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wren",
"sources":[
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_hi",
"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_store_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_result_m",
"sources":[
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_load_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_tlu_force_halt",
"~lsu|lsu>io_lsu_pic_picm_rd_data",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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lsu.fir Normal file
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12034
lsu.v Normal file
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111
lsu_addrcheck.anno.json Normal file
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@ -0,0 +1,111 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_addr_external_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_fir_nondccm_access_error_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_fast_int",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_misaligned_fault_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_dma",
"~lsu_addrcheck|lsu_addrcheck>io_addr_external_d",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_store",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_load",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_by",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_word",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_half",
"~lsu_addrcheck|lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_access_fault_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_dma",
"~lsu_addrcheck|lsu_addrcheck>io_addr_in_pic_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_word",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_rs1_region_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_exc_mscause_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_misaligned_fault_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_dma",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_addr_external_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_store",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_load",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_by",
"~lsu_addrcheck|lsu_addrcheck>io_addr_in_pic_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_word",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_half",
"~lsu_addrcheck|lsu_addrcheck>io_rs1_region_d",
"~lsu_addrcheck|lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_addr_in_dccm_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_addr_in_pic_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_fir_dccm_access_error_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_fast_int",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_addrcheck"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

253
lsu_addrcheck.fir Normal file
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_addrcheck :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 361:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 361:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]

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lsu_addrcheck.v Normal file
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@ -0,0 +1,193 @@
module lsu_addrcheck(
input clock,
input reset,
input io_lsu_c2_m_clk,
input [31:0] io_start_addr_d,
input [31:0] io_end_addr_d,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_d_bits_fast_int,
input io_lsu_pkt_d_bits_by,
input io_lsu_pkt_d_bits_half,
input io_lsu_pkt_d_bits_word,
input io_lsu_pkt_d_bits_dword,
input io_lsu_pkt_d_bits_load,
input io_lsu_pkt_d_bits_store,
input io_lsu_pkt_d_bits_unsign,
input io_lsu_pkt_d_bits_dma,
input io_lsu_pkt_d_bits_store_data_bypass_d,
input io_lsu_pkt_d_bits_load_ldst_bypass_d,
input io_lsu_pkt_d_bits_store_data_bypass_m,
input [31:0] io_dec_tlu_mrac_ff,
input [3:0] io_rs1_region_d,
input [31:0] io_rs1_d,
output io_is_sideeffects_m,
output io_addr_in_dccm_d,
output io_addr_in_pic_d,
output io_addr_external_d,
output io_access_fault_d,
output io_misaligned_fault_d,
output [3:0] io_exc_mscause_d,
output io_fir_dccm_access_error_d,
output io_fir_nondccm_access_error_d,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 356:49]
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39]
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 356:49]
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39]
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45]
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39]
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39]
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60]
wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55]
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91]
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50]
wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121]
wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62]
wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60]
wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137]
wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185]
wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158]
wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80]
wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56]
wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138]
wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116]
wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90]
wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148]
wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56]
wire _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88]
wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56]
wire _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88]
wire _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153]
wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56]
wire _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88]
wire _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153]
wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56]
wire _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88]
wire _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153]
wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57]
wire _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89]
wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58]
wire _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90]
wire _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154]
wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58]
wire _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90]
wire _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155]
wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58]
wire _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90]
wire _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155]
wire non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7]
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57]
wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76]
wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92]
wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90]
wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51]
wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87]
wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64]
wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62]
wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57]
wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36]
wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34]
wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112]
wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29]
wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85]
wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29]
wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85]
wire _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33]
wire _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64]
wire mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62]
wire _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49]
wire _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70]
wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92]
wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118]
wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141]
wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164]
wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120]
wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80]
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35]
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61]
wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59]
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57]
wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90]
wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57]
wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113]
wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80]
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39]
wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66]
wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64]
wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120]
wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118]
wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88]
wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142]
wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66]
wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36]
wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95]
reg _T_201; // @[lsu_addrcheck.scala 121:60]
assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50]
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32]
assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32]
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30]
assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21]
assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25]
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21]
assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31]
assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_201 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_201 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
if (reset) begin
_T_201 <= 1'h0;
end else begin
_T_201 <= _T_32 & _T_33;
end
end
endmodule

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lsu_bus_buffer.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
"~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_bus_buffer.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_bus_buffer"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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lsu_bus_intf.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_bus_read_data_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~lsu_bus_intf|lsu_bus_intf>io_store_data_r",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_load",
"~lsu_bus_intf|lsu_bus_intf>io_flush_m_up",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_valid",
"~lsu_bus_intf|lsu_bus_intf>io_is_sideeffects_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_tag_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_lsu_bus_buffer_full_any",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_d",
"~lsu_bus_intf|lsu_bus_intf>io_dec_lsu_valid_raw_d",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_bus_intf.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_bus_intf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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lsu_clkdomain.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_busm_clken",
"sources":[
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
"~lsu_clkdomain|lsu_clkdomain>io_clk_override",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_empty_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_obuf_c1_clken",
"sources":[
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
"~lsu_clkdomain|lsu_clkdomain>io_clk_override",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_pend_any",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_clkdomain.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_clkdomain"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

443
lsu_clkdomain.fir Normal file
View File

@ -0,0 +1,443 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_clkdomain :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_11 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_clkdomain :
input clock : Clock
input reset : AsyncReset
output io : {flip active_clk : Clock, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_bus_obuf_c1_clken : UInt<1>, lsu_busm_clken : UInt<1>, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36]
wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 61:36]
wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 62:36]
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 64:47]
node lsu_c1_m_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 64:65]
node _T_1 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 65:51]
node lsu_c1_r_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 65:70]
node _T_2 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 67:47]
node lsu_c2_m_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 67:66]
node _T_3 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 68:47]
node lsu_c2_r_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 68:66]
node _T_4 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 70:49]
node lsu_store_c1_m_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 70:76]
node _T_5 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 71:49]
node lsu_store_c1_r_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 71:76]
node _T_6 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 72:55]
node _T_7 = or(_T_6, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 72:77]
node lsu_stbuf_c1_clken = or(_T_7, io.clk_override) @[lsu_clkdomain.scala 72:107]
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 73:49]
node _T_8 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:62]
node _T_9 = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 74:80]
node _T_10 = and(_T_9, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 74:99]
io.lsu_bus_obuf_c1_clken <= _T_10 @[lsu_clkdomain.scala 74:30]
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 75:32]
node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 75:61]
node _T_13 = or(_T_12, io.dec_tlu_force_halt) @[lsu_clkdomain.scala 75:79]
node lsu_bus_buf_c1_clken = or(_T_13, io.clk_override) @[lsu_clkdomain.scala 75:103]
node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 77:48]
node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 77:69]
node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 77:90]
node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:114]
node _T_18 = or(_T_16, _T_17) @[lsu_clkdomain.scala 77:112]
node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:145]
node _T_20 = or(_T_18, _T_19) @[lsu_clkdomain.scala 77:143]
node lsu_free_c1_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:169]
node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 78:50]
node lsu_free_c2_clken = or(_T_21, io.clk_override) @[lsu_clkdomain.scala 78:72]
node _T_22 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 79:25]
node _T_23 = or(_T_22, io.lsu_busreq_r) @[lsu_clkdomain.scala 79:54]
node _T_24 = or(_T_23, io.clk_override) @[lsu_clkdomain.scala 79:72]
node _T_25 = and(_T_24, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 79:91]
io.lsu_busm_clken <= _T_25 @[lsu_clkdomain.scala 79:21]
reg _T_26 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:62]
_T_26 <= lsu_free_c1_clken @[lsu_clkdomain.scala 82:62]
lsu_free_c1_clken_q <= _T_26 @[lsu_clkdomain.scala 82:26]
reg _T_27 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 84:67]
_T_27 <= lsu_c1_m_clken @[lsu_clkdomain.scala 84:67]
lsu_c1_m_clken_q <= _T_27 @[lsu_clkdomain.scala 84:26]
reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67]
_T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67]
lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26]
node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:59]
inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 344:17]
rvclkhdr.io.en <= _T_29 @[lib.scala 345:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 87:26]
node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:59]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_1.io.en <= _T_30 @[lib.scala 345:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 88:26]
node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:59]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_2.io.en <= _T_31 @[lib.scala 345:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 89:26]
node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:59]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 343:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_3.io.en <= _T_32 @[lib.scala 345:16]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 90:26]
node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:65]
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 343:22]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_4.io.en <= _T_33 @[lib.scala 345:16]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 91:26]
node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:65]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_5.io.en <= _T_34 @[lib.scala 345:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 92:26]
node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:63]
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_6.io.en <= _T_35 @[lib.scala 345:16]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 93:26]
node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:66]
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_7.io.en <= _T_36 @[lib.scala 345:16]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 94:26]
node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69]
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_8.io.en <= _T_37 @[lib.scala 345:16]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 95:26]
node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:65]
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_9.io.en <= _T_38 @[lib.scala 345:16]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 96:26]
node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62]
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 343:22]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_10.io.en <= _T_39 @[lib.scala 345:16]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 97:26]
node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:62]
inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 343:22]
rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_11.io.en <= _T_40 @[lib.scala 345:16]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 98:26]

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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
endmodule
module lsu_clkdomain(
input clock,
input reset,
input io_active_clk,
input io_clk_override,
input io_dec_tlu_force_halt,
input io_dma_dccm_req,
input io_ldst_stbuf_reqvld_r,
input io_stbuf_reqvld_any,
input io_stbuf_reqvld_flushed_any,
input io_lsu_busreq_r,
input io_lsu_bus_buffer_pend_any,
input io_lsu_bus_buffer_empty_any,
input io_lsu_stbuf_empty_any,
input io_lsu_bus_clk_en,
input io_lsu_p_valid,
input io_lsu_p_bits_fast_int,
input io_lsu_p_bits_by,
input io_lsu_p_bits_half,
input io_lsu_p_bits_word,
input io_lsu_p_bits_dword,
input io_lsu_p_bits_load,
input io_lsu_p_bits_store,
input io_lsu_p_bits_unsign,
input io_lsu_p_bits_dma,
input io_lsu_p_bits_store_data_bypass_d,
input io_lsu_p_bits_load_ldst_bypass_d,
input io_lsu_p_bits_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_d_bits_fast_int,
input io_lsu_pkt_d_bits_by,
input io_lsu_pkt_d_bits_half,
input io_lsu_pkt_d_bits_word,
input io_lsu_pkt_d_bits_dword,
input io_lsu_pkt_d_bits_load,
input io_lsu_pkt_d_bits_store,
input io_lsu_pkt_d_bits_unsign,
input io_lsu_pkt_d_bits_dma,
input io_lsu_pkt_d_bits_store_data_bypass_d,
input io_lsu_pkt_d_bits_load_ldst_bypass_d,
input io_lsu_pkt_d_bits_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_lsu_pkt_r_bits_fast_int,
input io_lsu_pkt_r_bits_by,
input io_lsu_pkt_r_bits_half,
input io_lsu_pkt_r_bits_word,
input io_lsu_pkt_r_bits_dword,
input io_lsu_pkt_r_bits_load,
input io_lsu_pkt_r_bits_store,
input io_lsu_pkt_r_bits_unsign,
input io_lsu_pkt_r_bits_dma,
input io_lsu_pkt_r_bits_store_data_bypass_d,
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
input io_lsu_pkt_r_bits_store_data_bypass_m,
output io_lsu_bus_obuf_c1_clken,
output io_lsu_busm_clken,
output io_lsu_c1_m_clk,
output io_lsu_c1_r_clk,
output io_lsu_c2_m_clk,
output io_lsu_c2_r_clk,
output io_lsu_store_c1_m_clk,
output io_lsu_store_c1_r_clk,
output io_lsu_stbuf_c1_clk,
output io_lsu_bus_obuf_c1_clk,
output io_lsu_bus_ibuf_c1_clk,
output io_lsu_bus_buf_c1_clk,
output io_lsu_busm_clk,
output io_lsu_free_c2_clk,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_io_en; // @[lib.scala 343:22]
wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_1_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_1_io_en; // @[lib.scala 343:22]
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_2_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_2_io_en; // @[lib.scala 343:22]
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_3_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_3_io_en; // @[lib.scala 343:22]
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_4_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_4_io_en; // @[lib.scala 343:22]
wire rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_5_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_5_io_en; // @[lib.scala 343:22]
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_6_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_6_io_en; // @[lib.scala 343:22]
wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_7_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_7_io_en; // @[lib.scala 343:22]
wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_8_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_8_io_en; // @[lib.scala 343:22]
wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_9_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_9_io_en; // @[lib.scala 343:22]
wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_10_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_10_io_en; // @[lib.scala 343:22]
wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22]
wire rvclkhdr_11_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_11_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_11_io_en; // @[lib.scala 343:22]
wire rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22]
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 64:47]
wire lsu_c1_m_clken = _T | io_clk_override; // @[lsu_clkdomain.scala 64:65]
reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 84:67]
wire _T_1 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 65:51]
wire lsu_c1_r_clken = _T_1 | io_clk_override; // @[lsu_clkdomain.scala 65:70]
wire _T_2 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 67:47]
reg lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 85:67]
wire _T_3 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 68:47]
wire _T_4 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[lsu_clkdomain.scala 70:49]
wire _T_5 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[lsu_clkdomain.scala 71:49]
wire _T_6 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[lsu_clkdomain.scala 72:55]
wire _T_7 = _T_6 | io_stbuf_reqvld_flushed_any; // @[lsu_clkdomain.scala 72:77]
wire _T_8 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:62]
wire _T_9 = _T_8 | io_clk_override; // @[lsu_clkdomain.scala 74:80]
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 75:32]
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 75:61]
wire _T_13 = _T_12 | io_dec_tlu_force_halt; // @[lsu_clkdomain.scala 75:79]
wire _T_14 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[lsu_clkdomain.scala 77:48]
wire _T_15 = _T_14 | io_lsu_pkt_m_valid; // @[lsu_clkdomain.scala 77:69]
wire _T_16 = _T_15 | io_lsu_pkt_r_valid; // @[lsu_clkdomain.scala 77:90]
wire _T_18 = _T_16 | _T_11; // @[lsu_clkdomain.scala 77:112]
wire _T_19 = ~io_lsu_stbuf_empty_any; // @[lsu_clkdomain.scala 77:145]
wire _T_20 = _T_18 | _T_19; // @[lsu_clkdomain.scala 77:143]
wire lsu_free_c1_clken = _T_20 | io_clk_override; // @[lsu_clkdomain.scala 77:169]
reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 82:62]
wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 78:50]
wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72]
rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en),
.io_scan_mode(rvclkhdr_6_io_scan_mode)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en),
.io_scan_mode(rvclkhdr_7_io_scan_mode)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_8_io_l1clk),
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en),
.io_scan_mode(rvclkhdr_8_io_scan_mode)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_9_io_l1clk),
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_10_io_l1clk),
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en),
.io_scan_mode(rvclkhdr_10_io_scan_mode)
);
rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_11_io_l1clk),
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en),
.io_scan_mode(rvclkhdr_11_io_scan_mode)
);
assign io_lsu_bus_obuf_c1_clken = _T_9 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 74:30]
assign io_lsu_busm_clken = _T_24 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 79:21]
assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[lsu_clkdomain.scala 87:26]
assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[lsu_clkdomain.scala 88:26]
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[lsu_clkdomain.scala 89:26]
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[lsu_clkdomain.scala 90:26]
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[lsu_clkdomain.scala 91:26]
assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[lsu_clkdomain.scala 92:26]
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[lsu_clkdomain.scala 93:26]
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[lsu_clkdomain.scala 95:26]
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[lsu_clkdomain.scala 94:26]
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 96:26]
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 97:26]
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 98:26]
assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_io_en = _T | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_1_io_en = _T_1 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_2_io_en = _T_2 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_3_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_4_io_en = _T_4 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_5_io_en = _T_5 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_6_io_en = _T_7 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_8_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_9_io_en = _T_13 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_10_io_en = io_lsu_busm_clken; // @[lib.scala 345:16]
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
lsu_c1_m_clken_q = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
lsu_c1_r_clken_q = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
lsu_free_c1_clken_q = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
lsu_c1_m_clken_q = 1'h0;
end
if (reset) begin
lsu_c1_r_clken_q = 1'h0;
end
if (reset) begin
lsu_free_c1_clken_q = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
lsu_c1_m_clken_q <= 1'h0;
end else begin
lsu_c1_m_clken_q <= _T | io_clk_override;
end
end
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
lsu_c1_r_clken_q <= 1'h0;
end else begin
lsu_c1_r_clken_q <= _T_1 | io_clk_override;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
lsu_free_c1_clken_q <= 1'h0;
end else begin
lsu_free_c1_clken_q <= _T_20 | io_clk_override;
end
end
endmodule

386
lsu_dccm_ctl.anno.json Normal file
View File

@ -0,0 +1,386 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_commit_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_picm_mask_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ldst_dual_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rtag",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_mem_tag_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_hi_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_addr",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rvalid",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_bits_dma",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_mken",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_wdata",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_dccm_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_dccm_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2252
lsu_dccm_ctl.fir Normal file
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File diff suppressed because it is too large Load Diff

1308
lsu_dccm_ctl.v Normal file
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File diff suppressed because it is too large Load Diff

339
lsu_ecc.anno.json Normal file
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@ -0,0 +1,339 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_single_ecc_error_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_single_ecc_error_hi_r",
"~lsu_ecc|lsu_ecc>io_single_ecc_error_lo_r",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_ecc_hi",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_hi_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_hi",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_double_ecc_error_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_ecc_lo_r_ff",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_lo_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_lo",
"~lsu_ecc|lsu_ecc>io_stbuf_data_any",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_single_ecc_error_hi_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_lo_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_single_ecc_error_lo_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_hi_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_lo_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_ecc_hi_r_ff",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_hi_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_hi",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_hi_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_single_ecc_error_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_ecc_lo",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_lo_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_lo",
"~lsu_ecc|lsu_ecc>io_stbuf_data_any",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_stbuf_ecc_any",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_lo_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_lo",
"~lsu_ecc|lsu_ecc>io_stbuf_data_any",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_double_ecc_error_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_ecc.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_ecc"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1670
lsu_ecc.fir Normal file
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File diff suppressed because it is too large Load Diff

674
lsu_ecc.v Normal file
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@ -0,0 +1,674 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
endmodule
module lsu_ecc(
input clock,
input reset,
input io_lsu_c2_r_clk,
input io_clk_override,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_lsu_pkt_r_bits_fast_int,
input io_lsu_pkt_r_bits_by,
input io_lsu_pkt_r_bits_half,
input io_lsu_pkt_r_bits_word,
input io_lsu_pkt_r_bits_dword,
input io_lsu_pkt_r_bits_load,
input io_lsu_pkt_r_bits_store,
input io_lsu_pkt_r_bits_unsign,
input io_lsu_pkt_r_bits_dma,
input io_lsu_pkt_r_bits_store_data_bypass_d,
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
input io_lsu_pkt_r_bits_store_data_bypass_m,
input [31:0] io_stbuf_data_any,
input io_dec_tlu_core_ecc_disable,
input io_lsu_dccm_rden_r,
input io_addr_in_dccm_r,
input [15:0] io_lsu_addr_r,
input [15:0] io_end_addr_r,
input [15:0] io_lsu_addr_m,
input [15:0] io_end_addr_m,
input [31:0] io_dccm_rdata_hi_r,
input [31:0] io_dccm_rdata_lo_r,
input [31:0] io_dccm_rdata_hi_m,
input [31:0] io_dccm_rdata_lo_m,
input [6:0] io_dccm_data_ecc_hi_r,
input [6:0] io_dccm_data_ecc_lo_r,
input [6:0] io_dccm_data_ecc_hi_m,
input [6:0] io_dccm_data_ecc_lo_m,
input io_ld_single_ecc_error_r,
input io_ld_single_ecc_error_r_ff,
input io_lsu_dccm_rden_m,
input io_addr_in_dccm_m,
input io_dma_dccm_wen,
input [31:0] io_dma_dccm_wdata_lo,
input [31:0] io_dma_dccm_wdata_hi,
input io_scan_mode,
output [31:0] io_sec_data_hi_r,
output [31:0] io_sec_data_lo_r,
output [31:0] io_sec_data_hi_m,
output [31:0] io_sec_data_lo_m,
output [31:0] io_sec_data_hi_r_ff,
output [31:0] io_sec_data_lo_r_ff,
output [6:0] io_dma_dccm_wdata_ecc_hi,
output [6:0] io_dma_dccm_wdata_ecc_lo,
output [6:0] io_stbuf_ecc_any,
output [6:0] io_sec_data_ecc_hi_r_ff,
output [6:0] io_sec_data_ecc_lo_r_ff,
output io_single_ecc_error_hi_r,
output io_single_ecc_error_lo_r,
output io_lsu_single_ecc_error_r,
output io_lsu_double_ecc_error_r,
output io_lsu_single_ecc_error_m,
output io_lsu_double_ecc_error_m
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_io_en; // @[lib.scala 368:23]
wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_en; // @[lib.scala 368:23]
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_en; // @[lib.scala 368:23]
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_en; // @[lib.scala 368:23]
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30]
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44]
wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35]
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76]
wire _T_107 = ^_T_106; // @[lib.scala 193:83]
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71]
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103]
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103]
wire _T_124 = ^_T_123; // @[lib.scala 193:110]
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98]
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130]
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130]
wire _T_141 = ^_T_140; // @[lib.scala 193:137]
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125]
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157]
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157]
wire _T_161 = ^_T_160; // @[lib.scala 193:164]
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152]
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184]
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184]
wire _T_181 = ^_T_180; // @[lib.scala 193:191]
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179]
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211]
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211]
wire _T_201 = ^_T_200; // @[lib.scala 193:218]
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206]
wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44]
wire _T_1130 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 106:48]
wire _T_1137 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 124:65]
wire _T_1138 = io_lsu_pkt_m_valid & _T_1137; // @[lsu_ecc.scala 124:39]
wire _T_1139 = _T_1138 & io_addr_in_dccm_m; // @[lsu_ecc.scala 124:92]
wire is_ldst_m = _T_1139 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 124:112]
wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 123:39]
wire _T_1143 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 126:48]
wire _T_1144 = is_ldst_m & _T_1143; // @[lsu_ecc.scala 126:33]
wire is_ldst_hi_m = _T_1144 & _T_1130; // @[lsu_ecc.scala 126:73]
wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32]
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53]
wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55]
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53]
wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 199:41]
wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 199:41]
wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 199:41]
wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 199:41]
wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 199:41]
wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 199:41]
wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 199:41]
wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 199:41]
wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 199:41]
wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 199:41]
wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 199:41]
wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 199:41]
wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 199:41]
wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 199:41]
wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 199:41]
wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 199:41]
wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 199:41]
wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 199:41]
wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 199:41]
wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 199:41]
wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 199:41]
wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 199:41]
wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 199:41]
wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 199:41]
wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 199:41]
wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 199:41]
wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 199:41]
wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 199:41]
wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 199:41]
wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 199:41]
wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 199:41]
wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 199:41]
wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 199:41]
wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 199:41]
wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 199:41]
wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 199:41]
wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41]
wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41]
wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41]
wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69]
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69]
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69]
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 202:69]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 202:69]
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 202:76]
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31]
wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30]
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44]
wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35]
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76]
wire _T_485 = ^_T_484; // @[lib.scala 193:83]
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71]
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103]
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103]
wire _T_502 = ^_T_501; // @[lib.scala 193:110]
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98]
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130]
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130]
wire _T_519 = ^_T_518; // @[lib.scala 193:137]
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125]
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157]
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157]
wire _T_539 = ^_T_538; // @[lib.scala 193:164]
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152]
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184]
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184]
wire _T_559 = ^_T_558; // @[lib.scala 193:191]
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179]
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211]
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211]
wire _T_579 = ^_T_578; // @[lib.scala 193:218]
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206]
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44]
wire is_ldst_lo_m = is_ldst_m & _T_1130; // @[lsu_ecc.scala 125:33]
wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32]
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53]
wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55]
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53]
wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 199:41]
wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 199:41]
wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 199:41]
wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 199:41]
wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 199:41]
wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 199:41]
wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 199:41]
wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 199:41]
wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 199:41]
wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 199:41]
wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 199:41]
wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 199:41]
wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 199:41]
wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 199:41]
wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 199:41]
wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 199:41]
wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 199:41]
wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 199:41]
wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 199:41]
wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 199:41]
wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 199:41]
wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 199:41]
wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 199:41]
wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 199:41]
wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 199:41]
wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 199:41]
wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 199:41]
wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 199:41]
wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 199:41]
wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 199:41]
wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 199:41]
wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 199:41]
wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 199:41]
wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 199:41]
wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 199:41]
wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 199:41]
wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41]
wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41]
wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41]
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69]
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69]
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69]
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 202:69]
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 202:69]
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 202:76]
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31]
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
wire [31:0] _T_1159 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 148:87]
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1159; // @[lsu_ecc.scala 148:27]
wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74]
wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74]
wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74]
wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74]
wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74]
wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 119:74]
wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74]
wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74]
wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74]
wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 119:74]
wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74]
wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74]
wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74]
wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74]
wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74]
wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74]
wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74]
wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74]
wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74]
wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74]
wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74]
wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74]
wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74]
wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74]
wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74]
wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74]
wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74]
wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74]
wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74]
wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74]
wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74]
wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74]
wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74]
wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74]
wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74]
wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74]
wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74]
wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74]
wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74]
wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74]
wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74]
wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74]
wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74]
wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74]
wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74]
wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74]
wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74]
wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74]
wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74]
wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74]
wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74]
wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74]
wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74]
wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74]
wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74]
wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74]
wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74]
wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74]
wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74]
wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58]
wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13]
wire _T_936 = ^_T_934; // @[lib.scala 127:23]
wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18]
wire [31:0] _T_1163 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : 32'h0; // @[lsu_ecc.scala 149:87]
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1163; // @[lsu_ecc.scala 149:27]
wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74]
wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74]
wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74]
wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74]
wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74]
wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 119:74]
wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74]
wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74]
wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74]
wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 119:74]
wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74]
wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74]
wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74]
wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74]
wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74]
wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74]
wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74]
wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74]
wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74]
wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74]
wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74]
wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74]
wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74]
wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74]
wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74]
wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74]
wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74]
wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74]
wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74]
wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74]
wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74]
wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74]
wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74]
wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74]
wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74]
wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74]
wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74]
wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74]
wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74]
wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74]
wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74]
wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74]
wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74]
wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74]
wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74]
wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74]
wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74]
wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74]
wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74]
wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74]
wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74]
wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74]
wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74]
wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74]
wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74]
wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74]
wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74]
wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74]
wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74]
wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58]
wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13]
wire _T_1118 = ^_T_1116; // @[lib.scala 127:23]
wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18]
reg _T_1149; // @[lsu_ecc.scala 140:72]
reg _T_1150; // @[lsu_ecc.scala 141:72]
reg _T_1151; // @[lsu_ecc.scala 142:72]
reg _T_1152; // @[lsu_ecc.scala 143:72]
reg [31:0] _T_1154; // @[lib.scala 374:16]
reg [31:0] _T_1156; // @[lib.scala 374:16]
reg [31:0] _T_1166; // @[lib.scala 374:16]
reg [31:0] _T_1168; // @[lib.scala 374:16]
rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34]
assign io_sec_data_lo_r = _T_1156; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34]
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 133:27]
assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 135:27]
assign io_sec_data_hi_r_ff = _T_1166; // @[lsu_ecc.scala 156:23]
assign io_sec_data_lo_r_ff = _T_1168; // @[lsu_ecc.scala 157:23]
assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 153:28]
assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 154:28]
assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28]
assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 150:28]
assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28]
assign io_single_ecc_error_hi_r = _T_1152; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62]
assign io_single_ecc_error_lo_r = _T_1151; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62]
assign io_lsu_single_ecc_error_r = _T_1149; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62]
assign io_lsu_double_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62]
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33]
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33]
assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1149 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
_T_1150 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
_T_1151 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
_T_1152 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T_1154 = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
_T_1156 = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
_T_1166 = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
_T_1168 = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1149 = 1'h0;
end
if (reset) begin
_T_1150 = 1'h0;
end
if (reset) begin
_T_1151 = 1'h0;
end
if (reset) begin
_T_1152 = 1'h0;
end
if (reset) begin
_T_1154 = 32'h0;
end
if (reset) begin
_T_1156 = 32'h0;
end
if (reset) begin
_T_1166 = 32'h0;
end
if (reset) begin
_T_1168 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1149 <= 1'h0;
end else begin
_T_1149 <= io_lsu_single_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1150 <= 1'h0;
end else begin
_T_1150 <= io_lsu_double_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1151 <= 1'h0;
end else begin
_T_1151 <= _T_588 & _T_586[6];
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1152 <= 1'h0;
end else begin
_T_1152 <= _T_210 & _T_208[6];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_1154 <= 32'h0;
end else begin
_T_1154 <= io_sec_data_hi_m;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
_T_1156 <= 32'h0;
end else begin
_T_1156 <= io_sec_data_lo_m;
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
_T_1166 <= 32'h0;
end else begin
_T_1166 <= io_sec_data_hi_r;
end
end
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin
_T_1168 <= 32'h0;
end else begin
_T_1168 <= io_sec_data_lo_r;
end
end
endmodule

309
lsu_lsc_ctl.anno.json Normal file
View File

@ -0,0 +1,309 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_lsc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_lsc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

953
lsu_lsc_ctl.fir Normal file
View File

@ -0,0 +1,953 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_lsc_ctl :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 361:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 361:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_lsc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
wire end_addr_pre_m : UInt<29>
end_addr_pre_m <= UInt<29>("h00")
wire end_addr_pre_r : UInt<29>
end_addr_pre_r <= UInt<29>("h00")
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29]
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 98:29]
node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node lsu_offset_d = and(_T_1, _T_3) @[lsu_lsc_ctl.scala 101:51]
node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
node _T_5 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
node _T_7 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
node _T_9 = add(_T_6, _T_8) @[lib.scala 92:39]
node _T_10 = tail(_T_9, 1) @[lib.scala 92:39]
node _T_11 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
node _T_12 = bits(_T_10, 12, 12) @[lib.scala 93:50]
node _T_13 = xor(_T_11, _T_12) @[lib.scala 93:46]
node _T_14 = not(_T_13) @[lib.scala 93:33]
node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_17 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
node _T_18 = and(_T_16, _T_17) @[lib.scala 93:58]
node _T_19 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
node _T_20 = not(_T_19) @[lib.scala 94:18]
node _T_21 = bits(_T_10, 12, 12) @[lib.scala 94:34]
node _T_22 = and(_T_20, _T_21) @[lib.scala 94:30]
node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15]
node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_25 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
node _T_26 = add(_T_25, UInt<1>("h01")) @[lib.scala 94:54]
node _T_27 = tail(_T_26, 1) @[lib.scala 94:54]
node _T_28 = and(_T_24, _T_27) @[lib.scala 94:41]
node _T_29 = or(_T_18, _T_28) @[lib.scala 93:72]
node _T_30 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
node _T_31 = bits(_T_10, 12, 12) @[lib.scala 95:34]
node _T_32 = not(_T_31) @[lib.scala 95:31]
node _T_33 = and(_T_30, _T_32) @[lib.scala 95:29]
node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_36 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
node _T_37 = sub(_T_36, UInt<1>("h01")) @[lib.scala 95:54]
node _T_38 = tail(_T_37, 1) @[lib.scala 95:54]
node _T_39 = and(_T_35, _T_38) @[lib.scala 95:41]
node _T_40 = or(_T_29, _T_39) @[lib.scala 94:61]
node _T_41 = bits(_T_10, 11, 0) @[lib.scala 96:22]
node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_44 = and(_T_43, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_47 = and(_T_46, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
node _T_48 = or(_T_44, _T_47) @[lsu_lsc_ctl.scala 109:70]
node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_51 = and(_T_50, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
node addr_offset_d = or(_T_48, _T_51) @[lsu_lsc_ctl.scala 110:52]
node _T_52 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
node _T_53 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58]
node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_56 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58]
node _T_58 = add(_T_54, _T_57) @[lsu_lsc_ctl.scala 113:60]
node end_addr_offset_d = tail(_T_58, 1) @[lsu_lsc_ctl.scala 113:60]
node _T_59 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
node _T_60 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_63 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58]
node _T_65 = add(_T_59, _T_64) @[lsu_lsc_ctl.scala 114:39]
node full_end_addr_d = tail(_T_65, 1) @[lsu_lsc_ctl.scala 114:39]
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
addrcheck.clock <= clock
addrcheck.reset <= reset
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
node _T_66 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
addrcheck.io.rs1_region_d <= _T_66 @[lsu_lsc_ctl.scala 126:42]
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
wire exc_mscause_r : UInt<4>
exc_mscause_r <= UInt<4>("h00")
wire fir_dccm_access_error_r : UInt<1>
fir_dccm_access_error_r <= UInt<1>("h00")
wire fir_nondccm_access_error_r : UInt<1>
fir_nondccm_access_error_r <= UInt<1>("h00")
wire access_fault_r : UInt<1>
access_fault_r <= UInt<1>("h00")
wire misaligned_fault_r : UInt<1>
misaligned_fault_r <= UInt<1>("h00")
wire lsu_fir_error_m : UInt<2>
lsu_fir_error_m <= UInt<2>("h00")
wire fir_dccm_access_error_m : UInt<1>
fir_dccm_access_error_m <= UInt<1>("h00")
wire fir_nondccm_access_error_m : UInt<1>
fir_nondccm_access_error_m <= UInt<1>("h00")
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
_T_67 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
fir_dccm_access_error_m <= _T_67 @[lsu_lsc_ctl.scala 152:38]
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
_T_68 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
fir_nondccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 153:38]
node _T_69 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
io.lsu_exc_m <= _T_69 @[lsu_lsc_ctl.scala 155:16]
node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[lsu_lsc_ctl.scala 156:62]
node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
node _T_73 = and(_T_71, _T_72) @[lsu_lsc_ctl.scala 156:92]
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
io.lsu_single_ecc_error_incr <= _T_74 @[lsu_lsc_ctl.scala 156:32]
node _T_75 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 178:46]
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 178:67]
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 178:96]
node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:119]
node _T_79 = and(_T_77, _T_78) @[lsu_lsc_ctl.scala 178:117]
node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:144]
node _T_81 = and(_T_79, _T_80) @[lsu_lsc_ctl.scala 178:142]
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:174]
node _T_83 = and(_T_81, _T_82) @[lsu_lsc_ctl.scala 178:172]
lsu_error_pkt_m.valid <= _T_83 @[lsu_lsc_ctl.scala 178:27]
node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:75]
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[lsu_lsc_ctl.scala 179:73]
node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:101]
node _T_87 = and(_T_85, _T_86) @[lsu_lsc_ctl.scala 179:99]
lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[lsu_lsc_ctl.scala 179:43]
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 180:43]
node _T_88 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 181:46]
lsu_error_pkt_m.bits.exc_type <= _T_88 @[lsu_lsc_ctl.scala 181:43]
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:80]
node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[lsu_lsc_ctl.scala 182:78]
node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:102]
node _T_92 = and(_T_90, _T_91) @[lsu_lsc_ctl.scala 182:100]
node _T_93 = eq(_T_92, UInt<1>("h01")) @[lsu_lsc_ctl.scala 182:118]
node _T_94 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 182:149]
node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[lsu_lsc_ctl.scala 182:49]
lsu_error_pkt_m.bits.mscause <= _T_95 @[lsu_lsc_ctl.scala 182:43]
node _T_96 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 183:59]
lsu_error_pkt_m.bits.addr <= _T_96 @[lsu_lsc_ctl.scala 183:43]
node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:72]
node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:117]
node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 184:166]
node _T_100 = bits(_T_99, 0, 0) @[lsu_lsc_ctl.scala 184:195]
node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 184:137]
node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[lsu_lsc_ctl.scala 184:92]
node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[lsu_lsc_ctl.scala 184:44]
lsu_fir_error_m <= _T_103 @[lsu_lsc_ctl.scala 184:38]
node _T_104 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 185:73]
node _T_105 = or(_T_104, io.clk_override) @[lsu_lsc_ctl.scala 185:113]
node _T_106 = bits(_T_105, 0, 0) @[lib.scala 8:44]
node _T_107 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr of rvclkhdr @[lib.scala 378:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 380:18]
rvclkhdr.io.en <= _T_106 @[lib.scala 381:17]
rvclkhdr.io.scan_mode <= _T_107 @[lib.scala 382:24]
wire _T_108 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 384:33]
_T_108.bits.addr <= UInt<32>("h00") @[lib.scala 384:33]
_T_108.bits.mscause <= UInt<4>("h00") @[lib.scala 384:33]
_T_108.bits.exc_type <= UInt<1>("h00") @[lib.scala 384:33]
_T_108.bits.inst_type <= UInt<1>("h00") @[lib.scala 384:33]
_T_108.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 384:33]
_T_108.valid <= UInt<1>("h00") @[lib.scala 384:33]
reg _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, rvclkhdr.io.l1clk with : (reset => (reset, _T_108)) @[lib.scala 384:16]
_T_109.bits.addr <= lsu_error_pkt_m.bits.addr @[lib.scala 384:16]
_T_109.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lib.scala 384:16]
_T_109.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lib.scala 384:16]
_T_109.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lib.scala 384:16]
_T_109.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lib.scala 384:16]
_T_109.valid <= lsu_error_pkt_m.valid @[lib.scala 384:16]
io.lsu_error_pkt_r.bits.addr <= _T_109.bits.addr @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.mscause <= _T_109.bits.mscause @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.exc_type <= _T_109.bits.exc_type @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.inst_type <= _T_109.bits.inst_type @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_109.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.valid <= _T_109.valid @[lsu_lsc_ctl.scala 185:24]
reg _T_110 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:83]
_T_110 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 186:83]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110 @[lsu_lsc_ctl.scala 186:46]
reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67]
_T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67]
io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30]
reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 193:48]
_T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 193:48]
io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 193:38]
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 195:27]
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 196:27]
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 197:22]
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 198:27]
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 199:27]
node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 200:30]
dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 200:27]
node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 201:56]
node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 201:62]
dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 201:27]
node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 202:56]
node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 202:62]
dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 202:27]
node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 203:56]
node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 203:62]
dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 203:27]
node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 204:56]
node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 204:62]
dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 204:27]
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 205:39]
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 206:39]
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 207:39]
wire lsu_ld_datafn_r : UInt<32>
lsu_ld_datafn_r <= UInt<32>("h00")
wire lsu_ld_datafn_corr_r : UInt<32>
lsu_ld_datafn_corr_r <= UInt<32>("h00")
wire lsu_ld_datafn_m : UInt<32>
lsu_ld_datafn_m <= UInt<32>("h00")
node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 213:50]
node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 213:26]
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 213:20]
io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 213:20]
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 214:20]
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 215:20]
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 215:20]
node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 217:64]
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 217:61]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 217:45]
node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 217:43]
node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 217:90]
io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 217:24]
node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 218:68]
node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 218:65]
node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 218:49]
node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 218:47]
lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 218:24]
node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 219:68]
node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 219:65]
node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 219:49]
node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 219:47]
lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 219:24]
wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
_T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91]
reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 221:65]
_T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 221:65]
_T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 221:65]
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 221:28]
io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 221:28]
wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
_T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91]
reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 222:65]
_T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 222:65]
_T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 222:65]
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 222:28]
io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 222:28]
reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 223:65]
_T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 223:65]
io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 223:28]
reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:65]
_T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 224:65]
io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 224:28]
node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 226:59]
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 226:100]
node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58]
node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 226:66]
node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 227:63]
node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 227:91]
node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 227:122]
node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 227:34]
node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 228:73]
node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 228:95]
node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 228:114]
node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 228:34]
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:72]
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 230:72]
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62]
_T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 231:62]
io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 231:24]
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 232:62]
io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 232:24]
node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 234:71]
node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 234:27]
node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 234:128]
reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:114]
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 234:114]
node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 234:17]
node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 235:71]
node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 235:27]
node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 235:128]
reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:114]
_T_164 <= _T_163 @[lsu_lsc_ctl.scala 235:114]
node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 235:17]
node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 237:41]
node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 237:69]
node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 237:87]
node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_1.io.en <= _T_169 @[lib.scala 371:17]
rvclkhdr_1.io.scan_mode <= _T_170 @[lib.scala 372:24]
reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_171 <= _T_166 @[lib.scala 374:16]
end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 237:18]
node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 238:41]
node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 238:69]
node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 238:87]
node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_2.io.en <= _T_175 @[lib.scala 371:17]
rvclkhdr_2.io.scan_mode <= _T_176 @[lib.scala 372:24]
reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_177 <= _T_172 @[lib.scala 374:16]
end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 238:18]
reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:62]
_T_178 <= io.end_addr_d @[lsu_lsc_ctl.scala 241:62]
io.end_addr_m <= _T_178 @[lsu_lsc_ctl.scala 241:24]
reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 242:62]
_T_179 <= io.end_addr_m @[lsu_lsc_ctl.scala 242:62]
io.end_addr_r <= _T_179 @[lsu_lsc_ctl.scala 242:24]
reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 243:62]
_T_180 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 243:62]
io.addr_in_dccm_m <= _T_180 @[lsu_lsc_ctl.scala 243:24]
reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 244:62]
_T_181 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 244:62]
io.addr_in_dccm_r <= _T_181 @[lsu_lsc_ctl.scala 244:24]
reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 245:62]
_T_182 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 245:62]
io.addr_in_pic_m <= _T_182 @[lsu_lsc_ctl.scala 245:24]
reg _T_183 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 246:62]
_T_183 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 246:62]
io.addr_in_pic_r <= _T_183 @[lsu_lsc_ctl.scala 246:24]
reg _T_184 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 247:62]
_T_184 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 247:62]
io.addr_external_m <= _T_184 @[lsu_lsc_ctl.scala 247:24]
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 248:66]
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 248:66]
node _T_185 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 249:77]
node _T_186 = bits(_T_185, 0, 0) @[lib.scala 8:44]
node _T_187 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_3.io.en <= _T_186 @[lib.scala 371:17]
rvclkhdr_3.io.scan_mode <= _T_187 @[lib.scala 372:24]
reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
bus_read_data_r <= io.bus_read_data_m @[lib.scala 374:16]
node _T_188 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 252:52]
io.lsu_fir_addr <= _T_188 @[lsu_lsc_ctl.scala 252:28]
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 254:28]
node _T_189 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 256:68]
node _T_190 = and(io.lsu_pkt_r.valid, _T_189) @[lsu_lsc_ctl.scala 256:41]
node _T_191 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:96]
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 256:94]
node _T_193 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:110]
node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 256:108]
io.lsu_commit_r <= _T_194 @[lsu_lsc_ctl.scala 256:19]
node _T_195 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 257:52]
node _T_196 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 257:69]
node _T_197 = bits(_T_196, 0, 0) @[Bitwise.scala 72:15]
node _T_198 = mux(_T_197, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_199 = or(_T_195, _T_198) @[lsu_lsc_ctl.scala 257:59]
node _T_200 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 257:133]
node _T_201 = mux(_T_200, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 257:94]
node _T_202 = and(_T_199, _T_201) @[lsu_lsc_ctl.scala 257:89]
io.store_data_m <= _T_202 @[lsu_lsc_ctl.scala 257:29]
node _T_203 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 278:53]
node _T_204 = mux(_T_203, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 278:33]
lsu_ld_datafn_m <= _T_204 @[lsu_lsc_ctl.scala 278:27]
node _T_205 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 279:49]
node _T_206 = mux(_T_205, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 279:33]
lsu_ld_datafn_corr_r <= _T_206 @[lsu_lsc_ctl.scala 279:27]
node _T_207 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 280:66]
node _T_208 = bits(_T_207, 0, 0) @[Bitwise.scala 72:15]
node _T_209 = mux(_T_208, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_210 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 280:125]
node _T_211 = cat(UInt<24>("h00"), _T_210) @[Cat.scala 29:58]
node _T_212 = and(_T_209, _T_211) @[lsu_lsc_ctl.scala 280:94]
node _T_213 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 281:43]
node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_216 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 281:102]
node _T_217 = cat(UInt<16>("h00"), _T_216) @[Cat.scala 29:58]
node _T_218 = and(_T_215, _T_217) @[lsu_lsc_ctl.scala 281:71]
node _T_219 = or(_T_212, _T_218) @[lsu_lsc_ctl.scala 280:133]
node _T_220 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 282:17]
node _T_221 = and(_T_220, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 282:43]
node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15]
node _T_223 = mux(_T_222, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_224 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 282:102]
node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
node _T_226 = mux(_T_225, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_227 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 282:125]
node _T_228 = cat(_T_226, _T_227) @[Cat.scala 29:58]
node _T_229 = and(_T_223, _T_228) @[lsu_lsc_ctl.scala 282:71]
node _T_230 = or(_T_219, _T_229) @[lsu_lsc_ctl.scala 281:114]
node _T_231 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 283:17]
node _T_232 = and(_T_231, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 283:43]
node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15]
node _T_234 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_235 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 283:101]
node _T_236 = bits(_T_235, 0, 0) @[Bitwise.scala 72:15]
node _T_237 = mux(_T_236, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_238 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 283:125]
node _T_239 = cat(_T_237, _T_238) @[Cat.scala 29:58]
node _T_240 = and(_T_234, _T_239) @[lsu_lsc_ctl.scala 283:71]
node _T_241 = or(_T_230, _T_240) @[lsu_lsc_ctl.scala 282:134]
node _T_242 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_243 = mux(_T_242, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_244 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 284:60]
node _T_245 = and(_T_243, _T_244) @[lsu_lsc_ctl.scala 284:43]
node _T_246 = or(_T_241, _T_245) @[lsu_lsc_ctl.scala 283:134]
io.lsu_result_m <= _T_246 @[lsu_lsc_ctl.scala 280:27]
node _T_247 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 285:66]
node _T_248 = bits(_T_247, 0, 0) @[Bitwise.scala 72:15]
node _T_249 = mux(_T_248, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_250 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 285:130]
node _T_251 = cat(UInt<24>("h00"), _T_250) @[Cat.scala 29:58]
node _T_252 = and(_T_249, _T_251) @[lsu_lsc_ctl.scala 285:94]
node _T_253 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 286:43]
node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_256 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 286:107]
node _T_257 = cat(UInt<16>("h00"), _T_256) @[Cat.scala 29:58]
node _T_258 = and(_T_255, _T_257) @[lsu_lsc_ctl.scala 286:71]
node _T_259 = or(_T_252, _T_258) @[lsu_lsc_ctl.scala 285:138]
node _T_260 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 287:17]
node _T_261 = and(_T_260, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 287:43]
node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15]
node _T_263 = mux(_T_262, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 287:107]
node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
node _T_266 = mux(_T_265, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_267 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 287:135]
node _T_268 = cat(_T_266, _T_267) @[Cat.scala 29:58]
node _T_269 = and(_T_263, _T_268) @[lsu_lsc_ctl.scala 287:71]
node _T_270 = or(_T_259, _T_269) @[lsu_lsc_ctl.scala 286:119]
node _T_271 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 288:17]
node _T_272 = and(_T_271, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 288:43]
node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15]
node _T_274 = mux(_T_273, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 288:106]
node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15]
node _T_277 = mux(_T_276, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_278 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 288:135]
node _T_279 = cat(_T_277, _T_278) @[Cat.scala 29:58]
node _T_280 = and(_T_274, _T_279) @[lsu_lsc_ctl.scala 288:71]
node _T_281 = or(_T_270, _T_280) @[lsu_lsc_ctl.scala 287:144]
node _T_282 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_283 = mux(_T_282, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_284 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 289:65]
node _T_285 = and(_T_283, _T_284) @[lsu_lsc_ctl.scala 289:43]
node _T_286 = or(_T_281, _T_285) @[lsu_lsc_ctl.scala 288:144]
io.lsu_result_corr_r <= _T_286 @[lsu_lsc_ctl.scala 285:27]

1394
lsu_lsc_ctl.v Normal file
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142
lsu_stbuf.anno.json Normal file
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@ -0,0 +1,142 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwddata_lo_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_store_data_lo_r",
"~lsu_stbuf|lsu_stbuf>io_store_data_hi_r",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwddata_hi_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_store_data_lo_r",
"~lsu_stbuf|lsu_stbuf>io_store_data_hi_r",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_end_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_end_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_reqvld_any",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_valid",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_end_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_lsu_stbuf_full_any",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_dec_lsu_valid_raw_d",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_d",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_m",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_ldst_stbuf_reqvld_r",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_commit_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_stbuf.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_stbuf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_trigger|lsu_trigger>io_lsu_trigger_match_m",
"sources":[
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_valid",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_store",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_store",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_store",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_dma",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_load",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_store",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_store",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_match_pkt",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_match_pkt",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_match_pkt",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_match_pkt",
"~lsu_trigger|lsu_trigger>io_lsu_addr_m",
"~lsu_trigger|lsu_trigger>io_store_data_m",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_word",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_half"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_trigger"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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module lsu_trigger(
input clock,
input reset,
input io_trigger_pkt_any_0_select,
input io_trigger_pkt_any_0_match_pkt,
input io_trigger_pkt_any_0_store,
input io_trigger_pkt_any_0_load,
input io_trigger_pkt_any_0_execute,
input io_trigger_pkt_any_0_m,
input [31:0] io_trigger_pkt_any_0_tdata2,
input io_trigger_pkt_any_1_select,
input io_trigger_pkt_any_1_match_pkt,
input io_trigger_pkt_any_1_store,
input io_trigger_pkt_any_1_load,
input io_trigger_pkt_any_1_execute,
input io_trigger_pkt_any_1_m,
input [31:0] io_trigger_pkt_any_1_tdata2,
input io_trigger_pkt_any_2_select,
input io_trigger_pkt_any_2_match_pkt,
input io_trigger_pkt_any_2_store,
input io_trigger_pkt_any_2_load,
input io_trigger_pkt_any_2_execute,
input io_trigger_pkt_any_2_m,
input [31:0] io_trigger_pkt_any_2_tdata2,
input io_trigger_pkt_any_3_select,
input io_trigger_pkt_any_3_match_pkt,
input io_trigger_pkt_any_3_store,
input io_trigger_pkt_any_3_load,
input io_trigger_pkt_any_3_execute,
input io_trigger_pkt_any_3_m,
input [31:0] io_trigger_pkt_any_3_tdata2,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input [31:0] io_lsu_addr_m,
input [31:0] io_store_data_m,
output [3:0] io_lsu_trigger_match_m
);
wire _T = io_trigger_pkt_any_0_m | io_trigger_pkt_any_1_m; // @[lsu_trigger.scala 16:73]
wire _T_1 = _T | io_trigger_pkt_any_2_m; // @[lsu_trigger.scala 16:73]
wire trigger_enable = _T_1 | io_trigger_pkt_any_3_m; // @[lsu_trigger.scala 16:73]
wire [15:0] _T_4 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
wire [15:0] _T_6 = _T_4 & io_store_data_m[31:16]; // @[lsu_trigger.scala 17:66]
wire _T_7 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[lsu_trigger.scala 17:124]
wire [7:0] _T_9 = _T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_11 = _T_9 & io_store_data_m[15:8]; // @[lsu_trigger.scala 17:151]
wire [31:0] store_data_trigger_m = {_T_6,_T_11,io_store_data_m[7:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_15 = trigger_enable ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] ldst_addr_trigger_m = io_lsu_addr_m & _T_15; // @[lsu_trigger.scala 18:43]
wire _T_17 = ~io_trigger_pkt_any_0_select; // @[lsu_trigger.scala 19:53]
wire _T_18 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_20 = _T_17 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = _T_18 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_0 = _T_20 | _T_21; // @[Mux.scala 27:72]
wire _T_24 = ~io_trigger_pkt_any_1_select; // @[lsu_trigger.scala 19:53]
wire _T_25 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_27 = _T_24 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_28 = _T_25 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_1 = _T_27 | _T_28; // @[Mux.scala 27:72]
wire _T_31 = ~io_trigger_pkt_any_2_select; // @[lsu_trigger.scala 19:53]
wire _T_32 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_34 = _T_31 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_35 = _T_32 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_2 = _T_34 | _T_35; // @[Mux.scala 27:72]
wire _T_38 = ~io_trigger_pkt_any_3_select; // @[lsu_trigger.scala 19:53]
wire _T_39 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_41 = _T_38 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_42 = _T_39 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_3 = _T_41 | _T_42; // @[Mux.scala 27:72]
wire _T_44 = ~io_lsu_pkt_m_bits_dma; // @[lsu_trigger.scala 20:70]
wire _T_45 = io_lsu_pkt_m_valid & _T_44; // @[lsu_trigger.scala 20:68]
wire _T_46 = _T_45 & trigger_enable; // @[lsu_trigger.scala 20:93]
wire _T_47 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_48 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_50 = _T_48 & _T_17; // @[lsu_trigger.scala 21:58]
wire _T_51 = _T_47 | _T_50; // @[lsu_trigger.scala 20:168]
wire _T_52 = _T_46 & _T_51; // @[lsu_trigger.scala 20:110]
wire _T_55 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45]
wire _T_56 = ~_T_55; // @[lib.scala 101:39]
wire _T_57 = io_trigger_pkt_any_0_match_pkt & _T_56; // @[lib.scala 101:37]
wire _T_60 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 102:52]
wire _T_61 = _T_57 | _T_60; // @[lib.scala 102:41]
wire _T_63 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36]
wire _T_64 = _T_63 & _T_57; // @[lib.scala 104:41]
wire _T_67 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 104:78]
wire _T_68 = _T_64 | _T_67; // @[lib.scala 104:23]
wire _T_70 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_71 = _T_70 & _T_57; // @[lib.scala 104:41]
wire _T_74 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 104:78]
wire _T_75 = _T_71 | _T_74; // @[lib.scala 104:23]
wire _T_77 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_78 = _T_77 & _T_57; // @[lib.scala 104:41]
wire _T_81 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 104:78]
wire _T_82 = _T_78 | _T_81; // @[lib.scala 104:23]
wire _T_84 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_85 = _T_84 & _T_57; // @[lib.scala 104:41]
wire _T_88 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 104:78]
wire _T_89 = _T_85 | _T_88; // @[lib.scala 104:23]
wire _T_91 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_92 = _T_91 & _T_57; // @[lib.scala 104:41]
wire _T_95 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 104:78]
wire _T_96 = _T_92 | _T_95; // @[lib.scala 104:23]
wire _T_98 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_99 = _T_98 & _T_57; // @[lib.scala 104:41]
wire _T_102 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 104:78]
wire _T_103 = _T_99 | _T_102; // @[lib.scala 104:23]
wire _T_105 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_106 = _T_105 & _T_57; // @[lib.scala 104:41]
wire _T_109 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 104:78]
wire _T_110 = _T_106 | _T_109; // @[lib.scala 104:23]
wire _T_112 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_113 = _T_112 & _T_57; // @[lib.scala 104:41]
wire _T_116 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 104:78]
wire _T_117 = _T_113 | _T_116; // @[lib.scala 104:23]
wire _T_119 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_120 = _T_119 & _T_57; // @[lib.scala 104:41]
wire _T_123 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 104:78]
wire _T_124 = _T_120 | _T_123; // @[lib.scala 104:23]
wire _T_126 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_127 = _T_126 & _T_57; // @[lib.scala 104:41]
wire _T_130 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 104:78]
wire _T_131 = _T_127 | _T_130; // @[lib.scala 104:23]
wire _T_133 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_134 = _T_133 & _T_57; // @[lib.scala 104:41]
wire _T_137 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 104:78]
wire _T_138 = _T_134 | _T_137; // @[lib.scala 104:23]
wire _T_140 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_141 = _T_140 & _T_57; // @[lib.scala 104:41]
wire _T_144 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 104:78]
wire _T_145 = _T_141 | _T_144; // @[lib.scala 104:23]
wire _T_147 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_148 = _T_147 & _T_57; // @[lib.scala 104:41]
wire _T_151 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 104:78]
wire _T_152 = _T_148 | _T_151; // @[lib.scala 104:23]
wire _T_154 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_155 = _T_154 & _T_57; // @[lib.scala 104:41]
wire _T_158 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 104:78]
wire _T_159 = _T_155 | _T_158; // @[lib.scala 104:23]
wire _T_161 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_162 = _T_161 & _T_57; // @[lib.scala 104:41]
wire _T_165 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 104:78]
wire _T_166 = _T_162 | _T_165; // @[lib.scala 104:23]
wire _T_168 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_169 = _T_168 & _T_57; // @[lib.scala 104:41]
wire _T_172 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 104:78]
wire _T_173 = _T_169 | _T_172; // @[lib.scala 104:23]
wire _T_175 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_176 = _T_175 & _T_57; // @[lib.scala 104:41]
wire _T_179 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 104:78]
wire _T_180 = _T_176 | _T_179; // @[lib.scala 104:23]
wire _T_182 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_183 = _T_182 & _T_57; // @[lib.scala 104:41]
wire _T_186 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 104:78]
wire _T_187 = _T_183 | _T_186; // @[lib.scala 104:23]
wire _T_189 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_190 = _T_189 & _T_57; // @[lib.scala 104:41]
wire _T_193 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 104:78]
wire _T_194 = _T_190 | _T_193; // @[lib.scala 104:23]
wire _T_196 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_197 = _T_196 & _T_57; // @[lib.scala 104:41]
wire _T_200 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 104:78]
wire _T_201 = _T_197 | _T_200; // @[lib.scala 104:23]
wire _T_203 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_204 = _T_203 & _T_57; // @[lib.scala 104:41]
wire _T_207 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 104:78]
wire _T_208 = _T_204 | _T_207; // @[lib.scala 104:23]
wire _T_210 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_211 = _T_210 & _T_57; // @[lib.scala 104:41]
wire _T_214 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 104:78]
wire _T_215 = _T_211 | _T_214; // @[lib.scala 104:23]
wire _T_217 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_218 = _T_217 & _T_57; // @[lib.scala 104:41]
wire _T_221 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 104:78]
wire _T_222 = _T_218 | _T_221; // @[lib.scala 104:23]
wire _T_224 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_225 = _T_224 & _T_57; // @[lib.scala 104:41]
wire _T_228 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 104:78]
wire _T_229 = _T_225 | _T_228; // @[lib.scala 104:23]
wire _T_231 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_232 = _T_231 & _T_57; // @[lib.scala 104:41]
wire _T_235 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 104:78]
wire _T_236 = _T_232 | _T_235; // @[lib.scala 104:23]
wire _T_238 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_239 = _T_238 & _T_57; // @[lib.scala 104:41]
wire _T_242 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 104:78]
wire _T_243 = _T_239 | _T_242; // @[lib.scala 104:23]
wire _T_245 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_246 = _T_245 & _T_57; // @[lib.scala 104:41]
wire _T_249 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 104:78]
wire _T_250 = _T_246 | _T_249; // @[lib.scala 104:23]
wire _T_252 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_253 = _T_252 & _T_57; // @[lib.scala 104:41]
wire _T_256 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 104:78]
wire _T_257 = _T_253 | _T_256; // @[lib.scala 104:23]
wire _T_259 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_260 = _T_259 & _T_57; // @[lib.scala 104:41]
wire _T_263 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 104:78]
wire _T_264 = _T_260 | _T_263; // @[lib.scala 104:23]
wire _T_266 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_267 = _T_266 & _T_57; // @[lib.scala 104:41]
wire _T_270 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 104:78]
wire _T_271 = _T_267 | _T_270; // @[lib.scala 104:23]
wire _T_273 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_274 = _T_273 & _T_57; // @[lib.scala 104:41]
wire _T_277 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 104:78]
wire _T_278 = _T_274 | _T_277; // @[lib.scala 104:23]
wire [7:0] _T_285 = {_T_110,_T_103,_T_96,_T_89,_T_82,_T_75,_T_68,_T_61}; // @[lib.scala 105:14]
wire [15:0] _T_293 = {_T_166,_T_159,_T_152,_T_145,_T_138,_T_131,_T_124,_T_117,_T_285}; // @[lib.scala 105:14]
wire [7:0] _T_300 = {_T_222,_T_215,_T_208,_T_201,_T_194,_T_187,_T_180,_T_173}; // @[lib.scala 105:14]
wire [31:0] _T_309 = {_T_278,_T_271,_T_264,_T_257,_T_250,_T_243,_T_236,_T_229,_T_300,_T_293}; // @[lib.scala 105:14]
wire _T_310 = &_T_309; // @[lib.scala 105:25]
wire _T_311 = _T_52 & _T_310; // @[lsu_trigger.scala 21:92]
wire _T_315 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_316 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_318 = _T_316 & _T_24; // @[lsu_trigger.scala 21:58]
wire _T_319 = _T_315 | _T_318; // @[lsu_trigger.scala 20:168]
wire _T_320 = _T_46 & _T_319; // @[lsu_trigger.scala 20:110]
wire _T_323 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45]
wire _T_324 = ~_T_323; // @[lib.scala 101:39]
wire _T_325 = io_trigger_pkt_any_1_match_pkt & _T_324; // @[lib.scala 101:37]
wire _T_328 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 102:52]
wire _T_329 = _T_325 | _T_328; // @[lib.scala 102:41]
wire _T_331 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36]
wire _T_332 = _T_331 & _T_325; // @[lib.scala 104:41]
wire _T_335 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 104:78]
wire _T_336 = _T_332 | _T_335; // @[lib.scala 104:23]
wire _T_338 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_339 = _T_338 & _T_325; // @[lib.scala 104:41]
wire _T_342 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 104:78]
wire _T_343 = _T_339 | _T_342; // @[lib.scala 104:23]
wire _T_345 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_346 = _T_345 & _T_325; // @[lib.scala 104:41]
wire _T_349 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 104:78]
wire _T_350 = _T_346 | _T_349; // @[lib.scala 104:23]
wire _T_352 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_353 = _T_352 & _T_325; // @[lib.scala 104:41]
wire _T_356 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 104:78]
wire _T_357 = _T_353 | _T_356; // @[lib.scala 104:23]
wire _T_359 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_360 = _T_359 & _T_325; // @[lib.scala 104:41]
wire _T_363 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 104:78]
wire _T_364 = _T_360 | _T_363; // @[lib.scala 104:23]
wire _T_366 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_367 = _T_366 & _T_325; // @[lib.scala 104:41]
wire _T_370 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 104:78]
wire _T_371 = _T_367 | _T_370; // @[lib.scala 104:23]
wire _T_373 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_374 = _T_373 & _T_325; // @[lib.scala 104:41]
wire _T_377 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 104:78]
wire _T_378 = _T_374 | _T_377; // @[lib.scala 104:23]
wire _T_380 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_381 = _T_380 & _T_325; // @[lib.scala 104:41]
wire _T_384 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 104:78]
wire _T_385 = _T_381 | _T_384; // @[lib.scala 104:23]
wire _T_387 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_388 = _T_387 & _T_325; // @[lib.scala 104:41]
wire _T_391 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 104:78]
wire _T_392 = _T_388 | _T_391; // @[lib.scala 104:23]
wire _T_394 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_395 = _T_394 & _T_325; // @[lib.scala 104:41]
wire _T_398 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 104:78]
wire _T_399 = _T_395 | _T_398; // @[lib.scala 104:23]
wire _T_401 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_402 = _T_401 & _T_325; // @[lib.scala 104:41]
wire _T_405 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 104:78]
wire _T_406 = _T_402 | _T_405; // @[lib.scala 104:23]
wire _T_408 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_409 = _T_408 & _T_325; // @[lib.scala 104:41]
wire _T_412 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 104:78]
wire _T_413 = _T_409 | _T_412; // @[lib.scala 104:23]
wire _T_415 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_416 = _T_415 & _T_325; // @[lib.scala 104:41]
wire _T_419 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 104:78]
wire _T_420 = _T_416 | _T_419; // @[lib.scala 104:23]
wire _T_422 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_423 = _T_422 & _T_325; // @[lib.scala 104:41]
wire _T_426 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 104:78]
wire _T_427 = _T_423 | _T_426; // @[lib.scala 104:23]
wire _T_429 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_430 = _T_429 & _T_325; // @[lib.scala 104:41]
wire _T_433 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 104:78]
wire _T_434 = _T_430 | _T_433; // @[lib.scala 104:23]
wire _T_436 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_437 = _T_436 & _T_325; // @[lib.scala 104:41]
wire _T_440 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 104:78]
wire _T_441 = _T_437 | _T_440; // @[lib.scala 104:23]
wire _T_443 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_444 = _T_443 & _T_325; // @[lib.scala 104:41]
wire _T_447 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 104:78]
wire _T_448 = _T_444 | _T_447; // @[lib.scala 104:23]
wire _T_450 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_451 = _T_450 & _T_325; // @[lib.scala 104:41]
wire _T_454 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 104:78]
wire _T_455 = _T_451 | _T_454; // @[lib.scala 104:23]
wire _T_457 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_458 = _T_457 & _T_325; // @[lib.scala 104:41]
wire _T_461 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 104:78]
wire _T_462 = _T_458 | _T_461; // @[lib.scala 104:23]
wire _T_464 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_465 = _T_464 & _T_325; // @[lib.scala 104:41]
wire _T_468 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 104:78]
wire _T_469 = _T_465 | _T_468; // @[lib.scala 104:23]
wire _T_471 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_472 = _T_471 & _T_325; // @[lib.scala 104:41]
wire _T_475 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 104:78]
wire _T_476 = _T_472 | _T_475; // @[lib.scala 104:23]
wire _T_478 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_479 = _T_478 & _T_325; // @[lib.scala 104:41]
wire _T_482 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 104:78]
wire _T_483 = _T_479 | _T_482; // @[lib.scala 104:23]
wire _T_485 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_486 = _T_485 & _T_325; // @[lib.scala 104:41]
wire _T_489 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 104:78]
wire _T_490 = _T_486 | _T_489; // @[lib.scala 104:23]
wire _T_492 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_493 = _T_492 & _T_325; // @[lib.scala 104:41]
wire _T_496 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 104:78]
wire _T_497 = _T_493 | _T_496; // @[lib.scala 104:23]
wire _T_499 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_500 = _T_499 & _T_325; // @[lib.scala 104:41]
wire _T_503 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 104:78]
wire _T_504 = _T_500 | _T_503; // @[lib.scala 104:23]
wire _T_506 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_507 = _T_506 & _T_325; // @[lib.scala 104:41]
wire _T_510 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 104:78]
wire _T_511 = _T_507 | _T_510; // @[lib.scala 104:23]
wire _T_513 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_514 = _T_513 & _T_325; // @[lib.scala 104:41]
wire _T_517 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 104:78]
wire _T_518 = _T_514 | _T_517; // @[lib.scala 104:23]
wire _T_520 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_521 = _T_520 & _T_325; // @[lib.scala 104:41]
wire _T_524 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 104:78]
wire _T_525 = _T_521 | _T_524; // @[lib.scala 104:23]
wire _T_527 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_528 = _T_527 & _T_325; // @[lib.scala 104:41]
wire _T_531 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 104:78]
wire _T_532 = _T_528 | _T_531; // @[lib.scala 104:23]
wire _T_534 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_535 = _T_534 & _T_325; // @[lib.scala 104:41]
wire _T_538 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 104:78]
wire _T_539 = _T_535 | _T_538; // @[lib.scala 104:23]
wire _T_541 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_542 = _T_541 & _T_325; // @[lib.scala 104:41]
wire _T_545 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 104:78]
wire _T_546 = _T_542 | _T_545; // @[lib.scala 104:23]
wire [7:0] _T_553 = {_T_378,_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329}; // @[lib.scala 105:14]
wire [15:0] _T_561 = {_T_434,_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_553}; // @[lib.scala 105:14]
wire [7:0] _T_568 = {_T_490,_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441}; // @[lib.scala 105:14]
wire [31:0] _T_577 = {_T_546,_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_568,_T_561}; // @[lib.scala 105:14]
wire _T_578 = &_T_577; // @[lib.scala 105:25]
wire _T_579 = _T_320 & _T_578; // @[lsu_trigger.scala 21:92]
wire _T_583 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_584 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_586 = _T_584 & _T_31; // @[lsu_trigger.scala 21:58]
wire _T_587 = _T_583 | _T_586; // @[lsu_trigger.scala 20:168]
wire _T_588 = _T_46 & _T_587; // @[lsu_trigger.scala 20:110]
wire _T_591 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45]
wire _T_592 = ~_T_591; // @[lib.scala 101:39]
wire _T_593 = io_trigger_pkt_any_2_match_pkt & _T_592; // @[lib.scala 101:37]
wire _T_596 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 102:52]
wire _T_597 = _T_593 | _T_596; // @[lib.scala 102:41]
wire _T_599 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36]
wire _T_600 = _T_599 & _T_593; // @[lib.scala 104:41]
wire _T_603 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 104:78]
wire _T_604 = _T_600 | _T_603; // @[lib.scala 104:23]
wire _T_606 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_607 = _T_606 & _T_593; // @[lib.scala 104:41]
wire _T_610 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 104:78]
wire _T_611 = _T_607 | _T_610; // @[lib.scala 104:23]
wire _T_613 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_614 = _T_613 & _T_593; // @[lib.scala 104:41]
wire _T_617 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 104:78]
wire _T_618 = _T_614 | _T_617; // @[lib.scala 104:23]
wire _T_620 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_621 = _T_620 & _T_593; // @[lib.scala 104:41]
wire _T_624 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 104:78]
wire _T_625 = _T_621 | _T_624; // @[lib.scala 104:23]
wire _T_627 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_628 = _T_627 & _T_593; // @[lib.scala 104:41]
wire _T_631 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 104:78]
wire _T_632 = _T_628 | _T_631; // @[lib.scala 104:23]
wire _T_634 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_635 = _T_634 & _T_593; // @[lib.scala 104:41]
wire _T_638 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 104:78]
wire _T_639 = _T_635 | _T_638; // @[lib.scala 104:23]
wire _T_641 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_642 = _T_641 & _T_593; // @[lib.scala 104:41]
wire _T_645 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 104:78]
wire _T_646 = _T_642 | _T_645; // @[lib.scala 104:23]
wire _T_648 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_649 = _T_648 & _T_593; // @[lib.scala 104:41]
wire _T_652 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 104:78]
wire _T_653 = _T_649 | _T_652; // @[lib.scala 104:23]
wire _T_655 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_656 = _T_655 & _T_593; // @[lib.scala 104:41]
wire _T_659 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 104:78]
wire _T_660 = _T_656 | _T_659; // @[lib.scala 104:23]
wire _T_662 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_663 = _T_662 & _T_593; // @[lib.scala 104:41]
wire _T_666 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 104:78]
wire _T_667 = _T_663 | _T_666; // @[lib.scala 104:23]
wire _T_669 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_670 = _T_669 & _T_593; // @[lib.scala 104:41]
wire _T_673 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 104:78]
wire _T_674 = _T_670 | _T_673; // @[lib.scala 104:23]
wire _T_676 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_677 = _T_676 & _T_593; // @[lib.scala 104:41]
wire _T_680 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 104:78]
wire _T_681 = _T_677 | _T_680; // @[lib.scala 104:23]
wire _T_683 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_684 = _T_683 & _T_593; // @[lib.scala 104:41]
wire _T_687 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 104:78]
wire _T_688 = _T_684 | _T_687; // @[lib.scala 104:23]
wire _T_690 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_691 = _T_690 & _T_593; // @[lib.scala 104:41]
wire _T_694 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 104:78]
wire _T_695 = _T_691 | _T_694; // @[lib.scala 104:23]
wire _T_697 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_698 = _T_697 & _T_593; // @[lib.scala 104:41]
wire _T_701 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 104:78]
wire _T_702 = _T_698 | _T_701; // @[lib.scala 104:23]
wire _T_704 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_705 = _T_704 & _T_593; // @[lib.scala 104:41]
wire _T_708 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 104:78]
wire _T_709 = _T_705 | _T_708; // @[lib.scala 104:23]
wire _T_711 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_712 = _T_711 & _T_593; // @[lib.scala 104:41]
wire _T_715 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 104:78]
wire _T_716 = _T_712 | _T_715; // @[lib.scala 104:23]
wire _T_718 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_719 = _T_718 & _T_593; // @[lib.scala 104:41]
wire _T_722 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 104:78]
wire _T_723 = _T_719 | _T_722; // @[lib.scala 104:23]
wire _T_725 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_726 = _T_725 & _T_593; // @[lib.scala 104:41]
wire _T_729 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 104:78]
wire _T_730 = _T_726 | _T_729; // @[lib.scala 104:23]
wire _T_732 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_733 = _T_732 & _T_593; // @[lib.scala 104:41]
wire _T_736 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 104:78]
wire _T_737 = _T_733 | _T_736; // @[lib.scala 104:23]
wire _T_739 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_740 = _T_739 & _T_593; // @[lib.scala 104:41]
wire _T_743 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 104:78]
wire _T_744 = _T_740 | _T_743; // @[lib.scala 104:23]
wire _T_746 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_747 = _T_746 & _T_593; // @[lib.scala 104:41]
wire _T_750 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 104:78]
wire _T_751 = _T_747 | _T_750; // @[lib.scala 104:23]
wire _T_753 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_754 = _T_753 & _T_593; // @[lib.scala 104:41]
wire _T_757 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 104:78]
wire _T_758 = _T_754 | _T_757; // @[lib.scala 104:23]
wire _T_760 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_761 = _T_760 & _T_593; // @[lib.scala 104:41]
wire _T_764 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 104:78]
wire _T_765 = _T_761 | _T_764; // @[lib.scala 104:23]
wire _T_767 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_768 = _T_767 & _T_593; // @[lib.scala 104:41]
wire _T_771 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 104:78]
wire _T_772 = _T_768 | _T_771; // @[lib.scala 104:23]
wire _T_774 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_775 = _T_774 & _T_593; // @[lib.scala 104:41]
wire _T_778 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 104:78]
wire _T_779 = _T_775 | _T_778; // @[lib.scala 104:23]
wire _T_781 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_782 = _T_781 & _T_593; // @[lib.scala 104:41]
wire _T_785 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 104:78]
wire _T_786 = _T_782 | _T_785; // @[lib.scala 104:23]
wire _T_788 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_789 = _T_788 & _T_593; // @[lib.scala 104:41]
wire _T_792 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 104:78]
wire _T_793 = _T_789 | _T_792; // @[lib.scala 104:23]
wire _T_795 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_796 = _T_795 & _T_593; // @[lib.scala 104:41]
wire _T_799 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 104:78]
wire _T_800 = _T_796 | _T_799; // @[lib.scala 104:23]
wire _T_802 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_803 = _T_802 & _T_593; // @[lib.scala 104:41]
wire _T_806 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 104:78]
wire _T_807 = _T_803 | _T_806; // @[lib.scala 104:23]
wire _T_809 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_810 = _T_809 & _T_593; // @[lib.scala 104:41]
wire _T_813 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 104:78]
wire _T_814 = _T_810 | _T_813; // @[lib.scala 104:23]
wire [7:0] _T_821 = {_T_646,_T_639,_T_632,_T_625,_T_618,_T_611,_T_604,_T_597}; // @[lib.scala 105:14]
wire [15:0] _T_829 = {_T_702,_T_695,_T_688,_T_681,_T_674,_T_667,_T_660,_T_653,_T_821}; // @[lib.scala 105:14]
wire [7:0] _T_836 = {_T_758,_T_751,_T_744,_T_737,_T_730,_T_723,_T_716,_T_709}; // @[lib.scala 105:14]
wire [31:0] _T_845 = {_T_814,_T_807,_T_800,_T_793,_T_786,_T_779,_T_772,_T_765,_T_836,_T_829}; // @[lib.scala 105:14]
wire _T_846 = &_T_845; // @[lib.scala 105:25]
wire _T_847 = _T_588 & _T_846; // @[lsu_trigger.scala 21:92]
wire _T_851 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_852 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_854 = _T_852 & _T_38; // @[lsu_trigger.scala 21:58]
wire _T_855 = _T_851 | _T_854; // @[lsu_trigger.scala 20:168]
wire _T_856 = _T_46 & _T_855; // @[lsu_trigger.scala 20:110]
wire _T_859 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45]
wire _T_860 = ~_T_859; // @[lib.scala 101:39]
wire _T_861 = io_trigger_pkt_any_3_match_pkt & _T_860; // @[lib.scala 101:37]
wire _T_864 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 102:52]
wire _T_865 = _T_861 | _T_864; // @[lib.scala 102:41]
wire _T_867 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36]
wire _T_868 = _T_867 & _T_861; // @[lib.scala 104:41]
wire _T_871 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 104:78]
wire _T_872 = _T_868 | _T_871; // @[lib.scala 104:23]
wire _T_874 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_875 = _T_874 & _T_861; // @[lib.scala 104:41]
wire _T_878 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 104:78]
wire _T_879 = _T_875 | _T_878; // @[lib.scala 104:23]
wire _T_881 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_882 = _T_881 & _T_861; // @[lib.scala 104:41]
wire _T_885 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 104:78]
wire _T_886 = _T_882 | _T_885; // @[lib.scala 104:23]
wire _T_888 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_889 = _T_888 & _T_861; // @[lib.scala 104:41]
wire _T_892 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 104:78]
wire _T_893 = _T_889 | _T_892; // @[lib.scala 104:23]
wire _T_895 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_896 = _T_895 & _T_861; // @[lib.scala 104:41]
wire _T_899 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 104:78]
wire _T_900 = _T_896 | _T_899; // @[lib.scala 104:23]
wire _T_902 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_903 = _T_902 & _T_861; // @[lib.scala 104:41]
wire _T_906 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 104:78]
wire _T_907 = _T_903 | _T_906; // @[lib.scala 104:23]
wire _T_909 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_910 = _T_909 & _T_861; // @[lib.scala 104:41]
wire _T_913 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 104:78]
wire _T_914 = _T_910 | _T_913; // @[lib.scala 104:23]
wire _T_916 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_917 = _T_916 & _T_861; // @[lib.scala 104:41]
wire _T_920 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 104:78]
wire _T_921 = _T_917 | _T_920; // @[lib.scala 104:23]
wire _T_923 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_924 = _T_923 & _T_861; // @[lib.scala 104:41]
wire _T_927 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 104:78]
wire _T_928 = _T_924 | _T_927; // @[lib.scala 104:23]
wire _T_930 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_931 = _T_930 & _T_861; // @[lib.scala 104:41]
wire _T_934 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 104:78]
wire _T_935 = _T_931 | _T_934; // @[lib.scala 104:23]
wire _T_937 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_938 = _T_937 & _T_861; // @[lib.scala 104:41]
wire _T_941 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 104:78]
wire _T_942 = _T_938 | _T_941; // @[lib.scala 104:23]
wire _T_944 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_945 = _T_944 & _T_861; // @[lib.scala 104:41]
wire _T_948 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 104:78]
wire _T_949 = _T_945 | _T_948; // @[lib.scala 104:23]
wire _T_951 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_952 = _T_951 & _T_861; // @[lib.scala 104:41]
wire _T_955 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 104:78]
wire _T_956 = _T_952 | _T_955; // @[lib.scala 104:23]
wire _T_958 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_959 = _T_958 & _T_861; // @[lib.scala 104:41]
wire _T_962 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 104:78]
wire _T_963 = _T_959 | _T_962; // @[lib.scala 104:23]
wire _T_965 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_966 = _T_965 & _T_861; // @[lib.scala 104:41]
wire _T_969 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 104:78]
wire _T_970 = _T_966 | _T_969; // @[lib.scala 104:23]
wire _T_972 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_973 = _T_972 & _T_861; // @[lib.scala 104:41]
wire _T_976 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 104:78]
wire _T_977 = _T_973 | _T_976; // @[lib.scala 104:23]
wire _T_979 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_980 = _T_979 & _T_861; // @[lib.scala 104:41]
wire _T_983 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 104:78]
wire _T_984 = _T_980 | _T_983; // @[lib.scala 104:23]
wire _T_986 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_987 = _T_986 & _T_861; // @[lib.scala 104:41]
wire _T_990 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 104:78]
wire _T_991 = _T_987 | _T_990; // @[lib.scala 104:23]
wire _T_993 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_994 = _T_993 & _T_861; // @[lib.scala 104:41]
wire _T_997 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 104:78]
wire _T_998 = _T_994 | _T_997; // @[lib.scala 104:23]
wire _T_1000 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_1001 = _T_1000 & _T_861; // @[lib.scala 104:41]
wire _T_1004 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 104:78]
wire _T_1005 = _T_1001 | _T_1004; // @[lib.scala 104:23]
wire _T_1007 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_1008 = _T_1007 & _T_861; // @[lib.scala 104:41]
wire _T_1011 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 104:78]
wire _T_1012 = _T_1008 | _T_1011; // @[lib.scala 104:23]
wire _T_1014 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_1015 = _T_1014 & _T_861; // @[lib.scala 104:41]
wire _T_1018 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 104:78]
wire _T_1019 = _T_1015 | _T_1018; // @[lib.scala 104:23]
wire _T_1021 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_1022 = _T_1021 & _T_861; // @[lib.scala 104:41]
wire _T_1025 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 104:78]
wire _T_1026 = _T_1022 | _T_1025; // @[lib.scala 104:23]
wire _T_1028 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_1029 = _T_1028 & _T_861; // @[lib.scala 104:41]
wire _T_1032 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 104:78]
wire _T_1033 = _T_1029 | _T_1032; // @[lib.scala 104:23]
wire _T_1035 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_1036 = _T_1035 & _T_861; // @[lib.scala 104:41]
wire _T_1039 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 104:78]
wire _T_1040 = _T_1036 | _T_1039; // @[lib.scala 104:23]
wire _T_1042 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_1043 = _T_1042 & _T_861; // @[lib.scala 104:41]
wire _T_1046 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 104:78]
wire _T_1047 = _T_1043 | _T_1046; // @[lib.scala 104:23]
wire _T_1049 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_1050 = _T_1049 & _T_861; // @[lib.scala 104:41]
wire _T_1053 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 104:78]
wire _T_1054 = _T_1050 | _T_1053; // @[lib.scala 104:23]
wire _T_1056 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_1057 = _T_1056 & _T_861; // @[lib.scala 104:41]
wire _T_1060 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 104:78]
wire _T_1061 = _T_1057 | _T_1060; // @[lib.scala 104:23]
wire _T_1063 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_1064 = _T_1063 & _T_861; // @[lib.scala 104:41]
wire _T_1067 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 104:78]
wire _T_1068 = _T_1064 | _T_1067; // @[lib.scala 104:23]
wire _T_1070 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_1071 = _T_1070 & _T_861; // @[lib.scala 104:41]
wire _T_1074 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 104:78]
wire _T_1075 = _T_1071 | _T_1074; // @[lib.scala 104:23]
wire _T_1077 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_1078 = _T_1077 & _T_861; // @[lib.scala 104:41]
wire _T_1081 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 104:78]
wire _T_1082 = _T_1078 | _T_1081; // @[lib.scala 104:23]
wire [7:0] _T_1089 = {_T_914,_T_907,_T_900,_T_893,_T_886,_T_879,_T_872,_T_865}; // @[lib.scala 105:14]
wire [15:0] _T_1097 = {_T_970,_T_963,_T_956,_T_949,_T_942,_T_935,_T_928,_T_921,_T_1089}; // @[lib.scala 105:14]
wire [7:0] _T_1104 = {_T_1026,_T_1019,_T_1012,_T_1005,_T_998,_T_991,_T_984,_T_977}; // @[lib.scala 105:14]
wire [31:0] _T_1113 = {_T_1082,_T_1075,_T_1068,_T_1061,_T_1054,_T_1047,_T_1040,_T_1033,_T_1104,_T_1097}; // @[lib.scala 105:14]
wire _T_1114 = &_T_1113; // @[lib.scala 105:25]
wire _T_1115 = _T_856 & _T_1114; // @[lsu_trigger.scala 21:92]
wire [2:0] _T_1117 = {_T_1115,_T_847,_T_579}; // @[Cat.scala 29:58]
assign io_lsu_trigger_match_m = {_T_1117,_T_311}; // @[lsu_trigger.scala 20:25]
endmodule

49
src/main/scala/lsu/lsu.scala
View File

@ -37,6 +37,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val lsu_store_stall_any = Output(Bool()) val lsu_store_stall_any = Output(Bool())
val lsu_fastint_stall_any = Output(Bool()) val lsu_fastint_stall_any = Output(Bool())
val lsu_idle_any = Output(Bool()) val lsu_idle_any = Output(Bool())
val lsu_active = Output(Bool())
val lsu_fir_addr = Output(UInt(31.W)) val lsu_fir_addr = Output(UInt(31.W))
val lsu_fir_error = Output(UInt(2.W)) val lsu_fir_error = Output(UInt(2.W))
val lsu_single_ecc_error_incr = Output(Bool()) val lsu_single_ecc_error_incr = Output(Bool())
@ -47,7 +48,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val lsu_bus_clk_en = Input(Bool()) val lsu_bus_clk_en = Input(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val free_clk = Input(Clock()) val active_clk = Input(Clock())
}) })
val dma_dccm_wdata = WireInit(0.U(64.W)) val dma_dccm_wdata = WireInit(0.U(64.W))
@ -56,6 +57,10 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dma_mem_tag_m = WireInit(0.U(3.W)) val dma_mem_tag_m = WireInit(0.U(3.W))
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
val lsu_busm_clken = WireInit(0.U(1.W))
val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
@ -80,7 +85,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dma_mem_tag_d = io.lsu_dma.dma_mem_tag val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1)
val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
dma_dccm_wdata_hi := dma_dccm_wdata(63,32) dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
@ -93,13 +98,18 @@ class lsu extends Module with RequireAsyncReset with param with lib {
// Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
// Store buffer now have only non-dma dccm stores // Store buffer now have only non-dma dccm stores
// stbuf_empty not needed since it has only dccm stores // stbuf_empty not needed since it has only dccm stores
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any & bus_intf.io.lsu_bus_idle_any io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any
io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
// Instantiate the store buffer // Instantiate the store buffer
val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r))
// Disable Forwarding for now // Disable Forwarding for now
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
// Bus signals // Bus signals
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
// Dual signals
val ldst_dual_d = lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
val ldst_dual_m = lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
val ldst_dual_r = lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
// PMU signals // PMU signals
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
@ -107,6 +117,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
//LSU_LSC_Control //LSU_LSC_Control
//Inputs //Inputs
lsu_lsc_ctl.io.clk_override := io.clk_override
lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
@ -121,6 +132,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
lsu_lsc_ctl.io.flush_m_up := flush_m_up lsu_lsc_ctl.io.flush_m_up := flush_m_up
lsu_lsc_ctl.io.flush_r := flush_r lsu_lsc_ctl.io.flush_r := flush_r
lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d
lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m
lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r
lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu
lsu_lsc_ctl.io.lsu_p <> io.lsu_p lsu_lsc_ctl.io.lsu_p <> io.lsu_p
lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
@ -138,6 +152,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error
// DCCM Control // DCCM Control
//Inputs //Inputs
dccm_ctl.io.clk_override := io.clk_override
dccm_ctl.io.ldst_dual_m := ldst_dual_m
dccm_ctl.io.ldst_dual_r := ldst_dual_r
dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
@ -196,8 +213,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
io.lsu_pic <> dccm_ctl.io.lsu_pic io.lsu_pic <> dccm_ctl.io.lsu_pic
//Store Buffer //Store Buffer
//Inputs //Inputs
stbuf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk stbuf.io.ldst_dual_d := ldst_dual_d
stbuf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk stbuf.io.ldst_dual_m := ldst_dual_m
stbuf.io.ldst_dual_r := ldst_dual_r
stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
@ -223,6 +241,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
// ECC // ECC
//Inputs //Inputs
ecc.io.clk_override := io.clk_override
ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
@ -262,9 +281,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
//Clock Domain //Clock Domain
//Inputs //Inputs
clkdomain.io.free_clk := io.free_clk clkdomain.io.active_clk := io.active_clk
clkdomain.io.clk_override := io.clk_override clkdomain.io.clk_override := io.clk_override
clkdomain.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt
clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req
clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r
clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
@ -284,21 +303,24 @@ class lsu extends Module with RequireAsyncReset with param with lib {
//Inputs //Inputs
bus_intf.io.scan_mode := io.scan_mode bus_intf.io.scan_mode := io.scan_mode
io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
bus_intf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk bus_intf.io.clk_override := io.clk_override
bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
bus_intf.io.lsu_busm_clken := lsu_busm_clken
bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken
bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk
bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk
bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk
bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
bus_intf.io.free_clk := io.free_clk bus_intf.io.active_clk := io.active_clk
bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk
bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
bus_intf.io.lsu_busreq_m := lsu_busreq_m bus_intf.io.lsu_busreq_m := lsu_busreq_m
bus_intf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d bus_intf.io.ldst_dual_d := ldst_dual_d
bus_intf.io.ldst_dual_m := ldst_dual_m
bus_intf.io.ldst_dual_r := ldst_dual_r
bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
bus_intf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
bus_intf.io.store_data_r := dccm_ctl.io.store_data_r bus_intf.io.store_data_r := dccm_ctl.io.store_data_r
@ -319,3 +341,6 @@ class lsu extends Module with RequireAsyncReset with param with lib {
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
} }
object lsu_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
}

5
src/main/scala/lsu/lsu_addrcheck.scala
View File

@ -52,7 +52,7 @@ class lsu_addrcheck extends Module with RequireAsyncReset with lib
val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0) ,aslong(PIC_BASE_ADDR).U ,PIC_SIZE) val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0) ,aslong(PIC_BASE_ADDR).U ,PIC_SIZE)
val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region val base_reg_dccm_or_pic = ((io.rs1_region_d(3,0) === DCCM_REGION.U) & DCCM_ENABLE.U) | (io.rs1_region_d(3,0) === PIC_REGION.U)//base region
io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d) io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d) io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
@ -87,7 +87,7 @@ class lsu_addrcheck extends Module with RequireAsyncReset with lib
val unmapped_access_fault_d = WireInit(1.U(1.W)) val unmapped_access_fault_d = WireInit(1.U(1.W))
val mpu_access_fault_d = WireInit(1.U(1.W)) val mpu_access_fault_d = WireInit(1.U(1.W))
if(DCCM_REGION == PIC_REGION){ if(DCCM_ENABLE & (DCCM_REGION == PIC_REGION)){
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & !(start_addr_in_dccm_d | start_addr_in_pic_d)) | unmapped_access_fault_d := ((start_addr_in_dccm_region_d & !(start_addr_in_dccm_d | start_addr_in_pic_d)) |
// 0. Addr in dccm/pic region but not in dccm/pic offset // 0. Addr in dccm/pic region but not in dccm/pic offset
(end_addr_in_dccm_region_d & !(end_addr_in_dccm_d | end_addr_in_pic_d)) | (end_addr_in_dccm_region_d & !(end_addr_in_dccm_d | end_addr_in_pic_d)) |
@ -120,4 +120,3 @@ class lsu_addrcheck extends Module with RequireAsyncReset with lib
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
} }

53
src/main/scala/lsu/lsu_bus_buffer.scala
View File

@ -10,10 +10,13 @@ import ifu._
@chiselName @chiselName
class lsu_bus_buffer extends Module with RequireAsyncReset with lib { class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle { val io = IO(new Bundle {
val clk_override = Input(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val tlu_busbuff = new tlu_busbuff() val tlu_busbuff = new tlu_busbuff()
val dctl_busbuff = new dctl_busbuff() val dctl_busbuff = new dctl_busbuff()
val dec_tlu_force_halt = Input(Bool()) val dec_tlu_force_halt = Input(Bool())
val lsu_bus_obuf_c1_clken = Input(Bool())
val lsu_busm_clken = Input(Bool())
val lsu_c2_r_clk = Input(Clock()) val lsu_c2_r_clk = Input(Clock())
val lsu_bus_ibuf_c1_clk = Input(Clock()) val lsu_bus_ibuf_c1_clk = Input(Clock())
val lsu_bus_obuf_c1_clk = Input(Clock()) val lsu_bus_obuf_c1_clk = Input(Clock())
@ -48,7 +51,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val lsu_bus_buffer_pend_any = Output(Bool()) val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool()) val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool()) val lsu_bus_buffer_empty_any = Output(Bool())
val lsu_bus_idle_any = Output(Bool()) // val lsu_bus_idle_any = Output(Bool())
val ld_byte_hit_buf_lo = Output((UInt(4.W))) val ld_byte_hit_buf_lo = Output((UInt(4.W)))
val ld_byte_hit_buf_hi = Output((UInt(4.W))) val ld_byte_hit_buf_hi = Output((UInt(4.W)))
val ld_fwddata_buf_lo = Output((UInt(32.W))) val ld_fwddata_buf_lo = Output((UInt(32.W)))
@ -92,7 +95,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) val buf_ldfwd_in = Wire(Vec(DEPTH, Bool()))
buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B)
val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) val buf_ldfwd_en = Wire(Vec(DEPTH, Bool()))
buf_ldfwd_en := buf_ldfwd_en.map(i=> false.B) buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt)
val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) val buf_data_in = Wire(Vec(DEPTH, UInt(32.W)))
buf_data_in := buf_data_in.map(i=> 0.U) buf_data_in := buf_data_in.map(i=> 0.U)
val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W)))
@ -113,7 +116,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W)))
buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U)
val buf_rst = Wire(Vec(DEPTH, Bool())) val buf_rst = Wire(Vec(DEPTH, Bool()))
buf_rst := buf_rst.map(i=> false.B) buf_rst := buf_rst.map(i=> io.dec_tlu_force_halt)
val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U)
val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W)))
buf_byteen_in := buf_byteen_in.map(i=> 0.U) buf_byteen_in := buf_byteen_in.map(i=> 0.U)
@ -279,13 +282,13 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val bus_cmd_ready = WireInit(Bool(), false.B) val bus_cmd_ready = WireInit(Bool(), false.B)
val obuf_valid = WireInit(Bool(), false.B) val obuf_valid = WireInit(Bool(), false.B)
val obuf_nosend = WireInit(Bool(), false.B) val obuf_nosend = WireInit(Bool(), false.B)
val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B)
val bus_addr_match_pending = WireInit(Bool(), false.B) val bus_addr_match_pending = WireInit(Bool(), false.B)
obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) |
((indexing(buf_state, CmdPtr0) === cmd_C) & ((indexing(buf_state, CmdPtr0) === cmd_C) &
found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) &
(!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) |
obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !lsu_bus_cntr_overflow & !bus_addr_match_pending & io.lsu_bus_clk_en obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en
val bus_cmd_sent = WireInit(Bool(), false.B) val bus_cmd_sent = WireInit(Bool(), false.B)
val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0))
@ -313,8 +316,9 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
val obuf_write = WireInit(Bool(), false.B) val obuf_write = WireInit(Bool(), false.B)
val obuf_rdrsp_pend_in = (!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) |
((bus_cmd_sent & !obuf_write) & !io.dec_tlu_force_halt) (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt
val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt
val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U)
val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag)
val obuf_addr = WireInit(UInt(32.W), 0.U) val obuf_addr = WireInit(UInt(32.W), 0.U)
@ -328,7 +332,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)),
Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0))))
val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)),
Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1))))
val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_))
val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_))
@ -337,9 +341,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_dualhi := buf_dualhi.map(i=> false.B) buf_dualhi := buf_dualhi.map(i=> false.B)
obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) &
!indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) &
((indexing(buf_write, CmdPtr0) & indexing(buf_write, CmdPtr1) & (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) |
(indexing(buf_addr, CmdPtr0)(31,3)===indexing(buf_addr, CmdPtr1)(31,3)) & !bus_coalescing_disable & !BUILD_AXI_NATIVE.B) |
(!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0)))) |
(ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r)
val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)} val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)}
@ -409,7 +411,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_)))
val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W)))
buf_ageQ := buf_ageQ.map(i=> 0.U) buf_ageQ := buf_ageQ.map(i=> 0.U)
buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j))).asUInt).reverse.reduce(Cat(_,_))) buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j))).asUInt & !io.dec_tlu_force_halt).reverse.reduce(Cat(_,_)))
buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_)))
buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)))
@ -418,7 +420,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) |
(ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_)))
buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_)))
buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))).asUInt).reverse.reduce(Cat(_,_))) buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))).asUInt & !io.dec_tlu_force_halt).reverse.reduce(Cat(_,_)))
@ -445,10 +447,12 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_wr_en(i) := buf_state_en(i) buf_wr_en(i) := buf_state_en(i)
buf_data_en(i) := buf_state_en(i) buf_data_en(i) := buf_state_en(i)
buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0))
buf_cmd_state_bus_en(i) := 0.U
} }
is(wait_C) { is(wait_C) {
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C)
buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt
buf_cmd_state_bus_en(i) := 0.U
} }
is(cmd_C) { is(cmd_C) {
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C))
@ -463,7 +467,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)))
} }
is(resp_C) { is(resp_C) {
buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !(BUILD_AXI_NATIVE.B & bus_rsp_write_error))).asBool(), idle_C, buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & bus_rsp_write_error)).asBool(), idle_C,
Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C,
Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C)))
buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) |
@ -475,18 +479,21 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) |
(bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) |
(bus_rsp_write_error & BUILD_AXI_NATIVE.B & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W))))
buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))
buf_cmd_state_bus_en(i) := 0.U
} }
is(done_partial_C) { // Other part of dual load hasn't returned is(done_partial_C) { // Other part of dual load hasn't returned
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C))
buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) |
(buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt())))
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
buf_cmd_state_bus_en(i) := 0.U
} }
is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C)
buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt
buf_cmd_state_bus_en(i) := 0.U
} }
is(done_C) { is(done_C) {
buf_nxtstate(i) := idle_C buf_nxtstate(i) := idle_C
@ -494,6 +501,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_state_en(i) := 1.U buf_state_en(i) := 1.U
buf_ldfwd_in(i) := false.B buf_ldfwd_in(i) := false.B
buf_ldfwd_en(i) := buf_state_en(i) buf_ldfwd_en(i) := buf_state_en(i)
buf_cmd_state_bus_en(i) := 0.U
} }
} }
buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())}
@ -517,7 +525,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode))
buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & !buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & !buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_))
val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_)
buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
@ -532,7 +539,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B)
io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r
io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r
val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(BUILD_AXI_NATIVE.B & buf_write(i))))) val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i)))))
io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i))))
io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U))
val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i)))
@ -540,7 +547,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0)
val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U)
io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error
@ -551,7 +558,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn))
bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable)
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->
(BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U))))))
bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready)
bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready
@ -570,7 +577,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
io.lsu_axi.aw.bits.id := obuf_tag0 io.lsu_axi.aw.bits.id := obuf_tag0
io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W)))
io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W))
io.lsu_axi.aw.bits.prot := 0.U io.lsu_axi.aw.bits.prot := 1.U
io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U)
io.lsu_axi.aw.bits.region := obuf_addr(31,28) io.lsu_axi.aw.bits.region := obuf_addr(31,28)
io.lsu_axi.aw.bits.len := 0.U io.lsu_axi.aw.bits.len := 0.U
@ -587,7 +594,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
io.lsu_axi.ar.bits.id := obuf_tag0 io.lsu_axi.ar.bits.id := obuf_tag0
io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W)))
io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W))
io.lsu_axi.ar.bits.prot := 0.U io.lsu_axi.ar.bits.prot := 1.U
io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U)
io.lsu_axi.ar.bits.region := obuf_addr(31,28) io.lsu_axi.ar.bits.region := obuf_addr(31,28)
io.lsu_axi.ar.bits.len := 0.U io.lsu_axi.ar.bits.len := 0.U
@ -601,9 +608,9 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any
io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag))
lsu_bus_cntr_overflow := 0.U //lsu_bus_cntr_overflow := 0.U
io.lsu_bus_idle_any := 1.U // io.lsu_bus_idle_any := 1.U
// PMU signals // PMU signals
io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready)

40
src/main/scala/lsu/lsu_bus_intf.scala
View File

@ -7,15 +7,17 @@ import include._
class lsu_bus_intf extends Module with RequireAsyncReset with lib { class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val io = IO (new Bundle { val io = IO (new Bundle {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val clk_override = Input(Bool())
val tlu_busbuff = new tlu_busbuff() val tlu_busbuff = new tlu_busbuff()
val lsu_c1_m_clk = Input(Clock()) val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable
val lsu_busm_clken = Input(Bool())
val lsu_c1_r_clk = Input(Clock()) val lsu_c1_r_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock()) val lsu_c2_r_clk = Input(Clock())
val lsu_bus_ibuf_c1_clk = Input(Clock()) val lsu_bus_ibuf_c1_clk = Input(Clock())
val lsu_bus_obuf_c1_clk = Input(Clock()) val lsu_bus_obuf_c1_clk = Input(Clock())
val lsu_bus_buf_c1_clk = Input(Clock()) val lsu_bus_buf_c1_clk = Input(Clock())
val lsu_free_c2_clk = Input(Clock()) val lsu_free_c2_clk = Input(Clock())
val free_clk = Input(Clock()) val active_clk = Input(Clock())
val lsu_busm_clk = Input(Clock()) val lsu_busm_clk = Input(Clock())
val axi = new axi_channels(LSU_BUS_TAG) val axi = new axi_channels(LSU_BUS_TAG)
val dec_lsu_valid_raw_d = Input(Bool()) val dec_lsu_valid_raw_d = Input(Bool())
@ -24,13 +26,14 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t()))
val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t()))
val lsu_addr_d = Input(UInt(32.W))
val lsu_addr_m = Input(UInt(32.W)) val lsu_addr_m = Input(UInt(32.W))
val lsu_addr_r = Input(UInt(32.W)) val lsu_addr_r = Input(UInt(32.W))
val end_addr_d = Input(UInt(32.W))
val end_addr_m = Input(UInt(32.W)) val end_addr_m = Input(UInt(32.W))
val end_addr_r = Input(UInt(32.W)) val end_addr_r = Input(UInt(32.W))
val ldst_dual_d = Input(Bool())
val ldst_dual_m = Input(Bool())
val ldst_dual_r = Input(Bool())
val store_data_r = Input(UInt(32.W)) val store_data_r = Input(UInt(32.W))
val dec_tlu_force_halt = Input(Bool()) val dec_tlu_force_halt = Input(Bool())
@ -44,7 +47,7 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val lsu_bus_buffer_pend_any = Output(Bool()) val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool()) val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool()) val lsu_bus_buffer_empty_any = Output(Bool())
val lsu_bus_idle_any = Output(Bool()) //val lsu_bus_idle_any = Output(Bool())
val bus_read_data_m = Output(UInt(32.W)) val bus_read_data_m = Output(UInt(32.W))
val dctl_busbuff = new dctl_busbuff() val dctl_busbuff = new dctl_busbuff()
@ -53,9 +56,6 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
}) })
val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B)
val ldst_dual_d = WireInit(Bool(), init = false.B)
val ldst_dual_m = WireInit(Bool(), init = false.B)
val ldst_dual_r = WireInit(Bool(), init = false.B)
val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U)
val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U)
@ -101,7 +101,9 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
bus_buffer.io.scan_mode := io.scan_mode bus_buffer.io.scan_mode := io.scan_mode
io.tlu_busbuff <> bus_buffer.io.tlu_busbuff io.tlu_busbuff <> bus_buffer.io.tlu_busbuff
bus_buffer.io.clk_override := io.clk_override
bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken
bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken
bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt
bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk
bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk
@ -133,7 +135,7 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
@ -142,19 +144,18 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
bus_buffer.io.no_word_merge_r := no_word_merge_r bus_buffer.io.no_word_merge_r := no_word_merge_r
bus_buffer.io.no_dword_merge_r := no_dword_merge_r bus_buffer.io.no_dword_merge_r := no_dword_merge_r
bus_buffer.io.is_sideeffects_r := is_sideeffects_r bus_buffer.io.is_sideeffects_r := is_sideeffects_r
bus_buffer.io.ldst_dual_d := ldst_dual_d bus_buffer.io.ldst_dual_d := io.ldst_dual_d
bus_buffer.io.ldst_dual_m := ldst_dual_m bus_buffer.io.ldst_dual_m := io.ldst_dual_m
bus_buffer.io.ldst_dual_r := ldst_dual_r bus_buffer.io.ldst_dual_r := io.ldst_dual_r
bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m
bus_buffer.io.ld_full_hit_m := ld_full_hit_m bus_buffer.io.ld_full_hit_m := ld_full_hit_m
bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q
ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W)))
ldst_dual_d := io.lsu_addr_d(2) =/= io.end_addr_d(2)
addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m)
no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m)
ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0)
ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0)
@ -190,14 +191,11 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
io.bus_read_data_m := ld_fwddata_m(31,0) io.bus_read_data_m := ld_fwddata_m(31,0)
withClock(io.free_clk) { withClock(io.active_clk) {
lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U)
} }
withClock(io.lsu_c1_m_clk) {
ldst_dual_m := RegNext(ldst_dual_d, init = 0.U)
}
withClock(io.lsu_c1_r_clk) { withClock(io.lsu_c1_r_clk) {
ldst_dual_r := RegNext(ldst_dual_m, init = 0.U)
is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U)
ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W))
} }

27
src/main/scala/lsu/lsu_clkdomain.scala
View File

@ -9,10 +9,10 @@ import include._
class lsu_clkdomain extends Module with RequireAsyncReset with lib{ class lsu_clkdomain extends Module with RequireAsyncReset with lib{
val io = IO (new Bundle { val io = IO (new Bundle {
val free_clk = Input(Clock()) // clock val active_clk = Input(Clock()) // clock
// Inputs // Inputs
val clk_override = Input(Bool()) // chciken bit to turn off clock gating val clk_override = Input(Bool()) // chciken bit to turn off clock gating
val addr_in_dccm_m = Input(Bool()) // address in dccm val dec_tlu_force_halt = Input(Bool())
val dma_dccm_req = Input(Bool()) // dma is active val dma_dccm_req = Input(Bool()) // dma is active
val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue
@ -31,6 +31,8 @@ class lsu_clkdomain extends Module with RequireAsyncReset with lib{
val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t)) // lsu packet in r val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t)) // lsu packet in r
// Outputs // Outputs
val lsu_bus_obuf_c1_clken = Output(Bool())// obuf clock enable
val lsu_busm_clken = Output(Bool()) // bus clock enable
val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock
@ -54,13 +56,12 @@ class lsu_clkdomain extends Module with RequireAsyncReset with lib{
//------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------
// Clock Enable Logic // Clock Enable Logic
//------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------
val lsu_c1_d_clken_q = Wire(Bool())
val lsu_c1_m_clken_q = Wire(Bool()) val lsu_c1_m_clken_q = Wire(Bool())
val lsu_c1_r_clken_q = Wire(Bool()) val lsu_c1_r_clken_q = Wire(Bool())
val lsu_free_c1_clken_q = Wire(Bool()) val lsu_free_c1_clken_q = Wire(Bool())
val lsu_c1_d_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override val lsu_c1_m_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override
val lsu_c1_m_clken = io.lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override
val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override
val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override
@ -70,15 +71,16 @@ class lsu_clkdomain extends Module with RequireAsyncReset with lib{
val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.bits.store) | io.clk_override) val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.bits.store) | io.clk_override)
val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override
val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en io.lsu_bus_obuf_c1_clken := (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
val lsu_bus_buf_c1_clken = !io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override val lsu_bus_buf_c1_clken = !io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.dec_tlu_force_halt | io.clk_override
val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | !io.lsu_bus_buffer_empty_any | !io.lsu_stbuf_empty_any | io.clk_override val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | !io.lsu_bus_buffer_empty_any | !io.lsu_stbuf_empty_any | io.clk_override
val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override
io.lsu_busm_clken := (!io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
lsu_free_c1_clken_q := withClock(io.free_clk) {RegNext(lsu_free_c1_clken,0.U)} lsu_free_c1_clken_q := withClock(io.active_clk) {RegNext(lsu_free_c1_clken,0.U)}
lsu_c1_d_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_d_clken, 0.U)}
lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)} lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)}
lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)} lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)}
@ -90,10 +92,11 @@ class lsu_clkdomain extends Module with RequireAsyncReset with lib{
io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode) io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode)
io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode) io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode)
io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode) io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode)
io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,lsu_bus_obuf_c1_clken.asBool,io.scan_mode) io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,io.lsu_bus_obuf_c1_clken.asBool,io.scan_mode)
io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode) io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode)
io.lsu_busm_clk := rvclkhdr(clock,io.lsu_bus_clk_en.asBool,io.scan_mode) io.lsu_busm_clk := rvclkhdr(clock,io.lsu_busm_clken.asBool,io.scan_mode)
io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode) io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode)
} }

63
src/main/scala/lsu/lsu_dccm_ctl.scala
View File

@ -9,6 +9,7 @@ import chisel3.experimental.chiselName
class lsu_dccm_ctl extends Module with RequireAsyncReset with lib class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
{ {
val io = IO(new Bundle{ val io = IO(new Bundle{
val clk_override = Input(Bool())
val lsu_c2_m_clk = Input(Clock()) val lsu_c2_m_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock()) val lsu_c2_r_clk = Input(Clock())
val lsu_free_c2_clk = Input(Clock()) //tbd val lsu_free_c2_clk = Input(Clock()) //tbd
@ -29,6 +30,8 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
val lsu_raw_fwd_lo_r = Input(UInt(1.W)) val lsu_raw_fwd_lo_r = Input(UInt(1.W))
val lsu_raw_fwd_hi_r = Input(UInt(1.W)) val lsu_raw_fwd_hi_r = Input(UInt(1.W))
val lsu_commit_r = Input(UInt(1.W)) val lsu_commit_r = Input(UInt(1.W))
val ldst_dual_m = Input(UInt(1.W))
val ldst_dual_r = Input(UInt(1.W))
// lsu address down the pipe // lsu address down the pipe
val lsu_addr_d = Input(UInt(32.W))//verify bits val lsu_addr_d = Input(UInt(32.W))//verify bits
@ -109,26 +112,31 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
val picm_rd_data_r_32 = WireInit(UInt(32.W),0.U) val picm_rd_data_r_32 = WireInit(UInt(32.W),0.U)
val picm_rd_data_r = WireInit(UInt(64.W),0.U) val picm_rd_data_r = WireInit(UInt(64.W),0.U)
val lsu_ld_data_corr_m = WireInit(UInt(64.W),0.U) val lsu_ld_data_corr_m = WireInit(UInt(64.W),0.U)
val stbuf_fwddata_en = WireInit(UInt(1.W),0.U)
val lsu_double_ecc_error_r_ff = WireInit(UInt(1.W),0.U)
val ld_single_ecc_error_hi_r_ff = WireInit(UInt(1.W),0.U)
val ld_single_ecc_error_lo_r_ff = WireInit(UInt(1.W),0.U)
val ld_sec_addr_hi_r_ff = WireInit(UInt(DCCM_BITS.W),0.U)
val ld_sec_addr_lo_r_ff = WireInit(UInt(DCCM_BITS.W),0.U)
//Forwarding stbuf //Forwarding stbuf
if (LOAD_TO_USE_PLUS1 == 1){ if (LOAD_TO_USE_PLUS1 == 1){
io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma
io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc
io.dma_dccm_ctl.dccm_dma_rdata := lsu_rdata_corr_r io.dma_dccm_ctl.dccm_dma_rdata := Mux(io.ldst_dual_r,lsu_rdata_corr_r, Fill(2,lsu_rdata_corr_r(31,0)))
stbuf_fwddata_en := io.stbuf_fwdbyteen_hi_m.orR | io.stbuf_fwdbyteen_lo_m.orR | io.clk_override
//Registers //Registers
io.dccm_rdata_hi_r := rvdffe(io.dccm_rdata_hi_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool) io.dccm_rdata_hi_r := rvdffe(io.dccm_rdata_hi_m,((io.lsu_dccm_rden_m & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode.asBool)
io.dccm_rdata_lo_r := rvdffe(io.dccm_rdata_lo_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool) io.dccm_rdata_lo_r := rvdffe(io.dccm_rdata_lo_m,(io.lsu_dccm_rden_m|io.clk_override).asBool,clock,io.scan_mode.asBool)
io.dccm_data_ecc_hi_r := rvdffe(io.dccm_data_ecc_hi_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool) io.dccm_data_ecc_hi_r := rvdffe(io.dccm_data_ecc_hi_m,(io.lsu_dccm_rden_m|io.clk_override).asBool,clock,io.scan_mode.asBool)
io.dccm_data_ecc_lo_r := rvdffe(io.dccm_data_ecc_lo_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool) io.dccm_data_ecc_lo_r := rvdffe(io.dccm_data_ecc_lo_m,(io.lsu_dccm_rden_m|io.clk_override).asBool,clock,io.scan_mode.asBool)
stbuf_fwdbyteen_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m),0.U)} stbuf_fwdbyteen_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m),0.U)}
stbuf_fwddata_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwddata_hi_m ,io.stbuf_fwddata_lo_m ),0.U)} stbuf_fwddata_r := Cat (rvdffe (io.stbuf_fwddata_hi_m,stbuf_fwddata_en,clock,io.scan_mode),rvdffe(io.stbuf_fwddata_lo_m,stbuf_fwddata_en,clock,io.scan_mode))
picm_rd_data_r_32 := withClock(io.lsu_c2_r_clk){RegNext(picm_rd_data_m(31,0),0.U)} picm_rd_data_r_32 := rvdffe(picm_rd_data_m(31,0),(io.addr_in_pic_m | io.clk_override),clock,io.scan_mode)
picm_rd_data_r := Cat(picm_rd_data_r_32,picm_rd_data_r_32) picm_rd_data_r := Cat(picm_rd_data_r_32,picm_rd_data_r_32)
io.dma_dccm_ctl.dccm_dma_rtag := withClock(io.lsu_c1_r_clk){RegNext(io.dma_mem_tag_m,0.U)} io.dma_dccm_ctl.dccm_dma_rtag := withClock(io.lsu_c1_r_clk){RegNext(io.dma_mem_tag_m,0.U)}
lsu_rdata_corr_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i), Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),(Fill(8,io.addr_in_dccm_r) & dccm_rdata_corr_r((8*i)+7,8*i))))))))
lsu_rdata_corr_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_corr_r((8*i)+7,8*i))))))) lsu_rdata_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i), Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),(Fill(8,io.addr_in_dccm_r) & dccm_rdata_r((8*i)+7,8*i))))))))
lsu_rdata_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_r((8*i)+7,8*i)))))))
io.lsu_ld_data_r := lsu_rdata_r>> 8.U*io.lsu_addr_r(1,0) io.lsu_ld_data_r := lsu_rdata_r>> 8.U*io.lsu_addr_r(1,0)
io.lsu_ld_data_corr_r := lsu_rdata_corr_r >> 8.U*io.lsu_addr_r(1,0) io.lsu_ld_data_corr_r := lsu_rdata_corr_r >> 8.U*io.lsu_addr_r(1,0)
} }
@ -136,7 +144,7 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
else{ else{
io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma io.dma_dccm_ctl.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma
io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc io.dma_dccm_ctl.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc
io.dma_dccm_ctl.dccm_dma_rdata := lsu_rdata_corr_m io.dma_dccm_ctl.dccm_dma_rdata := Mux(io.ldst_dual_m,lsu_rdata_corr_m, Fill(2,lsu_rdata_corr_m))
io.dma_dccm_ctl.dccm_dma_rtag := io.dma_mem_tag_m io.dma_dccm_ctl.dccm_dma_rtag := io.dma_mem_tag_m
io.dccm_rdata_lo_r := 0.U io.dccm_rdata_lo_r := 0.U
io.dccm_rdata_hi_r := 0.U io.dccm_rdata_hi_r := 0.U
@ -144,9 +152,9 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
io.dccm_data_ecc_lo_r := 0.U io.dccm_data_ecc_lo_r := 0.U
io.lsu_ld_data_r := 0.U io.lsu_ld_data_r := 0.U
//Registers //Registers
io.lsu_ld_data_corr_r := withClock(io.lsu_c2_r_clk){RegNext(lsu_ld_data_corr_m,0.U)} lsu_rdata_corr_m := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(((Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m))(i)).asBool,(Cat(io.stbuf_fwddata_hi_m,io.stbuf_fwddata_lo_m))((8*i)+7,8*i), Mux(io.addr_in_pic_m.asBool,picm_rd_data_m((8*i)+7,8*i),(Fill(2,io.addr_in_dccm_m) & dccm_rdata_corr_m((8*i)+7,8*i))))))))
lsu_rdata_corr_m := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(((Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m))(i)).asBool,(Cat(io.stbuf_fwddata_hi_m,io.stbuf_fwddata_lo_m))((8*i)+7,8*i),Mux(io.addr_in_pic_m.asBool,picm_rd_data_m((8*i)+7,8*i),dccm_rdata_corr_m((8*i)+7,8*i))))))) lsu_rdata_m := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(((Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m))(i)).asBool,(Cat(io.stbuf_fwddata_hi_m,io.stbuf_fwddata_lo_m))((8*i)+7,8*i), Mux(io.addr_in_pic_m.asBool,picm_rd_data_m((8*i)+7,8*i),(Fill(2,io.addr_in_dccm_m) & dccm_rdata_m((8*i)+7,8*i))))))))
lsu_rdata_m := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(((Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m))(i)).asBool,(Cat(io.stbuf_fwddata_hi_m,io.stbuf_fwddata_lo_m))((8*i)+7,8*i),Mux(io.addr_in_pic_m.asBool,picm_rd_data_m((8*i)+7,8*i),dccm_rdata_m((8*i)+7,8*i))))))) io.lsu_ld_data_corr_r := rvdffe(lsu_ld_data_corr_m,((io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & (io.addr_in_pic_m | io.addr_in_dccm_m)) | io.clk_override),clock,io.scan_mode)
io.lsu_ld_data_m := lsu_rdata_m >> 8.U*io.lsu_addr_m(1,0) io.lsu_ld_data_m := lsu_rdata_m >> 8.U*io.lsu_addr_m(1,0)
lsu_ld_data_corr_m := lsu_rdata_corr_m >> 8.U*io.lsu_addr_m(1,0) lsu_ld_data_corr_m := lsu_rdata_corr_m >> 8.U*io.lsu_addr_m(1,0)
} }
@ -164,12 +172,6 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & !kill_ecc_corr_lo_r val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & !kill_ecc_corr_lo_r
val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & !kill_ecc_corr_hi_r val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & !kill_ecc_corr_hi_r
val lsu_double_ecc_error_r_ff = withClock(io.lsu_free_c2_clk){RegNext(io.lsu_double_ecc_error_r,0.U)}
val ld_single_ecc_error_hi_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_hi_r_ns,0.U)}
val ld_single_ecc_error_lo_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_lo_r_ns,0.U)}
val ld_sec_addr_hi_r_ff = rvdffe(io.end_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
val ld_sec_addr_lo_r_ff = rvdffe(io.lsu_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.bits.load | (io.lsu_pkt_d.bits.store & (!(io.lsu_pkt_d.bits.word | io.lsu_pkt_d.bits.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.bits.load | (io.lsu_pkt_d.bits.store & (!(io.lsu_pkt_d.bits.word | io.lsu_pkt_d.bits.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d
val lsu_dccm_wren_d = io.dma_dccm_wen val lsu_dccm_wren_d = io.dma_dccm_wen
@ -246,7 +248,7 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i).asBool, store_data_pre_lo_r((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo).asBool,io.stbuf_data_any((8*i)+7,(8*i)),Mux((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_lo_r((8*i)+7,8*i)))))))) io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i).asBool, store_data_pre_lo_r((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo).asBool,io.stbuf_data_any((8*i)+7,(8*i)),Mux((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_lo_r((8*i)+7,8*i))))))))
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i+4).asBool,store_data_pre_hi_r((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo).asBool,io.stbuf_data_any((8*i)+7,(8*i)),Mux((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_hi_r((8*i)+7,8*i)))))))) io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i+4).asBool,store_data_pre_hi_r((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo).asBool,io.stbuf_data_any((8*i)+7,(8*i)),Mux((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_hi_r((8*i)+7,8*i))))))))
dccm_wren_Q := withClock(io.lsu_free_c2_clk){RegNext(io.lsu_stbuf_commit_any,0.U)} dccm_wren_Q := withClock(io.lsu_free_c2_clk){RegNext(io.lsu_stbuf_commit_any,0.U)}
dccm_wr_data_Q := rvdffe(io.stbuf_data_any,io.lsu_stbuf_commit_any.asBool,clock,io.scan_mode.asBool) dccm_wr_data_Q := rvdffe(io.stbuf_data_any,(io.lsu_stbuf_commit_any | io.clk_override).asBool,clock,io.scan_mode.asBool)
dccm_wr_bypass_d_m_lo_Q := withClock(io.lsu_free_c2_clk){RegNext(dccm_wr_bypass_d_m_lo,0.U)} dccm_wr_bypass_d_m_lo_Q := withClock(io.lsu_free_c2_clk){RegNext(dccm_wr_bypass_d_m_lo,0.U)}
dccm_wr_bypass_d_m_hi_Q := withClock(io.lsu_free_c2_clk){RegNext(dccm_wr_bypass_d_m_hi,0.U)} dccm_wr_bypass_d_m_hi_Q := withClock(io.lsu_free_c2_clk){RegNext(dccm_wr_bypass_d_m_hi,0.U)}
io.store_data_r := withClock(io.lsu_store_c1_r_clk){RegNext(io.store_data_m,0.U)} io.store_data_r := withClock(io.lsu_store_c1_r_clk){RegNext(io.store_data_m,0.U)}
@ -257,7 +259,7 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
store_data_hi_m := store_data_pre_m(63,32) store_data_hi_m := store_data_pre_m(63,32)
store_data_lo_m := store_data_pre_m(31, 0) store_data_lo_m := store_data_pre_m(31, 0)
io.store_data_lo_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i).asBool, store_data_lo_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_lo_m((8*i)+7,8*i))))))),0.U)} io.store_data_lo_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i).asBool, store_data_lo_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_lo_m((8*i)+7,8*i))))))),0.U)}
io.store_data_hi_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i+4).asBool,store_data_hi_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_hi_m((8*i)+7,8*i))))))),0.U)} io.store_data_hi_r := rvdffe(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i+4).asBool,store_data_hi_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_hi_m((8*i)+7,8*i))))))),((io.ldst_dual_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.store) | io.clk_override),clock,io.scan_mode)
io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_lo_r((8*i)+7,8*i)))))) io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_lo_r((8*i)+7,8*i))))))
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & !store_byteen_ext_r(i+4)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i)))))) io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & !store_byteen_ext_r(i+4)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i))))))
io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i))))) io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i)))))
@ -274,14 +276,25 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
io.lsu_pic.picm_wraddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_dccm_ctl.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0))) io.lsu_pic.picm_wraddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_dccm_ctl.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0)))
io.picm_mask_data_m := picm_rd_data_m(31,0) io.picm_mask_data_m := picm_rd_data_m(31,0)
io.lsu_pic.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_dccm_ctl.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0)) io.lsu_pic.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_dccm_ctl.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0))
if(DCCM_ENABLE){ if(DCCM_ENABLE){
io.lsu_dccm_rden_m := withClock(io.lsu_c2_m_clk){RegNext(lsu_dccm_rden_d,0.U)} io.lsu_dccm_rden_m := withClock(io.lsu_c2_m_clk){RegNext(lsu_dccm_rden_d,0.U)}
io.lsu_dccm_rden_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_dccm_rden_m,0.U)} io.lsu_dccm_rden_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_dccm_rden_m,0.U)}
lsu_double_ecc_error_r_ff := withClock(io.lsu_free_c2_clk){RegNext(io.lsu_double_ecc_error_r,0.U)}
ld_single_ecc_error_hi_r_ff := withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_hi_r_ns,0.U)}
ld_single_ecc_error_lo_r_ff := withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_lo_r_ns,0.U)}
ld_sec_addr_hi_r_ff := rvdffe(io.end_addr_r(DCCM_BITS-1,0),(io.ld_single_ecc_error_r | io.clk_override),clock,io.scan_mode.asBool)
ld_sec_addr_lo_r_ff := rvdffe(io.lsu_addr_r(DCCM_BITS-1,0),(io.ld_single_ecc_error_r | io.clk_override),clock,io.scan_mode.asBool)
} }
else{ else{
io.lsu_dccm_rden_m := 0.U io.lsu_dccm_rden_m := 0.U
io.lsu_dccm_rden_r := 0.U} io.lsu_dccm_rden_r := 0.U
lsu_double_ecc_error_r_ff := 0.U
ld_single_ecc_error_hi_r_ff := 0.U
ld_single_ecc_error_lo_r_ff := 0.U
ld_sec_addr_hi_r_ff := 0.U
ld_sec_addr_lo_r_ff := 0.U
}
} }

14
src/main/scala/lsu/lsu_ecc.scala
View File

@ -10,6 +10,7 @@ class lsu_ecc extends Module with lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
val lsu_c2_r_clk = Input(Clock()) val lsu_c2_r_clk = Input(Clock())
val clk_override = Input(Bool())
val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t)) val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t))
val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t)) val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t))
val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W)) val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W))
@ -102,7 +103,7 @@ class lsu_ecc extends Module with lib with RequireAsyncReset {
ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2) ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2)
is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.load | io.lsu_pkt_r.bits.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.load | io.lsu_pkt_r.bits.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r
is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable
is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.bits.dma) & !io.dec_tlu_core_ecc_disable is_ldst_hi_r := is_ldst_r & ldst_dual_r & !io.dec_tlu_core_ecc_disable
is_ldst_hi_any := is_ldst_hi_r is_ldst_hi_any := is_ldst_hi_r
dccm_rdata_hi_any := io.dccm_rdata_hi_r dccm_rdata_hi_any := io.dccm_rdata_hi_r
dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r
@ -140,19 +141,18 @@ class lsu_ecc extends Module with lib with RequireAsyncReset {
withClock(io.lsu_c2_r_clk) {io.lsu_double_ecc_error_r := RegNext(io.lsu_double_ecc_error_m,0.U)} withClock(io.lsu_c2_r_clk) {io.lsu_double_ecc_error_r := RegNext(io.lsu_double_ecc_error_m,0.U)}
withClock(io.lsu_c2_r_clk) {io.single_ecc_error_lo_r := RegNext(single_ecc_error_lo_any,0.U)} withClock(io.lsu_c2_r_clk) {io.single_ecc_error_lo_r := RegNext(single_ecc_error_lo_any,0.U)}
withClock(io.lsu_c2_r_clk) {io.single_ecc_error_hi_r := RegNext(single_ecc_error_hi_any,0.U)} withClock(io.lsu_c2_r_clk) {io.single_ecc_error_hi_r := RegNext(single_ecc_error_hi_any,0.U)}
withClock(io.lsu_c2_r_clk) {io.sec_data_hi_r := RegNext(io.sec_data_hi_m,0.U)} io.sec_data_hi_r := rvdffe(io.sec_data_hi_m,io.lsu_single_ecc_error_m | io.clk_override,clock,io.scan_mode)
withClock(io.lsu_c2_r_clk) {io.sec_data_lo_r := RegNext(io.sec_data_lo_m,0.U)} io.sec_data_lo_r := rvdffe(io.sec_data_lo_m,io.lsu_single_ecc_error_m | io.clk_override,clock,io.scan_mode)
} }
// Logic for ECC generation during write // Logic for ECC generation during write
dccm_wdata_lo_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_lo_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_lo, io.stbuf_data_any)) dccm_wdata_lo_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_lo_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_lo, io.stbuf_data_any))
dccm_wdata_hi_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_hi_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_hi, io.stbuf_data_any)) dccm_wdata_hi_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_hi_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_hi, 0.U))
io.sec_data_ecc_hi_r_ff := dccm_wdata_ecc_hi_any io.sec_data_ecc_hi_r_ff := dccm_wdata_ecc_hi_any
io.sec_data_ecc_lo_r_ff := dccm_wdata_ecc_lo_any io.sec_data_ecc_lo_r_ff := dccm_wdata_ecc_lo_any
io.stbuf_ecc_any := dccm_wdata_ecc_lo_any io.stbuf_ecc_any := dccm_wdata_ecc_lo_any
io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any
io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any
io.sec_data_hi_r_ff := rvdffe(io.sec_data_hi_r, io.ld_single_ecc_error_r,clock,io.scan_mode) io.sec_data_hi_r_ff := rvdffe(io.sec_data_hi_r, io.ld_single_ecc_error_r| io.clk_override,clock,io.scan_mode)
io.sec_data_lo_r_ff := rvdffe(io.sec_data_lo_r, io.ld_single_ecc_error_r,clock,io.scan_mode) io.sec_data_lo_r_ff := rvdffe(io.sec_data_lo_r, io.ld_single_ecc_error_r| io.clk_override,clock,io.scan_mode)
} }

24
src/main/scala/lsu/lsu_lsc_ctl.scala
View File

@ -10,6 +10,7 @@ import chisel3.experimental.chiselName
class lsu_lsc_ctl extends Module with RequireAsyncReset with lib class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
{ {
val io = IO(new Bundle{ val io = IO(new Bundle{
val clk_override = Input(Bool())
val lsu_c1_m_clk = Input(Clock()) val lsu_c1_m_clk = Input(Clock())
val lsu_c1_r_clk = Input(Clock()) val lsu_c1_r_clk = Input(Clock())
val lsu_c2_m_clk = Input(Clock()) val lsu_c2_m_clk = Input(Clock())
@ -27,6 +28,9 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val flush_m_up = Input(UInt(1.W)) val flush_m_up = Input(UInt(1.W))
val flush_r = Input(UInt(1.W)) val flush_r = Input(UInt(1.W))
val ldst_dual_d = Input(UInt(1.W))
val ldst_dual_m = Input(UInt(1.W))
val ldst_dual_r = Input(UInt(1.W))
val lsu_exu = new lsu_exu() val lsu_exu = new lsu_exu()
@ -86,7 +90,8 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val scan_mode = Input(UInt(1.W)) val scan_mode = Input(UInt(1.W))
}) })
val end_addr_pre_m =WireInit(0.U(29.W))
val end_addr_pre_r =WireInit(0.U(29.W))
val dma_pkt_d = Wire(Valid(new lsu_pkt_t())) val dma_pkt_d = Wire(Valid(new lsu_pkt_t()))
val lsu_pkt_m_in = Wire(Valid(new lsu_pkt_t())) val lsu_pkt_m_in = Wire(Valid(new lsu_pkt_t()))
val lsu_pkt_r_in = Wire(Valid(new lsu_pkt_t())) val lsu_pkt_r_in = Wire(Valid(new lsu_pkt_t()))
@ -177,8 +182,10 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
lsu_error_pkt_m.bits.mscause := Mux(((io.lsu_double_ecc_error_m & !misaligned_fault_m & !access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0)) lsu_error_pkt_m.bits.mscause := Mux(((io.lsu_double_ecc_error_m & !misaligned_fault_m & !access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0))
lsu_error_pkt_m.bits.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr lsu_error_pkt_m.bits.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr
lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,3.U(2.W), Mux(fir_dccm_access_error_m.asBool,2.U(2.W), Mux((io.lsu_pkt_m.bits.fast_int & io.lsu_double_ecc_error_m).asBool,1.U(2.W),0.U(2.W)))) lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,3.U(2.W), Mux(fir_dccm_access_error_m.asBool,2.U(2.W), Mux((io.lsu_pkt_m.bits.fast_int & io.lsu_double_ecc_error_m).asBool,1.U(2.W),0.U(2.W))))
io.lsu_error_pkt_r := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m,0.U.asTypeOf(lsu_error_pkt_m.cloneType))} io.lsu_error_pkt_r := rvdffe(lsu_error_pkt_m,(lsu_error_pkt_m.valid | lsu_error_pkt_m.bits.single_ecc_error | io.clk_override),clock,io.scan_mode)
io.lsu_fir_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_fir_error_m,0.U)} io.lsu_error_pkt_r.bits.single_ecc_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m.bits.single_ecc_error, 0.U)}
io.lsu_error_pkt_r.valid := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m.valid, 0.U)}
io.lsu_fir_error := RegNext(lsu_fir_error_m,0.U)
} }
dma_pkt_d.bits.unsign := 0.U dma_pkt_d.bits.unsign := 0.U
dma_pkt_d.bits.fast_int := 0.U dma_pkt_d.bits.fast_int := 0.U
@ -218,6 +225,14 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)} val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)})
io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_m(2,0),0.U)})
end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode)
end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode)
io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)} io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)}
io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)} io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)}
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
@ -226,7 +241,8 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)} io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)}
io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)} io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)}
val addr_external_r = withClock(io.lsu_c1_r_clk){RegNext(io.addr_external_m,0.U)} val addr_external_r = withClock(io.lsu_c1_r_clk){RegNext(io.addr_external_m,0.U)}
val bus_read_data_r = withClock(io.lsu_c1_r_clk){RegNext(io.bus_read_data_m,0.U)} val bus_read_data_r = rvdffe(io.bus_read_data_m,io.addr_external_m | io.clk_override,clock,io.scan_mode)
// Fast interrupt address // Fast interrupt address
io.lsu_fir_addr := io.lsu_ld_data_corr_r(31,1) //original (31,1) TBD io.lsu_fir_addr := io.lsu_ld_data_corr_r(31,1) //original (31,1) TBD
// absence load/store all 0's // absence load/store all 0's

50
src/main/scala/lsu/lsu_stbuf.scala
View File

@ -8,8 +8,6 @@ import include._
@chiselName @chiselName
class lsu_stbuf extends Module with lib with RequireAsyncReset { class lsu_stbuf extends Module with lib with RequireAsyncReset {
val io = IO (new Bundle { val io = IO (new Bundle {
val lsu_c1_m_clk = Input(Clock())
val lsu_c1_r_clk = Input(Clock())
val lsu_stbuf_c1_clk = Input(Clock()) val lsu_stbuf_c1_clk = Input(Clock())
val lsu_free_c2_clk = Input(Clock()) val lsu_free_c2_clk = Input(Clock())
val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t)) val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t))
@ -28,7 +26,9 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
val end_addr_d = Input(UInt(LSU_SB_BITS.W)) val end_addr_d = Input(UInt(LSU_SB_BITS.W))
val end_addr_m = Input(UInt(32.W)) val end_addr_m = Input(UInt(32.W))
val end_addr_r = Input(UInt(32.W)) val end_addr_r = Input(UInt(32.W))
val ldst_dual_d = Input(Bool())
val ldst_dual_m = Input(Bool())
val ldst_dual_r = Input(Bool())
val addr_in_dccm_m = Input(Bool()) val addr_in_dccm_m = Input(Bool())
val addr_in_dccm_r = Input(Bool()) val addr_in_dccm_r = Input(Bool())
val lsu_cmpen_m = Input(Bool()) val lsu_cmpen_m = Input(Bool())
@ -81,8 +81,6 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => 0.U) stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val WrPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U) val WrPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U)
val RdPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U) val RdPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U)
val ldst_dual_m = WireInit(Bool(),init = 0.U)
val ldst_dual_r = WireInit(Bool(),init = 0.U)
val cmpaddr_hi_m = WireInit(0.U(16.W)) val cmpaddr_hi_m = WireInit(0.U(16.W))
val stbuf_specvld_m = WireInit(0.U(2.W)) val stbuf_specvld_m = WireInit(0.U(2.W))
val stbuf_specvld_r = WireInit(0.U(2.W)) val stbuf_specvld_r = WireInit(0.U(2.W))
@ -114,8 +112,7 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
io.lsu_pkt_r.bits.word.asBool -> "b00001111".U, io.lsu_pkt_r.bits.word.asBool -> "b00001111".U,
io.lsu_pkt_r.bits.dword.asBool -> "b11111111".U io.lsu_pkt_r.bits.dword.asBool -> "b11111111".U
)) ))
val ldst_dual_d = io.lsu_addr_d (2) =/= io.end_addr_d(2) val dual_stbuf_write_r = io.ldst_dual_r & io.store_stbuf_reqvld_r
val dual_stbuf_write_r = ldst_dual_r & io.store_stbuf_reqvld_r
store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0) store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0)
val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_r.bits.store) val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_r.bits.store)
@ -125,21 +122,21 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
val WrPtrPlus1 = WrPtr + "b01".U val WrPtrPlus1 = WrPtr + "b01".U
val WrPtrPlus2 = WrPtr + "b10".U val WrPtrPlus2 = WrPtr + "b10".U
io.ldst_stbuf_reqvld_r := io.lsu_commit_r & io.store_stbuf_reqvld_r io.ldst_stbuf_reqvld_r := (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & io.store_stbuf_reqvld_r
val store_matchvec_lo_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.lsu_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_)) val store_matchvec_lo_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.lsu_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_))
val store_matchvec_hi_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.end_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & dual_stbuf_write_r & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_)) val store_matchvec_hi_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.end_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & dual_stbuf_write_r & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_))
val store_coalesce_lo_r = store_matchvec_lo_r.orR val store_coalesce_lo_r = store_matchvec_lo_r.orR
val store_coalesce_hi_r = store_matchvec_hi_r.orR val store_coalesce_hi_r = store_matchvec_hi_r.orR
if (DCCM_ENABLE == 1) {
stbuf_wr_en := (0 until LSU_STBUF_DEPTH).map(i => (io.ldst_stbuf_reqvld_r & ( stbuf_wr_en := (0 until LSU_STBUF_DEPTH).map(i => (io.ldst_stbuf_reqvld_r & (
((i.asUInt === WrPtr) & !store_coalesce_lo_r) | ((i.asUInt === WrPtr) & !store_coalesce_lo_r) |
((i.asUInt === WrPtr) & dual_stbuf_write_r & !store_coalesce_hi_r) | ((i.asUInt === WrPtr) & dual_stbuf_write_r & !store_coalesce_hi_r) |
((i.asUInt === WrPtrPlus1) & dual_stbuf_write_r & !(store_coalesce_lo_r | store_coalesce_hi_r)) | ((i.asUInt === WrPtrPlus1) & dual_stbuf_write_r & !(store_coalesce_lo_r | store_coalesce_hi_r)) |
store_matchvec_lo_r(i) | store_matchvec_hi_r(i))).asUInt).reverse.reduce(Cat(_, _)) store_matchvec_lo_r(i) | store_matchvec_hi_r(i))).asUInt).reverse.reduce(Cat(_, _))
stbuf_reset := (0 until LSU_STBUF_DEPTH).map(i => ((io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any) & (i.asUInt === RdPtr).asBool).asUInt).reverse.reduce(Cat(_, _)) stbuf_reset := (0 until LSU_STBUF_DEPTH).map(i => ((io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any) & (i.asUInt === RdPtr).asBool).asUInt).reverse.reduce(Cat(_, _))
val sel_lo = (0 until LSU_STBUF_DEPTH).map(i=> (((!ldst_dual_r | io.store_stbuf_reqvld_r) & (i.asUInt === WrPtr).asBool & !store_coalesce_lo_r) | store_matchvec_lo_r(i)).asUInt).reverse.reduce(Cat(_,_)) val sel_lo = (0 until LSU_STBUF_DEPTH).map(i => (((!io.ldst_dual_r | io.store_stbuf_reqvld_r) & (i.asUInt === WrPtr).asBool & !store_coalesce_lo_r) | store_matchvec_lo_r(i)).asUInt).reverse.reduce(Cat(_, _))
stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i => Mux(sel_lo(i), io.lsu_addr_r(LSU_SB_BITS - 1, 0), io.end_addr_r(LSU_SB_BITS - 1, 0))) stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i => Mux(sel_lo(i), io.lsu_addr_r(LSU_SB_BITS - 1, 0), io.end_addr_r(LSU_SB_BITS - 1, 0)))
stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => Mux(sel_lo(i), stbuf_byteen(i) | store_byteen_lo_r, stbuf_byteen(i) | store_byteen_hi_r).asUInt) stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => Mux(sel_lo(i), stbuf_byteen(i) | store_byteen_lo_r, stbuf_byteen(i) | store_byteen_hi_r).asUInt)
@ -159,16 +156,28 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i => Cat(datain4(i), datain3(i), datain2(i), datain1(i))) stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i => Cat(datain4(i), datain3(i), datain2(i), datain1(i)))
stbuf_vld := (0 until LSU_STBUF_DEPTH).map(i => withClock(io.lsu_free_c2_clk) {
stbuf_vld := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),1.U ,stbuf_vld(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) RegNext(Mux(stbuf_wr_en(i).asBool(), 1.U, stbuf_vld(i)) & !stbuf_reset(i), 0.U)
stbuf_dma_kill := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){RegNext(Mux(stbuf_dma_kill_en(i).asBool,1.U ,stbuf_dma_kill(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) }).reverse.reduce(Cat(_, _))
stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_stbuf_c1_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),stbuf_byteenin(i) , stbuf_byteen(i)) & Fill(stbuf_byteenin(i).getWidth , !stbuf_reset(i)), 0.U)}) stbuf_dma_kill := (0 until LSU_STBUF_DEPTH).map(i => withClock(io.lsu_free_c2_clk) {
RegNext(Mux(stbuf_dma_kill_en(i).asBool, 1.U, stbuf_dma_kill(i)) & !stbuf_reset(i), 0.U)
}).reverse.reduce(Cat(_, _))
stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i => withClock(io.lsu_stbuf_c1_clk) {
RegNext(Mux(stbuf_wr_en(i).asBool(), stbuf_byteenin(i), stbuf_byteen(i)) & Fill(stbuf_byteenin(i).getWidth, !stbuf_reset(i)), 0.U)
})
for (i <- 0 until LSU_STBUF_DEPTH) { for (i <- 0 until LSU_STBUF_DEPTH) {
stbuf_addr(i) := rvdffe(stbuf_addrin(i), stbuf_wr_en(i).asBool(), clock, io.scan_mode) stbuf_addr(i) := rvdffe(stbuf_addrin(i), stbuf_wr_en(i).asBool(), clock, io.scan_mode)
stbuf_data(i) := rvdffe(stbuf_datain(i), stbuf_wr_en(i).asBool(), clock, io.scan_mode) stbuf_data(i) := rvdffe(stbuf_datain(i), stbuf_wr_en(i).asBool(), clock, io.scan_mode)
} }
withClock(io.lsu_c1_m_clk){ldst_dual_m := RegNext(ldst_dual_d,0.U)} } else {
withClock(io.lsu_c1_r_clk){ldst_dual_r := RegNext(ldst_dual_m,0.U)} stbuf_wr_en := 0.U
stbuf_reset := 0.U
stbuf_vld := 0.U
stbuf_dma_kill := 0.U
stbuf_addr := 0.U
stbuf_byteen := 0.U
stbuf_data := 0.U
}
// Store Buffer drain logic // Store Buffer drain logic
io.stbuf_reqvld_flushed_any := stbuf_vld(RdPtr) & stbuf_dma_kill(RdPtr) io.stbuf_reqvld_flushed_any := stbuf_vld(RdPtr) & stbuf_dma_kill(RdPtr)
@ -189,17 +198,14 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.store & io.addr_in_dccm_m & !io.lsu_pkt_m.bits.dma val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.store & io.addr_in_dccm_m & !io.lsu_pkt_m.bits.dma
val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.addr_in_dccm_r & !io.lsu_pkt_r.bits.dma val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.addr_in_dccm_r & !io.lsu_pkt_r.bits.dma
stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & ldst_dual_m) stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & io.ldst_dual_m)
stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & ldst_dual_r) stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & io.ldst_dual_r)
val stbuf_specvld_any = stbuf_numvld_any + Cat(0.U(2.W), stbuf_specvld_m) + Cat(0.U(2.W), stbuf_specvld_r) val stbuf_specvld_any = stbuf_numvld_any + Cat(0.U(2.W), stbuf_specvld_m) + Cat(0.U(2.W), stbuf_specvld_r)
io.lsu_stbuf_full_any := Mux((!ldst_dual_d & io.dec_lsu_valid_raw_d).asBool,(stbuf_specvld_any >= LSU_STBUF_DEPTH.U),(stbuf_specvld_any >= (LSU_STBUF_DEPTH-1).U)) io.lsu_stbuf_full_any := Mux((!io.ldst_dual_d & io.dec_lsu_valid_raw_d).asBool,(stbuf_specvld_any >= LSU_STBUF_DEPTH.U),(stbuf_specvld_any >= (LSU_STBUF_DEPTH-1).U))
io.lsu_stbuf_empty_any := stbuf_numvld_any === 0.U io.lsu_stbuf_empty_any := stbuf_numvld_any === 0.U
val cmpen_hi_m = io.lsu_cmpen_m & ldst_dual_m
cmpaddr_hi_m := io.end_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) cmpaddr_hi_m := io.end_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH))
val cmpen_lo_m = io.lsu_cmpen_m
cmpaddr_lo_m := io.lsu_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) cmpaddr_lo_m := io.lsu_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH))

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src/main/scala/lsu/lsu_trigger.scala
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@ -12,10 +12,12 @@ class lsu_trigger extends Module with RequireAsyncReset with lib {
val lsu_trigger_match_m = Output(UInt(4.W)) val lsu_trigger_match_m = Output(UInt(4.W))
}) })
val trigger_enable = WireInit(0.U(1.W))
trigger_enable := (0 until 4).map(i=>io.trigger_pkt_any(i).m).reduce(_|_)
val store_data_trigger_m= Cat((Fill(16,io.lsu_pkt_m.bits.word) & io.store_data_m(31,16)),(Fill(8,(io.lsu_pkt_m.bits.half | io.lsu_pkt_m.bits.word)) & io.store_data_m(15,8)), io.store_data_m(7,0)) val store_data_trigger_m= Cat((Fill(16,io.lsu_pkt_m.bits.word) & io.store_data_m(31,16)),(Fill(8,(io.lsu_pkt_m.bits.half | io.lsu_pkt_m.bits.word)) & io.store_data_m(15,8)), io.store_data_m(7,0))
val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m))) val ldst_addr_trigger_m = io.lsu_addr_m & Fill(32, trigger_enable)
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)| val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool-> ldst_addr_trigger_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m)))
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & trigger_enable & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)|
(io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )& (io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )&
rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_)) rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_))
} }

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