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Core with Bundles

This commit is contained in:
​Laraib Khan 2020-12-09 09:34:03 +05:00
parent d48d2bb461
commit b9c70b1fb5
748 changed files with 128180 additions and 682630 deletions
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18
EL2_IC_DATA.anno.json
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@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"EL2_IC_DATA"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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EL2_IC_DATA.fir
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit EL2_IC_DATA :
module EL2_IC_DATA :
input clock : Clock
input reset : UInt<1>
output io : {flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<15>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip mask : UInt<1>[2][2]}
smem ic_memory : UInt<26>[2][2][512], undefined @[el2_ifu_ic_mem.scala 209:30]
wire data : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 210:48]
data[0][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
data[0][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
data[1][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
data[1][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
wire mem_mask : UInt<1>[2] @[el2_ifu_ic_mem.scala 211:51]
mem_mask[0] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
mem_mask[1] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
wire mem_mask2 : UInt<1>[2][2] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[0][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[0][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[1][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[1][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 214:23]
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 215:17]
io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 216:16]
io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 217:16]

34
EL2_IC_DATA.v
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module EL2_IC_DATA(
input clock,
input reset,
input io_rst_l,
input io_clk_override,
input [11:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input io_ic_rd_en,
input [70:0] io_ic_wr_data_0,
input [70:0] io_ic_wr_data_1,
output [63:0] io_ic_rd_data,
input [70:0] io_ic_debug_wr_data,
output [70:0] io_ic_debug_rd_data,
output [1:0] io_ic_parerr,
output [1:0] io_ic_eccerr,
input [14:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
input [63:0] io_ic_premux_data,
input io_ic_sel_premux_data,
input [1:0] io_ic_rd_hit,
input io_scan_mode,
input io_mask_0_0,
input io_mask_0_1,
input io_mask_1_0,
input io_mask_1_1
);
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17]
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16]
endmodule

93
EL2_IC_TAG.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"EL2_IC_TAG"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2156
EL2_IC_TAG.fir
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384
EL2_IC_TAG.v
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module rvecc_decode(
input [31:0] io_din,
input [6:0] io_ecc_in,
output [6:0] io_ecc_out,
output [31:0] io_dout,
output io_single_ecc_error
);
wire w0_0 = io_din[0]; // @[beh_lib.scala 239:37]
wire w0_1 = io_din[1]; // @[beh_lib.scala 239:37]
wire w1_1 = io_din[2]; // @[beh_lib.scala 240:37]
wire w0_2 = io_din[3]; // @[beh_lib.scala 239:37]
wire w0_3 = io_din[4]; // @[beh_lib.scala 239:37]
wire w1_3 = io_din[5]; // @[beh_lib.scala 240:37]
wire w0_4 = io_din[6]; // @[beh_lib.scala 239:37]
wire w2_3 = io_din[7]; // @[beh_lib.scala 241:37]
wire w0_5 = io_din[8]; // @[beh_lib.scala 239:37]
wire w1_5 = io_din[9]; // @[beh_lib.scala 240:37]
wire w0_6 = io_din[10]; // @[beh_lib.scala 239:37]
wire w0_7 = io_din[11]; // @[beh_lib.scala 239:37]
wire w1_7 = io_din[12]; // @[beh_lib.scala 240:37]
wire w0_8 = io_din[13]; // @[beh_lib.scala 239:37]
wire w2_7 = io_din[14]; // @[beh_lib.scala 241:37]
wire w0_9 = io_din[15]; // @[beh_lib.scala 239:37]
wire w1_9 = io_din[16]; // @[beh_lib.scala 240:37]
wire w0_10 = io_din[17]; // @[beh_lib.scala 239:37]
wire w3_7 = io_din[18]; // @[beh_lib.scala 242:37]
wire w0_11 = io_din[19]; // @[beh_lib.scala 239:37]
wire w1_11 = io_din[20]; // @[beh_lib.scala 240:37]
wire w0_12 = io_din[21]; // @[beh_lib.scala 239:37]
wire w2_11 = io_din[22]; // @[beh_lib.scala 241:37]
wire w0_13 = io_din[23]; // @[beh_lib.scala 239:37]
wire w1_13 = io_din[24]; // @[beh_lib.scala 240:37]
wire w0_14 = io_din[25]; // @[beh_lib.scala 239:37]
wire w0_15 = io_din[26]; // @[beh_lib.scala 239:37]
wire w1_15 = io_din[27]; // @[beh_lib.scala 240:37]
wire w0_16 = io_din[28]; // @[beh_lib.scala 239:37]
wire w2_15 = io_din[29]; // @[beh_lib.scala 241:37]
wire w0_17 = io_din[30]; // @[beh_lib.scala 239:37]
wire w1_17 = io_din[31]; // @[beh_lib.scala 240:37]
wire [5:0] _T_100 = {w1_17,w0_17,w2_15,w0_16,w1_15,w0_15}; // @[beh_lib.scala 247:86]
wire _T_101 = ^_T_100; // @[beh_lib.scala 247:93]
wire _T_102 = io_ecc_in[5] ^ _T_101; // @[beh_lib.scala 247:81]
wire [6:0] _T_109 = {w0_10,w1_9,w0_9,w2_7,w0_8,w1_7,w0_7}; // @[beh_lib.scala 247:116]
wire [14:0] _T_117 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_109}; // @[beh_lib.scala 247:116]
wire _T_118 = ^_T_117; // @[beh_lib.scala 247:123]
wire _T_119 = io_ecc_in[4] ^ _T_118; // @[beh_lib.scala 247:111]
wire [6:0] _T_126 = {w0_6,w1_5,w0_5,w2_3,w0_4,w1_3,w0_3}; // @[beh_lib.scala 247:146]
wire [14:0] _T_134 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_126}; // @[beh_lib.scala 247:146]
wire _T_135 = ^_T_134; // @[beh_lib.scala 247:153]
wire _T_136 = io_ecc_in[3] ^ _T_135; // @[beh_lib.scala 247:141]
wire [8:0] _T_145 = {w0_9,w2_7,w0_6,w1_5,w0_5,w2_3,w0_2,w1_1,w0_1}; // @[beh_lib.scala 247:176]
wire [17:0] _T_154 = {w1_17,w0_17,w2_15,w0_14,w1_13,w0_13,w2_11,w0_10,w1_9,_T_145}; // @[beh_lib.scala 247:176]
wire _T_155 = ^_T_154; // @[beh_lib.scala 247:183]
wire _T_156 = io_ecc_in[2] ^ _T_155; // @[beh_lib.scala 247:171]
wire [8:0] _T_165 = {w0_8,w1_7,w0_6,w1_5,w0_4,w1_3,w0_2,w1_1,w0_0}; // @[beh_lib.scala 247:206]
wire [17:0] _T_174 = {w1_17,w0_16,w1_15,w0_14,w1_13,w0_12,w1_11,w0_10,w1_9,_T_165}; // @[beh_lib.scala 247:206]
wire _T_175 = ^_T_174; // @[beh_lib.scala 247:213]
wire _T_176 = io_ecc_in[1] ^ _T_175; // @[beh_lib.scala 247:201]
wire [8:0] _T_185 = {w0_8,w0_7,w0_6,w0_5,w0_4,w0_3,w0_2,w0_1,w0_0}; // @[beh_lib.scala 247:236]
wire [17:0] _T_194 = {w0_17,w0_16,w0_15,w0_14,w0_13,w0_12,w0_11,w0_10,w0_9,_T_185}; // @[beh_lib.scala 247:236]
wire _T_195 = ^_T_194; // @[beh_lib.scala 247:243]
wire _T_196 = io_ecc_in[0] ^ _T_195; // @[beh_lib.scala 247:231]
wire [6:0] ecc_check = {1'h0,_T_102,_T_119,_T_136,_T_156,_T_176,_T_196}; // @[Cat.scala 29:58]
wire error_mask_0 = ecc_check[5:0] == 6'h1; // @[beh_lib.scala 255:39]
wire error_mask_1 = ecc_check[5:0] == 6'h2; // @[beh_lib.scala 255:39]
wire error_mask_2 = ecc_check[5:0] == 6'h3; // @[beh_lib.scala 255:39]
wire error_mask_3 = ecc_check[5:0] == 6'h4; // @[beh_lib.scala 255:39]
wire error_mask_4 = ecc_check[5:0] == 6'h5; // @[beh_lib.scala 255:39]
wire error_mask_5 = ecc_check[5:0] == 6'h6; // @[beh_lib.scala 255:39]
wire error_mask_6 = ecc_check[5:0] == 6'h7; // @[beh_lib.scala 255:39]
wire error_mask_7 = ecc_check[5:0] == 6'h8; // @[beh_lib.scala 255:39]
wire error_mask_8 = ecc_check[5:0] == 6'h9; // @[beh_lib.scala 255:39]
wire error_mask_9 = ecc_check[5:0] == 6'ha; // @[beh_lib.scala 255:39]
wire error_mask_10 = ecc_check[5:0] == 6'hb; // @[beh_lib.scala 255:39]
wire error_mask_11 = ecc_check[5:0] == 6'hc; // @[beh_lib.scala 255:39]
wire error_mask_12 = ecc_check[5:0] == 6'hd; // @[beh_lib.scala 255:39]
wire error_mask_13 = ecc_check[5:0] == 6'he; // @[beh_lib.scala 255:39]
wire error_mask_14 = ecc_check[5:0] == 6'hf; // @[beh_lib.scala 255:39]
wire error_mask_15 = ecc_check[5:0] == 6'h10; // @[beh_lib.scala 255:39]
wire error_mask_16 = ecc_check[5:0] == 6'h11; // @[beh_lib.scala 255:39]
wire error_mask_17 = ecc_check[5:0] == 6'h12; // @[beh_lib.scala 255:39]
wire error_mask_18 = ecc_check[5:0] == 6'h13; // @[beh_lib.scala 255:39]
wire error_mask_19 = ecc_check[5:0] == 6'h14; // @[beh_lib.scala 255:39]
wire error_mask_20 = ecc_check[5:0] == 6'h15; // @[beh_lib.scala 255:39]
wire error_mask_21 = ecc_check[5:0] == 6'h16; // @[beh_lib.scala 255:39]
wire error_mask_22 = ecc_check[5:0] == 6'h17; // @[beh_lib.scala 255:39]
wire error_mask_23 = ecc_check[5:0] == 6'h18; // @[beh_lib.scala 255:39]
wire error_mask_24 = ecc_check[5:0] == 6'h19; // @[beh_lib.scala 255:39]
wire error_mask_25 = ecc_check[5:0] == 6'h1a; // @[beh_lib.scala 255:39]
wire error_mask_26 = ecc_check[5:0] == 6'h1b; // @[beh_lib.scala 255:39]
wire error_mask_27 = ecc_check[5:0] == 6'h1c; // @[beh_lib.scala 255:39]
wire error_mask_28 = ecc_check[5:0] == 6'h1d; // @[beh_lib.scala 255:39]
wire error_mask_29 = ecc_check[5:0] == 6'h1e; // @[beh_lib.scala 255:39]
wire error_mask_30 = ecc_check[5:0] == 6'h1f; // @[beh_lib.scala 255:39]
wire error_mask_31 = ecc_check[5:0] == 6'h20; // @[beh_lib.scala 255:39]
wire error_mask_32 = ecc_check[5:0] == 6'h21; // @[beh_lib.scala 255:39]
wire error_mask_33 = ecc_check[5:0] == 6'h22; // @[beh_lib.scala 255:39]
wire error_mask_34 = ecc_check[5:0] == 6'h23; // @[beh_lib.scala 255:39]
wire error_mask_35 = ecc_check[5:0] == 6'h24; // @[beh_lib.scala 255:39]
wire error_mask_36 = ecc_check[5:0] == 6'h25; // @[beh_lib.scala 255:39]
wire error_mask_37 = ecc_check[5:0] == 6'h26; // @[beh_lib.scala 255:39]
wire error_mask_38 = ecc_check[5:0] == 6'h27; // @[beh_lib.scala 255:39]
wire [7:0] _T_310 = {io_ecc_in[3],io_din[3:1],io_ecc_in[2],w0_0,io_ecc_in[1:0]}; // @[Cat.scala 29:58]
wire [38:0] din_plus_parity = {io_ecc_in[6],io_din[31:26],io_ecc_in[5],io_din[25:11],io_ecc_in[4],io_din[10:4],_T_310}; // @[Cat.scala 29:58]
wire [9:0] _T_333 = {error_mask_18,error_mask_17,error_mask_16,error_mask_15,error_mask_14,error_mask_13,error_mask_12,error_mask_11,error_mask_10,error_mask_9}; // @[beh_lib.scala 258:70]
wire [18:0] _T_334 = {_T_333,error_mask_8,error_mask_7,error_mask_6,error_mask_5,error_mask_4,error_mask_3,error_mask_2,error_mask_1,error_mask_0}; // @[beh_lib.scala 258:70]
wire [9:0] _T_343 = {error_mask_28,error_mask_27,error_mask_26,error_mask_25,error_mask_24,error_mask_23,error_mask_22,error_mask_21,error_mask_20,error_mask_19}; // @[beh_lib.scala 258:70]
wire [9:0] _T_352 = {error_mask_38,error_mask_37,error_mask_36,error_mask_35,error_mask_34,error_mask_33,error_mask_32,error_mask_31,error_mask_30,error_mask_29}; // @[beh_lib.scala 258:70]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[beh_lib.scala 258:70]
wire [38:0] _T_355 = _T_354 ^ din_plus_parity; // @[beh_lib.scala 258:77]
wire [38:0] dout_plus_parity = io_single_ecc_error ? _T_355 : din_plus_parity; // @[beh_lib.scala 258:29]
wire [3:0] _T_361 = {dout_plus_parity[6:4],dout_plus_parity[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_363 = {dout_plus_parity[37:32],dout_plus_parity[30:16],dout_plus_parity[14:8]}; // @[Cat.scala 29:58]
wire _T_367 = ecc_check == 7'h40; // @[beh_lib.scala 261:60]
wire _T_368 = dout_plus_parity[38] ^ _T_367; // @[beh_lib.scala 261:42]
wire [3:0] _T_375 = {dout_plus_parity[7],dout_plus_parity[3],dout_plus_parity[1:0]}; // @[Cat.scala 29:58]
wire [2:0] _T_377 = {_T_368,dout_plus_parity[31],dout_plus_parity[15]}; // @[Cat.scala 29:58]
assign io_ecc_out = {_T_377,_T_375}; // @[beh_lib.scala 248:14 beh_lib.scala 261:14]
assign io_dout = {_T_363,_T_361}; // @[beh_lib.scala 260:11]
assign io_single_ecc_error = 1'h0; // @[beh_lib.scala 250:23]
endmodule
module EL2_IC_TAG(
input clock,
input reset,
input io_clk,
input io_rst_l,
input io_clk_override,
input io_dec_tlu_core_ecc_disable,
input [31:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input [1:0] io_ic_tag_valid,
input io_ic_rd_en,
input [12:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
output [25:0] io_ictag_debug_rd_data,
input [70:0] io_ic_debug_wr_data,
output [1:0] io_ic_rd_hit,
output io_ic_tag_perr,
input io_scan_mode,
output [25:0] io_test,
output [31:0] io_test_ecc_data_out_0,
output [31:0] io_test_ecc_data_out_1,
output [6:0] io_test_ecc_out_0,
output [6:0] io_test_ecc_out_1,
output io_test_ecc_sb_out_0,
output io_test_ecc_sb_out_1,
output io_test_ecc_db_out_0,
output io_test_ecc_db_out_1
);
`ifdef RANDOMIZE_MEM_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_1;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
reg [25:0] ic_way_tag_0 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_0_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_0__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_0__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_0__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
reg [6:0] ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
reg [25:0] ic_way_tag_1 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_1_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_1__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_1__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_1__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
reg [6:0] ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
wire [31:0] rvecc_decode_io_din; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
wire [31:0] rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
wire rvecc_decode_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
wire [31:0] rvecc_decode_1_io_din; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_1_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
wire [31:0] rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
wire rvecc_decode_1_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
wire _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 73:93]
wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
wire [1:0] ic_tag_wren = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 73:33]
wire _T_5 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 75:68]
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_rd_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 75:93]
wire _T_8 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 76:68]
wire [1:0] _T_10 = {_T_8,_T_8}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_wr_way_en = _T_10 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 76:93]
wire _T_11 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 77:55]
wire [1:0] _T_13 = {_T_11,_T_11}; // @[Cat.scala 29:58]
wire [1:0] _T_14 = _T_13 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 77:74]
wire [1:0] _T_15 = _T_14 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 77:88]
wire [1:0] ic_tag_clken = _T_15 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 77:109]
reg [31:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 80:30]
wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
wire [31:0] _T_30 = {13'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
wire [8:0] _T_134 = {_T_30[16],_T_30[14],_T_30[12],_T_30[10],_T_30[8],_T_30[6],_T_30[5],_T_30[3],_T_30[1]}; // @[el2_lib.scala 211:22]
wire [17:0] _T_143 = {_T_30[31],_T_30[30],_T_30[28],_T_30[27],_T_30[25],_T_30[23],_T_30[21],_T_30[20],_T_30[18],_T_134}; // @[el2_lib.scala 211:22]
wire _T_144 = ^_T_143; // @[el2_lib.scala 211:29]
wire [8:0] _T_152 = {_T_30[15],_T_30[14],_T_30[11],_T_30[10],_T_30[7],_T_30[6],_T_30[4],_T_30[3],_T_30[0]}; // @[el2_lib.scala 211:39]
wire [17:0] _T_161 = {_T_30[31],_T_30[29],_T_30[28],_T_30[26],_T_30[25],_T_30[22],_T_30[21],_T_30[19],_T_30[18],_T_152}; // @[el2_lib.scala 211:39]
wire _T_162 = ^_T_161; // @[el2_lib.scala 211:46]
wire [8:0] _T_170 = {_T_30[15],_T_30[14],_T_30[9],_T_30[8],_T_30[7],_T_30[6],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:56]
wire [17:0] _T_179 = {_T_30[30],_T_30[29],_T_30[28],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[17],_T_30[16],_T_170}; // @[el2_lib.scala 211:56]
wire _T_180 = ^_T_179; // @[el2_lib.scala 211:63]
wire [6:0] _T_186 = {_T_30[12],_T_30[11],_T_30[10],_T_30[9],_T_30[8],_T_30[7],_T_30[6]}; // @[el2_lib.scala 211:73]
wire [14:0] _T_194 = {_T_30[27],_T_30[26],_T_30[25],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[13],_T_186}; // @[el2_lib.scala 211:73]
wire _T_195 = ^_T_194; // @[el2_lib.scala 211:80]
wire [14:0] _T_209 = {_T_30[20],_T_30[19],_T_30[18],_T_30[17],_T_30[16],_T_30[15],_T_30[14],_T_30[13],_T_186}; // @[el2_lib.scala 211:90]
wire _T_210 = ^_T_209; // @[el2_lib.scala 211:97]
wire [5:0] _T_215 = {_T_30[5],_T_30[4],_T_30[3],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:107]
wire _T_216 = ^_T_215; // @[el2_lib.scala 211:114]
wire [5:0] _T_221 = {_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
wire _T_222 = ^_T_30; // @[el2_lib.scala 212:13]
wire _T_223 = ^_T_221; // @[el2_lib.scala 212:23]
wire _T_224 = _T_222 ^ _T_223; // @[el2_lib.scala 212:18]
wire [6:0] _T_225 = {_T_224,_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
wire [25:0] _T_229 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
wire [25:0] _T_463 = {_T_225[4:0],2'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
wire _T_478 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 119:44]
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 123:38]
wire [25:0] _GEN_17 = ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 137:75]
wire [25:0] _GEN_18 = ic_way_tag_0_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
wire [36:0] w_tout_0 = {_GEN_18[25:21],_GEN_18[18:0],13'h0}; // @[Cat.scala 29:58]
wire [25:0] _GEN_22 = ic_way_tag_1_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
wire [36:0] w_tout_1 = {_GEN_22[25:21],_GEN_22[18:0],13'h0}; // @[Cat.scala 29:58]
wire ic_tag_way_perr_0 = io_test_ecc_sb_out_0 | io_test_ecc_db_out_0; // @[el2_ifu_ic_mem.scala 165:54]
wire ic_tag_way_perr_1 = io_test_ecc_sb_out_1 | io_test_ecc_db_out_1; // @[el2_ifu_ic_mem.scala 165:54]
wire [9:0] _T_533 = {ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
wire [18:0] _T_542 = {_T_533,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
wire [25:0] _T_549 = {_T_542,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
wire [25:0] _T_550 = _T_549 & ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
wire [9:0] _T_561 = {ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
wire [18:0] _T_570 = {_T_561,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
wire [25:0] _T_577 = {_T_570,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
wire [25:0] _T_578 = _T_577 & ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
wire [36:0] _T_636 = w_tout_0 & w_tout_1; // @[el2_ifu_ic_mem.scala 176:31]
wire [1:0] _T_637 = {ic_tag_way_perr_0,ic_tag_way_perr_1}; // @[Cat.scala 29:58]
wire [1:0] _T_638 = _T_637 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 177:55]
wire _T_642 = w_tout_0[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
wire [1:0] _GEN_25 = {{1'd0}, _T_642}; // @[el2_ifu_ic_mem.scala 179:133]
wire [1:0] _T_643 = _GEN_25 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
wire _T_646 = w_tout_1[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
wire [1:0] _GEN_26 = {{1'd0}, _T_646}; // @[el2_ifu_ic_mem.scala 179:133]
wire [1:0] _T_647 = _GEN_26 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
wire [3:0] _T_649 = {_T_643,_T_647}; // @[Cat.scala 29:58]
rvecc_decode rvecc_decode ( // @[el2_ifu_ic_mem.scala 149:27]
.io_din(rvecc_decode_io_din),
.io_ecc_in(rvecc_decode_io_ecc_in),
.io_ecc_out(rvecc_decode_io_ecc_out),
.io_dout(rvecc_decode_io_dout),
.io_single_ecc_error(rvecc_decode_io_single_ecc_error)
);
rvecc_decode rvecc_decode_1 ( // @[el2_ifu_ic_mem.scala 149:27]
.io_din(rvecc_decode_1_io_din),
.io_ecc_in(rvecc_decode_1_io_ecc_in),
.io_ecc_out(rvecc_decode_1_io_ecc_out),
.io_dout(rvecc_decode_1_io_dout),
.io_single_ecc_error(rvecc_decode_1_io_single_ecc_error)
);
assign ic_way_tag_0_ic_tag_data_raw_addr = ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
assign ic_way_tag_0_ic_tag_data_raw_data = ic_way_tag_0[ic_way_tag_0_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
assign ic_way_tag_0__T_487_data = _T_8 ? _T_229 : _T_463;
assign ic_way_tag_0__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
assign ic_way_tag_0__T_487_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
assign ic_way_tag_0__T_487_en = 1'h1;
assign ic_way_tag_1_ic_tag_data_raw_addr = ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
assign ic_way_tag_1_ic_tag_data_raw_data = ic_way_tag_1[ic_way_tag_1_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
assign ic_way_tag_1__T_487_data = _T_8 ? _T_229 : _T_463;
assign ic_way_tag_1__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
assign ic_way_tag_1__T_487_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
assign ic_way_tag_1__T_487_en = 1'h1;
assign io_ictag_debug_rd_data = _T_550 | _T_578; // @[el2_ifu_ic_mem.scala 175:26]
assign io_ic_rd_hit = _T_649[1:0]; // @[el2_ifu_ic_mem.scala 179:16]
assign io_ic_tag_perr = |_T_638; // @[el2_ifu_ic_mem.scala 177:18]
assign io_test = _T_636[25:0]; // @[el2_ifu_ic_mem.scala 176:13]
assign io_test_ecc_data_out_0 = rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
assign io_test_ecc_data_out_1 = rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
assign io_test_ecc_out_0 = rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
assign io_test_ecc_out_1 = rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
assign io_test_ecc_sb_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
assign io_test_ecc_sb_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
assign io_test_ecc_db_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
assign io_test_ecc_db_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
assign rvecc_decode_io_din = {11'h0,ic_way_tag_0_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
assign rvecc_decode_io_ecc_in = {2'h0,ic_way_tag_0_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
assign rvecc_decode_1_io_din = {11'h0,ic_way_tag_1_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
assign rvecc_decode_1_io_ecc_in = {2'h0,ic_way_tag_1_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {1{`RANDOM}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
ic_way_tag_0[initvar] = _RAND_0[25:0];
_RAND_2 = {1{`RANDOM}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
ic_way_tag_1[initvar] = _RAND_2[25:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 = _RAND_1[6:0];
_RAND_3 = {1{`RANDOM}};
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 = _RAND_3[6:0];
_RAND_4 = {1{`RANDOM}};
ic_rw_addr_ff = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
ic_debug_rd_way_en_ff = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(ic_way_tag_0__T_487_en & ic_way_tag_0__T_487_mask) begin
ic_way_tag_0[ic_way_tag_0__T_487_addr] <= ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
end
if (_T_478) begin
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
end else begin
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
end
if(ic_way_tag_1__T_487_en & ic_way_tag_1__T_487_mask) begin
ic_way_tag_1[ic_way_tag_1__T_487_addr] <= ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
end
if (_T_478) begin
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
end else begin
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
end
if (reset) begin
ic_rw_addr_ff <= 32'h0;
end else begin
ic_rw_addr_ff <= io_ic_rw_addr;
end
if (reset) begin
ic_debug_rd_way_en_ff <= 2'h0;
end else begin
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
end
end
endmodule

9
InoutPort.v
View File

@ -1,9 +0,0 @@
module InoutPort( inout [15:0] a,
input [15:0] b,
input sel,
output [15:0] c);
assign a = sel ? 'bz : b;
assign c = sel ? a : 'bz;
endmodule

24
MakeInout.anno.json
View File

@ -1,24 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxInlineAnno",
"target":"MakeInout.rvdff",
"name":"rvdff.v",
"text":"\nmodule InoutPort( input [15:0] in,\n input clk,\n input reset,\n output [15:0] out);\n always@(posedge clk or negedge reset)\n begin\n if(reset == 0)\n out <= 0;\n else\n out <= in\n end\nendmodule\n "
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"MakeInout"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

26
MakeInout.fir
View File

@ -1,26 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit MakeInout :
extmodule rvdff :
input in : UInt<16>
input clk : Clock
input reset : UInt<1>
output out : UInt<16>
defname = rvdff
module MakeInout :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>}
inst m of rvdff @[GCD.scala 40:17]
m.out is invalid
m.reset is invalid
m.clk is invalid
m.in is invalid
io.out <= m.out @[GCD.scala 42:8]
m.reset <= io.reset @[GCD.scala 42:8]
m.clk <= io.clk @[GCD.scala 42:8]
m.in <= io.in @[GCD.scala 42:8]

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MakeInout.v
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module MakeInout(
input clock,
input reset,
input [15:0] io_in,
input io_clk,
input io_reset,
output [15:0] io_out
);
wire [15:0] m_in; // @[GCD.scala 40:17]
wire m_clk; // @[GCD.scala 40:17]
wire m_reset; // @[GCD.scala 40:17]
wire [15:0] m_out; // @[GCD.scala 40:17]
rvdff m ( // @[GCD.scala 40:17]
.in(m_in),
.clk(m_clk),
.reset(m_reset),
.out(m_out)
);
assign io_out = m_out; // @[GCD.scala 42:8]
assign m_in = io_in; // @[GCD.scala 42:8]
assign m_clk = io_clk; // @[GCD.scala 42:8]
assign m_reset = io_reset; // @[GCD.scala 42:8]
endmodule

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README.md
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# EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
This repository contains the SweRV EL2 Core design in CHISEL
## Back ground
The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
## Directory Structure
├── configs # Configurations Dir
│   └── snapshots # Where generated configuration files are created
├── design # Design root dir
│   ├── dbg # Debugger
│   ├── dec # Decode, Registers and Exceptions
│   ├── dmi # DMI block
│   ├── exu # EXU (ALU/MUL/DIV)
│   ├── ifu # Fetch & Branch Prediction
│   ├── include
│   ├── lib
│   └── lsu # Load/Store
├── docs
├── tools # Scripts/Makefiles
└── testbench # (Very) simple testbench
   ├── asm # Example assembly files
   └── hex # Canned demo hex files

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RVCExpander.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs2",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rd",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs1",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_legal",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_bits",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_rvc",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs3",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"RVCExpander"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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RVCExpander.fir
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RVCExpander.v
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module RVCExpander(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out_bits,
output [4:0] io_out_rd,
output [4:0] io_out_rs1,
output [4:0] io_out_rs2,
output [4:0] io_out_rs3,
output io_rvc,
output io_legal
);
wire _T_3 = |io_in[12:5]; // @[RVC.scala 58:29]
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 58:20]
wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58]
wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58]
wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58]
wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_332 = |_T_213; // @[RVC.scala 95:29]
wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 95:20]
wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58]
wire _T_351 = io_in[11:7] == 5'h0; // @[RVC.scala 97:14]
wire _T_353 = io_in[11:7] == 5'h2; // @[RVC.scala 97:27]
wire _T_354 = _T_351 | _T_353; // @[RVC.scala 97:21]
wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 91:20]
wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58]
wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 97:10]
wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 97:10]
wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 97:10]
wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 97:10]
wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[RVC.scala 104:23]
wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[RVC.scala 104:23]
wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
wire _T_428 = io_in[6:5] == 2'h0; // @[RVC.scala 108:30]
wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[RVC.scala 108:22]
wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 109:22]
wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58]
wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[RVC.scala 110:43]
wire [30:0] _T_442 = _GEN_173 | _T_429; // @[RVC.scala 110:43]
wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[RVC.scala 112:19 RVC.scala 112:19]
wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[RVC.scala 112:19 RVC.scala 112:19]
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[RVC.scala 27:14]
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[RVC.scala 27:14]
wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[RVC.scala 112:19 RVC.scala 112:19]
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[RVC.scala 27:14]
wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
wire _T_673 = |io_in[11:7]; // @[RVC.scala 118:27]
wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[RVC.scala 118:23]
wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58]
wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58]
wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[RVC.scala 139:33]
wire _T_772 = |io_in[6:2]; // @[RVC.scala 140:27]
wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[RVC.scala 140:22]
wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[RVC.scala 140:22]
wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[RVC.scala 140:22]
wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 140:22]
wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 140:22]
wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58]
wire [24:0] _T_782 = _T_781 | 25'h100000; // @[RVC.scala 142:46]
wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[RVC.scala 143:33]
wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[RVC.scala 144:25]
wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[RVC.scala 144:25]
wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 144:25]
wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[RVC.scala 145:10]
wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[RVC.scala 145:10]
wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[RVC.scala 145:10]
wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[RVC.scala 145:10]
wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[RVC.scala 145:10]
wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58]
wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58]
wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58]
wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[RVC.scala 203:12]
wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[RVC.scala 203:12]
wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[RVC.scala 203:12]
wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 203:12]
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[RVC.scala 203:12]
wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[RVC.scala 203:12]
wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[RVC.scala 203:12]
wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[RVC.scala 203:12]
wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[RVC.scala 203:12]
wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[RVC.scala 203:12]
wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[RVC.scala 203:12]
wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[RVC.scala 203:12]
wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[RVC.scala 203:12]
wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[RVC.scala 203:12]
wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[RVC.scala 203:12]
wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[RVC.scala 203:12]
wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[RVC.scala 203:12]
wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[RVC.scala 203:12]
wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[RVC.scala 203:12]
wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[RVC.scala 203:12]
wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[RVC.scala 203:12]
wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[RVC.scala 203:12]
wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[RVC.scala 203:12]
wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[RVC.scala 203:12]
wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[RVC.scala 203:12]
wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[RVC.scala 203:12]
wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[RVC.scala 203:12]
wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[RVC.scala 203:12]
wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[RVC.scala 203:12]
wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[RVC.scala 203:12]
wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[RVC.scala 203:12]
wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[RVC.scala 203:12]
wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[RVC.scala 203:12]
wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[RVC.scala 203:12]
wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[RVC.scala 203:12]
wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[RVC.scala 203:12]
wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[RVC.scala 203:12]
wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[RVC.scala 203:12]
wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[RVC.scala 203:12]
wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[RVC.scala 203:12]
wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[RVC.scala 203:12]
wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[RVC.scala 203:12]
wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[RVC.scala 203:12]
wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[RVC.scala 203:12]
wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[RVC.scala 203:12]
wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[RVC.scala 203:12]
wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[RVC.scala 203:12]
wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[RVC.scala 203:12]
wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[RVC.scala 203:12]
wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[RVC.scala 203:12]
wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[RVC.scala 203:12]
wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[RVC.scala 203:12]
wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[RVC.scala 203:12]
wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[RVC.scala 203:12]
wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[RVC.scala 203:12]
wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[RVC.scala 203:12]
wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[RVC.scala 203:12]
wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[RVC.scala 203:12]
wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[RVC.scala 203:12]
wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[RVC.scala 203:12]
wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[RVC.scala 203:12]
wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[RVC.scala 203:12]
wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[RVC.scala 203:12]
wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[RVC.scala 203:12]
wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[RVC.scala 203:12]
wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[RVC.scala 203:12]
wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[RVC.scala 203:12]
wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[RVC.scala 203:12]
wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[RVC.scala 203:12]
wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[RVC.scala 203:12]
wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[RVC.scala 203:12]
wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[RVC.scala 203:12]
wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[RVC.scala 203:12]
wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[RVC.scala 203:12]
wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[RVC.scala 203:12]
wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[RVC.scala 203:12]
wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[RVC.scala 203:12]
wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[RVC.scala 203:12]
wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[RVC.scala 203:12]
wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[RVC.scala 203:12]
wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[RVC.scala 203:12]
wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[RVC.scala 203:12]
wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[RVC.scala 203:12]
wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[RVC.scala 203:12]
wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[RVC.scala 203:12]
wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[RVC.scala 203:12]
wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[RVC.scala 203:12]
wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[RVC.scala 203:12]
wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[RVC.scala 203:12]
wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[RVC.scala 203:12]
wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[RVC.scala 203:12]
wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[RVC.scala 203:12]
wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[RVC.scala 203:12]
wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[RVC.scala 203:12]
wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[RVC.scala 203:12]
wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[RVC.scala 203:12]
wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[RVC.scala 203:12]
wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[RVC.scala 203:12]
wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[RVC.scala 203:12]
wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[RVC.scala 203:12]
wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[RVC.scala 203:12]
wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[RVC.scala 203:12]
wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[RVC.scala 203:12]
wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[RVC.scala 203:12]
wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[RVC.scala 203:12]
wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[RVC.scala 203:12]
wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[RVC.scala 203:12]
wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[RVC.scala 203:12]
wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[RVC.scala 203:12]
wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[RVC.scala 203:12]
wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[RVC.scala 203:12]
wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[RVC.scala 203:12]
wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[RVC.scala 203:12]
wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[RVC.scala 203:12]
wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[RVC.scala 203:12]
wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[RVC.scala 203:12]
wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[RVC.scala 203:12]
wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[RVC.scala 203:12]
wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[RVC.scala 203:12]
wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[RVC.scala 203:12]
wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[RVC.scala 203:12]
wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[RVC.scala 203:12]
wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[RVC.scala 203:12]
wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[RVC.scala 203:12]
wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[RVC.scala 203:12]
wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[RVC.scala 203:12]
wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[RVC.scala 203:12]
wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[RVC.scala 203:12]
wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[RVC.scala 203:12]
wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[RVC.scala 203:12]
wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[RVC.scala 203:12]
wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[RVC.scala 203:12]
wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[RVC.scala 203:12]
wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[RVC.scala 203:12]
wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[RVC.scala 203:12]
wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[RVC.scala 203:12]
wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[RVC.scala 203:12]
wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[RVC.scala 203:12]
wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[RVC.scala 203:12]
wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[RVC.scala 203:12]
wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[RVC.scala 203:12]
wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[RVC.scala 203:12]
wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[RVC.scala 203:12]
wire _T_900 = ~io_in[13]; // @[RVC.scala 204:18]
wire _T_902 = ~io_in[12]; // @[RVC.scala 204:31]
wire _T_903 = _T_900 & _T_902; // @[RVC.scala 204:29]
wire _T_905 = _T_903 & io_in[11]; // @[RVC.scala 204:42]
wire _T_907 = _T_905 & io_in[1]; // @[RVC.scala 204:54]
wire _T_909 = ~io_in[0]; // @[RVC.scala 204:65]
wire _T_910 = _T_907 & _T_909; // @[RVC.scala 204:63]
wire _T_917 = _T_903 & io_in[6]; // @[RVC.scala 205:32]
wire _T_919 = _T_917 & io_in[1]; // @[RVC.scala 205:43]
wire _T_922 = _T_919 & _T_909; // @[RVC.scala 205:52]
wire _T_923 = _T_910 | _T_922; // @[RVC.scala 204:76]
wire _T_925 = ~io_in[15]; // @[RVC.scala 206:8]
wire _T_928 = _T_925 & _T_900; // @[RVC.scala 206:19]
wire _T_931 = ~io_in[1]; // @[RVC.scala 206:43]
wire _T_932 = io_in[11] >> _T_931; // @[RVC.scala 206:42]
wire _T_934 = _T_928 & _T_932; // @[RVC.scala 206:32]
wire _T_935 = _T_923 | _T_934; // @[RVC.scala 205:65]
wire _T_942 = _T_903 & io_in[5]; // @[RVC.scala 207:32]
wire _T_944 = _T_942 & io_in[1]; // @[RVC.scala 207:41]
wire _T_947 = _T_944 & _T_909; // @[RVC.scala 207:50]
wire _T_948 = _T_935 | _T_947; // @[RVC.scala 206:54]
wire _T_955 = _T_903 & io_in[10]; // @[RVC.scala 208:32]
wire _T_958 = _T_955 & _T_931; // @[RVC.scala 208:42]
wire _T_960 = _T_958 & io_in[0]; // @[RVC.scala 208:54]
wire _T_961 = _T_948 | _T_960; // @[RVC.scala 207:63]
wire _T_968 = _T_928 & io_in[6]; // @[RVC.scala 209:32]
wire _T_971 = _T_968 & _T_931; // @[RVC.scala 209:41]
wire _T_972 = _T_961 | _T_971; // @[RVC.scala 208:64]
wire _T_976 = io_in[15] & _T_902; // @[RVC.scala 209:65]
wire _T_979 = _T_976 & _T_931; // @[RVC.scala 209:78]
wire _T_981 = _T_979 & io_in[0]; // @[RVC.scala 209:90]
wire _T_982 = _T_972 | _T_981; // @[RVC.scala 209:54]
wire _T_989 = _T_903 & io_in[9]; // @[RVC.scala 210:32]
wire _T_991 = _T_989 & io_in[1]; // @[RVC.scala 210:41]
wire _T_994 = _T_991 & _T_909; // @[RVC.scala 210:50]
wire _T_995 = _T_982 | _T_994; // @[RVC.scala 209:100]
wire _T_999 = _T_902 & io_in[6]; // @[RVC.scala 211:19]
wire _T_1002 = _T_999 & _T_931; // @[RVC.scala 211:28]
wire _T_1004 = _T_1002 & io_in[0]; // @[RVC.scala 211:40]
wire _T_1005 = _T_995 | _T_1004; // @[RVC.scala 210:63]
wire _T_1012 = _T_928 & io_in[5]; // @[RVC.scala 212:32]
wire _T_1015 = _T_1012 & _T_931; // @[RVC.scala 212:41]
wire _T_1016 = _T_1005 | _T_1015; // @[RVC.scala 211:50]
wire _T_1023 = _T_903 & io_in[8]; // @[RVC.scala 213:32]
wire _T_1025 = _T_1023 & io_in[1]; // @[RVC.scala 213:41]
wire _T_1028 = _T_1025 & _T_909; // @[RVC.scala 213:50]
wire _T_1029 = _T_1016 | _T_1028; // @[RVC.scala 212:54]
wire _T_1033 = _T_902 & io_in[5]; // @[RVC.scala 214:19]
wire _T_1036 = _T_1033 & _T_931; // @[RVC.scala 214:28]
wire _T_1038 = _T_1036 & io_in[0]; // @[RVC.scala 214:40]
wire _T_1039 = _T_1029 | _T_1038; // @[RVC.scala 213:63]
wire _T_1046 = _T_928 & io_in[10]; // @[RVC.scala 215:32]
wire _T_1049 = _T_1046 & _T_931; // @[RVC.scala 215:42]
wire _T_1050 = _T_1039 | _T_1049; // @[RVC.scala 214:50]
wire _T_1057 = _T_903 & io_in[7]; // @[RVC.scala 215:82]
wire _T_1059 = _T_1057 & io_in[1]; // @[RVC.scala 215:91]
wire _T_1062 = _T_1059 & _T_909; // @[RVC.scala 215:100]
wire _T_1063 = _T_1050 | _T_1062; // @[RVC.scala 215:55]
wire _T_1066 = io_in[12] & io_in[11]; // @[RVC.scala 216:16]
wire _T_1068 = ~io_in[10]; // @[RVC.scala 216:28]
wire _T_1069 = _T_1066 & _T_1068; // @[RVC.scala 216:26]
wire _T_1072 = _T_1069 & _T_931; // @[RVC.scala 216:39]
wire _T_1074 = _T_1072 & io_in[0]; // @[RVC.scala 216:51]
wire _T_1075 = _T_1063 | _T_1074; // @[RVC.scala 215:113]
wire _T_1082 = _T_928 & io_in[9]; // @[RVC.scala 216:88]
wire _T_1085 = _T_1082 & _T_931; // @[RVC.scala 216:97]
wire _T_1086 = _T_1075 | _T_1085; // @[RVC.scala 216:61]
wire _T_1093 = _T_903 & io_in[4]; // @[RVC.scala 217:32]
wire _T_1095 = _T_1093 & io_in[1]; // @[RVC.scala 217:41]
wire _T_1098 = _T_1095 & _T_909; // @[RVC.scala 217:50]
wire _T_1099 = _T_1086 | _T_1098; // @[RVC.scala 216:110]
wire _T_1102 = io_in[13] & io_in[12]; // @[RVC.scala 217:74]
wire _T_1105 = _T_1102 & _T_931; // @[RVC.scala 217:84]
wire _T_1107 = _T_1105 & io_in[0]; // @[RVC.scala 217:96]
wire _T_1108 = _T_1099 | _T_1107; // @[RVC.scala 217:63]
wire _T_1115 = _T_928 & io_in[8]; // @[RVC.scala 218:32]
wire _T_1118 = _T_1115 & _T_931; // @[RVC.scala 218:41]
wire _T_1119 = _T_1108 | _T_1118; // @[RVC.scala 217:106]
wire _T_1126 = _T_903 & io_in[3]; // @[RVC.scala 218:81]
wire _T_1128 = _T_1126 & io_in[1]; // @[RVC.scala 218:90]
wire _T_1131 = _T_1128 & _T_909; // @[RVC.scala 218:99]
wire _T_1132 = _T_1119 | _T_1131; // @[RVC.scala 218:54]
wire _T_1135 = io_in[13] & io_in[4]; // @[RVC.scala 219:16]
wire _T_1138 = _T_1135 & _T_931; // @[RVC.scala 219:25]
wire _T_1140 = _T_1138 & io_in[0]; // @[RVC.scala 219:37]
wire _T_1141 = _T_1132 | _T_1140; // @[RVC.scala 218:112]
wire _T_1148 = _T_903 & io_in[2]; // @[RVC.scala 219:74]
wire _T_1150 = _T_1148 & io_in[1]; // @[RVC.scala 219:83]
wire _T_1153 = _T_1150 & _T_909; // @[RVC.scala 219:92]
wire _T_1154 = _T_1141 | _T_1153; // @[RVC.scala 219:47]
wire _T_1161 = _T_928 & io_in[7]; // @[RVC.scala 220:32]
wire _T_1164 = _T_1161 & _T_931; // @[RVC.scala 220:41]
wire _T_1165 = _T_1154 | _T_1164; // @[RVC.scala 219:105]
wire _T_1168 = io_in[13] & io_in[3]; // @[RVC.scala 220:65]
wire _T_1171 = _T_1168 & _T_931; // @[RVC.scala 220:74]
wire _T_1173 = _T_1171 & io_in[0]; // @[RVC.scala 220:86]
wire _T_1174 = _T_1165 | _T_1173; // @[RVC.scala 220:54]
wire _T_1177 = io_in[13] & io_in[2]; // @[RVC.scala 221:16]
wire _T_1180 = _T_1177 & _T_931; // @[RVC.scala 221:25]
wire _T_1182 = _T_1180 & io_in[0]; // @[RVC.scala 221:37]
wire _T_1183 = _T_1174 | _T_1182; // @[RVC.scala 220:96]
wire _T_1187 = io_in[14] & _T_900; // @[RVC.scala 221:58]
wire _T_1190 = _T_1187 & _T_931; // @[RVC.scala 221:71]
wire _T_1191 = _T_1183 | _T_1190; // @[RVC.scala 221:47]
wire _T_1193 = ~io_in[14]; // @[RVC.scala 222:8]
wire _T_1196 = _T_1193 & _T_902; // @[RVC.scala 222:19]
wire _T_1199 = _T_1196 & _T_931; // @[RVC.scala 222:32]
wire _T_1201 = _T_1199 & io_in[0]; // @[RVC.scala 222:44]
wire _T_1202 = _T_1191 | _T_1201; // @[RVC.scala 221:84]
wire _T_1206 = io_in[15] & _T_900; // @[RVC.scala 222:65]
wire _T_1208 = _T_1206 & io_in[12]; // @[RVC.scala 222:78]
wire _T_1210 = _T_1208 & io_in[1]; // @[RVC.scala 222:88]
wire _T_1213 = _T_1210 & _T_909; // @[RVC.scala 222:97]
wire _T_1214 = _T_1202 | _T_1213; // @[RVC.scala 222:54]
wire _T_1222 = _T_928 & _T_902; // @[RVC.scala 223:32]
wire _T_1224 = _T_1222 & io_in[1]; // @[RVC.scala 223:45]
wire _T_1227 = _T_1224 & _T_909; // @[RVC.scala 223:54]
wire _T_1228 = _T_1214 | _T_1227; // @[RVC.scala 222:110]
wire _T_1235 = _T_928 & io_in[12]; // @[RVC.scala 223:94]
wire _T_1238 = _T_1235 & _T_931; // @[RVC.scala 223:104]
wire _T_1239 = _T_1228 | _T_1238; // @[RVC.scala 223:67]
wire _T_1246 = _T_1187 & _T_909; // @[RVC.scala 224:29]
assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[RVC.scala 203:12]
assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[RVC.scala 203:12]
assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[RVC.scala 203:12]
assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[RVC.scala 203:12]
assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[RVC.scala 203:12]
assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 201:12]
assign io_legal = _T_1239 | _T_1246; // @[RVC.scala 204:14]
endmodule

15
TEC_RV_ICG.v
View File

@ -1,15 +0,0 @@
module TEC_RV_ICG(
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

34
ahb_to_axi4.anno.json
View File

@ -1,34 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_hreadyout",
"sources":[
"~ahb_to_axi4|ahb_to_axi4>io_ahb_hresp",
"~ahb_to_axi4|ahb_to_axi4>io_axi_awvalid",
"~ahb_to_axi4|ahb_to_axi4>io_axi_awready",
"~ahb_to_axi4|ahb_to_axi4>io_axi_arvalid",
"~ahb_to_axi4|ahb_to_axi4>io_axi_arready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"ahb_to_axi4.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ahb_to_axi4"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

536
ahb_to_axi4.fir
View File

@ -1,536 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit ahb_to_axi4 :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module ahb_to_axi4 :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_haddr : UInt<32>, flip ahb_hburst : UInt<3>, flip ahb_hmastlock : UInt<1>, flip ahb_hprot : UInt<4>, flip ahb_hsize : UInt<3>, flip ahb_htrans : UInt<2>, flip ahb_hwrite : UInt<1>, flip ahb_hwdata : UInt<64>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, ahb_hrdata : UInt<64>, ahb_hreadyout : UInt<1>, ahb_hresp : UInt<1>}
wire master_wstrb : UInt<8>
master_wstrb <= UInt<8>("h00")
wire buf_state_en : UInt<1>
buf_state_en <= UInt<1>("h00")
wire buf_read_error_in : UInt<1>
buf_read_error_in <= UInt<1>("h00")
wire buf_read_error : UInt<1>
buf_read_error <= UInt<1>("h00")
wire buf_rdata : UInt<64>
buf_rdata <= UInt<64>("h00")
wire ahb_hready : UInt<1>
ahb_hready <= UInt<1>("h00")
wire ahb_hready_q : UInt<1>
ahb_hready_q <= UInt<1>("h00")
wire ahb_htrans_in : UInt<2>
ahb_htrans_in <= UInt<2>("h00")
wire ahb_htrans_q : UInt<2>
ahb_htrans_q <= UInt<2>("h00")
wire ahb_hsize_q : UInt<3>
ahb_hsize_q <= UInt<3>("h00")
wire ahb_hwrite_q : UInt<1>
ahb_hwrite_q <= UInt<1>("h00")
wire ahb_haddr_q : UInt<32>
ahb_haddr_q <= UInt<32>("h00")
wire ahb_hwdata_q : UInt<64>
ahb_hwdata_q <= UInt<64>("h00")
wire ahb_hresp_q : UInt<1>
ahb_hresp_q <= UInt<1>("h00")
wire buf_rdata_en : UInt<1>
buf_rdata_en <= UInt<1>("h00")
wire ahb_bus_addr_clk_en : UInt<1>
ahb_bus_addr_clk_en <= UInt<1>("h00")
wire buf_rdata_clk_en : UInt<1>
buf_rdata_clk_en <= UInt<1>("h00")
wire ahb_clk : Clock @[ahb_to_axi4.scala 84:35]
wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 85:35]
wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 86:35]
wire cmdbuf_wr_en : UInt<1>
cmdbuf_wr_en <= UInt<1>("h00")
wire cmdbuf_rst : UInt<1>
cmdbuf_rst <= UInt<1>("h00")
wire cmdbuf_full : UInt<1>
cmdbuf_full <= UInt<1>("h00")
wire cmdbuf_vld : UInt<1>
cmdbuf_vld <= UInt<1>("h00")
wire cmdbuf_write : UInt<1>
cmdbuf_write <= UInt<1>("h00")
wire cmdbuf_size : UInt<2>
cmdbuf_size <= UInt<2>("h00")
wire cmdbuf_wstrb : UInt<8>
cmdbuf_wstrb <= UInt<8>("h00")
wire cmdbuf_addr : UInt<32>
cmdbuf_addr <= UInt<32>("h00")
wire cmdbuf_wdata : UInt<64>
cmdbuf_wdata <= UInt<64>("h00")
wire bus_clk : Clock @[ahb_to_axi4.scala 98:35]
node _T = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 224:25]
node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 224:47]
node _T_1 = bits(ahb_haddr_q, 31, 16) @[el2_lib.scala 227:14]
node ahb_addr_in_dccm = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 227:29]
node _T_2 = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 224:25]
node ahb_addr_in_iccm_region_nc = eq(_T_2, UInt<4>("h0e")) @[el2_lib.scala 224:47]
node _T_3 = bits(ahb_haddr_q, 31, 16) @[el2_lib.scala 227:14]
node ahb_addr_in_iccm = eq(_T_3, UInt<16>("h0ee00")) @[el2_lib.scala 227:29]
node _T_4 = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 224:25]
node ahb_addr_in_pic_region_nc = eq(_T_4, UInt<4>("h0f")) @[el2_lib.scala 224:47]
node _T_5 = bits(ahb_haddr_q, 31, 15) @[el2_lib.scala 227:14]
node ahb_addr_in_pic = eq(_T_5, UInt<17>("h01e018")) @[el2_lib.scala 227:29]
wire buf_state : UInt<2>
buf_state <= UInt<2>("h00")
wire buf_nxtstate : UInt<2>
buf_nxtstate <= UInt<2>("h00")
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 118:33]
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 119:33]
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 120:33]
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 121:33]
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 122:33]
node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
when _T_6 : @[Conditional.scala 40:58]
node _T_7 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 126:28]
buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 126:22]
node _T_8 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 127:51]
node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 127:36]
node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 127:55]
buf_state_en <= _T_10 @[ahb_to_axi4.scala 127:22]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
when _T_11 : @[Conditional.scala 39:67]
node _T_12 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 130:59]
node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 130:66]
node _T_14 = or(io.ahb_hresp, _T_13) @[ahb_to_axi4.scala 130:43]
node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 130:80]
node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 130:78]
node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 130:94]
node _T_18 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 130:111]
node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 130:28]
buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 130:22]
node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 131:26]
node _T_21 = or(_T_20, io.ahb_hresp) @[ahb_to_axi4.scala 131:39]
buf_state_en <= _T_21 @[ahb_to_axi4.scala 131:22]
node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 132:25]
node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 132:72]
node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 132:79]
node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 132:97]
node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 132:55]
node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 132:40]
node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 132:38]
cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 132:22]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
when _T_29 : @[Conditional.scala 39:67]
node _T_30 = mux(io.ahb_hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 135:28]
buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 135:22]
node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 136:26]
node _T_32 = or(_T_31, io.ahb_hresp) @[ahb_to_axi4.scala 136:39]
buf_state_en <= _T_32 @[ahb_to_axi4.scala 136:22]
node _T_33 = eq(io.ahb_hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 137:25]
node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 137:41]
node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 137:39]
cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 137:22]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
when _T_36 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 140:22]
node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 141:41]
node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 141:39]
buf_state_en <= _T_38 @[ahb_to_axi4.scala 141:22]
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 142:22]
node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 143:57]
node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 143:64]
node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 143:43]
buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 143:27]
skip @[Conditional.scala 39:67]
node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 146:101]
reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_42 : @[Reg.scala 28:19]
_T_43 <= buf_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_state <= _T_43 @[ahb_to_axi4.scala 146:33]
node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 148:56]
node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 148:62]
node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 148:94]
node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 148:80]
node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 148:72]
node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 149:56]
node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 149:62]
node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15]
node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 149:94]
node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 149:80]
node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 149:72]
node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 148:111]
node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 150:56]
node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 150:62]
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 150:94]
node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 150:80]
node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 150:72]
node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 149:111]
node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 151:56]
node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 151:62]
node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15]
node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 151:72]
node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 150:111]
master_wstrb <= _T_72 @[ahb_to_axi4.scala 148:33]
node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 154:68]
node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 154:66]
node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 154:86]
node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 154:112]
node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 154:99]
node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 154:137]
node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 154:156]
node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 154:144]
node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 154:125]
node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 154:123]
node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 154:169]
node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 154:167]
node _T_85 = mux(io.ahb_hresp, _T_74, _T_84) @[ahb_to_axi4.scala 154:39]
io.ahb_hreadyout <= _T_85 @[ahb_to_axi4.scala 154:33]
node _T_86 = and(io.ahb_hreadyout, io.ahb_hreadyin) @[ahb_to_axi4.scala 155:53]
ahb_hready <= _T_86 @[ahb_to_axi4.scala 155:33]
node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15]
node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_89 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 156:71]
node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 156:56]
ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 156:33]
node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 157:45]
io.ahb_hrdata <= _T_91 @[ahb_to_axi4.scala 157:33]
node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 158:50]
node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 158:56]
node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 158:78]
node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 158:65]
node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 159:57]
node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 159:38]
node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 160:75]
node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 160:55]
node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 160:109]
node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 160:115]
node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 160:138]
node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 160:144]
node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 160:124]
node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 160:95]
node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 160:93]
node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 159:78]
node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 161:49]
node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 161:55]
node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 161:77]
node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 161:64]
node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 160:155]
node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 162:49]
node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 162:55]
node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 162:78]
node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 162:85]
node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 162:64]
node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 161:84]
node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 163:49]
node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 163:55]
node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 163:78]
node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 163:85]
node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 163:64]
node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 162:90]
node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 158:89]
node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 163:92]
node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 165:51]
node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 165:49]
node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 164:51]
io.ahb_hresp <= _T_129 @[ahb_to_axi4.scala 158:33]
reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:68]
_T_130 <= io.axi_rdata @[ahb_to_axi4.scala 168:68]
buf_rdata <= _T_130 @[ahb_to_axi4.scala 168:33]
reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:62]
_T_131 <= buf_read_error_in @[ahb_to_axi4.scala 169:62]
buf_read_error <= _T_131 @[ahb_to_axi4.scala 169:33]
reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 172:62]
_T_132 <= io.ahb_hresp @[ahb_to_axi4.scala 172:62]
ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 172:33]
reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 173:62]
_T_133 <= ahb_hready @[ahb_to_axi4.scala 173:62]
ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 173:33]
reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 174:62]
_T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 174:62]
ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 174:33]
reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 175:67]
_T_135 <= io.ahb_hsize @[ahb_to_axi4.scala 175:67]
ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 175:33]
reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 176:67]
_T_136 <= io.ahb_hwrite @[ahb_to_axi4.scala 176:67]
ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 176:33]
reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 177:67]
_T_137 <= io.ahb_haddr @[ahb_to_axi4.scala 177:67]
ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 177:33]
node _T_138 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 180:79]
node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 180:64]
node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 180:50]
ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 180:33]
node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 181:50]
buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 181:33]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 183:33]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[el2_lib.scala 485:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 184:33]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_2.io.en <= buf_rdata_clk_en @[el2_lib.scala 485:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 185:33]
node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 187:54]
node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 187:90]
node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 187:72]
node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 187:111]
node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 187:109]
node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 187:144]
node _T_148 = and(io.ahb_hresp, _T_147) @[ahb_to_axi4.scala 187:142]
node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 187:126]
cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 187:33]
node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 188:68]
node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 188:104]
node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 188:86]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 188:50]
node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 188:48]
cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 188:33]
node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 190:88]
node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 190:68]
node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 190:112]
node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 190:110]
reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 190:63]
_T_159 <= _T_158 @[ahb_to_axi4.scala 190:63]
cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 190:33]
node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 194:57]
reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_160 : @[Reg.scala 28:19]
_T_161 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 193:33]
node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 197:56]
reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_162 : @[Reg.scala 28:19]
_T_163 <= ahb_hsize_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 196:33]
node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 200:57]
reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_165 <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 199:33]
node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 203:59]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18]
rvclkhdr_3.io.en <= _T_166 @[el2_lib.scala 511:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_167 <= ahb_haddr_q @[el2_lib.scala 514:16]
cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 203:17]
node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 204:62]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= bus_clk @[el2_lib.scala 510:18]
rvclkhdr_4.io.en <= _T_168 @[el2_lib.scala 511:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_169 <= io.ahb_hwdata @[el2_lib.scala 514:16]
cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 204:18]
node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 207:43]
io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 207:29]
io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 208:29]
io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 209:29]
node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 210:55]
node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58]
io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 210:29]
node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 211:29]
node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 212:29]
io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 213:29]
node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 215:43]
io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 215:29]
io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 216:29]
io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 217:29]
io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 218:29]
io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 220:29]
node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 222:45]
node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 222:43]
io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 222:29]
io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 223:29]
io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 224:29]
node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 225:55]
node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58]
io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 225:29]
node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 226:29]
node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 227:29]
io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 228:29]
io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 230:29]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_5.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 233:29]

561
ahb_to_axi4.v
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@ -1,561 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module ahb_to_axi4(
input clock,
input reset,
input io_scan_mode,
input io_bus_clk_en,
input io_clk_override,
input io_axi_awready,
input io_axi_wready,
input io_axi_bvalid,
input [1:0] io_axi_bresp,
input io_axi_arready,
input io_axi_rvalid,
input [63:0] io_axi_rdata,
input [1:0] io_axi_rresp,
input [31:0] io_ahb_haddr,
input [2:0] io_ahb_hburst,
input io_ahb_hmastlock,
input [3:0] io_ahb_hprot,
input [2:0] io_ahb_hsize,
input [1:0] io_ahb_htrans,
input io_ahb_hwrite,
input [63:0] io_ahb_hwdata,
input io_ahb_hsel,
input io_ahb_hreadyin,
output io_axi_awvalid,
output [31:0] io_axi_awaddr,
output [2:0] io_axi_awsize,
output [2:0] io_axi_awprot,
output [7:0] io_axi_awlen,
output [1:0] io_axi_awburst,
output io_axi_wvalid,
output [63:0] io_axi_wdata,
output [7:0] io_axi_wstrb,
output io_axi_wlast,
output io_axi_bready,
output io_axi_arvalid,
output [31:0] io_axi_araddr,
output [2:0] io_axi_arsize,
output [2:0] io_axi_arprot,
output [7:0] io_axi_arlen,
output [1:0] io_axi_arburst,
output io_axi_rready,
output [63:0] io_ahb_hrdata,
output io_ahb_hreadyout,
output io_ahb_hresp
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [63:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [63:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 85:35 ahb_to_axi4.scala 184:33]
reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 177:67]
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[el2_lib.scala 227:29]
wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[el2_lib.scala 227:29]
wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 84:35 ahb_to_axi4.scala 183:33]
reg [1:0] buf_state; // @[Reg.scala 27:20]
wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
wire ahb_hready = io_ahb_hreadyout & io_ahb_hreadyin; // @[ahb_to_axi4.scala 155:53]
wire _T_9 = ahb_hready & io_ahb_htrans[1]; // @[ahb_to_axi4.scala 127:36]
wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 127:55]
wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
wire _T_13 = io_ahb_htrans == 2'h0; // @[ahb_to_axi4.scala 130:66]
wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 130:43]
wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 130:80]
wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 130:78]
wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 98:35 ahb_to_axi4.scala 233:29]
reg cmdbuf_vld; // @[ahb_to_axi4.scala 190:63]
wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 188:68]
wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 188:104]
wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 188:86]
wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 188:50]
wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 188:48]
wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 131:26]
wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 131:39]
wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 132:79]
wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 132:97]
wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 132:55]
wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 132:40]
wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 132:38]
wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_33 = ~io_ahb_hresp; // @[ahb_to_axi4.scala 137:25]
wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 137:39]
wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
reg cmdbuf_write; // @[Reg.scala 27:20]
wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 141:41]
wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 141:39]
wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 143:64]
wire _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67]
wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67]
wire buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58]
wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 143:43]
wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67]
wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_29 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67]
wire _GEN_11 = _T_11 ? _T_28 : _GEN_6; // @[Conditional.scala 39:67]
wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 175:67]
wire _T_45 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 148:62]
wire [7:0] _T_47 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_49 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 148:80]
wire [7:0] _T_50 = _T_47 & _T_49; // @[ahb_to_axi4.scala 148:72]
wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 149:62]
wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 149:80]
wire [8:0] _GEN_23 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 149:72]
wire [8:0] _T_57 = _GEN_23 & _T_56; // @[ahb_to_axi4.scala 149:72]
wire [8:0] _GEN_24 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 148:111]
wire [8:0] _T_58 = _GEN_24 | _T_57; // @[ahb_to_axi4.scala 148:111]
wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 150:62]
wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 150:80]
wire [10:0] _GEN_25 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 150:72]
wire [10:0] _T_65 = _GEN_25 & _T_64; // @[ahb_to_axi4.scala 150:72]
wire [10:0] _GEN_26 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 149:111]
wire [10:0] _T_66 = _GEN_26 | _T_65; // @[ahb_to_axi4.scala 149:111]
wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 151:62]
wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_27 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 150:111]
wire [10:0] _T_72 = _T_66 | _GEN_27; // @[ahb_to_axi4.scala 150:111]
reg ahb_hready_q; // @[ahb_to_axi4.scala 173:62]
wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 154:68]
reg ahb_hresp_q; // @[ahb_to_axi4.scala 172:62]
wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 154:66]
wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 154:112]
wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 154:99]
wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 154:137]
wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 154:156]
wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 154:144]
wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 154:125]
wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 154:123]
reg buf_read_error; // @[ahb_to_axi4.scala 169:62]
wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 154:169]
wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 154:167]
wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 86:35 ahb_to_axi4.scala 185:33]
reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 168:68]
reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 174:62]
wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 158:56]
wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 158:78]
wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 158:65]
wire _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 159:57]
wire _T_97 = ~_T_96; // @[ahb_to_axi4.scala 159:38]
reg ahb_hwrite_q; // @[ahb_to_axi4.scala 176:67]
wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 160:75]
wire _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 160:55]
wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 160:115]
wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 160:144]
wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 160:124]
wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 160:95]
wire _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 160:93]
wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 159:78]
wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 161:64]
wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 160:155]
wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 162:85]
wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 162:64]
wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 161:84]
wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 163:85]
wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 163:64]
wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 162:90]
wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 158:89]
wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 163:92]
wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 187:111]
wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 187:109]
wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 187:142]
wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 187:126]
wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 190:68]
wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 190:112]
reg [2:0] _T_163; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 148:33]
reg [31:0] cmdbuf_addr; // @[el2_lib.scala 514:16]
reg [63:0] cmdbuf_wdata; // @[el2_lib.scala 514:16]
wire [1:0] cmdbuf_size = _T_163[1:0]; // @[ahb_to_axi4.scala 196:33]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 207:29]
assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 209:29]
assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 210:29]
assign io_axi_awprot = 3'h0; // @[ahb_to_axi4.scala 211:29]
assign io_axi_awlen = 8'h0; // @[ahb_to_axi4.scala 212:29]
assign io_axi_awburst = 2'h1; // @[ahb_to_axi4.scala 213:29]
assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 215:29]
assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 216:29]
assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 217:29]
assign io_axi_wlast = 1'h1; // @[ahb_to_axi4.scala 218:29]
assign io_axi_bready = 1'h1; // @[ahb_to_axi4.scala 220:29]
assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 222:29]
assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 224:29]
assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 225:29]
assign io_axi_arprot = 3'h0; // @[ahb_to_axi4.scala 226:29]
assign io_axi_arlen = 8'h0; // @[ahb_to_axi4.scala 227:29]
assign io_axi_arburst = 2'h1; // @[ahb_to_axi4.scala 228:29]
assign io_axi_rready = 1'h1; // @[ahb_to_axi4.scala 230:29]
assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 157:33]
assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 154:33]
assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 158:33]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_9; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[el2_lib.scala 510:18]
assign rvclkhdr_3_io_en = _T_6 ? 1'h0 : _GEN_11; // @[el2_lib.scala 511:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[el2_lib.scala 510:18]
assign rvclkhdr_4_io_en = _T_6 ? 1'h0 : _GEN_11; // @[el2_lib.scala 511:17]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_5_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
ahb_haddr_q = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
buf_state = _RAND_1[1:0];
_RAND_2 = {1{`RANDOM}};
cmdbuf_vld = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
cmdbuf_write = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
ahb_hsize_q = _RAND_4[2:0];
_RAND_5 = {1{`RANDOM}};
ahb_hready_q = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
ahb_hresp_q = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
buf_read_error = _RAND_7[0:0];
_RAND_8 = {2{`RANDOM}};
buf_rdata = _RAND_8[63:0];
_RAND_9 = {1{`RANDOM}};
ahb_htrans_q = _RAND_9[1:0];
_RAND_10 = {1{`RANDOM}};
ahb_hwrite_q = _RAND_10[0:0];
_RAND_11 = {1{`RANDOM}};
_T_163 = _RAND_11[2:0];
_RAND_12 = {1{`RANDOM}};
cmdbuf_wstrb = _RAND_12[7:0];
_RAND_13 = {1{`RANDOM}};
cmdbuf_addr = _RAND_13[31:0];
_RAND_14 = {2{`RANDOM}};
cmdbuf_wdata = _RAND_14[63:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
ahb_haddr_q = 32'h0;
end
if (reset) begin
buf_state = 2'h0;
end
if (reset) begin
cmdbuf_vld = 1'h0;
end
if (reset) begin
cmdbuf_write = 1'h0;
end
if (reset) begin
ahb_hsize_q = 3'h0;
end
if (reset) begin
ahb_hready_q = 1'h0;
end
if (reset) begin
ahb_hresp_q = 1'h0;
end
if (reset) begin
buf_read_error = 1'h0;
end
if (reset) begin
buf_rdata = 64'h0;
end
if (reset) begin
ahb_htrans_q = 2'h0;
end
if (reset) begin
ahb_hwrite_q = 1'h0;
end
if (reset) begin
_T_163 = 3'h0;
end
if (reset) begin
cmdbuf_wstrb = 8'h0;
end
if (reset) begin
cmdbuf_addr = 32'h0;
end
if (reset) begin
cmdbuf_wdata = 64'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge ahb_addr_clk or posedge reset) begin
if (reset) begin
ahb_haddr_q <= 32'h0;
end else begin
ahb_haddr_q <= io_ahb_haddr;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
buf_state <= 2'h0;
end else if (buf_state_en) begin
if (_T_6) begin
if (io_ahb_hwrite) begin
buf_state <= 2'h1;
end else begin
buf_state <= 2'h2;
end
end else if (_T_11) begin
if (_T_16) begin
buf_state <= 2'h0;
end else if (io_ahb_hwrite) begin
buf_state <= 2'h1;
end else begin
buf_state <= 2'h2;
end
end else if (_T_29) begin
if (io_ahb_hresp) begin
buf_state <= 2'h0;
end else begin
buf_state <= 2'h3;
end
end else begin
buf_state <= 2'h0;
end
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
cmdbuf_vld <= 1'h0;
end else begin
cmdbuf_vld <= _T_156 & _T_157;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
cmdbuf_write <= 1'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_write <= ahb_hwrite_q;
end
end
always @(posedge ahb_addr_clk or posedge reset) begin
if (reset) begin
ahb_hsize_q <= 3'h0;
end else begin
ahb_hsize_q <= io_ahb_hsize;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
ahb_hready_q <= 1'h0;
end else begin
ahb_hready_q <= io_ahb_hreadyout & io_ahb_hreadyin;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
ahb_hresp_q <= 1'h0;
end else begin
ahb_hresp_q <= io_ahb_hresp;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
buf_read_error <= 1'h0;
end else if (_T_6) begin
buf_read_error <= 1'h0;
end else if (_T_11) begin
buf_read_error <= 1'h0;
end else if (_T_29) begin
buf_read_error <= 1'h0;
end else begin
buf_read_error <= _GEN_3;
end
end
always @(posedge buf_rdata_clk or posedge reset) begin
if (reset) begin
buf_rdata <= 64'h0;
end else begin
buf_rdata <= io_axi_rdata;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
ahb_htrans_q <= 2'h0;
end else begin
ahb_htrans_q <= _T_88 & io_ahb_htrans;
end
end
always @(posedge ahb_addr_clk or posedge reset) begin
if (reset) begin
ahb_hwrite_q <= 1'h0;
end else begin
ahb_hwrite_q <= io_ahb_hwrite;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
_T_163 <= 3'h0;
end else if (cmdbuf_wr_en) begin
_T_163 <= ahb_hsize_q;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
cmdbuf_wstrb <= 8'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_wstrb <= master_wstrb;
end
end
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin
cmdbuf_addr <= 32'h0;
end else begin
cmdbuf_addr <= ahb_haddr_q;
end
end
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
if (reset) begin
cmdbuf_wdata <= 64'h0;
end else begin
cmdbuf_wdata <= io_ahb_hwdata;
end
end
endmodule

113
axi4_to_ahb.anno.json
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@ -1,113 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_araddr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arsize",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arprot"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1421
axi4_to_ahb.fir
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1127
axi4_to_ahb.v
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25
caller.anno.json
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@ -1,25 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~caller|caller>io_out",
"sources":[
"~caller|caller>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"caller"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

20
caller.fir
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@ -1,20 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit caller :
module rvdff :
input clock : Clock
input reset : Reset
output io : {flip in : UInt<32>, out : UInt}
io.out <= io.in @[GCD.scala 12:10]
module caller :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<32>, out : UInt}
inst u0 of rvdff @[GCD.scala 21:18]
u0.clock <= clock
u0.reset <= reset
io.out <= u0.io.out @[GCD.scala 22:6]
u0.io.in <= io.in @[GCD.scala 22:6]

21
caller.v
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@ -1,21 +0,0 @@
module rvdff(
input [31:0] io_in,
output [31:0] io_out
);
assign io_out = io_in; // @[GCD.scala 12:10]
endmodule
module caller(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out
);
wire [31:0] u0_io_in; // @[GCD.scala 21:18]
wire [31:0] u0_io_out; // @[GCD.scala 21:18]
rvdff u0 ( // @[GCD.scala 21:18]
.io_in(u0_io_in),
.io_out(u0_io_out)
);
assign io_out = u0_io_out; // @[GCD.scala 22:6]
assign u0_io_in = io_in; // @[GCD.scala 22:6]
endmodule

18
dmi_jtag_to_core_sync.anno.json
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@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_jtag_to_core_sync"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

39
dmi_jtag_to_core_sync.fir
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@ -1,39 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_jtag_to_core_sync :
module dmi_jtag_to_core_sync :
input clock : Clock
input reset : AsyncReset
output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
wire c_rd_en : UInt<1>
c_rd_en <= UInt<1>("h00")
wire c_wr_en : UInt<1>
c_wr_en <= UInt<1>("h00")
wire rden : UInt<3>
rden <= UInt<3>("h00")
wire wren : UInt<3>
wren <= UInt<3>("h00")
node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 26:18]
rden <= _T_2 @[dmi_jtag_to_core_sync.scala 26:8]
node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 27:27]
node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 27:18]
_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 27:18]
wren <= _T_5 @[dmi_jtag_to_core_sync.scala 27:8]
node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:17]
node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:28]
node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:23]
node _T_9 = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:21]
c_rd_en <= _T_9 @[dmi_jtag_to_core_sync.scala 28:10]
node _T_10 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:17]
node _T_11 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:28]
node _T_12 = eq(_T_11, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:23]
node _T_13 = and(_T_10, _T_12) @[dmi_jtag_to_core_sync.scala 29:21]
c_wr_en <= _T_13 @[dmi_jtag_to_core_sync.scala 29:10]
node _T_14 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:28]
io.reg_en <= _T_14 @[dmi_jtag_to_core_sync.scala 31:17]
io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:17]

87
dmi_jtag_to_core_sync.v
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@ -1,87 +0,0 @@
module dmi_jtag_to_core_sync(
input clock,
input reset,
input io_rd_en,
input io_wr_en,
output io_reg_en,
output io_reg_wr_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 26:18]
reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 27:18]
wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:23]
wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:21]
wire _T_12 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:23]
wire c_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 29:21]
assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 31:17]
assign io_reg_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 32:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rden = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wren = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
rden = 3'h0;
end
if (reset) begin
wren = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
rden <= 3'h0;
end else begin
rden <= {rden[1:0],io_rd_en};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wren <= 3'h0;
end else begin
wren <= {wren[1:0],io_wr_en};
end
end
endmodule

18
dmi_wrapper.anno.json
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@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_wrapper"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

88
dmi_wrapper.fir
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@ -1,88 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_wrapper :
module rvjtag_tap :
input clock : Clock
input reset : AsyncReset
output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, flip rd_data : UInt<32>, flip rd_status : UInt<2>, flip idle : UInt<3>, flip dmi_stat : UInt<2>, flip jtag_id : UInt<32>, flip version : UInt<4>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<7>, wr_en : UInt<1>, rd_en : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>}
io.tdo <= UInt<1>("h00") @[rvjtag_tap.scala 31:21]
io.tdoEnable <= UInt<1>("h00") @[rvjtag_tap.scala 32:21]
io.wr_data <= UInt<1>("h00") @[rvjtag_tap.scala 33:21]
io.wr_addr <= UInt<1>("h00") @[rvjtag_tap.scala 34:21]
io.wr_en <= UInt<1>("h00") @[rvjtag_tap.scala 35:21]
io.rd_en <= UInt<1>("h00") @[rvjtag_tap.scala 36:21]
io.dmi_reset <= UInt<1>("h00") @[rvjtag_tap.scala 37:21]
io.dmi_hard_reset <= UInt<1>("h00") @[rvjtag_tap.scala 38:21]
module dmi_jtag_to_core_sync :
input clock : Clock
input reset : AsyncReset
output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
io.reg_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 19:16]
io.reg_wr_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 20:16]
wire rden : UInt<3>
rden <= UInt<1>("h00")
wire wren : UInt<3>
wren <= UInt<1>("h00")
node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 25:27]
node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 25:18]
_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 25:18]
rden <= _T_2 @[dmi_jtag_to_core_sync.scala 25:8]
node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 26:18]
wren <= _T_5 @[dmi_jtag_to_core_sync.scala 26:8]
node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:21]
node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:32]
node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:27]
node c_rd_en = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:25]
node _T_9 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:21]
node _T_10 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:32]
node _T_11 = eq(_T_10, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:27]
node c_wr_en = and(_T_9, _T_11) @[dmi_jtag_to_core_sync.scala 29:25]
node _T_12 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:24]
io.reg_en <= _T_12 @[dmi_jtag_to_core_sync.scala 31:13]
io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:16]
module dmi_wrapper :
input clock : Clock
input reset : AsyncReset
output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip core_clk : Clock, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
wire rd_en : UInt<1>
rd_en <= UInt<1>("h00")
wire wr_en : UInt<1>
wr_en <= UInt<1>("h00")
wire dmireset : UInt<1>
dmireset <= UInt<1>("h00")
inst i_jtag_tap of rvjtag_tap @[dmi_wrapper.scala 33:27]
i_jtag_tap.clock <= clock
i_jtag_tap.reset <= reset
i_jtag_tap.io.tck <= io.tck @[dmi_wrapper.scala 36:27]
i_jtag_tap.io.tms <= io.tms @[dmi_wrapper.scala 37:27]
i_jtag_tap.io.tdi <= io.tdi @[dmi_wrapper.scala 38:27]
i_jtag_tap.io.rd_data <= io.rd_data @[dmi_wrapper.scala 39:27]
i_jtag_tap.io.rd_status <= UInt<2>("h00") @[dmi_wrapper.scala 40:27]
i_jtag_tap.io.idle <= UInt<3>("h00") @[dmi_wrapper.scala 41:27]
i_jtag_tap.io.dmi_stat <= UInt<2>("h00") @[dmi_wrapper.scala 42:27]
i_jtag_tap.io.jtag_id <= io.jtag_id @[dmi_wrapper.scala 43:27]
i_jtag_tap.io.version <= UInt<1>("h01") @[dmi_wrapper.scala 44:27]
io.tdo <= i_jtag_tap.io.tdo @[dmi_wrapper.scala 46:27]
io.tdoEnable <= i_jtag_tap.io.tdoEnable @[dmi_wrapper.scala 47:27]
io.reg_wr_data <= i_jtag_tap.io.wr_data @[dmi_wrapper.scala 48:27]
io.reg_wr_addr <= i_jtag_tap.io.wr_addr @[dmi_wrapper.scala 49:27]
rd_en <= i_jtag_tap.io.rd_en @[dmi_wrapper.scala 50:27]
wr_en <= i_jtag_tap.io.wr_en @[dmi_wrapper.scala 51:27]
io.dmi_hard_reset <= i_jtag_tap.io.dmi_hard_reset @[dmi_wrapper.scala 52:27]
dmireset <= i_jtag_tap.io.dmi_reset @[dmi_wrapper.scala 53:27]
inst i_dmi_jtag_to_core_sync of dmi_jtag_to_core_sync @[dmi_wrapper.scala 56:40]
i_dmi_jtag_to_core_sync.clock <= clock
i_dmi_jtag_to_core_sync.reset <= reset
i_dmi_jtag_to_core_sync.io.wr_en <= wr_en @[dmi_wrapper.scala 57:39]
i_dmi_jtag_to_core_sync.io.rd_en <= rd_en @[dmi_wrapper.scala 58:39]
io.reg_en <= i_dmi_jtag_to_core_sync.io.reg_en @[dmi_wrapper.scala 59:39]
io.reg_wr_en <= i_dmi_jtag_to_core_sync.io.reg_wr_en @[dmi_wrapper.scala 60:39]

122
dmi_wrapper.v
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@ -1,122 +0,0 @@
module dmi_jtag_to_core_sync(
input clock,
input reset,
output io_reg_en,
output io_reg_wr_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 25:18]
reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 26:18]
wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:27]
wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:25]
wire _T_11 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:27]
wire c_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 29:25]
assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 19:16 dmi_jtag_to_core_sync.scala 31:13]
assign io_reg_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 20:16 dmi_jtag_to_core_sync.scala 32:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rden = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wren = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
rden = 3'h0;
end
if (reset) begin
wren = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
rden <= 3'h0;
end else begin
rden <= {rden[1:0],1'h0};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wren <= 3'h0;
end else begin
wren <= {wren[1:0],1'h0};
end
end
endmodule
module dmi_wrapper(
input clock,
input reset,
input io_tck,
input io_tms,
input io_tdi,
output io_tdo,
output io_tdoEnable,
input io_core_clk,
input [31:0] io_jtag_id,
input [31:0] io_rd_data,
output [31:0] io_reg_wr_data,
output [6:0] io_reg_wr_addr,
output io_reg_en,
output io_reg_wr_en,
output io_dmi_hard_reset
);
wire i_dmi_jtag_to_core_sync_clock; // @[dmi_wrapper.scala 56:40]
wire i_dmi_jtag_to_core_sync_reset; // @[dmi_wrapper.scala 56:40]
wire i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 56:40]
wire i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 56:40]
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync ( // @[dmi_wrapper.scala 56:40]
.clock(i_dmi_jtag_to_core_sync_clock),
.reset(i_dmi_jtag_to_core_sync_reset),
.io_reg_en(i_dmi_jtag_to_core_sync_io_reg_en),
.io_reg_wr_en(i_dmi_jtag_to_core_sync_io_reg_wr_en)
);
assign io_tdo = 1'h0; // @[dmi_wrapper.scala 46:27]
assign io_tdoEnable = 1'h0; // @[dmi_wrapper.scala 47:27]
assign io_reg_wr_data = 32'h0; // @[dmi_wrapper.scala 48:27]
assign io_reg_wr_addr = 7'h0; // @[dmi_wrapper.scala 49:27]
assign io_reg_en = i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 59:39]
assign io_reg_wr_en = i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 60:39]
assign io_dmi_hard_reset = 1'h0; // @[dmi_wrapper.scala 52:27]
assign i_dmi_jtag_to_core_sync_clock = clock;
assign i_dmi_jtag_to_core_sync_reset = reset;
endmodule

23
dmi_wrapper_module.anno.json
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@ -1,23 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"dmi_wrapper_module.dmi_wrapper",
"resourceId":"/vsrc/dmi_wrapper.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_wrapper_module"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

59
dmi_wrapper_module.fir
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@ -1,59 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_wrapper_module :
extmodule dmi_wrapper :
input trst_n : UInt<1>
input tck : Clock
input tms : UInt<1>
input tdi : UInt<1>
output tdo : UInt<1>
output tdoEnable : UInt<1>
input core_rst_n : AsyncReset
input core_clk : Clock
input jtag_id : UInt<31>
input rd_data : UInt<32>
output reg_wr_data : UInt<32>
output reg_wr_addr : UInt<7>
output reg_en : UInt<1>
output reg_wr_en : UInt<1>
output dmi_hard_reset : UInt<1>
defname = dmi_wrapper
module dmi_wrapper_module :
input clock : Clock
input reset : UInt<1>
output io : {flip trst_n : UInt<1>, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip core_rst_n : AsyncReset, flip core_clk : Clock, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
inst dwrap of dmi_wrapper @[dmi_wrapper.scala 45:21]
dwrap.dmi_hard_reset is invalid
dwrap.reg_wr_en is invalid
dwrap.reg_en is invalid
dwrap.reg_wr_addr is invalid
dwrap.reg_wr_data is invalid
dwrap.rd_data is invalid
dwrap.jtag_id is invalid
dwrap.core_clk is invalid
dwrap.core_rst_n is invalid
dwrap.tdoEnable is invalid
dwrap.tdo is invalid
dwrap.tdi is invalid
dwrap.tms is invalid
dwrap.tck is invalid
dwrap.trst_n is invalid
io.dmi_hard_reset <= dwrap.dmi_hard_reset @[dmi_wrapper.scala 46:12]
io.reg_wr_en <= dwrap.reg_wr_en @[dmi_wrapper.scala 46:12]
io.reg_en <= dwrap.reg_en @[dmi_wrapper.scala 46:12]
io.reg_wr_addr <= dwrap.reg_wr_addr @[dmi_wrapper.scala 46:12]
io.reg_wr_data <= dwrap.reg_wr_data @[dmi_wrapper.scala 46:12]
dwrap.rd_data <= io.rd_data @[dmi_wrapper.scala 46:12]
dwrap.jtag_id <= io.jtag_id @[dmi_wrapper.scala 46:12]
dwrap.core_clk <= io.core_clk @[dmi_wrapper.scala 46:12]
dwrap.core_rst_n <= io.core_rst_n @[dmi_wrapper.scala 46:12]
io.tdoEnable <= dwrap.tdoEnable @[dmi_wrapper.scala 46:12]
io.tdo <= dwrap.tdo @[dmi_wrapper.scala 46:12]
dwrap.tdi <= io.tdi @[dmi_wrapper.scala 46:12]
dwrap.tms <= io.tms @[dmi_wrapper.scala 46:12]
dwrap.tck <= io.tck @[dmi_wrapper.scala 46:12]
dwrap.trst_n <= io.trst_n @[dmi_wrapper.scala 46:12]

67
dmi_wrapper_module.v
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@ -1,67 +0,0 @@
module dmi_wrapper_module(
input clock,
input reset,
input io_trst_n,
input io_tck,
input io_tms,
input io_tdi,
output io_tdo,
output io_tdoEnable,
input io_core_rst_n,
input io_core_clk,
input [31:0] io_jtag_id,
input [31:0] io_rd_data,
output [31:0] io_reg_wr_data,
output [6:0] io_reg_wr_addr,
output io_reg_en,
output io_reg_wr_en,
output io_dmi_hard_reset
);
wire dwrap_trst_n; // @[dmi_wrapper.scala 45:21]
wire dwrap_tck; // @[dmi_wrapper.scala 45:21]
wire dwrap_tms; // @[dmi_wrapper.scala 45:21]
wire dwrap_tdi; // @[dmi_wrapper.scala 45:21]
wire dwrap_tdo; // @[dmi_wrapper.scala 45:21]
wire dwrap_tdoEnable; // @[dmi_wrapper.scala 45:21]
wire dwrap_core_rst_n; // @[dmi_wrapper.scala 45:21]
wire dwrap_core_clk; // @[dmi_wrapper.scala 45:21]
wire [30:0] dwrap_jtag_id; // @[dmi_wrapper.scala 45:21]
wire [31:0] dwrap_rd_data; // @[dmi_wrapper.scala 45:21]
wire [31:0] dwrap_reg_wr_data; // @[dmi_wrapper.scala 45:21]
wire [6:0] dwrap_reg_wr_addr; // @[dmi_wrapper.scala 45:21]
wire dwrap_reg_en; // @[dmi_wrapper.scala 45:21]
wire dwrap_reg_wr_en; // @[dmi_wrapper.scala 45:21]
wire dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 45:21]
dmi_wrapper dwrap ( // @[dmi_wrapper.scala 45:21]
.trst_n(dwrap_trst_n),
.tck(dwrap_tck),
.tms(dwrap_tms),
.tdi(dwrap_tdi),
.tdo(dwrap_tdo),
.tdoEnable(dwrap_tdoEnable),
.core_rst_n(dwrap_core_rst_n),
.core_clk(dwrap_core_clk),
.jtag_id(dwrap_jtag_id),
.rd_data(dwrap_rd_data),
.reg_wr_data(dwrap_reg_wr_data),
.reg_wr_addr(dwrap_reg_wr_addr),
.reg_en(dwrap_reg_en),
.reg_wr_en(dwrap_reg_wr_en),
.dmi_hard_reset(dwrap_dmi_hard_reset)
);
assign io_tdo = dwrap_tdo; // @[dmi_wrapper.scala 46:12]
assign io_tdoEnable = dwrap_tdoEnable; // @[dmi_wrapper.scala 46:12]
assign io_reg_wr_data = dwrap_reg_wr_data; // @[dmi_wrapper.scala 46:12]
assign io_reg_wr_addr = dwrap_reg_wr_addr; // @[dmi_wrapper.scala 46:12]
assign io_reg_en = dwrap_reg_en; // @[dmi_wrapper.scala 46:12]
assign io_reg_wr_en = dwrap_reg_wr_en; // @[dmi_wrapper.scala 46:12]
assign io_dmi_hard_reset = dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 46:12]
assign dwrap_trst_n = io_trst_n; // @[dmi_wrapper.scala 46:12]
assign dwrap_tck = io_tck; // @[dmi_wrapper.scala 46:12]
assign dwrap_tms = io_tms; // @[dmi_wrapper.scala 46:12]
assign dwrap_tdi = io_tdi; // @[dmi_wrapper.scala 46:12]
assign dwrap_core_rst_n = io_core_rst_n; // @[dmi_wrapper.scala 46:12]
assign dwrap_core_clk = io_core_clk; // @[dmi_wrapper.scala 46:12]
assign dwrap_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 46:12]
assign dwrap_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:12]
endmodule

51
el2_dbg.anno.json
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@ -1,51 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"sources":[
"~el2_dbg|el2_dbg>io_dma_dbg_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dbg|el2_dbg>io_dbg_resume_req",
"sources":[
"~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only",
"~el2_dbg|el2_dbg>io_dec_tlu_debug_mode",
"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"~el2_dbg|el2_dbg>io_core_dbg_cmd_done",
"~el2_dbg|el2_dbg>io_dmi_reg_wr_en",
"~el2_dbg|el2_dbg>io_dmi_reg_en",
"~el2_dbg|el2_dbg>io_dma_dbg_ready",
"~el2_dbg|el2_dbg>io_dmi_reg_addr",
"~el2_dbg|el2_dbg>reset"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dbg.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dbg"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_dec.anno.json
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el2_dec.v
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368
el2_dec_dec_ctl.anno.json
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@ -1,368 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rd",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_presync",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs1_sign",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs2",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_pc",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_load",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_clr",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_alu",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_mul",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_imm12",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_beq",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_sra",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_ebreak",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_by",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_sub",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_write",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_sll",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_slt",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_fence",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rem",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_store",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_jal",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_blt",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_fence_i",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_unsign",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_lxor",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_mret",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs1",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_imm",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_bge",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_pm_alu",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_div",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_add",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_land",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_half",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_word",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_bne",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_read",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_lor",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_set",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_srl",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_low",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_ecall",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_condbr",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_legal",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_lsu",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_postsync",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_imm20",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs2_sign",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_shimm5",
"sources":[
"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_dec_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2041
el2_dec_dec_ctl.fir
View File

File diff suppressed because it is too large Load Diff

704
el2_dec_dec_ctl.v
View File

@ -1,704 +0,0 @@
module el2_dec_dec_ctl(
input clock,
input reset,
input [31:0] io_ins,
output io_out_alu,
output io_out_rs1,
output io_out_rs2,
output io_out_imm12,
output io_out_rd,
output io_out_shimm5,
output io_out_imm20,
output io_out_pc,
output io_out_load,
output io_out_store,
output io_out_lsu,
output io_out_add,
output io_out_sub,
output io_out_land,
output io_out_lor,
output io_out_lxor,
output io_out_sll,
output io_out_sra,
output io_out_srl,
output io_out_slt,
output io_out_unsign,
output io_out_condbr,
output io_out_beq,
output io_out_bne,
output io_out_bge,
output io_out_blt,
output io_out_jal,
output io_out_by,
output io_out_half,
output io_out_word,
output io_out_csr_read,
output io_out_csr_clr,
output io_out_csr_set,
output io_out_csr_write,
output io_out_csr_imm,
output io_out_presync,
output io_out_postsync,
output io_out_ebreak,
output io_out_ecall,
output io_out_mret,
output io_out_mul,
output io_out_rs1_sign,
output io_out_rs2_sign,
output io_out_low,
output io_out_div,
output io_out_rem,
output io_out_fence,
output io_out_fence_i,
output io_out_pm_alu,
output io_out_legal
);
wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27]
wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42]
wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53]
wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39]
wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68]
wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78]
wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51]
wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51]
wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90]
wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90]
wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55]
wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37]
wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37]
wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94]
wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76]
wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76]
wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41]
wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38]
wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38]
wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80]
wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76]
wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76]
wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42]
wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37]
wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37]
wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80]
wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75]
wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75]
wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41]
wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37]
wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37]
wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79]
wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75]
wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75]
wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41]
wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37]
wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37]
wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79]
wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71]
wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41]
wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106]
wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48]
wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48]
wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85]
wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85]
wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50]
wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90]
wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90]
wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90]
wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54]
wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40]
wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40]
wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40]
wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94]
wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81]
wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81]
wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81]
wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28]
wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55]
wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42]
wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58]
wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58]
wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58]
wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29]
wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53]
wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28]
wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41]
wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50]
wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49]
wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57]
wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57]
wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57]
wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61]
wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56]
wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57]
wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105]
wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61]
wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43]
wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109]
wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80]
wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80]
wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56]
wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104]
wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45]
wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94]
wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94]
wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94]
wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49]
wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34]
wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34]
wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98]
wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38]
wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44]
wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44]
wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44]
wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61]
wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109]
wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63]
wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58]
wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66]
wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62]
wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59]
wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59]
wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59]
wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99]
wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99]
wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99]
wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63]
wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37]
wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37]
wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103]
wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86]
wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41]
wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45]
wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56]
wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56]
wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56]
wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55]
wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55]
wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55]
wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54]
wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54]
wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54]
wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55]
wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55]
wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55]
wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56]
wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56]
wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53]
wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53]
wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50]
wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52]
wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87]
wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87]
wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56]
wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34]
wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34]
wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91]
wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69]
wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69]
wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38]
wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105]
wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105]
wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73]
wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35]
wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35]
wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57]
wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57]
wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57]
wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99]
wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99]
wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99]
wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61]
wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41]
wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41]
wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41]
wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103]
wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81]
wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81]
wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81]
wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45]
wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39]
wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39]
wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39]
wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57]
wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55]
wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55]
wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94]
wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94]
wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94]
wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59]
wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38]
wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38]
wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38]
wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98]
wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77]
wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77]
wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77]
wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42]
wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38]
wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38]
wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38]
wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81]
wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77]
wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77]
wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77]
wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55]
wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55]
wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55]
wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95]
wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95]
wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95]
wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59]
wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39]
wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39]
wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39]
wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99]
wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43]
wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62]
wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62]
wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56]
wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56]
wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56]
wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57]
wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69]
wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50]
wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62]
wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62]
wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62]
wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54]
wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54]
wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57]
wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57]
wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57]
wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47]
wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52]
wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52]
wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59]
wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63]
wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37]
wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37]
wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96]
wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88]
wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88]
wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53]
wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38]
wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38]
wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92]
wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77]
wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77]
wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42]
wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81]
wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78]
wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78]
wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42]
wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39]
wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39]
wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82]
wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78]
wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78]
wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43]
wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38]
wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38]
wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82]
wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77]
wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77]
wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42]
wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38]
wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38]
wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38]
wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81]
wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77]
wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77]
wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98]
wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57]
wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102]
wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42]
wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81]
wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42]
wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82]
wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43]
wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82]
wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42]
wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81]
wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144]
wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130]
wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148]
wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45]
wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127]
wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134]
wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68]
wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131]
wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77]
wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72]
wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74]
wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81]
wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66]
wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78]
wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54]
wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70]
wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48]
wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58]
wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47]
wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52]
wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99]
wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51]
wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47]
wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103]
wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142]
wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51]
wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110]
wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146]
wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51]
wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114]
wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95]
wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55]
wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46]
wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99]
wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99]
wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50]
wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43]
wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43]
assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14]
assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14]
assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14]
assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16]
assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13]
assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17]
assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16]
assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13]
assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15]
assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16]
assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14]
assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14]
assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14]
assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15]
assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14]
assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15]
assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14]
assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14]
assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14]
assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14]
assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17]
assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17]
assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14]
assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14]
assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14]
assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14]
assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14]
assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13]
assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15]
assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15]
assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19]
assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18]
assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18]
assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20]
assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18]
assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18]
assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19]
assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17]
assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16]
assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15]
assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14]
assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19]
assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19]
assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14]
assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14]
assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14]
assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16]
assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18]
assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17]
assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16]
endmodule

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el2_dec_gpr_ctl.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd1",
"sources":[
"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd0",
"sources":[
"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr0"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dec_gpr_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_gpr_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_dec_gpr_ctl.v
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el2_dec_ib_ctl.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_wdata_rs1_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_way",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_way"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_br_error",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_br_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_dbecc_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_dbecc"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_hist",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_hist"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_toffset",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_toffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_f1_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_f1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_btag",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_btag"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc4_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc4"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_ib0_valid_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_valid",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_instr_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_instr",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_prett",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_prett"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_fghr",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_fghr"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_br_start_error",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_br_start_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_ret",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_ret"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_index",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_index"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_type_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_type"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_valid",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_bank",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_bank"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_fence_d",
"sources":[
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr",
"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_ib_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

71
el2_dec_ib_ctl.fir
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@ -1,71 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_dec_ib_ctl :
module el2_dec_ib_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31]
io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31]
io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 10:31]
io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31]
io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31]
io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31]
io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31]
io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31]
io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31]
io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 17:31]
node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 31:60]
node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 31:41]
node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 32:38]
node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 32:36]
node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 33:36]
node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 35:55]
node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 35:37]
node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 36:55]
node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 36:37]
node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 37:55]
node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 37:37]
node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 38:55]
node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 38:37]
node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 40:40]
node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 41:40]
node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 44:20]
node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 45:21]
node _T_11 = cat(UInt<3>("h06"), dreg) @[Cat.scala 29:58]
node _T_12 = cat(_T_11, UInt<6>("h033")) @[Cat.scala 29:58]
node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 46:20]
node _T_14 = cat(dcsr, UInt<14>("h02073")) @[Cat.scala 29:58]
node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 47:21]
node _T_16 = cat(dcsr, UInt<13>("h01073")) @[Cat.scala 29:58]
node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
ib0_debug_in <= _T_23 @[Mux.scala 27:72]
node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 51:47]
io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 51:28]
node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 54:51]
node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 54:43]
io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 54:24]
node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 56:41]
io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 56:22]
node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 57:41]
node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 57:28]
io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 57:22]

101
el2_dec_ib_ctl.v
View File

@ -1,101 +0,0 @@
module el2_dec_ib_ctl(
input clock,
input reset,
input io_dbg_cmd_valid,
input io_dbg_cmd_write,
input [1:0] io_dbg_cmd_type,
input [31:0] io_dbg_cmd_addr,
input io_i0_brp_valid,
input [11:0] io_i0_brp_bits_toffset,
input [1:0] io_i0_brp_bits_hist,
input io_i0_brp_bits_br_error,
input io_i0_brp_bits_br_start_error,
input io_i0_brp_bits_bank,
input [30:0] io_i0_brp_bits_prett,
input io_i0_brp_bits_way,
input io_i0_brp_bits_ret,
input [7:0] io_ifu_i0_bp_index,
input [7:0] io_ifu_i0_bp_fghr,
input [4:0] io_ifu_i0_bp_btag,
input io_ifu_i0_pc4,
input io_ifu_i0_valid,
input io_ifu_i0_icaf,
input [1:0] io_ifu_i0_icaf_type,
input io_ifu_i0_icaf_f1,
input io_ifu_i0_dbecc,
input [31:0] io_ifu_i0_instr,
input [30:0] io_ifu_i0_pc,
output io_dec_ib0_valid_d,
output [1:0] io_dec_i0_icaf_type_d,
output [31:0] io_dec_i0_instr_d,
output [30:0] io_dec_i0_pc_d,
output io_dec_i0_pc4_d,
output io_dec_i0_brp_valid,
output [11:0] io_dec_i0_brp_bits_toffset,
output [1:0] io_dec_i0_brp_bits_hist,
output io_dec_i0_brp_bits_br_error,
output io_dec_i0_brp_bits_br_start_error,
output io_dec_i0_brp_bits_bank,
output [30:0] io_dec_i0_brp_bits_prett,
output io_dec_i0_brp_bits_way,
output io_dec_i0_brp_bits_ret,
output [7:0] io_dec_i0_bp_index,
output [7:0] io_dec_i0_bp_fghr,
output [4:0] io_dec_i0_bp_btag,
output io_dec_i0_icaf_d,
output io_dec_i0_icaf_f1_d,
output io_dec_i0_dbecc_d,
output io_dec_debug_wdata_rs1_d,
output io_dec_debug_fence_d
);
wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60]
wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41]
wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38]
wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36]
wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36]
wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55]
wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37]
wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37]
wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55]
wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37]
wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37]
wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40]
wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40]
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58]
wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58]
wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58]
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72]
wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72]
wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72]
wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72]
wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72]
wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72]
wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72]
wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72]
wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72]
wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51]
assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22]
assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31]
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22]
assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31]
assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31]
assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_bank = io_i0_brp_bits_bank; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 14:31]
assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31]
assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31]
assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31]
assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31]
assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31]
assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31]
assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28]
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24]
endmodule

521
el2_dec_tlu_ctl.anno.json
View File

@ -1,521 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_leak_one_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_hist_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_core_id",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_way",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_fence_i_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt2",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_path_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_npc_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt1",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_lower_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt0",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_i0_commit_cmt",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_valid",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_mp_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_pmu_i0_br_ataken"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_err_wb",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_wr_pause_r",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_lower_wb",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_tlu_exu_exu_i0_br_middle_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3",
"sources":[
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dec_tlu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_tlu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

8166
el2_dec_tlu_ctl.fir
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7133
el2_dec_tlu_ctl.v
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51
el2_dec_trigger.anno.json
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@ -1,51 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_trigger_match_d",
"sources":[
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_pkt",
"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_trigger"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1457
el2_dec_trigger.fir
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613
el2_dec_trigger.v
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@ -1,613 +0,0 @@
module el2_dec_trigger(
input clock,
input reset,
input io_trigger_pkt_any_0_select,
input io_trigger_pkt_any_0_match_pkt,
input io_trigger_pkt_any_0_store,
input io_trigger_pkt_any_0_load,
input io_trigger_pkt_any_0_execute,
input io_trigger_pkt_any_0_m,
input [31:0] io_trigger_pkt_any_0_tdata2,
input io_trigger_pkt_any_1_select,
input io_trigger_pkt_any_1_match_pkt,
input io_trigger_pkt_any_1_store,
input io_trigger_pkt_any_1_load,
input io_trigger_pkt_any_1_execute,
input io_trigger_pkt_any_1_m,
input [31:0] io_trigger_pkt_any_1_tdata2,
input io_trigger_pkt_any_2_select,
input io_trigger_pkt_any_2_match_pkt,
input io_trigger_pkt_any_2_store,
input io_trigger_pkt_any_2_load,
input io_trigger_pkt_any_2_execute,
input io_trigger_pkt_any_2_m,
input [31:0] io_trigger_pkt_any_2_tdata2,
input io_trigger_pkt_any_3_select,
input io_trigger_pkt_any_3_match_pkt,
input io_trigger_pkt_any_3_store,
input io_trigger_pkt_any_3_load,
input io_trigger_pkt_any_3_execute,
input io_trigger_pkt_any_3_m,
input [31:0] io_trigger_pkt_any_3_tdata2,
input [30:0] io_dec_i0_pc_d,
output [3:0] io_dec_i0_trigger_match_d
);
wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63]
wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127]
wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63]
wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127]
wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63]
wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127]
wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63]
wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93]
wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127]
wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83]
wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45]
wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39]
wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37]
wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52]
wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41]
wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36]
wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 244:41]
wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 244:78]
wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 244:23]
wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36]
wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 244:41]
wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 244:78]
wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 244:23]
wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36]
wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 244:41]
wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 244:78]
wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 244:23]
wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36]
wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 244:41]
wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 244:78]
wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 244:23]
wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36]
wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 244:41]
wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 244:78]
wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 244:23]
wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36]
wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 244:41]
wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 244:78]
wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 244:23]
wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36]
wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 244:41]
wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 244:78]
wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 244:23]
wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36]
wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 244:41]
wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 244:78]
wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 244:23]
wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36]
wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 244:41]
wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 244:78]
wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 244:23]
wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36]
wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 244:41]
wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 244:78]
wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 244:23]
wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36]
wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 244:41]
wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 244:78]
wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 244:23]
wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36]
wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 244:41]
wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 244:78]
wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 244:23]
wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36]
wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 244:41]
wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 244:78]
wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 244:23]
wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36]
wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 244:41]
wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 244:78]
wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 244:23]
wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36]
wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 244:41]
wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 244:78]
wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 244:23]
wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36]
wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 244:41]
wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 244:78]
wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 244:23]
wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36]
wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 244:41]
wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 244:78]
wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 244:23]
wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36]
wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 244:41]
wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 244:78]
wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 244:23]
wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36]
wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 244:41]
wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 244:78]
wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 244:23]
wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36]
wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 244:41]
wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 244:78]
wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 244:23]
wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36]
wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 244:41]
wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 244:78]
wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 244:23]
wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36]
wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 244:41]
wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 244:78]
wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 244:23]
wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36]
wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 244:41]
wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 244:78]
wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 244:23]
wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36]
wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 244:41]
wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 244:78]
wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 244:23]
wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36]
wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 244:41]
wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 244:78]
wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 244:23]
wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36]
wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 244:41]
wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 244:78]
wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 244:23]
wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36]
wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 244:41]
wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 244:78]
wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 244:23]
wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36]
wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 244:41]
wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 244:78]
wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 244:23]
wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36]
wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 244:41]
wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 244:78]
wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 244:23]
wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36]
wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 244:41]
wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 244:78]
wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 244:23]
wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36]
wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 244:41]
wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 244:78]
wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 244:23]
wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 245:14]
wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 245:14]
wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 245:14]
wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 245:14]
wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109]
wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83]
wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45]
wire _T_411 = ~_T_410; // @[el2_lib.scala 241:39]
wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[el2_lib.scala 241:37]
wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52]
wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 242:41]
wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36]
wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 244:41]
wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 244:78]
wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 244:23]
wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36]
wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 244:41]
wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 244:78]
wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 244:23]
wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36]
wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 244:41]
wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 244:78]
wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 244:23]
wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36]
wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 244:41]
wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 244:78]
wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 244:23]
wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36]
wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 244:41]
wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 244:78]
wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 244:23]
wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36]
wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 244:41]
wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 244:78]
wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 244:23]
wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36]
wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 244:41]
wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 244:78]
wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 244:23]
wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36]
wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 244:41]
wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 244:78]
wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 244:23]
wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36]
wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 244:41]
wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 244:78]
wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 244:23]
wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36]
wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 244:41]
wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 244:78]
wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 244:23]
wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36]
wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 244:41]
wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 244:78]
wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 244:23]
wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36]
wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 244:41]
wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 244:78]
wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 244:23]
wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36]
wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 244:41]
wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 244:78]
wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 244:23]
wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36]
wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 244:41]
wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 244:78]
wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 244:23]
wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36]
wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 244:41]
wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 244:78]
wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 244:23]
wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36]
wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 244:41]
wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 244:78]
wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 244:23]
wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36]
wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 244:41]
wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 244:78]
wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 244:23]
wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36]
wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 244:41]
wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 244:78]
wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 244:23]
wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36]
wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 244:41]
wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 244:78]
wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 244:23]
wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36]
wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 244:41]
wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 244:78]
wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 244:23]
wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36]
wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 244:41]
wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 244:78]
wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 244:23]
wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36]
wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 244:41]
wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 244:78]
wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 244:23]
wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36]
wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 244:41]
wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 244:78]
wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 244:23]
wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36]
wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 244:41]
wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 244:78]
wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 244:23]
wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36]
wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 244:41]
wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 244:78]
wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 244:23]
wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36]
wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 244:41]
wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 244:78]
wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 244:23]
wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36]
wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 244:41]
wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 244:78]
wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 244:23]
wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36]
wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 244:41]
wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 244:78]
wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 244:23]
wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36]
wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 244:41]
wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 244:78]
wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 244:23]
wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36]
wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 244:41]
wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 244:78]
wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 244:23]
wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36]
wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 244:41]
wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 244:78]
wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 244:23]
wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 245:14]
wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 245:14]
wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 245:14]
wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 245:14]
wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109]
wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83]
wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45]
wire _T_670 = ~_T_669; // @[el2_lib.scala 241:39]
wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[el2_lib.scala 241:37]
wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52]
wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 242:41]
wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36]
wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 244:41]
wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 244:78]
wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 244:23]
wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36]
wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 244:41]
wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 244:78]
wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 244:23]
wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36]
wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 244:41]
wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 244:78]
wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 244:23]
wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36]
wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 244:41]
wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 244:78]
wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 244:23]
wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36]
wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 244:41]
wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 244:78]
wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 244:23]
wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36]
wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 244:41]
wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 244:78]
wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 244:23]
wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36]
wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 244:41]
wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 244:78]
wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 244:23]
wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36]
wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 244:41]
wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 244:78]
wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 244:23]
wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36]
wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 244:41]
wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 244:78]
wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 244:23]
wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36]
wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 244:41]
wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 244:78]
wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 244:23]
wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36]
wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 244:41]
wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 244:78]
wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 244:23]
wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36]
wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 244:41]
wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 244:78]
wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 244:23]
wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36]
wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 244:41]
wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 244:78]
wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 244:23]
wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36]
wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 244:41]
wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 244:78]
wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 244:23]
wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36]
wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 244:41]
wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 244:78]
wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 244:23]
wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36]
wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 244:41]
wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 244:78]
wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 244:23]
wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36]
wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 244:41]
wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 244:78]
wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 244:23]
wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36]
wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 244:41]
wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 244:78]
wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 244:23]
wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36]
wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 244:41]
wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 244:78]
wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 244:23]
wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36]
wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 244:41]
wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 244:78]
wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 244:23]
wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36]
wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 244:41]
wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 244:78]
wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 244:23]
wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36]
wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 244:41]
wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 244:78]
wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 244:23]
wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36]
wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 244:41]
wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 244:78]
wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 244:23]
wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36]
wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 244:41]
wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 244:78]
wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 244:23]
wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36]
wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 244:41]
wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 244:78]
wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 244:23]
wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36]
wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 244:41]
wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 244:78]
wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 244:23]
wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36]
wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 244:41]
wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 244:78]
wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 244:23]
wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36]
wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 244:41]
wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 244:78]
wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 244:23]
wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36]
wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 244:41]
wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 244:78]
wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 244:23]
wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36]
wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 244:41]
wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 244:78]
wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 244:23]
wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36]
wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 244:41]
wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 244:78]
wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 244:23]
wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 245:14]
wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 245:14]
wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 245:14]
wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 245:14]
wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109]
wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83]
wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45]
wire _T_929 = ~_T_928; // @[el2_lib.scala 241:39]
wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[el2_lib.scala 241:37]
wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52]
wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 242:41]
wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36]
wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 244:41]
wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 244:78]
wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 244:23]
wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36]
wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 244:41]
wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 244:78]
wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 244:23]
wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36]
wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 244:41]
wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 244:78]
wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 244:23]
wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36]
wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 244:41]
wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 244:78]
wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 244:23]
wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36]
wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 244:41]
wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 244:78]
wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 244:23]
wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36]
wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 244:41]
wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 244:78]
wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 244:23]
wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36]
wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 244:41]
wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 244:78]
wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 244:23]
wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36]
wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 244:41]
wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 244:78]
wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 244:23]
wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36]
wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 244:41]
wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 244:78]
wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 244:23]
wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36]
wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 244:78]
wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 244:23]
wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36]
wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 244:78]
wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 244:23]
wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36]
wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 244:78]
wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 244:23]
wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36]
wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 244:78]
wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 244:23]
wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36]
wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 244:78]
wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 244:23]
wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36]
wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 244:78]
wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 244:23]
wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36]
wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 244:78]
wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 244:23]
wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36]
wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 244:78]
wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 244:23]
wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36]
wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 244:78]
wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 244:23]
wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36]
wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 244:78]
wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 244:23]
wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36]
wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 244:78]
wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 244:23]
wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36]
wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 244:78]
wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 244:23]
wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36]
wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 244:78]
wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 244:23]
wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36]
wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 244:78]
wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 244:23]
wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36]
wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 244:78]
wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 244:23]
wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36]
wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 244:78]
wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 244:23]
wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36]
wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 244:78]
wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 244:23]
wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36]
wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 244:78]
wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 244:23]
wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36]
wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 244:78]
wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 244:23]
wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36]
wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 244:78]
wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 244:23]
wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36]
wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 244:78]
wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 244:23]
wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36]
wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 244:41]
wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 244:78]
wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 244:23]
wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 245:14]
wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 245:14]
wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 245:14]
wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 245:14]
wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109]
wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109]
wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58]
assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29]
endmodule

130
el2_dma_ctrl.anno.json
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@ -1,130 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dma_ctrl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dma_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2269
el2_dma_ctrl.fir
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File diff suppressed because it is too large Load Diff

2049
el2_dma_ctrl.v
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File diff suppressed because it is too large Load Diff

135
el2_exu.anno.json
View File

@ -1,135 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_div_wren",
"sources":[
"~el2_exu|el2_exu>io_dec_div_cancel"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_flush_final",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
"~el2_exu|el2_exu>io_dec_i0_alu_decode_d",
"~el2_exu|el2_exu>io_i0_ap_jal",
"~el2_exu|el2_exu>io_i0_ap_predict_t",
"~el2_exu|el2_exu>io_i0_ap_predict_nt",
"~el2_exu|el2_exu>io_i0_ap_bge",
"~el2_exu|el2_exu>io_i0_ap_sub",
"~el2_exu|el2_exu>io_i0_ap_blt",
"~el2_exu|el2_exu>io_i0_ap_beq",
"~el2_exu|el2_exu>io_i0_ap_bne",
"~el2_exu|el2_exu>io_i0_ap_unsign",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pret",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_prett",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pja",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pcall",
"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
"~el2_exu|el2_exu>io_dec_i0_immed_d",
"~el2_exu|el2_exu>io_dbg_cmd_wrdata",
"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_pc_d",
"~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
"~el2_exu|el2_exu>io_dec_i0_select_pc_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_mp_fghr",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_lsu_rs1_d",
"sources":[
"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
"~el2_exu|el2_exu>io_dec_extint_stall",
"~el2_exu|el2_exu>io_dec_tlu_meihap",
"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d",
"sources":[
"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
"~el2_exu|el2_exu>io_dec_extint_stall",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu|el2_exu>io_exu_flush_path_final",
"sources":[
"~el2_exu|el2_exu>io_dec_tlu_flush_path_r",
"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
"~el2_exu|el2_exu>io_i0_ap_jal",
"~el2_exu|el2_exu>io_i0_ap_sub",
"~el2_exu|el2_exu>io_dec_i0_pc_d",
"~el2_exu|el2_exu>io_dec_i0_br_immed_d",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pret",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pja",
"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pcall",
"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
"~el2_exu|el2_exu>io_dec_i0_immed_d",
"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
"~el2_exu|el2_exu>io_dbg_cmd_wrdata",
"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
"~el2_exu|el2_exu>io_exu_i0_result_x",
"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
"~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
"~el2_exu|el2_exu>io_dec_i0_select_pc_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_exu|el2_exu>i0_rs2_d"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

244
el2_exu_alu_ctl.anno.json
View File

@ -1,244 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_hist",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_hist",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_valid",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_final_out",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_ataken",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_toffset",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_toffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_out",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_path_out",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pret",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pja",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pc4",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pc4"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_misp",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_way",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_way"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pcall",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_br_start_error",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_br_start_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_br_error",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_br_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_prett",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_boffset",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_boffset"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_alu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_alu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

568
el2_exu_alu_ctl.fir
View File

@ -1,568 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu_alu_ctl :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module el2_exu_alu_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}}
node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17]
rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24]
reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_1 <= io.pc_in @[el2_lib.scala 514:16]
io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12]
wire result : UInt<32>
result <= UInt<1>("h00")
node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17]
rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24]
reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_3 <= result @[el2_lib.scala 514:16]
io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16]
node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29]
node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37]
node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17]
wire aout : UInt<33>
aout <= UInt<1>("h00")
node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25]
node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58]
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70]
node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58]
node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55]
node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55]
node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80]
node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80]
node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58]
node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58]
node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58]
node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132]
node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132]
node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157]
node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157]
node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14]
aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8]
node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18]
node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22]
node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:14]
node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32]
node _T_28 = eq(_T_27, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:29]
node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27]
node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44]
node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37]
node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61]
node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71]
node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66]
node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:78]
node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76]
node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50]
node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50]
node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38]
node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29]
node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34]
node _T_39 = eq(io.ap.unsign, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:30]
node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51]
node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44]
node _T_42 = eq(cout, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:78]
node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76]
node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58]
node ge = eq(lt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 51:29]
node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19]
node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50]
node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16]
node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50]
node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39]
node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39]
node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15]
node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50]
node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39]
node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39]
node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16]
node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50]
node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39]
node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39]
wire _T_58 : SInt<32> @[Mux.scala 27:72]
node _T_59 = asUInt(_T_45) @[Mux.scala 27:72]
node _T_60 = asSInt(_T_59) @[Mux.scala 27:72]
_T_58 <= _T_60 @[Mux.scala 27:72]
wire _T_61 : SInt<32> @[Mux.scala 27:72]
node _T_62 = asUInt(_T_49) @[Mux.scala 27:72]
node _T_63 = asSInt(_T_62) @[Mux.scala 27:72]
_T_61 <= _T_63 @[Mux.scala 27:72]
wire _T_64 : SInt<32> @[Mux.scala 27:72]
node _T_65 = asUInt(_T_53) @[Mux.scala 27:72]
node _T_66 = asSInt(_T_65) @[Mux.scala 27:72]
_T_64 <= _T_66 @[Mux.scala 27:72]
wire _T_67 : SInt<32> @[Mux.scala 27:72]
node _T_68 = asUInt(_T_57) @[Mux.scala 27:72]
node _T_69 = asSInt(_T_68) @[Mux.scala 27:72]
_T_67 <= _T_69 @[Mux.scala 27:72]
node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72]
node _T_75 = asSInt(_T_74) @[Mux.scala 27:72]
node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72]
node _T_77 = asSInt(_T_76) @[Mux.scala 27:72]
node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72]
node _T_79 = asSInt(_T_78) @[Mux.scala 27:72]
wire lout : SInt<32> @[Mux.scala 27:72]
node _T_80 = asUInt(_T_79) @[Mux.scala 27:72]
node _T_81 = asSInt(_T_80) @[Mux.scala 27:72]
lout <= _T_81 @[Mux.scala 27:72]
node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15]
node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60]
node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58]
node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38]
node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38]
node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15]
node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60]
node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58]
node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15]
node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60]
node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58]
node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72]
wire shift_amount : UInt<6> @[Mux.scala 27:72]
shift_amount <= _T_97 @[Mux.scala 27:72]
wire shift_mask : UInt<32>
shift_mask <= UInt<1>("h00")
wire _T_98 : UInt<1>[5] @[el2_lib.scala 162:48]
_T_98[0] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[1] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[2] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[3] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[4] <= io.ap.sll @[el2_lib.scala 162:48]
node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58]
node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58]
node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58]
node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58]
node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70]
node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61]
node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39]
shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14]
wire shift_extend : UInt<63>
shift_extend <= UInt<1>("h00")
wire _T_106 : UInt<1>[31] @[el2_lib.scala 162:48]
_T_106[0] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[1] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[2] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[3] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[4] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[5] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[6] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[7] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[8] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[9] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[10] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[11] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[12] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[13] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[14] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[15] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[16] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[17] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[18] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[19] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[20] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[21] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[22] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[23] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[24] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[25] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[26] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[27] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[28] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[29] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[30] <= io.ap.sra @[el2_lib.scala 162:48]
node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58]
node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58]
node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58]
node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58]
node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58]
node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58]
node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58]
node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58]
node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58]
node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58]
node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58]
node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58]
node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58]
node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58]
node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58]
node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58]
node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58]
node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58]
node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58]
node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58]
node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58]
node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58]
node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58]
node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58]
node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58]
node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58]
node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58]
node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58]
node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58]
node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58]
node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61]
wire _T_138 : UInt<1>[31] @[el2_lib.scala 162:48]
_T_138[0] <= _T_137 @[el2_lib.scala 162:48]
_T_138[1] <= _T_137 @[el2_lib.scala 162:48]
_T_138[2] <= _T_137 @[el2_lib.scala 162:48]
_T_138[3] <= _T_137 @[el2_lib.scala 162:48]
_T_138[4] <= _T_137 @[el2_lib.scala 162:48]
_T_138[5] <= _T_137 @[el2_lib.scala 162:48]
_T_138[6] <= _T_137 @[el2_lib.scala 162:48]
_T_138[7] <= _T_137 @[el2_lib.scala 162:48]
_T_138[8] <= _T_137 @[el2_lib.scala 162:48]
_T_138[9] <= _T_137 @[el2_lib.scala 162:48]
_T_138[10] <= _T_137 @[el2_lib.scala 162:48]
_T_138[11] <= _T_137 @[el2_lib.scala 162:48]
_T_138[12] <= _T_137 @[el2_lib.scala 162:48]
_T_138[13] <= _T_137 @[el2_lib.scala 162:48]
_T_138[14] <= _T_137 @[el2_lib.scala 162:48]
_T_138[15] <= _T_137 @[el2_lib.scala 162:48]
_T_138[16] <= _T_137 @[el2_lib.scala 162:48]
_T_138[17] <= _T_137 @[el2_lib.scala 162:48]
_T_138[18] <= _T_137 @[el2_lib.scala 162:48]
_T_138[19] <= _T_137 @[el2_lib.scala 162:48]
_T_138[20] <= _T_137 @[el2_lib.scala 162:48]
_T_138[21] <= _T_137 @[el2_lib.scala 162:48]
_T_138[22] <= _T_137 @[el2_lib.scala 162:48]
_T_138[23] <= _T_137 @[el2_lib.scala 162:48]
_T_138[24] <= _T_137 @[el2_lib.scala 162:48]
_T_138[25] <= _T_137 @[el2_lib.scala 162:48]
_T_138[26] <= _T_137 @[el2_lib.scala 162:48]
_T_138[27] <= _T_137 @[el2_lib.scala 162:48]
_T_138[28] <= _T_137 @[el2_lib.scala 162:48]
_T_138[29] <= _T_137 @[el2_lib.scala 162:48]
_T_138[30] <= _T_137 @[el2_lib.scala 162:48]
node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58]
node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58]
node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58]
node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58]
node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58]
node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58]
node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58]
node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58]
node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58]
node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58]
node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58]
node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58]
node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58]
node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58]
node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58]
node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58]
node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58]
node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58]
node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58]
node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58]
node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58]
node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58]
node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58]
node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58]
node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58]
node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58]
node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58]
node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58]
node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58]
node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58]
node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44]
wire _T_170 : UInt<1>[31] @[el2_lib.scala 162:48]
_T_170[0] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[1] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[2] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[3] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[4] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[5] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[6] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[7] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[8] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[9] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[10] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[11] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[12] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[13] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[14] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[15] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[16] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[17] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[18] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[19] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[20] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[21] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[22] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[23] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[24] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[25] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[26] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[27] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[28] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[29] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[30] <= io.ap.sll @[el2_lib.scala 162:48]
node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58]
node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58]
node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58]
node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58]
node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58]
node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58]
node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58]
node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58]
node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58]
node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58]
node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58]
node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58]
node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58]
node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58]
node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58]
node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58]
node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58]
node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58]
node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58]
node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58]
node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58]
node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58]
node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58]
node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58]
node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58]
node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58]
node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58]
node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58]
node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58]
node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58]
node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99]
node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90]
node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68]
node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58]
node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58]
shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16]
wire shift_long : UInt<63>
shift_long <= UInt<1>("h00")
node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47]
node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32]
shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14]
node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27]
node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46]
node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34]
node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41]
node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53]
node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41]
node _T_212 = eq(io.ap.slt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 78:56]
node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54]
node _T_213 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 79:41]
node _T_214 = or(_T_213, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 79:63]
node sel_pc = or(_T_214, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 79:83]
node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47]
node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63]
node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32]
node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40]
node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24]
node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40]
node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31]
node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20]
node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27]
node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27]
node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20]
node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27]
node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27]
node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22]
node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39]
node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28]
node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26]
node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64]
node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76]
node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20]
node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39]
node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26]
node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64]
node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39]
node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28]
node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26]
node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64]
node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72]
node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72]
wire _T_247 : UInt<19> @[Mux.scala 27:72]
_T_247 <= _T_246 @[Mux.scala 27:72]
node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94]
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24]
node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58]
node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31]
node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15]
node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41]
node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15]
node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41]
node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12]
node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21]
node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51]
node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72]
node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72]
node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72]
wire _T_267 : UInt<32> @[Mux.scala 27:72]
_T_267 <= _T_266 @[Mux.scala 27:72]
node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56]
result <= _T_268 @[el2_exu_alu_ctl.scala 88:16]
node _T_269 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 96:45]
node _T_270 = or(_T_269, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 97:25]
node any_jal = or(_T_270, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 98:25]
node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40]
node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59]
node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46]
node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85]
node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72]
node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104]
node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91]
node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110]
node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42]
node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63]
node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61]
node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79]
node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77]
node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104]
node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123]
node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141]
node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139]
node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89]
io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26]
node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37]
node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49]
node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62]
node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28]
io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22]
node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47]
node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45]
node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82]
node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62]
node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:80]
node _T_296 = neq(io.pp_in.bits.prett, _T_295) @[el2_exu_alu_ctl.scala 114:72]
node target_mispredict = and(io.pp_in.bits.pret, _T_296) @[el2_exu_alu_ctl.scala 114:49]
node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42]
node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60]
node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81]
node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97]
node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95]
node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119]
node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117]
io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26]
node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42]
node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60]
node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81]
node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97]
node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95]
node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117]
io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26]
wire newhist : UInt<2>
newhist <= UInt<1>("h00")
node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:40]
node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:65]
node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:44]
node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:92]
node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:73]
node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:96]
node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:70]
node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:25]
node _T_318 = eq(_T_317, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:6]
node _T_319 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:31]
node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:29]
node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:68]
node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:72]
node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:47]
node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14]
io.predict_p_out.bits.way <= io.pp_in.bits.way @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30]
node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:38]
node _T_326 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:58]
node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:56]
node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:95]
node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:76]
io.predict_p_out.bits.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:35]
io.predict_p_out.bits.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:35]
io.predict_p_out.bits.hist <= newhist @[el2_exu_alu_ctl.scala 128:35]

347
el2_exu_alu_ctl.v
View File

@ -1,347 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_exu_alu_ctl(
input clock,
input reset,
input io_scan_mode,
input io_flush_upper_x,
input io_flush_lower_r,
input io_enable,
input io_valid_in,
input io_ap_land,
input io_ap_lor,
input io_ap_lxor,
input io_ap_sll,
input io_ap_srl,
input io_ap_sra,
input io_ap_beq,
input io_ap_bne,
input io_ap_blt,
input io_ap_bge,
input io_ap_add,
input io_ap_sub,
input io_ap_slt,
input io_ap_unsign,
input io_ap_jal,
input io_ap_predict_t,
input io_ap_predict_nt,
input io_ap_csr_write,
input io_ap_csr_imm,
input io_csr_ren_in,
input [31:0] io_a_in,
input [31:0] io_b_in,
input [30:0] io_pc_in,
input io_pp_in_valid,
input io_pp_in_bits_misp,
input io_pp_in_bits_ataken,
input io_pp_in_bits_boffset,
input io_pp_in_bits_pc4,
input [1:0] io_pp_in_bits_hist,
input [11:0] io_pp_in_bits_toffset,
input io_pp_in_bits_br_error,
input io_pp_in_bits_br_start_error,
input [30:0] io_pp_in_bits_prett,
input io_pp_in_bits_pcall,
input io_pp_in_bits_pret,
input io_pp_in_bits_pja,
input io_pp_in_bits_way,
input [11:0] io_brimm_in,
output [31:0] io_result_ff,
output io_flush_upper_out,
output io_flush_final_out,
output [30:0] io_flush_path_out,
output [30:0] io_pc_ff,
output io_pred_correct_out,
output io_predict_p_out_valid,
output io_predict_p_out_bits_misp,
output io_predict_p_out_bits_ataken,
output io_predict_p_out_bits_boffset,
output io_predict_p_out_bits_pc4,
output [1:0] io_predict_p_out_bits_hist,
output [11:0] io_predict_p_out_bits_toffset,
output io_predict_p_out_bits_br_error,
output io_predict_p_out_bits_br_start_error,
output [30:0] io_predict_p_out_bits_prett,
output io_predict_p_out_bits_pcall,
output io_predict_p_out_bits_pret,
output io_predict_p_out_bits_pja,
output io_predict_p_out_bits_way
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
reg [30:0] _T_1; // @[el2_lib.scala 514:16]
reg [31:0] _T_3; // @[el2_lib.scala 514:16]
wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37]
wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58]
wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55]
wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58]
wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80]
wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132]
wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157]
wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14]
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18]
wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14]
wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29]
wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27]
wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37]
wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66]
wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78]
wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76]
wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50]
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38]
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29]
wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30]
wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51]
wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44]
wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78]
wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76]
wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58]
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29]
wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72]
wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72]
wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72]
wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38]
wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72]
wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61]
wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39]
wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44]
wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90]
wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68]
wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58]
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32]
wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34]
wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41]
wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53]
wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41]
wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56]
wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54]
wire _T_213 = io_ap_jal | io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 79:41]
wire _T_214 = _T_213 | io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 79:63]
wire sel_pc = _T_214 | io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 79:83]
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40]
wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31]
wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27]
wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27]
wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28]
wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26]
wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20]
wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26]
wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26]
wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72]
wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24]
wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31]
wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51]
wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72]
wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72]
wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72]
wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40]
wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59]
wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46]
wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85]
wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72]
wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104]
wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91]
wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110]
wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42]
wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63]
wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61]
wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79]
wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77]
wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104]
wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123]
wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139]
wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45]
wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82]
wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62]
wire _T_296 = io_pp_in_bits_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:72]
wire target_mispredict = io_pp_in_bits_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:49]
wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42]
wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60]
wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81]
wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97]
wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95]
wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119]
wire _T_312 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:44]
wire _T_314 = ~io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:73]
wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:96]
wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:70]
wire _T_318 = ~io_pp_in_bits_hist[1]; // @[el2_exu_alu_ctl.scala 123:6]
wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:29]
wire _T_322 = io_pp_in_bits_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:72]
wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:47]
wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:56]
wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:95]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16]
assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26]
assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22]
assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12]
assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26]
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:35]
assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:35]
assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:35]
assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_prett = io_pp_in_bits_prett; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[el2_exu_alu_ctl.scala 125:30]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1 = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
_T_3 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1 = 31'h0;
end
if (reset) begin
_T_3 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_1 <= 31'h0;
end else begin
_T_1 <= io_pc_in;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
_T_3 <= 32'h0;
end else begin
_T_3 <= _T_252 | _T_266;
end
end
endmodule

30
el2_exu_div_ctl.anno.json
View File

@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_ctl|el2_exu_div_ctl>io_finish_dly",
"sources":[
"~el2_exu_div_ctl|el2_exu_div_ctl>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_div_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_div_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1865
el2_exu_div_ctl.fir
View File

File diff suppressed because it is too large Load Diff

853
el2_exu_div_ctl.v
View File

@ -1,853 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_exu_div_ctl(
input clock,
input reset,
input io_scan_mode,
input io_dp_valid,
input io_dp_bits_unsign,
input io_dp_bits_rem,
input [31:0] io_dividend,
input [31:0] io_divisor,
input io_cancel,
output [31:0] io_out,
output io_finish_dly
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 54:30]
reg valid_ff_x; // @[el2_exu_div_ctl.scala 204:26]
wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 54:28]
reg [32:0] q_ff; // @[el2_lib.scala 514:16]
wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:34]
reg [32:0] m_ff; // @[el2_lib.scala 514:16]
wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:57]
wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 60:43]
wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 60:80]
wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 60:66]
reg rem_ff; // @[Reg.scala 27:20]
wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 60:91]
wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 60:89]
wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 60:99]
wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 61:18]
wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 61:27]
wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 61:50]
wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 61:60]
wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 60:110]
wire pat1 = q_ff[3]; // @[el2_exu_div_ctl.scala 64:57]
wire _T_22 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 65:69]
wire _T_24 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 65:69]
wire _T_26 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 65:69]
wire _T_27 = _T_22 & _T_24; // @[el2_exu_div_ctl.scala 65:94]
wire pat2 = _T_27 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_28 = pat1 & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_33 = pat1 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_35 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 72:32]
wire _T_36 = _T_33 & _T_35; // @[el2_exu_div_ctl.scala 72:30]
wire pat1_2 = q_ff[2]; // @[el2_exu_div_ctl.scala 64:57]
wire _T_44 = pat1_2 & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_45 = _T_36 | _T_44; // @[el2_exu_div_ctl.scala 72:41]
wire pat1_3 = pat1 & pat1_2; // @[el2_exu_div_ctl.scala 64:94]
wire _T_52 = pat1_3 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_53 = _T_45 | _T_52; // @[el2_exu_div_ctl.scala 72:73]
wire _T_58 = pat1_2 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_61 = _T_58 & _T_35; // @[el2_exu_div_ctl.scala 74:30]
wire pat1_5 = q_ff[1]; // @[el2_exu_div_ctl.scala 64:57]
wire _T_69 = pat1_5 & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_70 = _T_61 | _T_69; // @[el2_exu_div_ctl.scala 74:41]
wire pat2_6 = _T_22 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_75 = pat1 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_78 = _T_75 & _T_35; // @[el2_exu_div_ctl.scala 74:103]
wire _T_79 = _T_70 | _T_78; // @[el2_exu_div_ctl.scala 74:76]
wire _T_82 = ~pat1_2; // @[el2_exu_div_ctl.scala 64:69]
wire pat1_7 = pat1 & _T_82; // @[el2_exu_div_ctl.scala 64:94]
wire _T_90 = _T_27 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
wire pat2_7 = _T_90 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_91 = pat1_7 & pat2_7; // @[el2_exu_div_ctl.scala 66:10]
wire _T_92 = _T_79 | _T_91; // @[el2_exu_div_ctl.scala 74:114]
wire _T_94 = ~pat1; // @[el2_exu_div_ctl.scala 64:69]
wire _T_97 = _T_94 & pat1_2; // @[el2_exu_div_ctl.scala 64:94]
wire pat1_8 = _T_97 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_102 = pat1_8 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_103 = _T_92 | _T_102; // @[el2_exu_div_ctl.scala 75:43]
wire _T_107 = pat1_3 & _T_22; // @[el2_exu_div_ctl.scala 66:10]
wire _T_110 = _T_107 & _T_35; // @[el2_exu_div_ctl.scala 75:104]
wire _T_111 = _T_103 | _T_110; // @[el2_exu_div_ctl.scala 75:78]
wire _T_119 = _T_22 & m_ff[2]; // @[el2_exu_div_ctl.scala 65:94]
wire pat2_10 = _T_119 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_120 = pat1_3 & pat2_10; // @[el2_exu_div_ctl.scala 66:10]
wire _T_121 = _T_111 | _T_120; // @[el2_exu_div_ctl.scala 75:116]
wire pat1_11 = pat1 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_128 = pat1_11 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_129 = _T_121 | _T_128; // @[el2_exu_div_ctl.scala 76:43]
wire pat1_12 = pat1_3 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_137 = pat1_12 & _T_119; // @[el2_exu_div_ctl.scala 66:10]
wire _T_138 = _T_129 | _T_137; // @[el2_exu_div_ctl.scala 76:77]
wire _T_142 = pat1_2 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire pat1_13 = _T_142 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_147 = pat1_13 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire pat1_14 = pat1_7 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_157 = _T_22 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
wire pat2_14 = _T_157 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_158 = pat1_14 & pat2_14; // @[el2_exu_div_ctl.scala 66:10]
wire _T_159 = _T_147 | _T_158; // @[el2_exu_div_ctl.scala 78:44]
wire _T_164 = pat1_2 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_167 = _T_164 & _T_35; // @[el2_exu_div_ctl.scala 78:111]
wire _T_168 = _T_159 | _T_167; // @[el2_exu_div_ctl.scala 78:84]
wire _T_173 = pat1_5 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_176 = _T_173 & _T_35; // @[el2_exu_div_ctl.scala 79:32]
wire _T_177 = _T_168 | _T_176; // @[el2_exu_div_ctl.scala 78:126]
wire _T_185 = q_ff[0] & pat2; // @[el2_exu_div_ctl.scala 66:10]
wire _T_186 = _T_177 | _T_185; // @[el2_exu_div_ctl.scala 79:46]
wire _T_191 = ~pat1_5; // @[el2_exu_div_ctl.scala 64:69]
wire pat1_18 = _T_97 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
wire _T_201 = pat1_18 & pat2_7; // @[el2_exu_div_ctl.scala 66:10]
wire _T_202 = _T_186 | _T_201; // @[el2_exu_div_ctl.scala 79:86]
wire _T_209 = pat1_8 & _T_22; // @[el2_exu_div_ctl.scala 66:10]
wire _T_212 = _T_209 & _T_35; // @[el2_exu_div_ctl.scala 80:35]
wire _T_213 = _T_202 | _T_212; // @[el2_exu_div_ctl.scala 79:128]
wire pat2_20 = _T_24 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_218 = pat1 & pat2_20; // @[el2_exu_div_ctl.scala 66:10]
wire _T_221 = _T_218 & _T_35; // @[el2_exu_div_ctl.scala 80:74]
wire _T_222 = _T_213 | _T_221; // @[el2_exu_div_ctl.scala 80:46]
wire pat2_21 = _T_119 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_231 = pat1_7 & pat2_21; // @[el2_exu_div_ctl.scala 66:10]
wire _T_232 = _T_222 | _T_231; // @[el2_exu_div_ctl.scala 80:86]
wire _T_244 = pat1_8 & pat2_10; // @[el2_exu_div_ctl.scala 66:10]
wire _T_245 = _T_232 | _T_244; // @[el2_exu_div_ctl.scala 80:128]
wire pat1_23 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_255 = pat1_23 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
wire _T_256 = _T_245 | _T_255; // @[el2_exu_div_ctl.scala 81:46]
wire pat1_24 = pat1_7 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
wire pat2_24 = _T_119 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_268 = pat1_24 & pat2_24; // @[el2_exu_div_ctl.scala 66:10]
wire _T_269 = _T_256 | _T_268; // @[el2_exu_div_ctl.scala 81:86]
wire _T_274 = _T_82 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire pat1_25 = _T_274 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_279 = pat1_25 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
wire _T_280 = _T_269 | _T_279; // @[el2_exu_div_ctl.scala 81:128]
wire _T_284 = pat1_3 & _T_26; // @[el2_exu_div_ctl.scala 66:10]
wire _T_287 = _T_284 & _T_35; // @[el2_exu_div_ctl.scala 82:73]
wire _T_288 = _T_280 | _T_287; // @[el2_exu_div_ctl.scala 82:46]
wire pat1_27 = pat1_8 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_299 = pat1_27 & _T_119; // @[el2_exu_div_ctl.scala 66:10]
wire _T_300 = _T_288 | _T_299; // @[el2_exu_div_ctl.scala 82:86]
wire pat2_28 = m_ff[3] & _T_24; // @[el2_exu_div_ctl.scala 65:94]
wire _T_306 = pat1_3 & pat2_28; // @[el2_exu_div_ctl.scala 66:10]
wire _T_307 = _T_300 | _T_306; // @[el2_exu_div_ctl.scala 82:128]
wire pat2_29 = pat2_28 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_316 = pat1_11 & pat2_29; // @[el2_exu_div_ctl.scala 66:10]
wire _T_317 = _T_307 | _T_316; // @[el2_exu_div_ctl.scala 83:46]
wire pat1_30 = pat1 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_324 = pat1_30 & pat2_20; // @[el2_exu_div_ctl.scala 66:10]
wire _T_325 = _T_317 | _T_324; // @[el2_exu_div_ctl.scala 83:86]
wire pat1_31 = pat1 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
wire pat2_31 = pat2_21 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
wire _T_336 = pat1_31 & pat2_31; // @[el2_exu_div_ctl.scala 66:10]
wire _T_337 = _T_325 | _T_336; // @[el2_exu_div_ctl.scala 83:128]
wire _T_342 = pat1_12 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
wire _T_345 = _T_342 & _T_35; // @[el2_exu_div_ctl.scala 84:75]
wire _T_346 = _T_337 | _T_345; // @[el2_exu_div_ctl.scala 84:46]
wire pat2_33 = m_ff[3] & _T_26; // @[el2_exu_div_ctl.scala 65:94]
wire _T_354 = pat1_12 & pat2_33; // @[el2_exu_div_ctl.scala 66:10]
wire _T_355 = _T_346 | _T_354; // @[el2_exu_div_ctl.scala 84:86]
wire pat1_34 = pat1_3 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_363 = pat1_34 & pat2_33; // @[el2_exu_div_ctl.scala 66:10]
wire _T_364 = _T_355 | _T_363; // @[el2_exu_div_ctl.scala 84:128]
wire pat1_35 = pat1_7 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
wire _T_373 = pat1_35 & _T_157; // @[el2_exu_div_ctl.scala 66:10]
wire _T_374 = _T_364 | _T_373; // @[el2_exu_div_ctl.scala 85:46]
wire pat1_36 = pat1_11 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_380 = pat1_36 & _T_24; // @[el2_exu_div_ctl.scala 66:10]
wire _T_381 = _T_374 | _T_380; // @[el2_exu_div_ctl.scala 85:86]
wire pat1_37 = pat1_12 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
wire _T_388 = pat1_37 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
wire _T_389 = _T_381 | _T_388; // @[el2_exu_div_ctl.scala 85:128]
wire _T_393 = pat1_11 & _T_24; // @[el2_exu_div_ctl.scala 66:10]
wire _T_396 = _T_393 & _T_35; // @[el2_exu_div_ctl.scala 86:72]
wire _T_397 = _T_389 | _T_396; // @[el2_exu_div_ctl.scala 86:46]
wire [1:0] _T_398 = {_T_138,_T_397}; // @[Cat.scala 29:58]
wire [1:0] _T_399 = {_T_28,_T_53}; // @[Cat.scala 29:58]
reg sign_ff; // @[Reg.scala 27:20]
wire _T_401 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 96:34]
wire [32:0] short_dividend = {_T_401,q_ff[31:0]}; // @[Cat.scala 29:58]
wire _T_406 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 101:7]
wire _T_409 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 101:60]
wire _T_414 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 102:59]
wire _T_415 = _T_406 & _T_409; // @[Mux.scala 27:72]
wire _T_416 = short_dividend[32] & _T_414; // @[Mux.scala 27:72]
wire _T_417 = _T_415 | _T_416; // @[Mux.scala 27:72]
wire _T_424 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 105:60]
wire _T_429 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 106:59]
wire _T_430 = _T_406 & _T_424; // @[Mux.scala 27:72]
wire _T_431 = short_dividend[32] & _T_429; // @[Mux.scala 27:72]
wire _T_432 = _T_430 | _T_431; // @[Mux.scala 27:72]
wire _T_439 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 109:59]
wire _T_444 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 110:58]
wire _T_445 = _T_406 & _T_439; // @[Mux.scala 27:72]
wire _T_446 = short_dividend[32] & _T_444; // @[Mux.scala 27:72]
wire _T_447 = _T_445 | _T_446; // @[Mux.scala 27:72]
wire [2:0] a_cls = {_T_417,_T_432,_T_447}; // @[Cat.scala 29:58]
wire _T_452 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 115:7]
wire _T_455 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 115:40]
wire _T_460 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 116:39]
wire _T_461 = _T_452 & _T_455; // @[Mux.scala 27:72]
wire _T_462 = m_ff[32] & _T_460; // @[Mux.scala 27:72]
wire _T_463 = _T_461 | _T_462; // @[Mux.scala 27:72]
wire _T_470 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 119:40]
wire _T_475 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 120:39]
wire _T_476 = _T_452 & _T_470; // @[Mux.scala 27:72]
wire _T_477 = m_ff[32] & _T_475; // @[Mux.scala 27:72]
wire _T_478 = _T_476 | _T_477; // @[Mux.scala 27:72]
wire _T_485 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 123:39]
wire _T_490 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 124:38]
wire _T_491 = _T_452 & _T_485; // @[Mux.scala 27:72]
wire _T_492 = m_ff[32] & _T_490; // @[Mux.scala 27:72]
wire _T_493 = _T_491 | _T_492; // @[Mux.scala 27:72]
wire [2:0] b_cls = {_T_463,_T_478,_T_493}; // @[Cat.scala 29:58]
wire _T_497 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 128:19]
wire _T_500 = _T_497 & b_cls[2]; // @[el2_exu_div_ctl.scala 128:34]
wire _T_502 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 129:21]
wire _T_505 = _T_502 & b_cls[2]; // @[el2_exu_div_ctl.scala 129:36]
wire _T_506 = _T_500 | _T_505; // @[el2_exu_div_ctl.scala 128:65]
wire _T_508 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 130:21]
wire _T_511 = _T_508 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:36]
wire _T_512 = _T_506 | _T_511; // @[el2_exu_div_ctl.scala 129:67]
wire _T_516 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 131:50]
wire _T_517 = _T_502 & _T_516; // @[el2_exu_div_ctl.scala 131:36]
wire _T_518 = _T_512 | _T_517; // @[el2_exu_div_ctl.scala 130:67]
wire _T_523 = _T_508 & _T_516; // @[el2_exu_div_ctl.scala 132:36]
wire _T_524 = _T_518 | _T_523; // @[el2_exu_div_ctl.scala 131:67]
wire _T_528 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 133:50]
wire _T_529 = _T_508 & _T_528; // @[el2_exu_div_ctl.scala 133:36]
wire _T_530 = _T_524 | _T_529; // @[el2_exu_div_ctl.scala 132:67]
wire _T_535 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 135:34]
wire _T_540 = _T_497 & _T_516; // @[el2_exu_div_ctl.scala 136:36]
wire _T_541 = _T_535 | _T_540; // @[el2_exu_div_ctl.scala 135:65]
wire _T_546 = _T_502 & _T_528; // @[el2_exu_div_ctl.scala 137:36]
wire _T_547 = _T_541 | _T_546; // @[el2_exu_div_ctl.scala 136:67]
wire _T_551 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 138:50]
wire _T_552 = _T_508 & _T_551; // @[el2_exu_div_ctl.scala 138:36]
wire _T_553 = _T_547 | _T_552; // @[el2_exu_div_ctl.scala 137:67]
wire _T_558 = a_cls[2] & _T_516; // @[el2_exu_div_ctl.scala 140:34]
wire _T_563 = _T_497 & _T_528; // @[el2_exu_div_ctl.scala 141:36]
wire _T_564 = _T_558 | _T_563; // @[el2_exu_div_ctl.scala 140:65]
wire _T_569 = _T_502 & _T_551; // @[el2_exu_div_ctl.scala 142:36]
wire _T_570 = _T_564 | _T_569; // @[el2_exu_div_ctl.scala 141:67]
wire _T_575 = a_cls[2] & _T_528; // @[el2_exu_div_ctl.scala 144:34]
wire _T_580 = _T_497 & _T_551; // @[el2_exu_div_ctl.scala 145:36]
wire _T_581 = _T_575 | _T_580; // @[el2_exu_div_ctl.scala 144:65]
wire [3:0] shortq_raw = {_T_530,_T_553,_T_570,_T_581}; // @[Cat.scala 29:58]
wire _T_586 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 148:35]
wire _T_587 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 148:78]
wire shortq_enable = _T_586 & _T_587; // @[el2_exu_div_ctl.scala 148:64]
wire [3:0] _T_589 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
reg [3:0] shortq_shift_xx; // @[el2_exu_div_ctl.scala 215:31]
wire [4:0] _T_598 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_599 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_600 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [3:0] _T_601 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_602 = _T_598 | _T_599; // @[Mux.scala 27:72]
wire [4:0] _T_603 = _T_602 | _T_600; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_601}; // @[Mux.scala 27:72]
wire [4:0] shortq_shift_ff = _T_603 | _GEN_4; // @[Mux.scala 27:72]
reg [5:0] count; // @[el2_exu_div_ctl.scala 207:21]
wire _T_606 = count == 6'h20; // @[el2_exu_div_ctl.scala 159:55]
wire _T_607 = count == 6'h21; // @[el2_exu_div_ctl.scala 159:76]
wire _T_608 = _T_9 ? _T_606 : _T_607; // @[el2_exu_div_ctl.scala 159:39]
wire finish = smallnum_case | _T_608; // @[el2_exu_div_ctl.scala 159:34]
reg run_state; // @[el2_exu_div_ctl.scala 206:25]
wire _T_609 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 160:32]
wire _T_610 = _T_609 | finish; // @[el2_exu_div_ctl.scala 160:44]
reg finish_ff; // @[el2_exu_div_ctl.scala 205:25]
wire _T_612 = ~finish; // @[el2_exu_div_ctl.scala 161:48]
wire _T_613 = _T_609 & _T_612; // @[el2_exu_div_ctl.scala 161:46]
wire _T_616 = run_state & _T_612; // @[el2_exu_div_ctl.scala 162:35]
wire _T_618 = _T_616 & _T; // @[el2_exu_div_ctl.scala 162:45]
wire _T_619 = ~shortq_enable; // @[el2_exu_div_ctl.scala 162:60]
wire _T_620 = _T_618 & _T_619; // @[el2_exu_div_ctl.scala 162:58]
wire [5:0] _T_622 = _T_620 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [5:0] _T_623 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [5:0] _T_625 = count + _T_623; // @[el2_exu_div_ctl.scala 162:86]
wire [5:0] _T_627 = _T_625 + 6'h1; // @[el2_exu_div_ctl.scala 162:113]
wire _T_631 = ~io_dp_bits_unsign; // @[el2_exu_div_ctl.scala 166:20]
wire _T_632 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 166:53]
wire sign_eff = _T_631 & _T_632; // @[el2_exu_div_ctl.scala 166:39]
wire _T_633 = ~run_state; // @[el2_exu_div_ctl.scala 170:6]
wire [32:0] _T_635 = {1'h0,io_dividend}; // @[Cat.scala 29:58]
reg shortq_enable_ff; // @[el2_exu_div_ctl.scala 214:32]
wire _T_636 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 171:30]
wire _T_637 = run_state & _T_636; // @[el2_exu_div_ctl.scala 171:16]
reg dividend_neg_ff; // @[Reg.scala 27:20]
wire _T_660 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 175:32]
wire _T_845 = |q_ff[30:0]; // @[el2_lib.scala 543:35]
wire _T_847 = ~q_ff[31]; // @[el2_lib.scala 543:40]
wire _T_849 = _T_845 ? _T_847 : q_ff[31]; // @[el2_lib.scala 543:23]
wire _T_839 = |q_ff[29:0]; // @[el2_lib.scala 543:35]
wire _T_841 = ~q_ff[30]; // @[el2_lib.scala 543:40]
wire _T_843 = _T_839 ? _T_841 : q_ff[30]; // @[el2_lib.scala 543:23]
wire _T_833 = |q_ff[28:0]; // @[el2_lib.scala 543:35]
wire _T_835 = ~q_ff[29]; // @[el2_lib.scala 543:40]
wire _T_837 = _T_833 ? _T_835 : q_ff[29]; // @[el2_lib.scala 543:23]
wire _T_827 = |q_ff[27:0]; // @[el2_lib.scala 543:35]
wire _T_829 = ~q_ff[28]; // @[el2_lib.scala 543:40]
wire _T_831 = _T_827 ? _T_829 : q_ff[28]; // @[el2_lib.scala 543:23]
wire _T_821 = |q_ff[26:0]; // @[el2_lib.scala 543:35]
wire _T_823 = ~q_ff[27]; // @[el2_lib.scala 543:40]
wire _T_825 = _T_821 ? _T_823 : q_ff[27]; // @[el2_lib.scala 543:23]
wire _T_815 = |q_ff[25:0]; // @[el2_lib.scala 543:35]
wire _T_817 = ~q_ff[26]; // @[el2_lib.scala 543:40]
wire _T_819 = _T_815 ? _T_817 : q_ff[26]; // @[el2_lib.scala 543:23]
wire _T_809 = |q_ff[24:0]; // @[el2_lib.scala 543:35]
wire _T_811 = ~q_ff[25]; // @[el2_lib.scala 543:40]
wire _T_813 = _T_809 ? _T_811 : q_ff[25]; // @[el2_lib.scala 543:23]
wire _T_803 = |q_ff[23:0]; // @[el2_lib.scala 543:35]
wire _T_805 = ~q_ff[24]; // @[el2_lib.scala 543:40]
wire _T_807 = _T_803 ? _T_805 : q_ff[24]; // @[el2_lib.scala 543:23]
wire _T_797 = |q_ff[22:0]; // @[el2_lib.scala 543:35]
wire _T_799 = ~q_ff[23]; // @[el2_lib.scala 543:40]
wire _T_801 = _T_797 ? _T_799 : q_ff[23]; // @[el2_lib.scala 543:23]
wire _T_791 = |q_ff[21:0]; // @[el2_lib.scala 543:35]
wire _T_793 = ~q_ff[22]; // @[el2_lib.scala 543:40]
wire _T_795 = _T_791 ? _T_793 : q_ff[22]; // @[el2_lib.scala 543:23]
wire _T_785 = |q_ff[20:0]; // @[el2_lib.scala 543:35]
wire _T_787 = ~q_ff[21]; // @[el2_lib.scala 543:40]
wire _T_789 = _T_785 ? _T_787 : q_ff[21]; // @[el2_lib.scala 543:23]
wire _T_779 = |q_ff[19:0]; // @[el2_lib.scala 543:35]
wire _T_781 = ~q_ff[20]; // @[el2_lib.scala 543:40]
wire _T_783 = _T_779 ? _T_781 : q_ff[20]; // @[el2_lib.scala 543:23]
wire _T_773 = |q_ff[18:0]; // @[el2_lib.scala 543:35]
wire _T_775 = ~q_ff[19]; // @[el2_lib.scala 543:40]
wire _T_777 = _T_773 ? _T_775 : q_ff[19]; // @[el2_lib.scala 543:23]
wire _T_767 = |q_ff[17:0]; // @[el2_lib.scala 543:35]
wire _T_769 = ~q_ff[18]; // @[el2_lib.scala 543:40]
wire _T_771 = _T_767 ? _T_769 : q_ff[18]; // @[el2_lib.scala 543:23]
wire _T_761 = |q_ff[16:0]; // @[el2_lib.scala 543:35]
wire _T_763 = ~q_ff[17]; // @[el2_lib.scala 543:40]
wire _T_765 = _T_761 ? _T_763 : q_ff[17]; // @[el2_lib.scala 543:23]
wire _T_755 = |q_ff[15:0]; // @[el2_lib.scala 543:35]
wire _T_757 = ~q_ff[16]; // @[el2_lib.scala 543:40]
wire _T_759 = _T_755 ? _T_757 : q_ff[16]; // @[el2_lib.scala 543:23]
wire [7:0] _T_870 = {_T_801,_T_795,_T_789,_T_783,_T_777,_T_771,_T_765,_T_759}; // @[el2_lib.scala 545:14]
wire _T_749 = |q_ff[14:0]; // @[el2_lib.scala 543:35]
wire _T_751 = ~q_ff[15]; // @[el2_lib.scala 543:40]
wire _T_753 = _T_749 ? _T_751 : q_ff[15]; // @[el2_lib.scala 543:23]
wire _T_743 = |q_ff[13:0]; // @[el2_lib.scala 543:35]
wire _T_745 = ~q_ff[14]; // @[el2_lib.scala 543:40]
wire _T_747 = _T_743 ? _T_745 : q_ff[14]; // @[el2_lib.scala 543:23]
wire _T_737 = |q_ff[12:0]; // @[el2_lib.scala 543:35]
wire _T_739 = ~q_ff[13]; // @[el2_lib.scala 543:40]
wire _T_741 = _T_737 ? _T_739 : q_ff[13]; // @[el2_lib.scala 543:23]
wire _T_731 = |q_ff[11:0]; // @[el2_lib.scala 543:35]
wire _T_733 = ~q_ff[12]; // @[el2_lib.scala 543:40]
wire _T_735 = _T_731 ? _T_733 : q_ff[12]; // @[el2_lib.scala 543:23]
wire _T_725 = |q_ff[10:0]; // @[el2_lib.scala 543:35]
wire _T_727 = ~q_ff[11]; // @[el2_lib.scala 543:40]
wire _T_729 = _T_725 ? _T_727 : q_ff[11]; // @[el2_lib.scala 543:23]
wire _T_719 = |q_ff[9:0]; // @[el2_lib.scala 543:35]
wire _T_721 = ~q_ff[10]; // @[el2_lib.scala 543:40]
wire _T_723 = _T_719 ? _T_721 : q_ff[10]; // @[el2_lib.scala 543:23]
wire _T_713 = |q_ff[8:0]; // @[el2_lib.scala 543:35]
wire _T_715 = ~q_ff[9]; // @[el2_lib.scala 543:40]
wire _T_717 = _T_713 ? _T_715 : q_ff[9]; // @[el2_lib.scala 543:23]
wire _T_707 = |q_ff[7:0]; // @[el2_lib.scala 543:35]
wire _T_709 = ~q_ff[8]; // @[el2_lib.scala 543:40]
wire _T_711 = _T_707 ? _T_709 : q_ff[8]; // @[el2_lib.scala 543:23]
wire _T_701 = |q_ff[6:0]; // @[el2_lib.scala 543:35]
wire _T_703 = ~q_ff[7]; // @[el2_lib.scala 543:40]
wire _T_705 = _T_701 ? _T_703 : q_ff[7]; // @[el2_lib.scala 543:23]
wire _T_695 = |q_ff[5:0]; // @[el2_lib.scala 543:35]
wire _T_697 = ~q_ff[6]; // @[el2_lib.scala 543:40]
wire _T_699 = _T_695 ? _T_697 : q_ff[6]; // @[el2_lib.scala 543:23]
wire _T_689 = |q_ff[4:0]; // @[el2_lib.scala 543:35]
wire _T_691 = ~q_ff[5]; // @[el2_lib.scala 543:40]
wire _T_693 = _T_689 ? _T_691 : q_ff[5]; // @[el2_lib.scala 543:23]
wire _T_683 = |q_ff[3:0]; // @[el2_lib.scala 543:35]
wire _T_685 = ~q_ff[4]; // @[el2_lib.scala 543:40]
wire _T_687 = _T_683 ? _T_685 : q_ff[4]; // @[el2_lib.scala 543:23]
wire _T_677 = |q_ff[2:0]; // @[el2_lib.scala 543:35]
wire _T_679 = ~q_ff[3]; // @[el2_lib.scala 543:40]
wire _T_681 = _T_677 ? _T_679 : q_ff[3]; // @[el2_lib.scala 543:23]
wire _T_671 = |q_ff[1:0]; // @[el2_lib.scala 543:35]
wire _T_673 = ~q_ff[2]; // @[el2_lib.scala 543:40]
wire _T_675 = _T_671 ? _T_673 : q_ff[2]; // @[el2_lib.scala 543:23]
wire _T_665 = |q_ff[0]; // @[el2_lib.scala 543:35]
wire _T_667 = ~q_ff[1]; // @[el2_lib.scala 543:40]
wire _T_669 = _T_665 ? _T_667 : q_ff[1]; // @[el2_lib.scala 543:23]
wire [6:0] _T_855 = {_T_705,_T_699,_T_693,_T_687,_T_681,_T_675,_T_669}; // @[el2_lib.scala 545:14]
wire [14:0] _T_863 = {_T_753,_T_747,_T_741,_T_735,_T_729,_T_723,_T_717,_T_711,_T_855}; // @[el2_lib.scala 545:14]
wire [30:0] _T_879 = {_T_849,_T_843,_T_837,_T_831,_T_825,_T_819,_T_813,_T_807,_T_870,_T_863}; // @[el2_lib.scala 545:14]
wire [31:0] _T_881 = {_T_879,q_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] dividend_eff = _T_660 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 175:22]
wire [32:0] _T_917 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
wire _T_929 = _T_607 & rem_ff; // @[el2_exu_div_ctl.scala 191:41]
reg [32:0] a_ff; // @[el2_lib.scala 514:16]
wire rem_correct = _T_929 & a_ff[32]; // @[el2_exu_div_ctl.scala 191:50]
wire [32:0] _T_902 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
wire _T_890 = ~rem_correct; // @[el2_exu_div_ctl.scala 182:6]
wire _T_891 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 182:21]
wire _T_892 = _T_890 & _T_891; // @[el2_exu_div_ctl.scala 182:19]
wire [32:0] _T_896 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
wire [32:0] _T_903 = _T_892 ? _T_896 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_905 = _T_902 | _T_903; // @[Mux.scala 27:72]
wire _T_898 = _T_890 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 183:19]
wire [55:0] _T_887 = {24'h0,dividend_eff}; // @[Cat.scala 29:58]
wire [86:0] _GEN_5 = {{31'd0}, _T_887}; // @[el2_exu_div_ctl.scala 179:47]
wire [86:0] _T_888 = _GEN_5 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 179:47]
wire [55:0] a_eff_shift = _T_888[55:0]; // @[el2_exu_div_ctl.scala 179:15]
wire [32:0] _T_901 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58]
wire [32:0] _T_904 = _T_898 ? _T_901 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] a_eff = _T_905 | _T_904; // @[Mux.scala 27:72]
wire [32:0] a_shift = _T_917 & a_eff; // @[el2_exu_div_ctl.scala 186:33]
wire _T_926 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 190:21]
reg divisor_neg_ff; // @[Reg.scala 27:20]
wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 188:48]
wire add = _T_926 ^ m_already_comp; // @[el2_exu_div_ctl.scala 190:36]
wire [32:0] _T_885 = ~m_ff; // @[el2_exu_div_ctl.scala 178:35]
wire [32:0] m_eff = add ? m_ff : _T_885; // @[el2_exu_div_ctl.scala 178:15]
wire [32:0] _T_919 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 187:41]
wire _T_920 = ~add; // @[el2_exu_div_ctl.scala 187:65]
wire [32:0] _T_921 = {32'h0,_T_920}; // @[Cat.scala 29:58]
wire [32:0] _T_923 = _T_919 + _T_921; // @[el2_exu_div_ctl.scala 187:49]
wire [32:0] a_in = _T_917 & _T_923; // @[el2_exu_div_ctl.scala 187:30]
wire _T_641 = ~a_in[32]; // @[el2_exu_div_ctl.scala 171:85]
wire [32:0] _T_642 = {dividend_eff,_T_641}; // @[Cat.scala 29:58]
wire [63:0] _GEN_6 = {{31'd0}, _T_642}; // @[el2_exu_div_ctl.scala 171:96]
wire [63:0] _T_643 = _GEN_6 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 171:96]
wire _T_645 = ~_T_636; // @[el2_exu_div_ctl.scala 172:18]
wire _T_646 = run_state & _T_645; // @[el2_exu_div_ctl.scala 172:16]
wire [32:0] _T_651 = {q_ff[31:0],_T_641}; // @[Cat.scala 29:58]
wire [32:0] _T_652 = _T_633 ? _T_635 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _T_653 = _T_637 ? _T_643 : 64'h0; // @[Mux.scala 27:72]
wire [32:0] _T_654 = _T_646 ? _T_651 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _GEN_7 = {{31'd0}, _T_652}; // @[Mux.scala 27:72]
wire [63:0] _T_655 = _GEN_7 | _T_653; // @[Mux.scala 27:72]
wire [63:0] _GEN_8 = {{31'd0}, _T_654}; // @[Mux.scala 27:72]
wire [63:0] _T_656 = _T_655 | _GEN_8; // @[Mux.scala 27:72]
wire _T_659 = run_state & _T_619; // @[el2_exu_div_ctl.scala 174:48]
wire _T_910 = count != 6'h21; // @[el2_exu_div_ctl.scala 185:73]
wire _T_911 = _T_659 & _T_910; // @[el2_exu_div_ctl.scala 185:64]
wire _T_912 = io_dp_valid | _T_911; // @[el2_exu_div_ctl.scala 185:34]
wire _T_932 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 192:50]
wire _T_933 = sign_ff & _T_932; // @[el2_exu_div_ctl.scala 192:31]
wire [31:0] q_ff_eff = _T_933 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 192:21]
wire _T_1161 = |a_ff[0]; // @[el2_lib.scala 543:35]
wire _T_1163 = ~a_ff[1]; // @[el2_lib.scala 543:40]
wire _T_1165 = _T_1161 ? _T_1163 : a_ff[1]; // @[el2_lib.scala 543:23]
wire _T_1167 = |a_ff[1:0]; // @[el2_lib.scala 543:35]
wire _T_1169 = ~a_ff[2]; // @[el2_lib.scala 543:40]
wire _T_1171 = _T_1167 ? _T_1169 : a_ff[2]; // @[el2_lib.scala 543:23]
wire _T_1173 = |a_ff[2:0]; // @[el2_lib.scala 543:35]
wire _T_1175 = ~a_ff[3]; // @[el2_lib.scala 543:40]
wire _T_1177 = _T_1173 ? _T_1175 : a_ff[3]; // @[el2_lib.scala 543:23]
wire _T_1179 = |a_ff[3:0]; // @[el2_lib.scala 543:35]
wire _T_1181 = ~a_ff[4]; // @[el2_lib.scala 543:40]
wire _T_1183 = _T_1179 ? _T_1181 : a_ff[4]; // @[el2_lib.scala 543:23]
wire _T_1185 = |a_ff[4:0]; // @[el2_lib.scala 543:35]
wire _T_1187 = ~a_ff[5]; // @[el2_lib.scala 543:40]
wire _T_1189 = _T_1185 ? _T_1187 : a_ff[5]; // @[el2_lib.scala 543:23]
wire _T_1191 = |a_ff[5:0]; // @[el2_lib.scala 543:35]
wire _T_1193 = ~a_ff[6]; // @[el2_lib.scala 543:40]
wire _T_1195 = _T_1191 ? _T_1193 : a_ff[6]; // @[el2_lib.scala 543:23]
wire _T_1197 = |a_ff[6:0]; // @[el2_lib.scala 543:35]
wire _T_1199 = ~a_ff[7]; // @[el2_lib.scala 543:40]
wire _T_1201 = _T_1197 ? _T_1199 : a_ff[7]; // @[el2_lib.scala 543:23]
wire _T_1203 = |a_ff[7:0]; // @[el2_lib.scala 543:35]
wire _T_1205 = ~a_ff[8]; // @[el2_lib.scala 543:40]
wire _T_1207 = _T_1203 ? _T_1205 : a_ff[8]; // @[el2_lib.scala 543:23]
wire _T_1209 = |a_ff[8:0]; // @[el2_lib.scala 543:35]
wire _T_1211 = ~a_ff[9]; // @[el2_lib.scala 543:40]
wire _T_1213 = _T_1209 ? _T_1211 : a_ff[9]; // @[el2_lib.scala 543:23]
wire _T_1215 = |a_ff[9:0]; // @[el2_lib.scala 543:35]
wire _T_1217 = ~a_ff[10]; // @[el2_lib.scala 543:40]
wire _T_1219 = _T_1215 ? _T_1217 : a_ff[10]; // @[el2_lib.scala 543:23]
wire _T_1221 = |a_ff[10:0]; // @[el2_lib.scala 543:35]
wire _T_1223 = ~a_ff[11]; // @[el2_lib.scala 543:40]
wire _T_1225 = _T_1221 ? _T_1223 : a_ff[11]; // @[el2_lib.scala 543:23]
wire _T_1227 = |a_ff[11:0]; // @[el2_lib.scala 543:35]
wire _T_1229 = ~a_ff[12]; // @[el2_lib.scala 543:40]
wire _T_1231 = _T_1227 ? _T_1229 : a_ff[12]; // @[el2_lib.scala 543:23]
wire _T_1233 = |a_ff[12:0]; // @[el2_lib.scala 543:35]
wire _T_1235 = ~a_ff[13]; // @[el2_lib.scala 543:40]
wire _T_1237 = _T_1233 ? _T_1235 : a_ff[13]; // @[el2_lib.scala 543:23]
wire _T_1239 = |a_ff[13:0]; // @[el2_lib.scala 543:35]
wire _T_1241 = ~a_ff[14]; // @[el2_lib.scala 543:40]
wire _T_1243 = _T_1239 ? _T_1241 : a_ff[14]; // @[el2_lib.scala 543:23]
wire _T_1245 = |a_ff[14:0]; // @[el2_lib.scala 543:35]
wire _T_1247 = ~a_ff[15]; // @[el2_lib.scala 543:40]
wire _T_1249 = _T_1245 ? _T_1247 : a_ff[15]; // @[el2_lib.scala 543:23]
wire _T_1251 = |a_ff[15:0]; // @[el2_lib.scala 543:35]
wire _T_1253 = ~a_ff[16]; // @[el2_lib.scala 543:40]
wire _T_1255 = _T_1251 ? _T_1253 : a_ff[16]; // @[el2_lib.scala 543:23]
wire _T_1257 = |a_ff[16:0]; // @[el2_lib.scala 543:35]
wire _T_1259 = ~a_ff[17]; // @[el2_lib.scala 543:40]
wire _T_1261 = _T_1257 ? _T_1259 : a_ff[17]; // @[el2_lib.scala 543:23]
wire _T_1263 = |a_ff[17:0]; // @[el2_lib.scala 543:35]
wire _T_1265 = ~a_ff[18]; // @[el2_lib.scala 543:40]
wire _T_1267 = _T_1263 ? _T_1265 : a_ff[18]; // @[el2_lib.scala 543:23]
wire _T_1269 = |a_ff[18:0]; // @[el2_lib.scala 543:35]
wire _T_1271 = ~a_ff[19]; // @[el2_lib.scala 543:40]
wire _T_1273 = _T_1269 ? _T_1271 : a_ff[19]; // @[el2_lib.scala 543:23]
wire _T_1275 = |a_ff[19:0]; // @[el2_lib.scala 543:35]
wire _T_1277 = ~a_ff[20]; // @[el2_lib.scala 543:40]
wire _T_1279 = _T_1275 ? _T_1277 : a_ff[20]; // @[el2_lib.scala 543:23]
wire _T_1281 = |a_ff[20:0]; // @[el2_lib.scala 543:35]
wire _T_1283 = ~a_ff[21]; // @[el2_lib.scala 543:40]
wire _T_1285 = _T_1281 ? _T_1283 : a_ff[21]; // @[el2_lib.scala 543:23]
wire _T_1287 = |a_ff[21:0]; // @[el2_lib.scala 543:35]
wire _T_1289 = ~a_ff[22]; // @[el2_lib.scala 543:40]
wire _T_1291 = _T_1287 ? _T_1289 : a_ff[22]; // @[el2_lib.scala 543:23]
wire _T_1293 = |a_ff[22:0]; // @[el2_lib.scala 543:35]
wire _T_1295 = ~a_ff[23]; // @[el2_lib.scala 543:40]
wire _T_1297 = _T_1293 ? _T_1295 : a_ff[23]; // @[el2_lib.scala 543:23]
wire _T_1299 = |a_ff[23:0]; // @[el2_lib.scala 543:35]
wire _T_1301 = ~a_ff[24]; // @[el2_lib.scala 543:40]
wire _T_1303 = _T_1299 ? _T_1301 : a_ff[24]; // @[el2_lib.scala 543:23]
wire _T_1305 = |a_ff[24:0]; // @[el2_lib.scala 543:35]
wire _T_1307 = ~a_ff[25]; // @[el2_lib.scala 543:40]
wire _T_1309 = _T_1305 ? _T_1307 : a_ff[25]; // @[el2_lib.scala 543:23]
wire _T_1311 = |a_ff[25:0]; // @[el2_lib.scala 543:35]
wire _T_1313 = ~a_ff[26]; // @[el2_lib.scala 543:40]
wire _T_1315 = _T_1311 ? _T_1313 : a_ff[26]; // @[el2_lib.scala 543:23]
wire _T_1317 = |a_ff[26:0]; // @[el2_lib.scala 543:35]
wire _T_1319 = ~a_ff[27]; // @[el2_lib.scala 543:40]
wire _T_1321 = _T_1317 ? _T_1319 : a_ff[27]; // @[el2_lib.scala 543:23]
wire _T_1323 = |a_ff[27:0]; // @[el2_lib.scala 543:35]
wire _T_1325 = ~a_ff[28]; // @[el2_lib.scala 543:40]
wire _T_1327 = _T_1323 ? _T_1325 : a_ff[28]; // @[el2_lib.scala 543:23]
wire _T_1329 = |a_ff[28:0]; // @[el2_lib.scala 543:35]
wire _T_1331 = ~a_ff[29]; // @[el2_lib.scala 543:40]
wire _T_1333 = _T_1329 ? _T_1331 : a_ff[29]; // @[el2_lib.scala 543:23]
wire _T_1335 = |a_ff[29:0]; // @[el2_lib.scala 543:35]
wire _T_1337 = ~a_ff[30]; // @[el2_lib.scala 543:40]
wire _T_1339 = _T_1335 ? _T_1337 : a_ff[30]; // @[el2_lib.scala 543:23]
wire _T_1341 = |a_ff[30:0]; // @[el2_lib.scala 543:35]
wire _T_1343 = ~a_ff[31]; // @[el2_lib.scala 543:40]
wire _T_1345 = _T_1341 ? _T_1343 : a_ff[31]; // @[el2_lib.scala 543:23]
wire [6:0] _T_1351 = {_T_1201,_T_1195,_T_1189,_T_1183,_T_1177,_T_1171,_T_1165}; // @[el2_lib.scala 545:14]
wire [14:0] _T_1359 = {_T_1249,_T_1243,_T_1237,_T_1231,_T_1225,_T_1219,_T_1213,_T_1207,_T_1351}; // @[el2_lib.scala 545:14]
wire [7:0] _T_1366 = {_T_1297,_T_1291,_T_1285,_T_1279,_T_1273,_T_1267,_T_1261,_T_1255}; // @[el2_lib.scala 545:14]
wire [30:0] _T_1375 = {_T_1345,_T_1339,_T_1333,_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1366,_T_1359}; // @[el2_lib.scala 545:14]
wire [31:0] _T_1377 = {_T_1375,a_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] a_ff_eff = _T_660 ? _T_1377 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 193:21]
reg smallnum_case_ff; // @[el2_exu_div_ctl.scala 212:32]
reg [3:0] smallnum_ff; // @[el2_exu_div_ctl.scala 213:27]
wire [31:0] _T_1380 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
wire _T_1382 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 198:6]
wire _T_1384 = _T_1382 & _T_9; // @[el2_exu_div_ctl.scala 198:24]
wire [31:0] _T_1386 = smallnum_case_ff ? _T_1380 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1387 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1388 = _T_1384 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1389 = _T_1386 | _T_1387; // @[Mux.scala 27:72]
wire _T_1421 = _T_631 & io_divisor[31]; // @[el2_exu_div_ctl.scala 219:41]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
assign io_out = _T_1389 | _T_1388; // @[el2_exu_div_ctl.scala 50:10 el2_exu_div_ctl.scala 195:10]
assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 51:17 el2_exu_div_ctl.scala 165:18]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = _T_610 | finish_ff; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_1_io_en = io_dp_valid | _T_659; // @[el2_lib.scala 511:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_2_io_en = _T_912 | rem_correct; // @[el2_lib.scala 511:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_3_io_en = io_dp_valid; // @[el2_lib.scala 511:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
valid_ff_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
q_ff = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
m_ff = _RAND_2[32:0];
_RAND_3 = {1{`RANDOM}};
rem_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
sign_ff = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
shortq_shift_xx = _RAND_5[3:0];
_RAND_6 = {1{`RANDOM}};
count = _RAND_6[5:0];
_RAND_7 = {1{`RANDOM}};
run_state = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
finish_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
shortq_enable_ff = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
dividend_neg_ff = _RAND_10[0:0];
_RAND_11 = {2{`RANDOM}};
a_ff = _RAND_11[32:0];
_RAND_12 = {1{`RANDOM}};
divisor_neg_ff = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
smallnum_case_ff = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
smallnum_ff = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valid_ff_x = 1'h0;
end
if (reset) begin
q_ff = 33'h0;
end
if (reset) begin
m_ff = 33'h0;
end
if (reset) begin
rem_ff = 1'h0;
end
if (reset) begin
sign_ff = 1'h0;
end
if (reset) begin
shortq_shift_xx = 4'h0;
end
if (reset) begin
count = 6'h0;
end
if (reset) begin
run_state = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
dividend_neg_ff = 1'h0;
end
if (reset) begin
a_ff = 33'h0;
end
if (reset) begin
divisor_neg_ff = 1'h0;
end
if (reset) begin
smallnum_case_ff = 1'h0;
end
if (reset) begin
smallnum_ff = 4'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
valid_ff_x <= 1'h0;
end else begin
valid_ff_x <= io_dp_valid & _T;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
q_ff <= 33'h0;
end else begin
q_ff <= _T_656[32:0];
end
end
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin
m_ff <= 33'h0;
end else begin
m_ff <= {_T_1421,io_divisor};
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
rem_ff <= 1'h0;
end else if (io_dp_valid) begin
rem_ff <= io_dp_bits_rem;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
sign_ff <= 1'h0;
end else if (io_dp_valid) begin
sign_ff <= sign_eff;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
shortq_shift_xx <= 4'h0;
end else begin
shortq_shift_xx <= _T_589 & shortq_raw;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
count <= 6'h0;
end else begin
count <= _T_622 & _T_627;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
run_state <= 1'h0;
end else begin
run_state <= _T_613 & _T;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else begin
finish_ff <= finish & _T;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else begin
shortq_enable_ff <= _T_586 & _T_587;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
dividend_neg_ff <= 1'h0;
end else if (io_dp_valid) begin
dividend_neg_ff <= io_dividend[31];
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
a_ff <= 33'h0;
end else begin
a_ff <= _T_917 & _T_923;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
divisor_neg_ff <= 1'h0;
end else if (io_dp_valid) begin
divisor_neg_ff <= io_divisor[31];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
smallnum_case_ff <= 1'h0;
end else begin
smallnum_case_ff <= _T_11 | _T_19;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
smallnum_ff <= 4'h0;
end else begin
smallnum_ff <= {_T_399,_T_398};
end
end
endmodule

23
el2_exu_mul_ctl.anno.json
View File

@ -1,23 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_mul_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_mul_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

145
el2_exu_mul_ctl.fir
View File

@ -1,145 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu_mul_ctl :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module el2_exu_mul_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
wire rs1_ext_in : SInt<33>
rs1_ext_in <= asSInt(UInt<1>("h00"))
wire rs2_ext_in : SInt<33>
rs2_ext_in <= asSInt(UInt<1>("h00"))
wire rs1_x : SInt<33>
rs1_x <= asSInt(UInt<1>("h00"))
wire rs2_x : SInt<33>
rs2_x <= asSInt(UInt<1>("h00"))
wire prod_x : SInt<66>
prod_x <= asSInt(UInt<1>("h00"))
wire low_x : UInt<1>
low_x <= UInt<1>("h00")
node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:55]
node _T_1 = and(io.mul_p.bits.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:44]
node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:71]
rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14]
node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:55]
node _T_5 = and(io.mul_p.bits.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:44]
node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:71]
rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 29:52]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr.io.en <= _T_8 @[el2_lib.scala 511:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16]
low_x <= _T_9 @[el2_exu_mul_ctl.scala 29:9]
node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 30:44]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 528:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 530:18]
rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 531:17]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
_T_11 <= rs1_ext_in @[el2_lib.scala 534:16]
rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 30:9]
node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 31:45]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 528:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 530:18]
rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 531:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
_T_13 <= rs2_ext_in @[el2_lib.scala 534:16]
rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 31:9]
node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 33:20]
prod_x <= _T_14 @[el2_exu_mul_ctl.scala 33:10]
node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:36]
node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 34:29]
node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 34:52]
node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:67]
node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 34:83]
node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
wire _T_23 : UInt<32> @[Mux.scala 27:72]
_T_23 <= _T_22 @[Mux.scala 27:72]
io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 34:15]

181
el2_exu_mul_ctl.v
View File

@ -1,181 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_exu_mul_ctl(
input clock,
input reset,
input io_scan_mode,
input io_mul_p_valid,
input io_mul_p_bits_rs1_sign,
input io_mul_p_bits_rs2_sign,
input io_mul_p_bits_low,
input io_mul_p_bits_bext,
input io_mul_p_bits_bdep,
input io_mul_p_bits_clmul,
input io_mul_p_bits_clmulh,
input io_mul_p_bits_clmulr,
input io_mul_p_bits_grev,
input io_mul_p_bits_shfl,
input io_mul_p_bits_unshfl,
input io_mul_p_bits_crc32_b,
input io_mul_p_bits_crc32_h,
input io_mul_p_bits_crc32_w,
input io_mul_p_bits_crc32c_b,
input io_mul_p_bits_crc32c_h,
input io_mul_p_bits_crc32c_w,
input io_mul_p_bits_bfp,
input [31:0] io_rs1_in,
input [31:0] io_rs2_in,
output [31:0] io_result_x
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 528:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 528:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 528:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 528:23]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 528:23]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 528:23]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 528:23]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 528:23]
wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:44]
wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:44]
reg low_x; // @[el2_lib.scala 514:16]
reg [32:0] rs1_x; // @[el2_lib.scala 534:16]
reg [32:0] rs2_x; // @[el2_lib.scala 534:16]
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 33:20]
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 34:29]
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 528:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 528:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 34:15]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 530:18]
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 530:18]
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
low_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
rs1_x = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
rs2_x = _RAND_2[32:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
low_x = 1'h0;
end
if (reset) begin
rs1_x = 33'sh0;
end
if (reset) begin
rs2_x = 33'sh0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
low_x <= 1'h0;
end else begin
low_x <= io_mul_p_bits_low;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
rs1_x <= 33'sh0;
end else begin
rs1_x <= {_T_1,io_rs1_in};
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
rs2_x <= 33'sh0;
end else begin
rs2_x <= {_T_5,io_rs2_in};
end
end
endmodule

367
el2_ifu.anno.json
View File

@ -1,367 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_ifu_pmu_instr_aligned",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr",
"sources":[
"~el2_ifu|el2_ifu>io_dma_mem_addr",
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_rd_en",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_en",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_addr",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rden",
"sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_size",
"sources":[
"~el2_ifu|el2_ifu>io_dma_mem_sz",
"~el2_ifu|el2_ifu>io_dma_iccm_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start",
"sources":[
"~el2_ifu|el2_ifu>io_ic_eccerr",
"~el2_ifu|el2_ifu>io_ic_tag_perr",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_mrac_ff",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
"sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_wdata",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_way",
"sources":[
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wren",
"sources":[
"~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_iccm_rd_data",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_r_bits_id",
"~el2_ifu|el2_ifu>io_ifu_r_valid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
"sources":[
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_ifc_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

64203
el2_ifu.fir
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45245
el2_ifu.v
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File diff suppressed because it is too large Load Diff

53
el2_ifu_aln_ctl.anno.json
View File

@ -1,53 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_i0_brp_bits_br_error",
"sources":[
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_i0_brp_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_fb_consume1",
"sources":[
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_exu_flush_final",
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_pmu_instr_aligned",
"sources":[
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_fb_consume2",
"sources":[
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_exu_flush_final",
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_aln_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_aln_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_ifu_aln_ctl.fir
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1465
el2_ifu_aln_ctl.v
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el2_ifu_bp_ctl.anno.json
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@ -1,154 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist0_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist1_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_valid_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_inst_mask_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_poffset_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_ret_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_btb_target_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_way_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_bits_misp",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_pc4_f",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_bp_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_bp_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_ifu_bp_ctl.v
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el2_ifu_compress_ctl.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_out",
"sources":[
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_compress_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_ifu_compress_ctl.fir
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el2_ifu_compress_ctl.v
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@ -1,187 +0,0 @@
module el2_ifu_compress_ctl(
input clock,
input reset,
input [15:0] io_in,
output [31:0] io_out
);
wire _T_4 = ~io_in[14]; // @[el2_ifu_compress_ctl.scala 18:34]
wire _T_5 = io_in[15] & _T_4; // @[el2_ifu_compress_ctl.scala 18:32]
wire _T_7 = ~io_in[13]; // @[el2_ifu_compress_ctl.scala 18:47]
wire _T_8 = _T_5 & _T_7; // @[el2_ifu_compress_ctl.scala 18:45]
wire _T_10 = _T_8 & io_in[10]; // @[el2_ifu_compress_ctl.scala 18:58]
wire _T_12 = ~io_in[6]; // @[el2_ifu_compress_ctl.scala 18:70]
wire _T_13 = _T_10 & _T_12; // @[el2_ifu_compress_ctl.scala 18:68]
wire _T_15 = ~io_in[5]; // @[el2_ifu_compress_ctl.scala 18:82]
wire _T_16 = _T_13 & _T_15; // @[el2_ifu_compress_ctl.scala 18:80]
wire _T_18 = _T_16 & io_in[0]; // @[el2_ifu_compress_ctl.scala 18:92]
wire _T_22 = io_in[14] & _T_4; // @[el2_ifu_compress_ctl.scala 19:27]
wire _T_25 = _T_22 & _T_7; // @[el2_ifu_compress_ctl.scala 19:40]
wire _T_27 = ~io_in[11]; // @[el2_ifu_compress_ctl.scala 19:55]
wire _T_28 = _T_25 & _T_27; // @[el2_ifu_compress_ctl.scala 19:53]
wire _T_30 = _T_28 & io_in[10]; // @[el2_ifu_compress_ctl.scala 19:66]
wire _T_32 = _T_30 & io_in[0]; // @[el2_ifu_compress_ctl.scala 19:76]
wire _T_33 = _T_18 | _T_32; // @[el2_ifu_compress_ctl.scala 19:15]
wire _T_38 = _T_4 & io_in[12]; // @[el2_ifu_compress_ctl.scala 20:25]
wire _T_41 = _T_38 & _T_27; // @[el2_ifu_compress_ctl.scala 20:35]
wire _T_43 = ~io_in[10]; // @[el2_ifu_compress_ctl.scala 20:50]
wire _T_44 = _T_41 & _T_43; // @[el2_ifu_compress_ctl.scala 20:48]
wire _T_46 = ~io_in[9]; // @[el2_ifu_compress_ctl.scala 20:63]
wire _T_47 = _T_44 & _T_46; // @[el2_ifu_compress_ctl.scala 20:61]
wire _T_49 = ~io_in[8]; // @[el2_ifu_compress_ctl.scala 20:75]
wire _T_50 = _T_47 & _T_49; // @[el2_ifu_compress_ctl.scala 20:73]
wire _T_52 = ~io_in[7]; // @[el2_ifu_compress_ctl.scala 20:87]
wire _T_53 = _T_50 & _T_52; // @[el2_ifu_compress_ctl.scala 20:85]
wire _T_56 = _T_53 & _T_12; // @[el2_ifu_compress_ctl.scala 20:97]
wire _T_59 = _T_56 & _T_15; // @[el2_ifu_compress_ctl.scala 20:109]
wire _T_61 = ~io_in[4]; // @[el2_ifu_compress_ctl.scala 21:16]
wire _T_62 = _T_59 & _T_61; // @[el2_ifu_compress_ctl.scala 20:121]
wire _T_64 = ~io_in[3]; // @[el2_ifu_compress_ctl.scala 21:28]
wire _T_65 = _T_62 & _T_64; // @[el2_ifu_compress_ctl.scala 21:26]
wire _T_67 = ~io_in[2]; // @[el2_ifu_compress_ctl.scala 21:40]
wire _T_68 = _T_65 & _T_67; // @[el2_ifu_compress_ctl.scala 21:38]
wire _T_70 = _T_68 & io_in[1]; // @[el2_ifu_compress_ctl.scala 21:50]
wire _T_81 = _T_8 & _T_27; // @[el2_ifu_compress_ctl.scala 22:50]
wire _T_83 = _T_81 & io_in[0]; // @[el2_ifu_compress_ctl.scala 22:63]
wire _T_93 = _T_8 & _T_43; // @[el2_ifu_compress_ctl.scala 23:51]
wire _T_95 = _T_93 & io_in[0]; // @[el2_ifu_compress_ctl.scala 23:64]
wire _T_96 = _T_83 | _T_95; // @[el2_ifu_compress_ctl.scala 23:15]
wire _T_105 = _T_8 & io_in[6]; // @[el2_ifu_compress_ctl.scala 24:51]
wire _T_107 = _T_105 & io_in[0]; // @[el2_ifu_compress_ctl.scala 24:60]
wire _T_108 = _T_96 | _T_107; // @[el2_ifu_compress_ctl.scala 24:15]
wire _T_117 = _T_8 & io_in[5]; // @[el2_ifu_compress_ctl.scala 25:51]
wire _T_119 = _T_117 & io_in[0]; // @[el2_ifu_compress_ctl.scala 25:60]
wire _T_120 = _T_108 | _T_119; // @[el2_ifu_compress_ctl.scala 25:15]
wire _T_131 = _T_105 & io_in[5]; // @[el2_ifu_compress_ctl.scala 26:59]
wire _T_133 = _T_131 & io_in[0]; // @[el2_ifu_compress_ctl.scala 26:68]
wire _T_146 = _T_133 | _T_83; // @[el2_ifu_compress_ctl.scala 27:15]
wire _T_159 = _T_146 | _T_95; // @[el2_ifu_compress_ctl.scala 28:15]
wire _T_161 = ~io_in[15]; // @[el2_ifu_compress_ctl.scala 29:17]
wire _T_164 = _T_161 & _T_4; // @[el2_ifu_compress_ctl.scala 29:28]
wire _T_166 = _T_164 & io_in[1]; // @[el2_ifu_compress_ctl.scala 29:41]
wire _T_167 = _T_159 | _T_166; // @[el2_ifu_compress_ctl.scala 29:15]
wire _T_170 = io_in[15] & io_in[14]; // @[el2_ifu_compress_ctl.scala 29:62]
wire _T_172 = _T_170 & io_in[13]; // @[el2_ifu_compress_ctl.scala 29:72]
wire _T_173 = _T_167 | _T_172; // @[el2_ifu_compress_ctl.scala 29:51]
wire _T_234 = _T_5 & _T_12; // @[el2_ifu_compress_ctl.scala 34:37]
wire _T_237 = _T_234 & _T_15; // @[el2_ifu_compress_ctl.scala 34:49]
wire _T_240 = _T_237 & _T_61; // @[el2_ifu_compress_ctl.scala 34:61]
wire _T_243 = _T_240 & _T_64; // @[el2_ifu_compress_ctl.scala 34:73]
wire _T_246 = _T_243 & _T_67; // @[el2_ifu_compress_ctl.scala 34:85]
wire _T_248 = ~io_in[0]; // @[el2_ifu_compress_ctl.scala 34:99]
wire _T_249 = _T_246 & _T_248; // @[el2_ifu_compress_ctl.scala 34:97]
wire _T_253 = _T_4 & io_in[13]; // @[el2_ifu_compress_ctl.scala 35:28]
wire _T_254 = _T_249 | _T_253; // @[el2_ifu_compress_ctl.scala 35:15]
wire _T_259 = _T_170 & io_in[0]; // @[el2_ifu_compress_ctl.scala 35:60]
wire _T_260 = _T_254 | _T_259; // @[el2_ifu_compress_ctl.scala 35:39]
wire _T_264 = io_in[15] & _T_248; // @[el2_ifu_compress_ctl.scala 35:80]
wire _T_267 = io_in[15] & io_in[11]; // @[el2_ifu_compress_ctl.scala 36:25]
wire _T_269 = _T_267 & io_in[10]; // @[el2_ifu_compress_ctl.scala 36:35]
wire _T_270 = _T_264 | _T_269; // @[el2_ifu_compress_ctl.scala 36:15]
wire _T_274 = io_in[13] & _T_49; // @[el2_ifu_compress_ctl.scala 36:57]
wire _T_275 = _T_270 | _T_274; // @[el2_ifu_compress_ctl.scala 36:46]
wire _T_280 = _T_275 | _T_274; // @[el2_ifu_compress_ctl.scala 37:15]
wire _T_283 = io_in[13] & io_in[7]; // @[el2_ifu_compress_ctl.scala 37:47]
wire _T_284 = _T_280 | _T_283; // @[el2_ifu_compress_ctl.scala 37:37]
wire _T_287 = io_in[13] & io_in[9]; // @[el2_ifu_compress_ctl.scala 37:66]
wire _T_288 = _T_284 | _T_287; // @[el2_ifu_compress_ctl.scala 37:56]
wire _T_291 = io_in[13] & io_in[10]; // @[el2_ifu_compress_ctl.scala 37:85]
wire _T_292 = _T_288 | _T_291; // @[el2_ifu_compress_ctl.scala 37:75]
wire _T_295 = io_in[13] & io_in[11]; // @[el2_ifu_compress_ctl.scala 38:25]
wire _T_296 = _T_292 | _T_295; // @[el2_ifu_compress_ctl.scala 38:15]
wire _T_300 = io_in[13] & _T_4; // @[el2_ifu_compress_ctl.scala 38:45]
wire _T_301 = _T_296 | _T_300; // @[el2_ifu_compress_ctl.scala 38:35]
wire _T_304 = io_in[14] & io_in[15]; // @[el2_ifu_compress_ctl.scala 38:68]
wire _T_305 = _T_301 | _T_304; // @[el2_ifu_compress_ctl.scala 38:58]
wire _T_310 = _T_4 & _T_27; // @[el2_ifu_compress_ctl.scala 39:25]
wire _T_313 = _T_310 & _T_43; // @[el2_ifu_compress_ctl.scala 39:38]
wire _T_316 = _T_313 & _T_46; // @[el2_ifu_compress_ctl.scala 39:51]
wire _T_319 = _T_316 & _T_49; // @[el2_ifu_compress_ctl.scala 39:63]
wire _T_322 = _T_319 & _T_52; // @[el2_ifu_compress_ctl.scala 39:75]
wire _T_325 = _T_322 & _T_248; // @[el2_ifu_compress_ctl.scala 39:87]
wire _T_333 = _T_164 & _T_248; // @[el2_ifu_compress_ctl.scala 40:41]
wire _T_334 = _T_325 | _T_333; // @[el2_ifu_compress_ctl.scala 40:15]
wire _T_338 = _T_4 & io_in[6]; // @[el2_ifu_compress_ctl.scala 40:66]
wire _T_341 = _T_338 & _T_248; // @[el2_ifu_compress_ctl.scala 40:75]
wire _T_342 = _T_334 | _T_341; // @[el2_ifu_compress_ctl.scala 40:53]
wire _T_346 = _T_161 & io_in[14]; // @[el2_ifu_compress_ctl.scala 41:28]
wire _T_348 = _T_346 & io_in[0]; // @[el2_ifu_compress_ctl.scala 41:38]
wire _T_349 = _T_342 | _T_348; // @[el2_ifu_compress_ctl.scala 41:15]
wire _T_353 = _T_4 & io_in[5]; // @[el2_ifu_compress_ctl.scala 41:60]
wire _T_356 = _T_353 & _T_248; // @[el2_ifu_compress_ctl.scala 41:69]
wire _T_357 = _T_349 | _T_356; // @[el2_ifu_compress_ctl.scala 41:47]
wire _T_361 = _T_4 & io_in[4]; // @[el2_ifu_compress_ctl.scala 42:28]
wire _T_364 = _T_361 & _T_248; // @[el2_ifu_compress_ctl.scala 42:37]
wire _T_365 = _T_357 | _T_364; // @[el2_ifu_compress_ctl.scala 42:15]
wire _T_370 = _T_4 & _T_7; // @[el2_ifu_compress_ctl.scala 42:64]
wire _T_372 = _T_370 & io_in[0]; // @[el2_ifu_compress_ctl.scala 42:77]
wire _T_373 = _T_365 | _T_372; // @[el2_ifu_compress_ctl.scala 42:50]
wire _T_377 = _T_4 & io_in[3]; // @[el2_ifu_compress_ctl.scala 43:28]
wire _T_380 = _T_377 & _T_248; // @[el2_ifu_compress_ctl.scala 43:37]
wire _T_381 = _T_373 | _T_380; // @[el2_ifu_compress_ctl.scala 43:15]
wire _T_385 = _T_4 & io_in[2]; // @[el2_ifu_compress_ctl.scala 43:64]
wire _T_388 = _T_385 & _T_248; // @[el2_ifu_compress_ctl.scala 43:73]
wire _T_389 = _T_381 | _T_388; // @[el2_ifu_compress_ctl.scala 43:50]
wire _T_399 = _T_38 & io_in[11]; // @[el2_ifu_compress_ctl.scala 45:35]
wire _T_402 = _T_399 & _T_12; // @[el2_ifu_compress_ctl.scala 45:45]
wire _T_405 = _T_402 & _T_15; // @[el2_ifu_compress_ctl.scala 45:57]
wire _T_408 = _T_405 & _T_61; // @[el2_ifu_compress_ctl.scala 45:69]
wire _T_411 = _T_408 & _T_64; // @[el2_ifu_compress_ctl.scala 45:81]
wire _T_414 = _T_411 & _T_67; // @[el2_ifu_compress_ctl.scala 45:93]
wire _T_416 = _T_414 & io_in[1]; // @[el2_ifu_compress_ctl.scala 45:105]
wire _T_422 = _T_38 & io_in[10]; // @[el2_ifu_compress_ctl.scala 46:38]
wire _T_425 = _T_422 & _T_12; // @[el2_ifu_compress_ctl.scala 46:48]
wire _T_428 = _T_425 & _T_15; // @[el2_ifu_compress_ctl.scala 46:60]
wire _T_431 = _T_428 & _T_61; // @[el2_ifu_compress_ctl.scala 46:72]
wire _T_434 = _T_431 & _T_64; // @[el2_ifu_compress_ctl.scala 46:84]
wire _T_437 = _T_434 & _T_67; // @[el2_ifu_compress_ctl.scala 46:96]
wire _T_439 = _T_437 & io_in[1]; // @[el2_ifu_compress_ctl.scala 46:108]
wire _T_440 = _T_416 | _T_439; // @[el2_ifu_compress_ctl.scala 46:15]
wire _T_446 = _T_38 & io_in[9]; // @[el2_ifu_compress_ctl.scala 47:38]
wire _T_449 = _T_446 & _T_12; // @[el2_ifu_compress_ctl.scala 47:47]
wire _T_452 = _T_449 & _T_15; // @[el2_ifu_compress_ctl.scala 47:59]
wire _T_455 = _T_452 & _T_61; // @[el2_ifu_compress_ctl.scala 47:71]
wire _T_458 = _T_455 & _T_64; // @[el2_ifu_compress_ctl.scala 47:83]
wire _T_461 = _T_458 & _T_67; // @[el2_ifu_compress_ctl.scala 47:95]
wire _T_463 = _T_461 & io_in[1]; // @[el2_ifu_compress_ctl.scala 47:107]
wire _T_464 = _T_440 | _T_463; // @[el2_ifu_compress_ctl.scala 47:15]
wire _T_470 = _T_38 & io_in[8]; // @[el2_ifu_compress_ctl.scala 48:38]
wire _T_473 = _T_470 & _T_12; // @[el2_ifu_compress_ctl.scala 48:47]
wire _T_476 = _T_473 & _T_15; // @[el2_ifu_compress_ctl.scala 48:59]
wire _T_479 = _T_476 & _T_61; // @[el2_ifu_compress_ctl.scala 48:71]
wire _T_482 = _T_479 & _T_64; // @[el2_ifu_compress_ctl.scala 48:83]
wire _T_485 = _T_482 & _T_67; // @[el2_ifu_compress_ctl.scala 48:95]
wire _T_487 = _T_485 & io_in[1]; // @[el2_ifu_compress_ctl.scala 48:107]
wire _T_488 = _T_464 | _T_487; // @[el2_ifu_compress_ctl.scala 48:15]
wire _T_494 = _T_38 & io_in[7]; // @[el2_ifu_compress_ctl.scala 49:38]
wire _T_497 = _T_494 & _T_12; // @[el2_ifu_compress_ctl.scala 49:47]
wire _T_500 = _T_497 & _T_15; // @[el2_ifu_compress_ctl.scala 49:59]
wire _T_503 = _T_500 & _T_61; // @[el2_ifu_compress_ctl.scala 49:71]
wire _T_506 = _T_503 & _T_64; // @[el2_ifu_compress_ctl.scala 49:83]
wire _T_509 = _T_506 & _T_67; // @[el2_ifu_compress_ctl.scala 49:95]
wire _T_511 = _T_509 & io_in[1]; // @[el2_ifu_compress_ctl.scala 49:107]
wire _T_512 = _T_488 | _T_511; // @[el2_ifu_compress_ctl.scala 49:15]
wire _T_518 = ~io_in[12]; // @[el2_ifu_compress_ctl.scala 50:40]
wire _T_519 = _T_5 & _T_518; // @[el2_ifu_compress_ctl.scala 50:38]
wire _T_522 = _T_519 & _T_12; // @[el2_ifu_compress_ctl.scala 50:51]
wire _T_525 = _T_522 & _T_15; // @[el2_ifu_compress_ctl.scala 50:63]
wire _T_528 = _T_525 & _T_61; // @[el2_ifu_compress_ctl.scala 50:75]
wire _T_531 = _T_528 & _T_64; // @[el2_ifu_compress_ctl.scala 50:87]
wire _T_534 = _T_531 & _T_67; // @[el2_ifu_compress_ctl.scala 50:99]
wire _T_537 = _T_534 & _T_248; // @[el2_ifu_compress_ctl.scala 50:111]
wire _T_538 = _T_512 | _T_537; // @[el2_ifu_compress_ctl.scala 50:15]
wire _T_542 = _T_161 & io_in[13]; // @[el2_ifu_compress_ctl.scala 51:28]
wire _T_545 = _T_542 & _T_49; // @[el2_ifu_compress_ctl.scala 51:38]
wire _T_546 = _T_538 | _T_545; // @[el2_ifu_compress_ctl.scala 51:15]
wire _T_552 = _T_542 & io_in[7]; // @[el2_ifu_compress_ctl.scala 51:75]
wire _T_553 = _T_546 | _T_552; // @[el2_ifu_compress_ctl.scala 51:51]
wire _T_559 = _T_542 & io_in[9]; // @[el2_ifu_compress_ctl.scala 51:109]
wire _T_560 = _T_553 | _T_559; // @[el2_ifu_compress_ctl.scala 51:85]
wire _T_566 = _T_542 & io_in[10]; // @[el2_ifu_compress_ctl.scala 52:38]
wire _T_567 = _T_560 | _T_566; // @[el2_ifu_compress_ctl.scala 52:15]
wire _T_573 = _T_542 & io_in[11]; // @[el2_ifu_compress_ctl.scala 52:73]
wire _T_574 = _T_567 | _T_573; // @[el2_ifu_compress_ctl.scala 52:49]
wire _T_579 = _T_574 | _T_253; // @[el2_ifu_compress_ctl.scala 52:84]
wire [11:0] _T_586 = {5'h0,_T_260,_T_305,_T_389,_T_253,_T_579,2'h3}; // @[Cat.scala 29:58]
wire [19:0] _T_593 = {1'h0,_T_33,9'h0,_T_70,5'h0,_T_120,_T_173,_T_173}; // @[Cat.scala 29:58]
assign io_out = {_T_593,_T_586}; // @[el2_ifu_compress_ctl.scala 111:10]
endmodule

18
el2_ifu_ic_mem.anno.json
View File

@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_ic_mem"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

15
el2_ifu_ic_mem.fir
View File

@ -1,15 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ic_mem :
module el2_ifu_ic_mem :
input clock : Clock
input reset : UInt<1>
output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18]
io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16]
io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16]
io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23]
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17]

38
el2_ifu_ic_mem.v
View File

@ -1,38 +0,0 @@
module el2_ifu_ic_mem(
input clock,
input reset,
input io_clk,
input io_rst_l,
input io_clk_override,
input io_dec_tlu_core_ecc_disable,
input [30:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input io_ic_rd_en,
input [8:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
input [63:0] io_ic_premux_data,
input io_ic_sel_premux_data,
input [70:0] io_ic_wr_data_0,
input [70:0] io_ic_wr_data_1,
output [63:0] io_ic_rd_data,
output [70:0] io_ic_debug_rd_data,
output [25:0] io_ictag_debug_rd_data,
input [70:0] io_ic_debug_wr_data,
output [1:0] io_ic_eccerr,
output [1:0] io_ic_parerr,
input [1:0] io_ic_tag_valid,
output [1:0] io_ic_rd_hit,
output io_ic_tag_perr,
input io_scan_mode
);
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 40:17]
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 39:23]
assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 37:16]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 36:16]
assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18]
endmodule

127
el2_ifu_ifc_ctl.anno.json
View File

@ -1,127 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_dma_access_ok",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_region_acc_fault_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_uncacheable_bf",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_mrac_ff",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_ifc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_ifc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

295
el2_ifu_ifc_ctl.fir
View File

@ -1,295 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_ifc_ctl :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module el2_ifu_ifc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<31>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next_0 : UInt<1>
fetch_addr_next_0 <= UInt<1>("h00")
wire fetch_addr_next : UInt<31>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<31> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24]
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39]
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:45]
_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:45]
state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
wire _T_130 : UInt<4> @[Mux.scala 27:72]
_T_130 <= _T_129 @[Mux.scala 27:72]
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 119:17]
idle <= _T_131 @[el2_ifu_ifc_ctl.scala 119:8]
node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 120:16]
wfm <= _T_132 @[el2_ifu_ifc_ctl.scala 120:7]
node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 122:30]
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctl.scala 122:16]
reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 123:52]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 123:52]
reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 124:50]
_T_134 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 124:50]
fb_write_f <= _T_134 @[el2_ifu_ifc_ctl.scala 124:14]
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 127:40]
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 127:61]
node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 127:19]
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctl.scala 127:17]
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctl.scala 127:84]
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctl.scala 126:60]
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctl.scala 126:33]
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctl.scala 126:26]
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 224:25]
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 224:47]
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 227:14]
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 227:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 132:25]
node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 133:30]
node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 134:39]
node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 134:18]
node _T_148 = and(fb_full_f, _T_147) @[el2_ifu_ifc_ctl.scala 134:16]
node _T_149 = or(_T_145, _T_148) @[el2_ifu_ifc_ctl.scala 133:53]
node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:13]
node _T_151 = and(wfm, _T_150) @[el2_ifu_ifc_ctl.scala 135:11]
node _T_152 = or(_T_149, _T_151) @[el2_ifu_ifc_ctl.scala 134:62]
node _T_153 = or(_T_152, idle) @[el2_ifu_ifc_ctl.scala 135:35]
node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:46]
node _T_155 = and(_T_153, _T_154) @[el2_ifu_ifc_ctl.scala 135:44]
node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 135:67]
io.ifc_dma_access_ok <= _T_156 @[el2_ifu_ifc_ctl.scala 133:24]
node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:33]
node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 137:55]
io.ifc_region_acc_fault_bf <= _T_158 @[el2_ifu_ifc_ctl.scala 137:30]
node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 138:78]
node _T_160 = cat(_T_159, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_161 = dshr(io.dec_tlu_mrac_ff, _T_160) @[el2_ifu_ifc_ctl.scala 138:53]
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_ifc_ctl.scala 138:53]
node _T_163 = not(_T_162) @[el2_ifu_ifc_ctl.scala 138:34]
io.ifc_fetch_uncacheable_bf <= _T_163 @[el2_ifu_ifc_ctl.scala 138:31]
reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 140:57]
_T_164 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 140:57]
io.ifc_fetch_req_f <= _T_164 @[el2_ifu_ifc_ctl.scala 140:22]
node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:73]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr.io.en <= _T_165 @[el2_lib.scala 511:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_166 <= io.ifc_fetch_addr_bf @[el2_lib.scala 514:16]
io.ifc_fetch_addr_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:23]

327
el2_ifu_ifc_ctl.v
View File

@ -1,327 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module el2_ifu_ifc_ctl(
input clock,
input reset,
input io_free_clk,
input io_active_clk,
input io_scan_mode,
input io_ic_hit_f,
input io_ifu_ic_mb_empty,
input io_ifu_fb_consume1,
input io_ifu_fb_consume2,
input io_dec_tlu_flush_noredir_wb,
input io_exu_flush_final,
input [30:0] io_exu_flush_path_final,
input io_ifu_bp_hit_taken_f,
input [30:0] io_ifu_bp_btb_target_f,
input io_ic_dma_active,
input io_ic_write_stall,
input io_dma_iccm_stall_any,
input [31:0] io_dec_tlu_mrac_ff,
output [30:0] io_ifc_fetch_addr_f,
output [30:0] io_ifc_fetch_addr_bf,
output io_ifc_fetch_req_f,
output io_ifu_pmu_fetch_stall,
output io_ifc_fetch_uncacheable_bf,
output io_ifc_fetch_req_bf,
output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:45]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 119:17]
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 124:50]
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 122:30]
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 120:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 123:52]
wire _T_136 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 127:61]
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctl.scala 127:19]
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctl.scala 127:17]
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84]
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60]
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 224:47]
wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 227:29]
wire _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30]
wire _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16]
wire _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53]
wire _T_150 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 135:13]
wire _T_151 = wfm & _T_150; // @[el2_ifu_ifc_ctl.scala 135:11]
wire _T_152 = _T_149 | _T_151; // @[el2_ifu_ifc_ctl.scala 134:62]
wire _T_153 = _T_152 | idle; // @[el2_ifu_ifc_ctl.scala 135:35]
wire _T_155 = _T_153 & _T_2; // @[el2_ifu_ifc_ctl.scala 135:44]
wire _T_157 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 137:33]
wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53]
reg _T_164; // @[el2_ifu_ifc_ctl.scala 140:57]
reg [30:0] _T_166; // @[el2_lib.scala 514:16]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23]
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctl.scala 126:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[el2_ifu_ifc_ctl.scala 138:31]
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25]
assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30]
assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
dma_iccm_stall_any_f = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
miss_a = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
state = _RAND_2[1:0];
_RAND_3 = {1{`RANDOM}};
fb_write_f = _RAND_3[3:0];
_RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_164 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_166 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
dma_iccm_stall_any_f = 1'h0;
end
if (reset) begin
miss_a = 1'h0;
end
if (reset) begin
state = 2'h0;
end
if (reset) begin
fb_write_f = 4'h0;
end
if (reset) begin
fb_full_f = 1'h0;
end
if (reset) begin
_T_164 = 1'h0;
end
if (reset) begin
_T_166 = 31'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
dma_iccm_stall_any_f <= 1'h0;
end else begin
dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
miss_a <= 1'h0;
end else begin
miss_a <= _T_48 & _T_2;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
state <= 2'h0;
end else begin
state <= {next_state_1,next_state_0};
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
fb_write_f <= 4'h0;
end else begin
fb_write_f <= _T_128 | _T_125;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
fb_full_f <= 1'h0;
end else begin
fb_full_f <= fb_write_ns[3];
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
_T_164 <= 1'h0;
end else begin
_T_164 <= io_ifc_fetch_req_bf;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_166 <= 31'h0;
end else begin
_T_166 <= io_ifc_fetch_addr_bf;
end
end
endmodule

357
el2_ifu_mem_ctl.anno.json
View File

@ -1,357 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_sel_premux_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_write_stall",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rw_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_addr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_way",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wren",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_en",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_uncacheable_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_force_halt",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_premux_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_size",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_sz",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_en",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wr_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_dma_active",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_flush_err_wb",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_i0_commit_cmt",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_fetch_val",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_data_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_ready",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_tag_array",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_valid",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_data_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_mem_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_mem_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

15682
el2_ifu_mem_ctl.fir
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File diff suppressed because it is too large Load Diff

11916
el2_ifu_mem_ctl.v
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File diff suppressed because it is too large Load Diff

506
el2_lsu.anno.json
View File

@ -1,506 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_single_ecc_error_incr",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_dma_dccm_ready",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_pkt",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu|el2_lsu>io_axi_rchannel_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_load_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_wren",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_fastint_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_rdaddr",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_wraddr",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_mken",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_rden",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu|el2_lsu>io_axi_rchannel_lsu_axi_arready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_awready",
"~el2_lsu|el2_lsu>io_axi_wchannel_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_inv_r",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_result_m",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_exu_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
"~el2_lsu|el2_lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_pic_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

15814
el2_lsu.fir
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File diff suppressed because it is too large Load Diff

111
el2_lsu_addrcheck.anno.json
View File

@ -1,111 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_exc_mscause_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_nondccm_access_error_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_dccm_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_dccm_access_error_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_access_fault_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_addrcheck"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

252
el2_lsu_addrcheck.fir
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@ -1,252 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_addrcheck :
module el2_lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 253:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 253:49]
wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 258:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 258:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 253:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 253:49]
wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 258:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 258:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[el2_lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 253:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 253:49]
wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 258:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
start_addr_in_pic_d <= _T_11 @[el2_lib.scala 258:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 253:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 253:49]
wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 258:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
end_addr_in_pic_d <= _T_15 @[el2_lib.scala 258:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:48]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:54]
node _T_18 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:91]
node _T_19 = eq(_T_18, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:97]
node base_reg_dccm_or_pic = or(_T_17, _T_19) @[el2_lsu_addrcheck.scala 55:73]
node _T_20 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_20 @[el2_lsu_addrcheck.scala 56:32]
node _T_21 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_21 @[el2_lsu_addrcheck.scala 57:32]
node _T_22 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 59:63]
node _T_23 = not(_T_22) @[el2_lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_23 @[el2_lsu_addrcheck.scala 59:30]
node _T_24 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_24, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_25 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 61:50]
node _T_26 = bits(_T_25, 0, 0) @[el2_lsu_addrcheck.scala 61:50]
node _T_27 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 61:92]
node _T_28 = or(_T_27, addr_in_iccm) @[el2_lsu_addrcheck.scala 61:121]
node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62]
node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60]
node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137]
node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180]
node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158]
node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69]
node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75]
node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51]
node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124]
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128]
node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106]
node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85]
node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138]
node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
node _T_43 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58]
node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:87]
node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 65:33]
node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:47]
node _T_50 = or(_T_49, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:54]
node _T_51 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:99]
node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:76]
node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:28]
node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:47]
node _T_55 = or(_T_54, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:54]
node _T_56 = or(UInt<32>("h00"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:99]
node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:76]
node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:28]
node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:121]
node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:47]
node _T_61 = or(_T_60, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:54]
node _T_62 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:99]
node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:76]
node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:28]
node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:121]
node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:47]
node _T_67 = or(_T_66, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:54]
node _T_68 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:99]
node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:76]
node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:28]
node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:121]
node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:47]
node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:54]
node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:99]
node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:76]
node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:28]
node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:121]
node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:47]
node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:54]
node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:99]
node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:76]
node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:28]
node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:121]
node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:47]
node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:54]
node _T_86 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:99]
node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:76]
node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:28]
node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:121]
node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:47]
node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:54]
node _T_92 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:99]
node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:76]
node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:28]
node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:121]
node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:46]
node _T_97 = or(_T_96, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:55]
node _T_98 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:100]
node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:77]
node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:29]
node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:47]
node _T_102 = or(_T_101, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:56]
node _T_103 = or(UInt<32>("h00"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:101]
node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:78]
node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:30]
node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:122]
node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:47]
node _T_108 = or(_T_107, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:56]
node _T_109 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:101]
node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:78]
node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:30]
node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:123]
node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:47]
node _T_114 = or(_T_113, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:56]
node _T_115 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:101]
node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:78]
node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:30]
node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:123]
node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:47]
node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:56]
node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:101]
node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:78]
node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:30]
node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:123]
node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:47]
node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:56]
node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:101]
node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:78]
node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:30]
node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:123]
node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:47]
node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:56]
node _T_133 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:101]
node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:78]
node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:30]
node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:123]
node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:47]
node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:56]
node _T_139 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:101]
node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:78]
node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:30]
node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:123]
node _T_143 = and(_T_95, _T_142) @[el2_lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:92]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57]
node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70]
node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76]
node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92]
node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_148 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[el2_lsu_addrcheck.scala 91:87]
node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 91:64]
node _T_150 = and(start_addr_in_dccm_region_d, _T_149) @[el2_lsu_addrcheck.scala 91:62]
node _T_151 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 93:57]
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:36]
node _T_153 = and(end_addr_in_dccm_region_d, _T_152) @[el2_lsu_addrcheck.scala 93:34]
node _T_154 = or(_T_150, _T_153) @[el2_lsu_addrcheck.scala 91:112]
node _T_155 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 95:29]
node _T_156 = or(_T_154, _T_155) @[el2_lsu_addrcheck.scala 93:85]
node _T_157 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 97:29]
node _T_158 = or(_T_156, _T_157) @[el2_lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_158 @[el2_lsu_addrcheck.scala 91:29]
node _T_159 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:33]
node _T_160 = eq(non_dccm_access_ok, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:64]
node _T_161 = and(_T_159, _T_160) @[el2_lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_161 @[el2_lsu_addrcheck.scala 99:29]
node _T_162 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 111:49]
node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70]
node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92]
node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118]
node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141]
node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21]
node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60]
node _T_169 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:100]
node _T_170 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:144]
node _T_171 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:185]
node _T_172 = mux(_T_171, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 112:164]
node _T_173 = mux(_T_170, UInt<4>("h05"), _T_172) @[el2_lsu_addrcheck.scala 112:120]
node _T_174 = mux(_T_169, UInt<4>("h03"), _T_173) @[el2_lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_168, UInt<4>("h02"), _T_174) @[el2_lsu_addrcheck.scala 112:35]
node _T_175 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:53]
node _T_176 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_175, _T_176) @[el2_lsu_addrcheck.scala 113:61]
node _T_177 = eq(is_aligned_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_177) @[el2_lsu_addrcheck.scala 114:57]
node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90]
node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57]
node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113]
node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136]
node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25]
node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111]
node _T_184 = mux(_T_183, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_184) @[el2_lsu_addrcheck.scala 116:39]
node _T_185 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 117:50]
node _T_186 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:84]
node _T_187 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:113]
node _T_188 = mux(_T_185, _T_186, _T_187) @[el2_lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_188 @[el2_lsu_addrcheck.scala 117:21]
node _T_189 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:66]
node _T_190 = and(start_addr_in_dccm_region_d, _T_189) @[el2_lsu_addrcheck.scala 118:64]
node _T_191 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:120]
node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118]
node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88]
node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142]
node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31]
node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66]
node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36]
node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95]
node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33]
reg _T_200 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
_T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_200 @[el2_lsu_addrcheck.scala 121:50]

193
el2_lsu_addrcheck.v
View File

@ -1,193 +0,0 @@
module el2_lsu_addrcheck(
input clock,
input reset,
input io_lsu_c2_m_clk,
input [31:0] io_start_addr_d,
input [31:0] io_end_addr_d,
input io_lsu_pkt_d_fast_int,
input io_lsu_pkt_d_by,
input io_lsu_pkt_d_half,
input io_lsu_pkt_d_word,
input io_lsu_pkt_d_dword,
input io_lsu_pkt_d_load,
input io_lsu_pkt_d_store,
input io_lsu_pkt_d_unsign,
input io_lsu_pkt_d_dma,
input io_lsu_pkt_d_store_data_bypass_d,
input io_lsu_pkt_d_load_ldst_bypass_d,
input io_lsu_pkt_d_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input [31:0] io_dec_tlu_mrac_ff,
input [3:0] io_rs1_region_d,
input [31:0] io_rs1_d,
output io_is_sideeffects_m,
output io_addr_in_dccm_d,
output io_addr_in_pic_d,
output io_addr_external_d,
output io_access_fault_d,
output io_misaligned_fault_d,
output [3:0] io_exc_mscause_d,
output io_fir_dccm_access_error_d,
output io_fir_nondccm_access_error_d,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 253:49]
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 258:39]
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 253:49]
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 258:39]
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 42:45]
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 258:39]
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 258:39]
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 54:60]
wire _T_17 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 55:54]
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[el2_lsu_addrcheck.scala 55:73]
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
wire [31:0] _T_25 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 61:50]
wire _T_28 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 61:121]
wire _T_29 = ~_T_28; // @[el2_lsu_addrcheck.scala 61:62]
wire _T_30 = _T_25[0] & _T_29; // @[el2_lsu_addrcheck.scala 61:60]
wire _T_31 = _T_30 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 61:137]
wire _T_32 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 61:180]
wire is_sideeffects_d = _T_31 & _T_32; // @[el2_lsu_addrcheck.scala 61:158]
wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 62:75]
wire _T_35 = io_lsu_pkt_d_word & _T_34; // @[el2_lsu_addrcheck.scala 62:51]
wire _T_37 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 62:128]
wire _T_38 = io_lsu_pkt_d_half & _T_37; // @[el2_lsu_addrcheck.scala 62:106]
wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:85]
wire is_aligned_d = _T_39 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 62:138]
wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:54]
wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:76]
wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:54]
wire _T_57 = _T_55 == 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:76]
wire _T_59 = _T_52 | _T_57; // @[el2_lsu_addrcheck.scala 67:121]
wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 69:54]
wire _T_63 = _T_61 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 69:76]
wire _T_65 = _T_59 | _T_63; // @[el2_lsu_addrcheck.scala 68:121]
wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 70:54]
wire _T_69 = _T_67 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 70:76]
wire _T_71 = _T_65 | _T_69; // @[el2_lsu_addrcheck.scala 69:121]
wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:55]
wire _T_99 = _T_97 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:77]
wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:56]
wire _T_104 = _T_102 == 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:78]
wire _T_106 = _T_99 | _T_104; // @[el2_lsu_addrcheck.scala 76:122]
wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 78:56]
wire _T_110 = _T_108 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 78:78]
wire _T_112 = _T_106 | _T_110; // @[el2_lsu_addrcheck.scala 77:123]
wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 79:56]
wire _T_116 = _T_114 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 79:78]
wire _T_118 = _T_112 | _T_116; // @[el2_lsu_addrcheck.scala 78:123]
wire non_dccm_access_ok = _T_71 & _T_118; // @[el2_lsu_addrcheck.scala 75:7]
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 85:57]
wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 86:76]
wire _T_146 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 86:92]
wire _T_147 = _T_145 | _T_146; // @[el2_lsu_addrcheck.scala 86:90]
wire picm_access_fault_d = io_addr_in_pic_d & _T_147; // @[el2_lsu_addrcheck.scala 86:51]
wire _T_148 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 91:87]
wire _T_149 = ~_T_148; // @[el2_lsu_addrcheck.scala 91:64]
wire _T_150 = start_addr_in_dccm_region_d & _T_149; // @[el2_lsu_addrcheck.scala 91:62]
wire _T_151 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 93:57]
wire _T_152 = ~_T_151; // @[el2_lsu_addrcheck.scala 93:36]
wire _T_153 = end_addr_in_dccm_region_d & _T_152; // @[el2_lsu_addrcheck.scala 93:34]
wire _T_154 = _T_150 | _T_153; // @[el2_lsu_addrcheck.scala 91:112]
wire _T_155 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 95:29]
wire _T_156 = _T_154 | _T_155; // @[el2_lsu_addrcheck.scala 93:85]
wire _T_157 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 97:29]
wire unmapped_access_fault_d = _T_156 | _T_157; // @[el2_lsu_addrcheck.scala 95:85]
wire _T_159 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 99:33]
wire _T_160 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 99:64]
wire mpu_access_fault_d = _T_159 & _T_160; // @[el2_lsu_addrcheck.scala 99:62]
wire _T_162 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 111:49]
wire _T_163 = _T_162 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 111:70]
wire _T_164 = _T_163 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 111:92]
wire _T_165 = _T_164 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 111:118]
wire _T_166 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 111:141]
wire [3:0] _T_172 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 112:164]
wire [3:0] _T_173 = regpred_access_fault_d ? 4'h5 : _T_172; // @[el2_lsu_addrcheck.scala 112:120]
wire [3:0] _T_174 = mpu_access_fault_d ? 4'h3 : _T_173; // @[el2_lsu_addrcheck.scala 112:80]
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_174; // @[el2_lsu_addrcheck.scala 112:35]
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 113:61]
wire _T_177 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 114:59]
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_177; // @[el2_lsu_addrcheck.scala 114:57]
wire _T_178 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 115:90]
wire _T_179 = regcross_misaligned_fault_d | _T_178; // @[el2_lsu_addrcheck.scala 115:57]
wire _T_180 = _T_179 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 115:113]
wire [3:0] _T_184 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 116:80]
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_184; // @[el2_lsu_addrcheck.scala 116:39]
wire _T_189 = ~start_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:66]
wire _T_190 = start_addr_in_dccm_region_d & _T_189; // @[el2_lsu_addrcheck.scala 118:64]
wire _T_191 = ~end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:120]
wire _T_192 = end_addr_in_dccm_region_d & _T_191; // @[el2_lsu_addrcheck.scala 118:118]
wire _T_193 = _T_190 | _T_192; // @[el2_lsu_addrcheck.scala 118:88]
wire _T_194 = _T_193 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 118:142]
wire _T_196 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 119:66]
wire _T_197 = ~_T_196; // @[el2_lsu_addrcheck.scala 119:36]
wire _T_198 = _T_197 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 119:95]
reg _T_200; // @[el2_lsu_addrcheck.scala 121:60]
assign io_is_sideeffects_m = _T_200; // @[el2_lsu_addrcheck.scala 121:50]
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 56:32]
assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 57:32]
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 59:30]
assign io_access_fault_d = _T_165 & _T_166; // @[el2_lsu_addrcheck.scala 111:21]
assign io_misaligned_fault_d = _T_180 & _T_166; // @[el2_lsu_addrcheck.scala 115:25]
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 117:21]
assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 118:31]
assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 119:33]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_200 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_200 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
if (reset) begin
_T_200 <= 1'h0;
end else begin
_T_200 <= _T_31 & _T_32;
end
end
endmodule

179
el2_lsu_bus_buffer.anno.json
View File

@ -1,179 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_full_hit_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_load",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_flush_m_up",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_valid",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_inv_r",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_misaligned",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_error",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data",
"sources":[
"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_bus_buffer.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_bus_buffer"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

6507
el2_lsu_bus_buffer.fir
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File diff suppressed because it is too large Load Diff

4578
el2_lsu_bus_buffer.v
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File diff suppressed because it is too large Load Diff

102
el2_lsu_bus_intf.anno.json
View File

@ -1,102 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_misaligned",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_load",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_bus_buffer_full_any",
"sources":[
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_dec_lsu_valid_raw_d",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_d",
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_bus_intf.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_bus_intf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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