lsc_ctl updated
This commit is contained in:
Laraib Khan
parent
26ff2b4009
commit
bfeaa72eda
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@ -24,6 +24,14 @@
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
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]
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]
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},
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
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"sources":[
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
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]
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
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@ -93,6 +101,14 @@
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
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]
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]
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},
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
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"sources":[
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
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]
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
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"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
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302
lsu_lsc_ctl.fir
302
lsu_lsc_ctl.fir
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@ -766,24 +766,24 @@ circuit lsu_lsc_ctl :
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_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
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_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
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io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 227:24]
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io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 227:24]
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node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
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node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
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node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
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node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 228:71]
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node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 229:27]
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node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 228:27]
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node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
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node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 228:128]
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reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
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reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:114]
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_T_158 <= _T_157 @[lsu_lsc_ctl.scala 229:114]
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_T_158 <= _T_157 @[lsu_lsc_ctl.scala 228:114]
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node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
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node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
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io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 229:17]
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io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 228:17]
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node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
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node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
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node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
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node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 229:71]
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node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27]
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node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 229:27]
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node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
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node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 229:128]
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reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
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reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
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_T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114]
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_T_164 <= _T_163 @[lsu_lsc_ctl.scala 229:114]
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node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
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node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
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io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17]
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io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 229:17]
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node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 232:41]
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node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 230:41]
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node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 232:69]
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node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 230:69]
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node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
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node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 230:87]
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node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
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node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
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node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23]
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inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23]
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@ -794,10 +794,10 @@ circuit lsu_lsc_ctl :
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rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
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rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
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reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
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reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
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_T_171 <= _T_166 @[lib.scala 383:16]
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_T_171 <= _T_166 @[lib.scala 383:16]
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end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 232:18]
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end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 230:18]
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node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 233:41]
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node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 231:41]
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node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 233:69]
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node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 231:69]
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node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 233:87]
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node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
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node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
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node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
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node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23]
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inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23]
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@ -808,146 +808,140 @@ circuit lsu_lsc_ctl :
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rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
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rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
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reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
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reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
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_T_177 <= _T_172 @[lib.scala 383:16]
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_T_177 <= _T_172 @[lib.scala 383:16]
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end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 233:18]
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end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 231:18]
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reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
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reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
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_T_178 <= io.end_addr_d @[lsu_lsc_ctl.scala 236:62]
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_T_178 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 232:62]
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io.end_addr_m <= _T_178 @[lsu_lsc_ctl.scala 236:24]
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io.addr_in_dccm_m <= _T_178 @[lsu_lsc_ctl.scala 232:24]
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reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
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reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
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_T_179 <= io.end_addr_m @[lsu_lsc_ctl.scala 237:62]
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_T_179 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 233:62]
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io.end_addr_r <= _T_179 @[lsu_lsc_ctl.scala 237:24]
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io.addr_in_dccm_r <= _T_179 @[lsu_lsc_ctl.scala 233:24]
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reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62]
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reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
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_T_180 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 238:62]
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_T_180 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 234:62]
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io.addr_in_dccm_m <= _T_180 @[lsu_lsc_ctl.scala 238:24]
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io.addr_in_pic_m <= _T_180 @[lsu_lsc_ctl.scala 234:24]
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reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62]
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reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
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_T_181 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 239:62]
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_T_181 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 235:62]
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io.addr_in_dccm_r <= _T_181 @[lsu_lsc_ctl.scala 239:24]
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io.addr_in_pic_r <= _T_181 @[lsu_lsc_ctl.scala 235:24]
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reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62]
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reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
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_T_182 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 240:62]
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_T_182 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 236:62]
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io.addr_in_pic_m <= _T_182 @[lsu_lsc_ctl.scala 240:24]
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io.addr_external_m <= _T_182 @[lsu_lsc_ctl.scala 236:24]
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reg _T_183 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:62]
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reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:66]
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_T_183 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 241:62]
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addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66]
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io.addr_in_pic_r <= _T_183 @[lsu_lsc_ctl.scala 241:24]
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node _T_183 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77]
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reg _T_184 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 242:62]
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node _T_184 = bits(_T_183, 0, 0) @[lib.scala 8:44]
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_T_184 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 242:62]
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node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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io.addr_external_m <= _T_184 @[lsu_lsc_ctl.scala 242:24]
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reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 243:66]
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addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 243:66]
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node _T_185 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 244:77]
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node _T_186 = bits(_T_185, 0, 0) @[lib.scala 8:44]
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node _T_187 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
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inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23]
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inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23]
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rvclkhdr_3.clock <= clock
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rvclkhdr_3.clock <= clock
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rvclkhdr_3.reset <= reset
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rvclkhdr_3.reset <= reset
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rvclkhdr_3.io.clk <= clock @[lib.scala 379:18]
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rvclkhdr_3.io.clk <= clock @[lib.scala 379:18]
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rvclkhdr_3.io.en <= _T_186 @[lib.scala 380:17]
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rvclkhdr_3.io.en <= _T_184 @[lib.scala 380:17]
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rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
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rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
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reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
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reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
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bus_read_data_r <= io.bus_read_data_m @[lib.scala 383:16]
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bus_read_data_r <= io.bus_read_data_m @[lib.scala 383:16]
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node _T_188 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 247:52]
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node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 241:52]
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io.lsu_fir_addr <= _T_188 @[lsu_lsc_ctl.scala 247:28]
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io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 241:28]
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io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 249:28]
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io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 243:28]
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node _T_189 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 251:68]
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node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 245:68]
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node _T_190 = and(io.lsu_pkt_r.valid, _T_189) @[lsu_lsc_ctl.scala 251:41]
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node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 245:41]
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node _T_191 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 251:96]
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node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:96]
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node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 251:94]
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node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 245:94]
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node _T_193 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 251:110]
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node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:110]
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node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 251:108]
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node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 245:108]
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io.lsu_commit_r <= _T_194 @[lsu_lsc_ctl.scala 251:19]
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io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 245:19]
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node _T_195 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 252:52]
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node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 246:52]
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node _T_196 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 252:69]
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node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:69]
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node _T_197 = bits(_T_196, 0, 0) @[Bitwise.scala 72:15]
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node _T_195 = bits(_T_194, 0, 0) @[Bitwise.scala 72:15]
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node _T_198 = mux(_T_197, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_196 = mux(_T_195, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
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node _T_199 = or(_T_195, _T_198) @[lsu_lsc_ctl.scala 252:59]
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node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 246:59]
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node _T_200 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 252:133]
|
node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 246:133]
|
||||||
node _T_201 = mux(_T_200, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 252:94]
|
node _T_199 = mux(_T_198, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 246:94]
|
||||||
node _T_202 = and(_T_199, _T_201) @[lsu_lsc_ctl.scala 252:89]
|
node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 246:89]
|
||||||
io.store_data_m <= _T_202 @[lsu_lsc_ctl.scala 252:29]
|
io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 246:29]
|
||||||
node _T_203 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 273:53]
|
node _T_201 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 267:53]
|
||||||
node _T_204 = mux(_T_203, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 273:33]
|
node _T_202 = mux(_T_201, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 267:33]
|
||||||
lsu_ld_datafn_m <= _T_204 @[lsu_lsc_ctl.scala 273:27]
|
lsu_ld_datafn_m <= _T_202 @[lsu_lsc_ctl.scala 267:27]
|
||||||
node _T_205 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 274:49]
|
node _T_203 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 268:49]
|
||||||
node _T_206 = mux(_T_205, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 274:33]
|
node _T_204 = mux(_T_203, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 268:33]
|
||||||
lsu_ld_datafn_corr_r <= _T_206 @[lsu_lsc_ctl.scala 274:27]
|
lsu_ld_datafn_corr_r <= _T_204 @[lsu_lsc_ctl.scala 268:27]
|
||||||
node _T_207 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:66]
|
node _T_205 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 269:66]
|
||||||
node _T_208 = bits(_T_207, 0, 0) @[Bitwise.scala 72:15]
|
node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_209 = mux(_T_208, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_210 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125]
|
node _T_208 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 269:125]
|
||||||
node _T_211 = cat(UInt<24>("h00"), _T_210) @[Cat.scala 29:58]
|
node _T_209 = cat(UInt<24>("h00"), _T_208) @[Cat.scala 29:58]
|
||||||
node _T_212 = and(_T_209, _T_211) @[lsu_lsc_ctl.scala 275:94]
|
node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 269:94]
|
||||||
node _T_213 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43]
|
node _T_211 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 270:43]
|
||||||
node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
|
node _T_212 = bits(_T_211, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_213 = mux(_T_212, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_216 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:102]
|
node _T_214 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 270:102]
|
||||||
node _T_217 = cat(UInt<16>("h00"), _T_216) @[Cat.scala 29:58]
|
node _T_215 = cat(UInt<16>("h00"), _T_214) @[Cat.scala 29:58]
|
||||||
node _T_218 = and(_T_215, _T_217) @[lsu_lsc_ctl.scala 276:71]
|
node _T_216 = and(_T_213, _T_215) @[lsu_lsc_ctl.scala 270:71]
|
||||||
node _T_219 = or(_T_212, _T_218) @[lsu_lsc_ctl.scala 275:133]
|
node _T_217 = or(_T_210, _T_216) @[lsu_lsc_ctl.scala 269:133]
|
||||||
node _T_220 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
node _T_218 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 271:17]
|
||||||
node _T_221 = and(_T_220, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 277:43]
|
node _T_219 = and(_T_218, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 271:43]
|
||||||
node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15]
|
node _T_220 = bits(_T_219, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_223 = mux(_T_222, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_224 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 277:102]
|
node _T_222 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 271:102]
|
||||||
node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
|
node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_226 = mux(_T_225, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
node _T_224 = mux(_T_223, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_227 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 277:125]
|
node _T_225 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 271:125]
|
||||||
node _T_228 = cat(_T_226, _T_227) @[Cat.scala 29:58]
|
node _T_226 = cat(_T_224, _T_225) @[Cat.scala 29:58]
|
||||||
node _T_229 = and(_T_223, _T_228) @[lsu_lsc_ctl.scala 277:71]
|
node _T_227 = and(_T_221, _T_226) @[lsu_lsc_ctl.scala 271:71]
|
||||||
node _T_230 = or(_T_219, _T_229) @[lsu_lsc_ctl.scala 276:114]
|
node _T_228 = or(_T_217, _T_227) @[lsu_lsc_ctl.scala 270:114]
|
||||||
node _T_231 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17]
|
node _T_229 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||||
node _T_232 = and(_T_231, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 278:43]
|
node _T_230 = and(_T_229, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 272:43]
|
||||||
node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15]
|
node _T_231 = bits(_T_230, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_234 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_232 = mux(_T_231, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_235 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 278:101]
|
node _T_233 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 272:101]
|
||||||
node _T_236 = bits(_T_235, 0, 0) @[Bitwise.scala 72:15]
|
node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_237 = mux(_T_236, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
node _T_235 = mux(_T_234, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_238 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 278:125]
|
node _T_236 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||||
node _T_239 = cat(_T_237, _T_238) @[Cat.scala 29:58]
|
node _T_237 = cat(_T_235, _T_236) @[Cat.scala 29:58]
|
||||||
node _T_240 = and(_T_234, _T_239) @[lsu_lsc_ctl.scala 278:71]
|
node _T_238 = and(_T_232, _T_237) @[lsu_lsc_ctl.scala 272:71]
|
||||||
node _T_241 = or(_T_230, _T_240) @[lsu_lsc_ctl.scala 277:134]
|
node _T_239 = or(_T_228, _T_238) @[lsu_lsc_ctl.scala 271:134]
|
||||||
node _T_242 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
node _T_240 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_243 = mux(_T_242, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_244 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 279:60]
|
node _T_242 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 273:60]
|
||||||
node _T_245 = and(_T_243, _T_244) @[lsu_lsc_ctl.scala 279:43]
|
node _T_243 = and(_T_241, _T_242) @[lsu_lsc_ctl.scala 273:43]
|
||||||
node _T_246 = or(_T_241, _T_245) @[lsu_lsc_ctl.scala 278:134]
|
node _T_244 = or(_T_239, _T_243) @[lsu_lsc_ctl.scala 272:134]
|
||||||
io.lsu_result_m <= _T_246 @[lsu_lsc_ctl.scala 275:27]
|
io.lsu_result_m <= _T_244 @[lsu_lsc_ctl.scala 269:27]
|
||||||
node _T_247 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:66]
|
node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 274:66]
|
||||||
node _T_248 = bits(_T_247, 0, 0) @[Bitwise.scala 72:15]
|
node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_249 = mux(_T_248, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_250 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:130]
|
node _T_248 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 274:130]
|
||||||
node _T_251 = cat(UInt<24>("h00"), _T_250) @[Cat.scala 29:58]
|
node _T_249 = cat(UInt<24>("h00"), _T_248) @[Cat.scala 29:58]
|
||||||
node _T_252 = and(_T_249, _T_251) @[lsu_lsc_ctl.scala 280:94]
|
node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 274:94]
|
||||||
node _T_253 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43]
|
node _T_251 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 275:43]
|
||||||
node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
|
node _T_252 = bits(_T_251, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_253 = mux(_T_252, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_256 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:107]
|
node _T_254 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 275:107]
|
||||||
node _T_257 = cat(UInt<16>("h00"), _T_256) @[Cat.scala 29:58]
|
node _T_255 = cat(UInt<16>("h00"), _T_254) @[Cat.scala 29:58]
|
||||||
node _T_258 = and(_T_255, _T_257) @[lsu_lsc_ctl.scala 281:71]
|
node _T_256 = and(_T_253, _T_255) @[lsu_lsc_ctl.scala 275:71]
|
||||||
node _T_259 = or(_T_252, _T_258) @[lsu_lsc_ctl.scala 280:138]
|
node _T_257 = or(_T_250, _T_256) @[lsu_lsc_ctl.scala 274:138]
|
||||||
node _T_260 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 282:17]
|
node _T_258 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17]
|
||||||
node _T_261 = and(_T_260, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 282:43]
|
node _T_259 = and(_T_258, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 276:43]
|
||||||
node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15]
|
node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_263 = mux(_T_262, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_261 = mux(_T_260, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 282:107]
|
node _T_262 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 276:107]
|
||||||
node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
|
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_266 = mux(_T_265, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
node _T_264 = mux(_T_263, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_267 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 282:135]
|
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 276:135]
|
||||||
node _T_268 = cat(_T_266, _T_267) @[Cat.scala 29:58]
|
node _T_266 = cat(_T_264, _T_265) @[Cat.scala 29:58]
|
||||||
node _T_269 = and(_T_263, _T_268) @[lsu_lsc_ctl.scala 282:71]
|
node _T_267 = and(_T_261, _T_266) @[lsu_lsc_ctl.scala 276:71]
|
||||||
node _T_270 = or(_T_259, _T_269) @[lsu_lsc_ctl.scala 281:119]
|
node _T_268 = or(_T_257, _T_267) @[lsu_lsc_ctl.scala 275:119]
|
||||||
node _T_271 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 283:17]
|
node _T_269 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||||
node _T_272 = and(_T_271, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 283:43]
|
node _T_270 = and(_T_269, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 277:43]
|
||||||
node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15]
|
node _T_271 = bits(_T_270, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_274 = mux(_T_273, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 283:106]
|
node _T_273 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 277:106]
|
||||||
node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15]
|
node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_277 = mux(_T_276, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
node _T_275 = mux(_T_274, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_278 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 283:135]
|
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||||
node _T_279 = cat(_T_277, _T_278) @[Cat.scala 29:58]
|
node _T_277 = cat(_T_275, _T_276) @[Cat.scala 29:58]
|
||||||
node _T_280 = and(_T_274, _T_279) @[lsu_lsc_ctl.scala 283:71]
|
node _T_278 = and(_T_272, _T_277) @[lsu_lsc_ctl.scala 277:71]
|
||||||
node _T_281 = or(_T_270, _T_280) @[lsu_lsc_ctl.scala 282:144]
|
node _T_279 = or(_T_268, _T_278) @[lsu_lsc_ctl.scala 276:144]
|
||||||
node _T_282 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
node _T_280 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_283 = mux(_T_282, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
node _T_281 = mux(_T_280, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_284 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 284:65]
|
node _T_282 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 278:65]
|
||||||
node _T_285 = and(_T_283, _T_284) @[lsu_lsc_ctl.scala 284:43]
|
node _T_283 = and(_T_281, _T_282) @[lsu_lsc_ctl.scala 278:43]
|
||||||
node _T_286 = or(_T_281, _T_285) @[lsu_lsc_ctl.scala 283:144]
|
node _T_284 = or(_T_279, _T_283) @[lsu_lsc_ctl.scala 277:144]
|
||||||
io.lsu_result_corr_r <= _T_286 @[lsu_lsc_ctl.scala 280:27]
|
io.lsu_result_corr_r <= _T_284 @[lsu_lsc_ctl.scala 274:27]
|
||||||
|
|
||||||
|
|
|
||||||
270
lsu_lsc_ctl.v
270
lsu_lsc_ctl.v
|
|
@ -369,6 +369,8 @@ module lsu_lsc_ctl(
|
||||||
reg [31:0] _RAND_47;
|
reg [31:0] _RAND_47;
|
||||||
reg [31:0] _RAND_48;
|
reg [31:0] _RAND_48;
|
||||||
reg [31:0] _RAND_49;
|
reg [31:0] _RAND_49;
|
||||||
|
reg [31:0] _RAND_50;
|
||||||
|
reg [31:0] _RAND_51;
|
||||||
`endif // RANDOMIZE_REG_INIT
|
`endif // RANDOMIZE_REG_INIT
|
||||||
wire addrcheck_reset; // @[lsu_lsc_ctl.scala 118:25]
|
wire addrcheck_reset; // @[lsu_lsc_ctl.scala 118:25]
|
||||||
wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 118:25]
|
wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 118:25]
|
||||||
|
|
@ -520,76 +522,80 @@ module lsu_lsc_ctl(
|
||||||
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72]
|
reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72]
|
||||||
reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 226:62]
|
reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 226:62]
|
||||||
reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 227:62]
|
reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 227:62]
|
||||||
wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 232:69]
|
reg [28:0] end_addr_pre_m; // @[lib.scala 383:16]
|
||||||
wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 233:69]
|
wire [28:0] _T_156 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 228:27]
|
||||||
reg [31:0] _T_178; // @[lsu_lsc_ctl.scala 236:62]
|
reg [2:0] _T_158; // @[lsu_lsc_ctl.scala 228:114]
|
||||||
reg [31:0] _T_179; // @[lsu_lsc_ctl.scala 237:62]
|
reg [28:0] end_addr_pre_r; // @[lib.scala 383:16]
|
||||||
reg _T_180; // @[lsu_lsc_ctl.scala 238:62]
|
wire [28:0] _T_162 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 229:27]
|
||||||
reg _T_181; // @[lsu_lsc_ctl.scala 239:62]
|
reg [2:0] _T_164; // @[lsu_lsc_ctl.scala 229:114]
|
||||||
reg _T_182; // @[lsu_lsc_ctl.scala 240:62]
|
wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 230:69]
|
||||||
reg _T_183; // @[lsu_lsc_ctl.scala 241:62]
|
wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 231:69]
|
||||||
reg _T_184; // @[lsu_lsc_ctl.scala 242:62]
|
reg _T_178; // @[lsu_lsc_ctl.scala 232:62]
|
||||||
reg addr_external_r; // @[lsu_lsc_ctl.scala 243:66]
|
reg _T_179; // @[lsu_lsc_ctl.scala 233:62]
|
||||||
|
reg _T_180; // @[lsu_lsc_ctl.scala 234:62]
|
||||||
|
reg _T_181; // @[lsu_lsc_ctl.scala 235:62]
|
||||||
|
reg _T_182; // @[lsu_lsc_ctl.scala 236:62]
|
||||||
|
reg addr_external_r; // @[lsu_lsc_ctl.scala 237:66]
|
||||||
reg [31:0] bus_read_data_r; // @[lib.scala 383:16]
|
reg [31:0] bus_read_data_r; // @[lib.scala 383:16]
|
||||||
wire _T_189 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 251:68]
|
wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 245:68]
|
||||||
wire _T_190 = io_lsu_pkt_r_valid & _T_189; // @[lsu_lsc_ctl.scala 251:41]
|
wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 245:41]
|
||||||
wire _T_191 = ~io_flush_r; // @[lsu_lsc_ctl.scala 251:96]
|
wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 245:96]
|
||||||
wire _T_192 = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 251:94]
|
wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 245:94]
|
||||||
wire _T_193 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 251:110]
|
wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 245:110]
|
||||||
wire _T_196 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 252:69]
|
wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 246:69]
|
||||||
wire [31:0] _T_198 = _T_196 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_196 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_199 = io_picm_mask_data_m | _T_198; // @[lsu_lsc_ctl.scala 252:59]
|
wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 246:59]
|
||||||
wire [31:0] _T_201 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 252:94]
|
wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 246:94]
|
||||||
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 273:33]
|
wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 267:33]
|
||||||
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 274:33]
|
wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 268:33]
|
||||||
wire _T_207 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 275:66]
|
wire _T_205 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 269:66]
|
||||||
wire [31:0] _T_209 = _T_207 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_207 = _T_205 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_211 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_209 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_212 = _T_209 & _T_211; // @[lsu_lsc_ctl.scala 275:94]
|
wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 269:94]
|
||||||
wire _T_213 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 276:43]
|
wire _T_211 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 270:43]
|
||||||
wire [31:0] _T_215 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_213 = _T_211 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_217 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_215 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_218 = _T_215 & _T_217; // @[lsu_lsc_ctl.scala 276:71]
|
wire [31:0] _T_216 = _T_213 & _T_215; // @[lsu_lsc_ctl.scala 270:71]
|
||||||
wire [31:0] _T_219 = _T_212 | _T_218; // @[lsu_lsc_ctl.scala 275:133]
|
wire [31:0] _T_217 = _T_210 | _T_216; // @[lsu_lsc_ctl.scala 269:133]
|
||||||
wire _T_220 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 277:17]
|
wire _T_218 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 271:17]
|
||||||
wire _T_221 = _T_220 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 277:43]
|
wire _T_219 = _T_218 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 271:43]
|
||||||
wire [31:0] _T_223 = _T_221 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_221 = _T_219 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [23:0] _T_226 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
wire [23:0] _T_224 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_228 = {_T_226,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_226 = {_T_224,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_229 = _T_223 & _T_228; // @[lsu_lsc_ctl.scala 277:71]
|
wire [31:0] _T_227 = _T_221 & _T_226; // @[lsu_lsc_ctl.scala 271:71]
|
||||||
wire [31:0] _T_230 = _T_219 | _T_229; // @[lsu_lsc_ctl.scala 276:114]
|
wire [31:0] _T_228 = _T_217 | _T_227; // @[lsu_lsc_ctl.scala 270:114]
|
||||||
wire _T_232 = _T_220 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 278:43]
|
wire _T_230 = _T_218 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 272:43]
|
||||||
wire [31:0] _T_234 = _T_232 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_232 = _T_230 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [15:0] _T_237 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
wire [15:0] _T_235 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_239 = {_T_237,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_237 = {_T_235,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_240 = _T_234 & _T_239; // @[lsu_lsc_ctl.scala 278:71]
|
wire [31:0] _T_238 = _T_232 & _T_237; // @[lsu_lsc_ctl.scala 272:71]
|
||||||
wire [31:0] _T_241 = _T_230 | _T_240; // @[lsu_lsc_ctl.scala 277:134]
|
wire [31:0] _T_239 = _T_228 | _T_238; // @[lsu_lsc_ctl.scala 271:134]
|
||||||
wire [31:0] _T_243 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_241 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_245 = _T_243 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 279:43]
|
wire [31:0] _T_243 = _T_241 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 273:43]
|
||||||
wire _T_247 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 280:66]
|
wire _T_245 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 274:66]
|
||||||
wire [31:0] _T_249 = _T_247 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_247 = _T_245 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_251 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_249 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_252 = _T_249 & _T_251; // @[lsu_lsc_ctl.scala 280:94]
|
wire [31:0] _T_250 = _T_247 & _T_249; // @[lsu_lsc_ctl.scala 274:94]
|
||||||
wire _T_253 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 281:43]
|
wire _T_251 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 275:43]
|
||||||
wire [31:0] _T_255 = _T_253 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_253 = _T_251 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_257 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_255 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_258 = _T_255 & _T_257; // @[lsu_lsc_ctl.scala 281:71]
|
wire [31:0] _T_256 = _T_253 & _T_255; // @[lsu_lsc_ctl.scala 275:71]
|
||||||
wire [31:0] _T_259 = _T_252 | _T_258; // @[lsu_lsc_ctl.scala 280:138]
|
wire [31:0] _T_257 = _T_250 | _T_256; // @[lsu_lsc_ctl.scala 274:138]
|
||||||
wire _T_260 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 282:17]
|
wire _T_258 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 276:17]
|
||||||
wire _T_261 = _T_260 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 282:43]
|
wire _T_259 = _T_258 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 276:43]
|
||||||
wire [31:0] _T_263 = _T_261 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_261 = _T_259 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [23:0] _T_266 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
wire [23:0] _T_264 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_268 = {_T_266,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_266 = {_T_264,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_269 = _T_263 & _T_268; // @[lsu_lsc_ctl.scala 282:71]
|
wire [31:0] _T_267 = _T_261 & _T_266; // @[lsu_lsc_ctl.scala 276:71]
|
||||||
wire [31:0] _T_270 = _T_259 | _T_269; // @[lsu_lsc_ctl.scala 281:119]
|
wire [31:0] _T_268 = _T_257 | _T_267; // @[lsu_lsc_ctl.scala 275:119]
|
||||||
wire _T_272 = _T_260 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 283:43]
|
wire _T_270 = _T_258 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 277:43]
|
||||||
wire [31:0] _T_274 = _T_272 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_272 = _T_270 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [15:0] _T_277 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
wire [15:0] _T_275 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_279 = {_T_277,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
wire [31:0] _T_277 = {_T_275,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_280 = _T_274 & _T_279; // @[lsu_lsc_ctl.scala 283:71]
|
wire [31:0] _T_278 = _T_272 & _T_277; // @[lsu_lsc_ctl.scala 277:71]
|
||||||
wire [31:0] _T_281 = _T_270 | _T_280; // @[lsu_lsc_ctl.scala 282:144]
|
wire [31:0] _T_279 = _T_268 | _T_278; // @[lsu_lsc_ctl.scala 276:144]
|
||||||
wire [31:0] _T_283 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_281 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [31:0] _T_285 = _T_283 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 284:43]
|
wire [31:0] _T_283 = _T_281 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 278:43]
|
||||||
lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25]
|
lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25]
|
||||||
.reset(addrcheck_reset),
|
.reset(addrcheck_reset),
|
||||||
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
.io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
|
||||||
|
|
@ -635,18 +641,18 @@ module lsu_lsc_ctl(
|
||||||
.io_clk(rvclkhdr_3_io_clk),
|
.io_clk(rvclkhdr_3_io_clk),
|
||||||
.io_en(rvclkhdr_3_io_en)
|
.io_en(rvclkhdr_3_io_en)
|
||||||
);
|
);
|
||||||
assign io_lsu_result_m = _T_241 | _T_245; // @[lsu_lsc_ctl.scala 275:27]
|
assign io_lsu_result_m = _T_239 | _T_243; // @[lsu_lsc_ctl.scala 269:27]
|
||||||
assign io_lsu_result_corr_r = _T_281 | _T_285; // @[lsu_lsc_ctl.scala 280:27]
|
assign io_lsu_result_corr_r = _T_279 | _T_283; // @[lsu_lsc_ctl.scala 274:27]
|
||||||
assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 249:28]
|
assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 243:28]
|
||||||
assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 226:24]
|
assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 226:24]
|
||||||
assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 227:24]
|
assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 227:24]
|
||||||
assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 115:24]
|
assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 115:24]
|
||||||
assign io_end_addr_m = _T_178; // @[lsu_lsc_ctl.scala 229:17 lsu_lsc_ctl.scala 236:24]
|
assign io_end_addr_m = {_T_156,_T_158}; // @[lsu_lsc_ctl.scala 228:17]
|
||||||
assign io_end_addr_r = _T_179; // @[lsu_lsc_ctl.scala 230:17 lsu_lsc_ctl.scala 237:24]
|
assign io_end_addr_r = {_T_162,_T_164}; // @[lsu_lsc_ctl.scala 229:17]
|
||||||
assign io_store_data_m = _T_199 & _T_201; // @[lsu_lsc_ctl.scala 252:29]
|
assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 246:29]
|
||||||
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16]
|
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16]
|
||||||
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42]
|
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42]
|
||||||
assign io_lsu_commit_r = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 251:19]
|
assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 245:19]
|
||||||
assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32]
|
assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32]
|
||||||
assign io_lsu_error_pkt_r_valid = _T_111; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 187:30]
|
assign io_lsu_error_pkt_r_valid = _T_111; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 187:30]
|
||||||
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_110; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 186:46]
|
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_110; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 186:46]
|
||||||
|
|
@ -654,15 +660,15 @@ module lsu_lsc_ctl(
|
||||||
assign io_lsu_error_pkt_r_bits_exc_type = _T_109_bits_exc_type; // @[lsu_lsc_ctl.scala 185:24]
|
assign io_lsu_error_pkt_r_bits_exc_type = _T_109_bits_exc_type; // @[lsu_lsc_ctl.scala 185:24]
|
||||||
assign io_lsu_error_pkt_r_bits_mscause = _T_109_bits_mscause; // @[lsu_lsc_ctl.scala 185:24]
|
assign io_lsu_error_pkt_r_bits_mscause = _T_109_bits_mscause; // @[lsu_lsc_ctl.scala 185:24]
|
||||||
assign io_lsu_error_pkt_r_bits_addr = _T_109_bits_addr; // @[lsu_lsc_ctl.scala 185:24]
|
assign io_lsu_error_pkt_r_bits_addr = _T_109_bits_addr; // @[lsu_lsc_ctl.scala 185:24]
|
||||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 247:28]
|
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 241:28]
|
||||||
assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 188:38]
|
assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 188:38]
|
||||||
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42]
|
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42]
|
||||||
assign io_addr_in_dccm_m = _T_180; // @[lsu_lsc_ctl.scala 238:24]
|
assign io_addr_in_dccm_m = _T_178; // @[lsu_lsc_ctl.scala 232:24]
|
||||||
assign io_addr_in_dccm_r = _T_181; // @[lsu_lsc_ctl.scala 239:24]
|
assign io_addr_in_dccm_r = _T_179; // @[lsu_lsc_ctl.scala 233:24]
|
||||||
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42]
|
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42]
|
||||||
assign io_addr_in_pic_m = _T_182; // @[lsu_lsc_ctl.scala 240:24]
|
assign io_addr_in_pic_m = _T_180; // @[lsu_lsc_ctl.scala 234:24]
|
||||||
assign io_addr_in_pic_r = _T_183; // @[lsu_lsc_ctl.scala 241:24]
|
assign io_addr_in_pic_r = _T_181; // @[lsu_lsc_ctl.scala 235:24]
|
||||||
assign io_addr_external_m = _T_184; // @[lsu_lsc_ctl.scala 242:24]
|
assign io_addr_external_m = _T_182; // @[lsu_lsc_ctl.scala 236:24]
|
||||||
assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
|
assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
|
||||||
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
|
assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
|
||||||
assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20]
|
assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20]
|
||||||
|
|
@ -842,23 +848,27 @@ initial begin
|
||||||
_RAND_40 = {1{`RANDOM}};
|
_RAND_40 = {1{`RANDOM}};
|
||||||
_T_153 = _RAND_40[31:0];
|
_T_153 = _RAND_40[31:0];
|
||||||
_RAND_41 = {1{`RANDOM}};
|
_RAND_41 = {1{`RANDOM}};
|
||||||
_T_178 = _RAND_41[31:0];
|
end_addr_pre_m = _RAND_41[28:0];
|
||||||
_RAND_42 = {1{`RANDOM}};
|
_RAND_42 = {1{`RANDOM}};
|
||||||
_T_179 = _RAND_42[31:0];
|
_T_158 = _RAND_42[2:0];
|
||||||
_RAND_43 = {1{`RANDOM}};
|
_RAND_43 = {1{`RANDOM}};
|
||||||
_T_180 = _RAND_43[0:0];
|
end_addr_pre_r = _RAND_43[28:0];
|
||||||
_RAND_44 = {1{`RANDOM}};
|
_RAND_44 = {1{`RANDOM}};
|
||||||
_T_181 = _RAND_44[0:0];
|
_T_164 = _RAND_44[2:0];
|
||||||
_RAND_45 = {1{`RANDOM}};
|
_RAND_45 = {1{`RANDOM}};
|
||||||
_T_182 = _RAND_45[0:0];
|
_T_178 = _RAND_45[0:0];
|
||||||
_RAND_46 = {1{`RANDOM}};
|
_RAND_46 = {1{`RANDOM}};
|
||||||
_T_183 = _RAND_46[0:0];
|
_T_179 = _RAND_46[0:0];
|
||||||
_RAND_47 = {1{`RANDOM}};
|
_RAND_47 = {1{`RANDOM}};
|
||||||
_T_184 = _RAND_47[0:0];
|
_T_180 = _RAND_47[0:0];
|
||||||
_RAND_48 = {1{`RANDOM}};
|
_RAND_48 = {1{`RANDOM}};
|
||||||
addr_external_r = _RAND_48[0:0];
|
_T_181 = _RAND_48[0:0];
|
||||||
_RAND_49 = {1{`RANDOM}};
|
_RAND_49 = {1{`RANDOM}};
|
||||||
bus_read_data_r = _RAND_49[31:0];
|
_T_182 = _RAND_49[0:0];
|
||||||
|
_RAND_50 = {1{`RANDOM}};
|
||||||
|
addr_external_r = _RAND_50[0:0];
|
||||||
|
_RAND_51 = {1{`RANDOM}};
|
||||||
|
bus_read_data_r = _RAND_51[31:0];
|
||||||
`endif // RANDOMIZE_REG_INIT
|
`endif // RANDOMIZE_REG_INIT
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
access_fault_m = 1'h0;
|
access_fault_m = 1'h0;
|
||||||
|
|
@ -984,10 +994,22 @@ initial begin
|
||||||
_T_153 = 32'h0;
|
_T_153 = 32'h0;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_178 = 32'h0;
|
end_addr_pre_m = 29'h0;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_179 = 32'h0;
|
_T_158 = 3'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
end_addr_pre_r = 29'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
_T_164 = 3'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
_T_178 = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
_T_179 = 1'h0;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_180 = 1'h0;
|
_T_180 = 1'h0;
|
||||||
|
|
@ -998,12 +1020,6 @@ initial begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_182 = 1'h0;
|
_T_182 = 1'h0;
|
||||||
end
|
end
|
||||||
if (reset) begin
|
|
||||||
_T_183 = 1'h0;
|
|
||||||
end
|
|
||||||
if (reset) begin
|
|
||||||
_T_184 = 1'h0;
|
|
||||||
end
|
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
addr_external_r = 1'h0;
|
addr_external_r = 1'h0;
|
||||||
end
|
end
|
||||||
|
|
@ -1315,53 +1331,67 @@ end // initial
|
||||||
_T_153 <= io_lsu_addr_m;
|
_T_153 <= io_lsu_addr_m;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
end_addr_pre_m <= 29'h0;
|
||||||
|
end else begin
|
||||||
|
end_addr_pre_m <= io_end_addr_d[31:3];
|
||||||
|
end
|
||||||
|
end
|
||||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_178 <= 32'h0;
|
_T_158 <= 3'h0;
|
||||||
end else begin
|
end else begin
|
||||||
_T_178 <= io_end_addr_d;
|
_T_158 <= io_end_addr_d[2:0];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
end_addr_pre_r <= 29'h0;
|
||||||
|
end else begin
|
||||||
|
end_addr_pre_r <= io_end_addr_m[31:3];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
_T_164 <= 3'h0;
|
||||||
|
end else begin
|
||||||
|
_T_164 <= io_end_addr_m[2:0];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
_T_178 <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
_T_178 <= io_addr_in_dccm_d;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_179 <= 32'h0;
|
_T_179 <= 1'h0;
|
||||||
end else begin
|
end else begin
|
||||||
_T_179 <= io_end_addr_m;
|
_T_179 <= io_addr_in_dccm_m;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_180 <= 1'h0;
|
_T_180 <= 1'h0;
|
||||||
end else begin
|
end else begin
|
||||||
_T_180 <= io_addr_in_dccm_d;
|
_T_180 <= io_addr_in_pic_d;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_181 <= 1'h0;
|
_T_181 <= 1'h0;
|
||||||
end else begin
|
end else begin
|
||||||
_T_181 <= io_addr_in_dccm_m;
|
_T_181 <= io_addr_in_pic_m;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
_T_182 <= 1'h0;
|
_T_182 <= 1'h0;
|
||||||
end else begin
|
end else begin
|
||||||
_T_182 <= io_addr_in_pic_d;
|
_T_182 <= addrcheck_io_addr_external_d;
|
||||||
end
|
|
||||||
end
|
|
||||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
|
||||||
if (reset) begin
|
|
||||||
_T_183 <= 1'h0;
|
|
||||||
end else begin
|
|
||||||
_T_183 <= io_addr_in_pic_m;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
always @(posedge io_lsu_c1_m_clk or posedge reset) begin
|
|
||||||
if (reset) begin
|
|
||||||
_T_184 <= 1'h0;
|
|
||||||
end else begin
|
|
||||||
_T_184 <= addrcheck_io_addr_external_d;
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
always @(posedge io_lsu_c1_r_clk or posedge reset) begin
|
||||||
|
|
|
||||||
|
|
@ -225,16 +225,10 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
|
||||||
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
|
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
|
||||||
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
|
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
|
||||||
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
|
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
|
||||||
|
|
||||||
io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)})
|
io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)})
|
||||||
io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_m(2,0),0.U)})
|
io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_m(2,0),0.U)})
|
||||||
|
|
||||||
end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode)
|
end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode)
|
||||||
end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode)
|
end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode)
|
||||||
|
|
||||||
|
|
||||||
io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)}
|
|
||||||
io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)}
|
|
||||||
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
|
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
|
||||||
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
|
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
|
||||||
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
|
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
|
||||||
|
|
|
||||||
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Reference in New Issue