bus buffer added

lsu_bus_buffer.fir

@@ -2540,34 +2540,34 @@ circuit lsu_bus_buffer :
     reg _T_1779 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33]
     _T_1779 <= obuf_rdrsp_tag_in @[lib.scala 377:33]
     obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 353:18]
-    reg _T_1780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1780 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1780 <= obuf_tag0_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_tag0 <= _T_1780 @[lsu_bus_buffer.scala 354:13]
-    reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_merge : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_merge <= obuf_merge_en @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1781 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1781 <= obuf_write_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_write <= _T_1781 @[lsu_bus_buffer.scala 357:14]
-    reg _T_1782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1782 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1782 <= obuf_sideeffect_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_sideeffect <= _T_1782 @[lsu_bus_buffer.scala 358:19]
-    reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_sz <= obuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]

lsu_bus_buffer.v

@@ -3743,7 +3743,7 @@ end // initial
       buf_ageQ_3 <= {_T_2467,_T_2390};
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_1780 <= 2'h0;
     end else if (obuf_wr_en) begin
@@ -3754,14 +3754,14 @@ end // initial
       end
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       obuf_merge <= 1'h0;
     end else if (obuf_wr_en) begin
       obuf_merge <= obuf_merge_en;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       obuf_tag1 <= 2'h0;
     end else if (obuf_wr_en) begin
@@ -4142,7 +4142,7 @@ end // initial
       _T_4305 <= buf_sideeffect_in[0];
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       obuf_sideeffect <= 1'h0;
     end else if (obuf_wr_en) begin
@@ -4209,7 +4209,7 @@ end // initial
       buf_samedw_0 <= buf_samedw_in[0];
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       obuf_write <= 1'h0;
     end else if (obuf_wr_en) begin
@@ -4336,7 +4336,7 @@ end // initial
       buf_dualhi_0 <= buf_dualhi_in[0];
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       obuf_sz <= 2'h0;
     end else if (obuf_wr_en) begin
@@ -4347,7 +4347,7 @@ end // initial
       end
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
     if (reset) begin
       obuf_byteen <= 8'h0;
     end else if (obuf_wr_en) begin

src/main/scala/lib/lib.scala

@@ -381,7 +381,7 @@ trait lib extends param{
     def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = {
       if (RV_FPGA_OPTIMIZE)
         withClock (clk) {RegEnable (din, 0.U, clken & en)}
-      else RegEnable (din, 0.U,en)
+      else withClock (clk) {RegEnable (din, 0.U,en)}
     }
   }
   ////rvdffe ///////////////////////////////////////////////////////////////////////