Aligner Updated
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@ -3,13 +3,13 @@ circuit el2_ifu_ic_mem :
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module el2_ifu_ic_mem :
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module el2_ifu_ic_mem :
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input clock : Clock
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input clock : Clock
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input reset : UInt<1>
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input reset : UInt<1>
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output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
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output io : {flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
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io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18]
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io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 32:18]
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io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
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io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 33:16]
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io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16]
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io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:16]
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io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16]
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io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
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io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26]
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io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:26]
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io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23]
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io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:23]
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io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17]
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io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:17]
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@ -1,8 +1,6 @@
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module el2_ifu_ic_mem(
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module el2_ifu_ic_mem(
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input clock,
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input clock,
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input reset,
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input reset,
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input io_clk,
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input io_rst_l,
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input io_clk_override,
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input io_clk_override,
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input io_dec_tlu_core_ecc_disable,
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input io_dec_tlu_core_ecc_disable,
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input [30:0] io_ic_rw_addr,
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input [30:0] io_ic_rw_addr,
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@ -28,11 +26,11 @@ module el2_ifu_ic_mem(
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output io_ic_tag_perr,
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output io_ic_tag_perr,
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input io_scan_mode
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input io_scan_mode
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);
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);
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assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 40:17]
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assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 38:17]
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assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 39:23]
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assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 37:23]
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assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26]
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assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 36:26]
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assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 37:16]
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assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
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assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 36:16]
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assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 34:16]
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assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
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assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 33:16]
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assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18]
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assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 32:18]
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endmodule
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endmodule
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@ -17,7 +17,7 @@ class el2_ifu_ic_mem extends Module with param{
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val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_premux_data = Input(UInt(64.W))
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val ic_premux_data = Input(UInt(64.W))
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val ic_sel_premux_data = Input(Bool())
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val ic_sel_premux_data = Input(Bool())
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val ic_wr_data = Vec(ICACHE_BANKS_WAY, Input(UInt(71.W)))
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val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, Input(UInt(71.W))))
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val ic_rd_data = Output(UInt(64.W))
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val ic_rd_data = Output(UInt(64.W))
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val ic_debug_rd_data = Output(UInt(71.W))
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val ic_debug_rd_data = Output(UInt(71.W))
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val ictag_debug_rd_data = Output(UInt(26.W))
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val ictag_debug_rd_data = Output(UInt(26.W))
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@ -230,5 +230,5 @@ class EL2_IC_DATA extends Module with el2_lib {
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}
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}
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object ifu_ic extends App {
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object ifu_ic extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG()))
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ic_mem()))
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}
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}
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