Traits added

el2_dec_dec_ctl.anno.json

@@ -349,12 +349,6 @@
       "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins"
     ]
   },
-  {
-    "class":"logger.LogLevelAnnotation",
-    "globalLogLevel":{
-      
-    }
-  },
   {
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"

el2_ifu_bp_ctl.anno.json

@@ -0,0 +1,25 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_out",
+    "sources":[
+      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_ifu_bp_ctl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

el2_ifu_bp_ctl.fir

@@ -0,0 +1,18 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_ifu_bp_ctl : 
+  module el2_ifu_bp_ctl : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip in : UInt<32>, out : UInt}
+    
+    node _T = bits(io.in, 14, 10) @[el2_lib.scala 18:33]
+    node _T_1 = bits(io.in, 19, 15) @[el2_lib.scala 18:33]
+    node _T_2 = bits(io.in, 24, 20) @[el2_lib.scala 18:33]
+    wire _T_3 : UInt<5>[3] @[el2_lib.scala 18:25]
+    _T_3[0] <= _T @[el2_lib.scala 18:25]
+    _T_3[1] <= _T_1 @[el2_lib.scala 18:25]
+    _T_3[2] <= _T_2 @[el2_lib.scala 18:25]
+    node _T_4 = xor(_T_3[0], _T_3[1]) @[el2_lib.scala 18:113]
+    node _T_5 = xor(_T_4, _T_3[2]) @[el2_lib.scala 18:113]
+    io.out <= _T_5 @[el2_ifu_bp_ctl.scala 12:10]
+    

el2_ifu_bp_ctl.v

@@ -0,0 +1,9 @@
+module el2_ifu_bp_ctl(
+  input         clock,
+  input         reset,
+  input  [31:0] io_in,
+  output [4:0]  io_out
+);
+  wire [4:0] _T_4 = io_in[14:10] ^ io_in[19:15]; // @[el2_lib.scala 18:113]
+  assign io_out = _T_4 ^ io_in[24:20]; // @[el2_ifu_bp_ctl.scala 12:10]
+endmodule

project/target/config-classes/$d5de37ac4c1cb7029269.cache

@@ -0,0 +1 @@
+sbt.internal.DslEntry

project/target/streams/compile/compileIncremental/_global/streams/out

@@ -1 +1 @@
-[debug] Full compilation, no sources in previous analysis.
+[debug] Full compilation, no sources in previous analysis.

project/target/streams/compile/copyResources/_global/streams/out

@@ -1,2 +1,2 @@
-[debug] Copy resource mappings: 
-[debug] 	
+[debug] Copy resource mappings: 
+[debug] 	

src/main/scala/dec/el2_dec_dec_ctl.scala

@@ -168,6 +168,6 @@ class el2_dec_dec_ctl extends Module{
     pattern(List(-6,4,-3,-2,1,0)).reduce(_&_)
 }
 
-object dec extends App {
-  println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl()))
-}
+//object dec extends App {
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl()))
+//}

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -1,5 +1,17 @@
 package ifu
 
-class el2_ifu_bp_ctl {
+import lib._
+import chisel3._
+import chisel3.util._
 
+class el2_ifu_bp_ctl extends Module with el2_lib {
+  val io = IO (new Bundle {
+    val in = Input(UInt(32.W))
+    val out = Output(UInt())
+  })
+  io.out := el2_btb_tag_hash(io.in)
+}
+
+object ifu extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
 }

src/main/scala/lib/el2_lib.scala

@@ -1,5 +1,25 @@
 package lib
 
-trait el2_lib {
-
+import chisel3._
+trait param {
+  val BTB_ADDR_HI      = 9
+  val BTB_ADDR_LO      = 2
+  val BTB_BTAG_SIZE    = 5
+  val BTB_INDEX1_HI    = 9
+  val BTB_INDEX1_LO    = 2
+  val BTB_INDEX2_HI    = 17
+  val BTB_INDEX2_LO    = 10
+  val BTB_INDEX3_HI    = 25
+  val BTB_INDEX3_LO    = 18
+}
+
+trait el2_lib extends param{
+  def el2_btb_tag_hash(pc : UInt) =
+    (VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1))).reduce(_^_)
+
+  def el2_btb_tag_hash_fold(pc : UInt) =
+    pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
+
+  def el2_btb_addr_hash(pc : UInt) : UInt = 0.U
+  //  def el2_btb_ghr_hash
 }

target/streams/_global/_global/checkBuildSources/_global/streams/out

@@ -1 +1 @@
-[debug] Checking for meta build source updates
+[debug] Checking for meta build source updates