Core Comp

src/main/scala/dec/dec.scala

@@ -32,10 +32,7 @@ class dec_IO extends Bundle with lib {
   val mpc_debug_run_ack     = Output(Bool())  // Run ack
   val debug_brkpt_status    = Output(Bool())  // debug breakpoint
   val lsu_pmu_misaligned_m          = Input(Bool())      // D side load or store misaligned
-  val dma_pmu_dccm_read             = Input(Bool())      // DMA DCCM read
-  val dma_pmu_dccm_write            = Input(Bool())      // DMA DCCM write
-  val dma_pmu_any_read              = Input(Bool())      // DMA read
-  val dma_pmu_any_write             = Input(Bool())      // DMA write
+
 
   val lsu_fir_addr                  = Input(UInt(31.W)) //[31:1] Fast int address
   val lsu_fir_error                 = Input(UInt(2.W))  //[1:0]  Fast int lookup error
@@ -51,22 +48,15 @@ class dec_IO extends Bundle with lib {
 
   val lsu_load_stall_any            = Input(Bool())            // This is for blocking loads
   val lsu_store_stall_any           = Input(Bool())            // This is for blocking stores
-  val dma_dccm_stall_any            = Input(Bool())            // stall any load/store at decode, pmu event
-  val dma_iccm_stall_any            = Input(Bool())            // iccm stalled, pmu event
+
 
   val iccm_dma_sb_error             = Input(Bool())            // ICCM DMA single bit error
 
   val exu_flush_final               = Input(Bool())             // slot0 flush
-  val mexintpend                = Input(Bool())        // External interrupt pending
   val timer_int                 = Input(Bool())        // Timer interrupt pending (from pin)
   val soft_int                  = Input(Bool())        // Software interrupt pending (from pin)
 
-  val pic_claimid               = Input(UInt(8.W))      // PIC claimid
-  val pic_pl                    = Input(UInt(4.W))      // PIC priv level
-  val mhwakeup                  = Input(Bool())      // High priority wakeup
 
-  val dec_tlu_meicurpl          = Output(UInt(4.W))     // to PIC, Current priv level
-  val dec_tlu_meipt             = Output(UInt(4.W))     // to PIC
 
   // Debug start
   val dbg_halt_req              = Input(Bool())        // DM requests a halt
@@ -90,8 +80,7 @@ class dec_IO extends Bundle with lib {
   val dec_tlu_perfcnt2          = Output(Bool())      // toggles when slot0 perf counter 2 has an event inc
   val dec_tlu_perfcnt3          = Output(Bool())      // toggles when slot0 perf counter 3 has an event inc
   val dec_lsu_valid_raw_d       = Output(Bool())
-  val rv_trace_pkt              = Output(new trace_pkt_t)        // trace packet
-  val dec_tlu_dma_qos_prty      = Output(UInt(3.W))       // DMA QoS priority coming from MFDC [18:16]
+  val rv_trace_pkt              = (new trace_pkt_t)        // trace packet
 
   // clock gating overrides from mcgc
   val dec_tlu_misc_clk_override = Output(Bool())       // override misc clock domain gating
@@ -108,6 +97,8 @@ class dec_IO extends Bundle with lib {
   val lsu_dec = Flipped (new lsu_dec)
   val lsu_tlu = Flipped (new lsu_tlu)
   val dec_dbg = new dec_dbg
+  val dec_dma = new dec_dma
+  val dec_pic = new dec_pic
 }
 class dec extends Module with param with RequireAsyncReset{
   val io = IO(new dec_IO)
@@ -140,9 +131,11 @@ class dec extends Module with param with RequireAsyncReset{
   val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
   dontTouch(dec_i0_trigger_match_d)
   decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
+
   decode.io.decode_exu<> io.dec_exu.decode_exu
   decode.io.dec_alu<> io.dec_exu.dec_alu
   decode.io.dec_div<> io.dec_exu.dec_div
+  decode.io.dctl_dma <> io.dec_dma.dctl_dma
   decode.io.dec_tlu_flush_extint               :=  tlu.io.dec_tlu_flush_extint
   decode.io.dec_tlu_force_halt                 :=  tlu.io.tlu_mem.dec_tlu_force_halt
   decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
@@ -167,10 +160,9 @@ class dec extends Module with param with RequireAsyncReset{
   decode.io.lsu_idle_any                       :=  io.lsu_idle_any
   decode.io.lsu_load_stall_any                 :=  io.lsu_load_stall_any
   decode.io.lsu_store_stall_any                :=  io.lsu_store_stall_any
-  decode.io.dma_dccm_stall_any                 :=  io.dma_dccm_stall_any
   decode.io.exu_div_wren                       :=  io.exu_div_wren
   decode.io.dec_tlu_i0_kill_writeb_wb          :=  tlu.io.dec_tlu_i0_kill_writeb_wb
-  decode.io.dec_tlu_flush_lower_wb             :=  tlu.io.tlu_bp.dec_tlu_flush_lower_wb
+  decode.io.dec_tlu_flush_lower_wb             :=  tlu.io.dec_tlu_flush_lower_wb
   decode.io.dec_tlu_i0_kill_writeb_r           :=  tlu.io.dec_tlu_i0_kill_writeb_r
   decode.io.dec_tlu_flush_lower_r              :=  tlu.io.tlu_exu.dec_tlu_flush_lower_r
   decode.io.dec_tlu_flush_pause_r              :=  tlu.io.dec_tlu_flush_pause_r
@@ -211,6 +203,7 @@ class dec extends Module with param with RequireAsyncReset{
   tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
   tlu.io.tlu_bp  <> io.ifu_dec.dec_bp
   tlu.io.tlu_exu <> io.dec_exu.tlu_exu
+  tlu.io.tlu_dma <> io.dec_dma.tlu_dma
   tlu.io.active_clk                         :=  io.active_clk
   tlu.io.free_clk                           :=  io.free_clk
   tlu.io.scan_mode                          :=  io.scan_mode
@@ -226,14 +219,9 @@ class dec extends Module with param with RequireAsyncReset{
   tlu.io.dec_pmu_presync_stall              :=  decode.io.dec_pmu_presync_stall
   tlu.io.dec_pmu_postsync_stall             :=  decode.io.dec_pmu_postsync_stall
   tlu.io.lsu_store_stall_any                :=  io.lsu_store_stall_any
-  tlu.io.dma_dccm_stall_any                 :=  io.dma_dccm_stall_any
-  tlu.io.dma_iccm_stall_any                 :=  io.dma_iccm_stall_any
   io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
   io.lsu_tlu <> tlu.io.lsu_tlu
-  tlu.io.dma_pmu_dccm_read                  :=  io.dma_pmu_dccm_read
-  tlu.io.dma_pmu_dccm_write                 :=  io.dma_pmu_dccm_write
-  tlu.io.dma_pmu_any_read                   :=  io.dma_pmu_any_read
-  tlu.io.dma_pmu_any_write                  :=  io.dma_pmu_any_write
+  io.dec_pic <> tlu.io.dec_pic
   tlu.io.lsu_fir_addr                       :=  io.lsu_fir_addr
   tlu.io.lsu_fir_error                      :=  io.lsu_fir_error
   tlu.io.iccm_dma_sb_error                  :=  io.iccm_dma_sb_error
@@ -257,10 +245,10 @@ class dec extends Module with param with RequireAsyncReset{
   tlu.io.dbg_resume_req                     :=  io.dbg_resume_req
   tlu.io.lsu_idle_any                       :=  io.lsu_idle_any
   tlu.io.dec_div_active                     :=  decode.io.dec_div_active
-  tlu.io.pic_claimid                        :=  io.pic_claimid
-  tlu.io.pic_pl                             :=  io.pic_pl
-  tlu.io.mhwakeup                           :=  io.mhwakeup
-  tlu.io.mexintpend                         :=  io.mexintpend
+//  tlu.io.pic_claimid                        :=  io.dec_pic.pic_claimid
+//  tlu.io.pic_pl                             :=  io.dec_pic.pic_pl
+//  tlu.io.mhwakeup                           :=  io.dec_pic.mhwakeup
+//  tlu.io.mexintpend                         :=  io.mexintpend
   tlu.io.timer_int                          :=  io.timer_int
   tlu.io.soft_int                           :=  io.soft_int
   tlu.io.core_id                            :=  io.core_id
@@ -281,8 +269,8 @@ class dec extends Module with param with RequireAsyncReset{
   io.mpc_debug_halt_ack     := tlu.io.mpc_debug_halt_ack
   io.mpc_debug_run_ack      := tlu.io.mpc_debug_run_ack
   io.debug_brkpt_status     := tlu.io.debug_brkpt_status
-  io.dec_tlu_meicurpl       := tlu.io.dec_tlu_meicurpl
-  io.dec_tlu_meipt          := tlu.io.dec_tlu_meipt
+//  io.dec_pic.dec_tlu_meicurpl       := tlu.io.dec_tlu_meicurpl
+//  io.dec_pic.dec_tlu_meipt          := tlu.io.dec_tlu_meipt
   io.dec_tlu_i0_kill_writeb_r    := tlu.io.dec_tlu_i0_kill_writeb_r
   io.dec_tlu_perfcnt0       := tlu.io.dec_tlu_perfcnt0
   io.dec_tlu_perfcnt1       := tlu.io.dec_tlu_perfcnt1
@@ -293,7 +281,6 @@ class dec extends Module with param with RequireAsyncReset{
   dec_tlu_int_valid_wb1        := tlu.io.dec_tlu_int_valid_wb1
   dec_tlu_exc_cause_wb1        := tlu.io.dec_tlu_exc_cause_wb1
   dec_tlu_mtval_wb1            := tlu.io.dec_tlu_mtval_wb1
-  io.dec_tlu_dma_qos_prty         := tlu.io.dec_tlu_dma_qos_prty
   io.dec_tlu_misc_clk_override    := tlu.io.dec_tlu_misc_clk_override
   io.dec_tlu_ifu_clk_override      := tlu.io.dec_tlu_ifu_clk_override
   io.dec_tlu_lsu_clk_override      := tlu.io.dec_tlu_lsu_clk_override
@@ -316,3 +303,7 @@ class dec extends Module with param with RequireAsyncReset{
   // debug command read data
   io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
 }
+
+object dec_main extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
+}

src/main/scala/dec/dec_decode_ctl.scala

@@ -14,6 +14,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
     val dec_alu = Flipped(new dec_alu)
     val dec_div = Flipped(new dec_div)
     val dctl_busbuff = Flipped(new dctl_busbuff())
+    val dctl_dma = new dctl_dma
     val dec_tlu_flush_extint          = Input(Bool())
     val dec_tlu_force_halt            = Input(Bool()) // invalidate nonblock load cam on a force halt event
     val dec_i0_inst_wb1               = Output(UInt(32.W))      // 32b instruction at wb+1 for trace encoder
@@ -38,7 +39,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
     val lsu_idle_any               =   Input(Bool())        // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode
     val lsu_load_stall_any         =   Input(Bool())              // stall any load at decode
     val lsu_store_stall_any        =   Input(Bool())              // stall any store at decode6
-    val dma_dccm_stall_any         =   Input(Bool())              // stall any load/store at decode
     val exu_div_wren               =   Input(Bool())           // nonblocking divide write enable to GPR.
     val dec_tlu_i0_kill_writeb_wb  =   Input(Bool())           // I0 is flushed, don't writeback any results to arch state
     val dec_tlu_flush_lower_wb     =   Input(Bool())           // trap lower flush
@@ -513,8 +513,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
     ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall |
     i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall
 
-  val i0_store_stall_d =  i0_dp.store & (io.lsu_store_stall_any | io.dma_dccm_stall_any)
-  val i0_load_stall_d =   i0_dp.load & (io.lsu_load_stall_any | io.dma_dccm_stall_any)
+  val i0_store_stall_d =  i0_dp.store & (io.lsu_store_stall_any | io.dctl_dma.dma_dccm_stall_any)
+  val i0_load_stall_d =   i0_dp.load & (io.lsu_load_stall_any | io.dctl_dma.dma_dccm_stall_any)
   val i0_block_d    = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d
   val i0_exublock_d = i0_block_raw_d
 
@@ -784,7 +784,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
     i0_rs2bypass(0).asBool -> i0_result_r,
     (!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data,
   ))
-  io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall)
+  io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dctl_dma.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall)
   io.dec_lsu_offset_d := Mux1H(Seq(
     (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool  ->     i0(31,20),
     (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool ->     Cat(i0(31,25),i0(11,7))))

src/main/scala/dec/dec_tlu_ctl.scala

@@ -44,6 +44,7 @@ trait CSR_VAL {
 
 class dec_tlu_ctl_IO extends Bundle with lib {
 	val tlu_exu = Flipped(new tlu_exu)
+	val tlu_dma = new tlu_dma
 	val active_clk    = Input(Clock())
 	val free_clk      = Input(Clock())
 	val scan_mode     = Input(Bool())
@@ -60,12 +61,6 @@ class dec_tlu_ctl_IO extends Bundle with lib {
 	val       dec_pmu_presync_stall   = Input(UInt(1.W))// decode stall due to presync'd inst
 	val       dec_pmu_postsync_stall  = Input(UInt(1.W))// decode stall due to postsync'd inst
 	val       lsu_store_stall_any     = Input(UInt(1.W))// SB or WB is full, stall decode
-	val       dma_dccm_stall_any      = Input(UInt(1.W))// DMA stall of lsu
-	val       dma_iccm_stall_any      = Input(UInt(1.W))// DMA stall of ifu
-	val       dma_pmu_dccm_read       = Input(UInt(1.W))   // DMA DCCM read
-	val       dma_pmu_dccm_write      = Input(UInt(1.W))   // DMA DCCM write
-	val       dma_pmu_any_read        = Input(UInt(1.W))   // DMA read
-	val       dma_pmu_any_write       = Input(UInt(1.W))   // DMA write
 	val     lsu_fir_addr           = Input(UInt(31.W)) // Fast int address
 	val     lsu_fir_error           = Input(UInt(2.W)) // Fast int lookup error
 	val     iccm_dma_sb_error  = Input(UInt(1.W))      // I side dma single bit error
@@ -99,10 +94,10 @@ class dec_tlu_ctl_IO extends Bundle with lib {
 	val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume
 	val dec_div_active = Input(UInt(1.W)) // oop div is active
 	val trigger_pkt_any             = Output(Vec(4,new trigger_pkt_t))// trigger info for trigger blocks
-	val pic_claimid  = Input(UInt(8.W)) // pic claimid for csr
-	val pic_pl = Input(UInt(4.W)) // pic priv level for csr
-	val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted
-	val mexintpend= Input(UInt(1.W)) // external interrupt pending
+//	val pic_claimid  = Input(UInt(8.W)) // pic claimid for csr
+//	val pic_pl = Input(UInt(4.W)) // pic priv level for csr
+//	val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted
+//	val mexintpend= Input(UInt(1.W)) // external interrupt pending
 	val timer_int= Input(UInt(1.W)) // timer interrupt pending
 	val soft_int= Input(UInt(1.W)) // software interrupt pending
 	val o_cpu_halt_status     = Output(UInt(1.W)) // PMU interface, halted
@@ -117,8 +112,8 @@ class dec_tlu_ctl_IO extends Bundle with lib {
 	val mpc_debug_halt_ack          = Output(UInt(1.W)) // Halt ack
 	val mpc_debug_run_ack           = Output(UInt(1.W)) // Run ack
 	val debug_brkpt_status          = Output(UInt(1.W)) // debug breakpoint
-	val dec_tlu_meicurpl            = Output(UInt(4.W)) // to PIC
-	val  dec_tlu_meipt              = Output(UInt(4.W)) // to PIC
+//	val dec_tlu_meicurpl            = Output(UInt(4.W)) // to PIC
+//	val  dec_tlu_meipt              = Output(UInt(4.W)) // to PIC
 	val  dec_csr_rddata_d           = Output(UInt(32.W))      // csr read data at wb
 	val dec_csr_legal_d             = Output(UInt(1.W))              // csr indicates legal operation
 	val dec_tlu_i0_kill_writeb_wb   = Output(UInt(1.W))    // I0 is flushed, don't writeback any results to arch state
@@ -137,7 +132,6 @@ class dec_tlu_ctl_IO extends Bundle with lib {
 	val dec_tlu_exc_cause_wb1       = Output(UInt(5.W)) // exception or int cause
 	val dec_tlu_mtval_wb1           = Output(UInt(32.W)) // MTVAL value
 	val  dec_tlu_pipelining_disable         = Output(UInt(1.W))      // disable pipelining
-	val   dec_tlu_dma_qos_prty              = Output(UInt(3.W))    // DMA QoS priority coming from MFDC [18:16]
 	// clock gating overrides from mcgc
 	val  dec_tlu_misc_clk_override  = Output(UInt(1.W)) // override misc clock domain gating
 	val  dec_tlu_dec_clk_override   = Output(UInt(1.W)) // override decode clock domain gating
@@ -147,12 +141,14 @@ class dec_tlu_ctl_IO extends Bundle with lib {
 	val  dec_tlu_pic_clk_override   = Output(UInt(1.W)) // override PIC clock domain gating
 	val  dec_tlu_dccm_clk_override  = Output(UInt(1.W)) // override DCCM clock domain gating
 	val  dec_tlu_icm_clk_override   = Output(UInt(1.W)) // override ICCM clock domain gating
+	val dec_tlu_flush_lower_wb = Output(Bool())
 	val ifu_pmu_instr_aligned = Input(UInt(1.W))
 	val tlu_bp  = Flipped(new dec_bp)
 	val tlu_ifc = Flipped(new dec_ifc)
 	val tlu_mem = Flipped(new dec_mem_ctrl)
 	val tlu_busbuff = Flipped (new tlu_busbuff)
 	val lsu_tlu = Flipped (new lsu_tlu)
+	val dec_pic = new dec_pic
 }
 class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
   val io = IO(new dec_tlu_ctl_IO)
@@ -445,7 +441,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
 	val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted
 
    // used to hold off commits after an in-pipe debug mode request (triggers, DCSR)
-	val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.tlu_bp.dec_tlu_flush_lower_wb)
+	val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb)
 
 	val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f
 	
@@ -521,7 +517,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
 
    val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled
    // Qual trigger hits
-   val i0_trigger_r = ~(Fill(4,io.tlu_bp.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r
+   val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r
 
    // chaining can mask raw trigger info
    val i0_trigger_chain_masked_r  = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1)))
@@ -601,7 +597,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
    io.o_debug_mode_status := debug_mode_status
    
       // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts
-   i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1)
+   i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.dec_pic.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1)
 
    //--------------------------------------------------------------------------------
    //--------------------------------------------------------------------------------
@@ -610,7 +606,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
    mdseac_locked_f					:=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)}
    val lsu_single_ecc_error_r_d1	=withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)}
    val lsu_error_pkt_addr_r		 	=io.lsu_error_pkt_r.bits.addr
-   val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.tlu_bp.dec_tlu_flush_lower_wb
+   val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb
    lsu_i0_exc_r_raw :=  io.lsu_error_pkt_r.valid
    val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r
    val lsu_exc_valid_r = lsu_i0_exc_r
@@ -802,8 +798,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
 
 	val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this
 
-   	io.tlu_bp.dec_tlu_flush_lower_wb 	:= tlu_flush_lower_r_d1
-    io.tlu_mem.dec_tlu_flush_lower_wb 	:= io.tlu_bp.dec_tlu_flush_lower_wb
+   	io.dec_tlu_flush_lower_wb 	:= tlu_flush_lower_r_d1
+//    io.tlu_mem.dec_tlu_flush_lower_wb 	:= io.dec_tlu_flush_lower_wb
    	io.tlu_exu.dec_tlu_flush_lower_r 	:= tlu_flush_lower_r
    	io.tlu_exu.dec_tlu_flush_path_r 	:= tlu_flush_path_r ///After Combining Code revisit this
 
@@ -830,8 +826,8 @@ val csr=Module(new csr_tlu)
   csr.io.dec_i0_decode_d                   := io.dec_i0_decode_d
   csr.io.ifu_ic_debug_rd_data_valid        := io.tlu_mem.ifu_ic_debug_rd_data_valid
   csr.io.ifu_pmu_bus_trxn                  := io.tlu_mem.ifu_pmu_bus_trxn
-  csr.io.dma_iccm_stall_any                :=io.dma_iccm_stall_any     
-  csr.io.dma_dccm_stall_any                :=io.dma_dccm_stall_any     
+  csr.io.dma_iccm_stall_any                :=io.tlu_dma.dma_iccm_stall_any
+  csr.io.dma_dccm_stall_any                :=io.tlu_dma.dma_dccm_stall_any
   csr.io.lsu_store_stall_any               :=io.lsu_store_stall_any    
   csr.io.dec_pmu_presync_stall             :=io.dec_pmu_presync_stall  
   csr.io.dec_pmu_postsync_stall            :=io.dec_pmu_postsync_stall 
@@ -847,10 +843,10 @@ val csr=Module(new csr_tlu)
   csr.io.ifu_pmu_ic_hit                    :=io.tlu_mem.ifu_pmu_ic_hit
   csr.io.dec_csr_wen_r                     := io.dec_csr_wen_r
   csr.io.dec_tlu_dbg_halted                := io.dec_tlu_dbg_halted  
-  csr.io.dma_pmu_dccm_write                := io.dma_pmu_dccm_write  
-  csr.io.dma_pmu_dccm_read                 := io.dma_pmu_dccm_read   
-  csr.io.dma_pmu_any_write                 := io.dma_pmu_any_write   
-  csr.io.dma_pmu_any_read                  := io.dma_pmu_any_read    
+  csr.io.dma_pmu_dccm_write                := io.tlu_dma.dma_pmu_dccm_write
+  csr.io.dma_pmu_dccm_read                 := io.tlu_dma.dma_pmu_dccm_read
+  csr.io.dma_pmu_any_write                 := io.tlu_dma.dma_pmu_any_write
+  csr.io.dma_pmu_any_read                  := io.tlu_dma.dma_pmu_any_read
   csr.io.lsu_pmu_bus_busy                  := io.tlu_busbuff.lsu_pmu_bus_busy
   csr.io.dec_tlu_i0_pc_r                   := io.dec_tlu_i0_pc_r
   csr.io.dec_tlu_i0_valid_r                := io.dec_tlu_i0_valid_r  
@@ -862,24 +858,24 @@ val csr=Module(new csr_tlu)
   csr.io.lsu_pmu_bus_misaligned            := io.tlu_busbuff.lsu_pmu_bus_misaligned
   csr.io.lsu_pmu_bus_trxn                  := io.tlu_busbuff.lsu_pmu_bus_trxn
   csr.io.ifu_ic_debug_rd_data              := io.tlu_mem.ifu_ic_debug_rd_data
-  csr.io.pic_pl                            := io.pic_pl
-  csr.io.pic_claimid                       := io.pic_claimid                  
+  csr.io.pic_pl                            := io.dec_pic.pic_pl
+  csr.io.pic_claimid                       := io.dec_pic.pic_claimid
   csr.io.iccm_dma_sb_error                 := io.iccm_dma_sb_error            
   csr.io.lsu_imprecise_error_addr_any      := io.tlu_busbuff.lsu_imprecise_error_addr_any
   csr.io.lsu_imprecise_error_load_any      := io.tlu_busbuff.lsu_imprecise_error_load_any
   csr.io.lsu_imprecise_error_store_any     := io.tlu_busbuff.lsu_imprecise_error_store_any
   csr.io.dec_illegal_inst                  := io.dec_illegal_inst  
   csr.io.lsu_error_pkt_r                   := io.lsu_error_pkt_r   
-  csr.io.mexintpend                        := io.mexintpend        
+  csr.io.mexintpend                        := io.dec_pic.mexintpend
   csr.io.exu_npc_r                         := io.tlu_exu.exu_npc_r
   csr.io.mpc_reset_run_req                 := io.mpc_reset_run_req 
   csr.io.rst_vec                           := io.rst_vec           
   csr.io.core_id                           := io.core_id           
   csr.io.dec_timer_rddata_d                := dec_timer_rddata_d
   csr.io.dec_timer_read_d                  := dec_timer_read_d  
-  io.dec_tlu_meicurpl                      := csr.io.dec_tlu_meicurpl
+  io.dec_pic.dec_tlu_meicurpl                      := csr.io.dec_tlu_meicurpl
   io.tlu_exu.dec_tlu_meihap                        := csr.io.dec_tlu_meihap
-  io.dec_tlu_meipt                         := csr.io.dec_tlu_meipt           
+  io.dec_pic.dec_tlu_meipt                         := csr.io.dec_tlu_meipt
   io.dec_tlu_int_valid_wb1                 := csr.io.dec_tlu_int_valid_wb1   
   io.dec_tlu_i0_exc_valid_wb1              := csr.io.dec_tlu_i0_exc_valid_wb1
   io.dec_tlu_i0_valid_wb1                  := csr.io.dec_tlu_i0_valid_wb1  
@@ -908,10 +904,10 @@ val csr=Module(new csr_tlu)
   io.tlu_busbuff.dec_tlu_sideeffect_posted_disable := csr.io.dec_tlu_sideeffect_posted_disable
   io.tlu_mem.dec_tlu_core_ecc_disable          := csr.io.dec_tlu_core_ecc_disable
   io.tlu_busbuff.dec_tlu_external_ldfwd_disable    := csr.io.dec_tlu_external_ldfwd_disable
-  io.dec_tlu_dma_qos_prty              := csr.io.dec_tlu_dma_qos_prty             
+  io.tlu_dma.dec_tlu_dma_qos_prty              := csr.io.dec_tlu_dma_qos_prty
   csr.io.dec_illegal_inst                  := io.dec_illegal_inst      
   csr.io.lsu_error_pkt_r                   := io.lsu_error_pkt_r    
-  csr.io.mexintpend                        := io.mexintpend                            
+  csr.io.mexintpend                        := io.dec_pic.mexintpend
   csr.io.exu_npc_r                         := io.tlu_exu.exu_npc_r
   csr.io.mpc_reset_run_req                 := io.mpc_reset_run_req           
   csr.io.rst_vec                           := io.rst_vec                      
@@ -2503,7 +2499,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)}
  				        io.csr_pkt.csr_misa.asBool            -> 0x40001104.U(32.W),
                 io.csr_pkt.csr_mvendorid.asBool       -> 0x00000045.U(32.W),
                 io.csr_pkt.csr_marchid.asBool         -> 0x00000010.U(32.W),
-                io.csr_pkt.csr_mimpid.asBool          -> 0x2.U(32.W),
+                io.csr_pkt.csr_mimpid.asBool          -> 0x1.U(32.W),
                 io.csr_pkt.csr_mhartid.asBool         -> Cat(io.core_id,0.U(4.W)),
                 io.csr_pkt.csr_mstatus.asBool         -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)),
                 io.csr_pkt.csr_mtvec.asBool           -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)),

src/main/scala/dma_ctrl.scala

@@ -18,18 +18,12 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
     val dma_dbg_cmd_fail      = Output(Bool())
     val dbg_dma = new dec_dbg()
     val dbg_dma_io = new dbg_dma()
+    val dec_dma = Flipped(new dec_dma())
     val iccm_dma_rvalid       = Input(Bool())     // iccm data valid for DMA read
     val iccm_dma_ecc_error    = Input(Bool())     // ECC error on DMA read
     val iccm_dma_rtag         = Input(UInt(3.W))  // Tag of the DMA req
     val iccm_dma_rdata        = Input(UInt(64.W)) // iccm data for DMA read
-    val dma_dccm_stall_any    = Output(Bool())    // stall dccm pipe (bubble) so that DMA can proceed
     val iccm_ready            = Input(Bool())     // iccm ready to accept DMA request
-    val dec_tlu_dma_qos_prty  = Input(UInt(3.W))  // DMA QoS priority coming from MFDC [18:15]
-    // PMU signals
-    val dma_pmu_dccm_read     = Output(Bool())
-    val dma_pmu_dccm_write    = Output(Bool())
-    val dma_pmu_any_read      = Output(Bool())
-    val dma_pmu_any_write     = Output(Bool())
     // AXI Write Channels
     val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
     val lsu_dma = Flipped(new lsu_dma)
@@ -331,16 +325,17 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
 
   // Block the decode if fifo full
 
-  io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
+  io.dec_dma.tlu_dma.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
   io.ifu_dma.dma_ifc.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
-
+  io.dec_dma.tlu_dma.dma_iccm_stall_any :=  io.ifu_dma.dma_ifc.dma_iccm_stall_any
+  io.dec_dma.dctl_dma.dma_dccm_stall_any :=  io.dec_dma.tlu_dma.dma_dccm_stall_any
   // Used to indicate ready to debug
 
   fifo_empty := ~(fifo_valid.orR)
 
   // Nack counter, stall the lsu pipe if 7 nacks
 
-  dma_nack_count_csr := io.dec_tlu_dma_qos_prty
+  dma_nack_count_csr := io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty
   val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
 
   dma_nack_count     := withClock(dma_free_clk) {
@@ -363,10 +358,10 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
 
   // PMU outputs
 
-  io.dma_pmu_dccm_read   := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
-  io.dma_pmu_dccm_write  := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
-  io.dma_pmu_any_read    := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
-  io.dma_pmu_any_write   := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
+  io.dec_dma.tlu_dma.dma_pmu_dccm_read   := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
+  io.dec_dma.tlu_dma.dma_pmu_dccm_write  := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
+  io.dec_dma.tlu_dma.dma_pmu_any_read    := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
+  io.dec_dma.tlu_dma.dma_pmu_any_write   := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
 
   // Inputs
 

src/main/scala/ifu/ifu.scala

@@ -30,8 +30,7 @@ class ifu extends Module with lib with RequireAsyncReset {
     val iccm_ready = Output(Bool())
     // Performance counter
     val iccm_dma_sb_error = Output(Bool())
-//    val iccm_buf_correct_ecc = Output(Bool())
-  //  val iccm_correction_state = Output(Bool())
+    val dec_tlu_flush_lower_wb = Input(Bool())
     val scan_mode = Input(Bool())
   })
   val mem_ctl = Module(new ifu_mem_ctl)
@@ -87,7 +86,7 @@ class ifu extends Module with lib with RequireAsyncReset {
   bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp
   bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
   bp_ctl.io.exu_flush_final := io.exu_flush_final
-
+  bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
   // mem-ctl wiring
   mem_ctl.io.free_clk := io.free_clk
   mem_ctl.io.active_clk := io.active_clk
@@ -108,6 +107,7 @@ class ifu extends Module with lib with RequireAsyncReset {
   mem_ctl.io.ic <> io.ic
   mem_ctl.io.iccm <> io.iccm
   mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f
+  mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
   mem_ctl.io.scan_mode := io.scan_mode
 
   io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error

src/main/scala/ifu/ifu_bp_ctl.scala

@@ -15,6 +15,7 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
     val ifc_fetch_addr_f = Input(UInt(31.W))
     val ifc_fetch_req_f = Input(Bool())           // Fetch request generated by the IFC
     val dec_bp = new dec_bp()
+    val dec_tlu_flush_lower_wb = Input(Bool())
     val exu_bp = Flipped(new exu_bp())
     val ifu_bp_hit_taken_f = Output(Bool())
     val ifu_bp_btb_target_f = Output(UInt(31.W))
@@ -119,7 +120,7 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
   val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_flush_final, init = 0.U)}
 
   // If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side
-  leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_bp.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_bp.dec_tlu_flush_lower_wb)
+  leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_tlu_flush_lower_wb)
 
   // For a tag to match the branch should be valid tag should match and a fetch request should be generated
   // Also there should be no bank conflict or leak-one

src/main/scala/ifu/ifu_mem_ctl.scala

@@ -39,7 +39,7 @@ class mem_ctl_io extends Bundle with lib{
   val iccm_dma_rtag = Output(UInt(3.W))
   val iccm_ready = Output(Bool())
 
-
+  val dec_tlu_flush_lower_wb = Input(Bool())
   val iccm_rd_ecc_double_err = Output(Bool())
   val iccm_dma_sb_error = Output(Bool())
 
@@ -420,12 +420,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
     }
     is(ic_wff_C){
       perr_nxtstate := err_idle_C
-      perr_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt
-      perr_sel_invalidate := io.dec_mem_ctrl.dec_tlu_flush_lower_wb & io.dec_mem_ctrl.dec_tlu_flush_err_wb
+      perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt
+      perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_mem_ctrl.dec_tlu_flush_err_wb
     }
     is(ecc_wff_C){
-      perr_nxtstate := Mux(((!io.dec_mem_ctrl.dec_tlu_flush_err_wb & io.dec_mem_ctrl.dec_tlu_flush_lower_wb ) | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C)
-      perr_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt
+      perr_nxtstate := Mux(((!io.dec_mem_ctrl.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C)
+      perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt
     }
     is(dma_sb_err_C){
       perr_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, err_idle_C, ecc_cor_C)
@@ -447,24 +447,24 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
       err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_err_wb & (perr_state === ecc_wff_C) & !io.dec_mem_ctrl.dec_tlu_force_halt
     }
     is(err_fetch1_C){
-      err_stop_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_stop_idle_C,
+      err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_stop_idle_C,
         Mux(((io.ifu_fetch_val===3.U)|(io.ifu_fetch_val(0)&two_byte_instr)).asBool(), err_stop_fetch_C,
           Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C)))
-      err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_mem_ctrl.dec_tlu_force_halt
+      err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_mem_ctrl.dec_tlu_force_halt
       err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr))  & !(io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt)
       io.iccm.correction_state := true.B
     }
     is(err_fetch2_C){
-      err_stop_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
+      err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
         err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C))
-      err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_mem_ctrl.dec_tlu_force_halt
+      err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_mem_ctrl.dec_tlu_force_halt
       err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_mem_ctrl.dec_tlu_i0_commit_cmt
       io.iccm.correction_state := true.B
     }
     is(err_stop_fetch_C){
-      err_stop_nxtstate := Mux(((io.dec_mem_ctrl.dec_tlu_flush_lower_wb & !io.dec_mem_ctrl.dec_tlu_flush_err_wb) | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
+      err_stop_nxtstate := Mux(((io.dec_tlu_flush_lower_wb & !io.dec_mem_ctrl.dec_tlu_flush_err_wb) | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool,
         err_stop_idle_C, Mux(io.dec_mem_ctrl.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C))
-      err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt
+      err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt
       err_stop_fetch := true.B
       io.iccm.correction_state := true.B
     }

src/main/scala/include/bundle.scala

@@ -6,9 +6,35 @@ import ifu._
 import dec._
 import lsu._
 import lib._
+class dec_pic extends Bundle{
+  val pic_claimid               = Input(UInt(8.W))      // PIC claimid
+  val pic_pl                    = Input(UInt(4.W))      // PIC priv level
+  val mhwakeup                  = Input(Bool())      // High priority wakeup
+  val dec_tlu_meicurpl          = Output(UInt(4.W))     // to PIC, Current priv level
+  val dec_tlu_meipt             = Output(UInt(4.W))     // to PIC
+  val mexintpend               = Input(UInt(1.W)) // external interrupt pending
+}
+
+class dec_dma extends Bundle{
+  val dctl_dma = new dctl_dma()
+  val tlu_dma  = new tlu_dma()
+}
+class dctl_dma extends Bundle{
+  val dma_dccm_stall_any            = Input(Bool())            // stall any load/store at decode, pmu event
+}
+class tlu_dma extends Bundle{
+  val dma_pmu_dccm_read             = Input(Bool())      // DMA DCCM read
+  val dma_pmu_dccm_write            = Input(Bool())      // DMA DCCM write
+  val dma_pmu_any_read              = Input(Bool())      // DMA read
+  val dma_pmu_any_write             = Input(Bool())      // DMA write
+  val dec_tlu_dma_qos_prty      = Output(UInt(3.W))       // DMA QoS priority coming from MFDC [18:16]
+  val dma_dccm_stall_any            = Input(Bool())            // stall any load/store at decode, pmu event
+  val dma_iccm_stall_any            = Input(Bool())            // iccm stalled, pmu event
+}
+
 class dec_bp extends Bundle{
   val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t))
-  val dec_tlu_flush_lower_wb = Input(Bool())
+//  val dec_tlu_flush_lower_wb = Input(Bool())
   val dec_tlu_flush_leak_one_wb = Input(Bool())
   val dec_tlu_bpred_disable = Input(Bool())
 }
@@ -64,22 +90,9 @@ class write_resp(val TAG : Int=3) extends Bundle with lib{ // write_response
   val resp = UInt(2.W)
   val id = UInt(TAG.W)
 }
-class ahb_channel extends Bundle with lib{
-  val haddr = Output(UInt(32.W)) // [31:0]  // ahb bus address
-  val hburst = Output(UInt(3.W)) // [2:0]   // tied to 0
-  val hmastlock = Output(Bool()) // tied to 0
-  val hprot = Output(UInt(4.W)) // [3:0]   // tied to 4'b0011
-  val hsize = Output(UInt(3.W)) // [2:0]   // size of bus transaction (possible values 0,1,2,3)
-  val htrans = Output(UInt(2.W))
-  val hwrite = Output(Bool()) // ahb bus write
-  val hwdata = Output(UInt(64.W)) // [63:0]  // ahb bus write dat
-  val hrdata = Input(UInt(64.W)) // [63:0]    // ahb bus read data
-  val hready = Input(Bool()) // slave ready to accept transaction
-  val hresp = Input(Bool()) // slave response (high indicates erro)
-}
 
 class dec_mem_ctrl extends Bundle with lib{
-  val dec_tlu_flush_lower_wb = Input(Bool())
+//  val dec_tlu_flush_lower_wb = Input(Bool())
   val dec_tlu_flush_err_wb = Input(Bool())
   val dec_tlu_i0_commit_cmt = Input(Bool())
   val dec_tlu_force_halt = Input(Bool())
@@ -250,13 +263,13 @@ class dma_ifc extends  Bundle{
 }
 
 class trace_pkt_t extends Bundle{
-  val rv_i_valid_ip      = UInt(2.W)
-  val rv_i_insn_ip       = UInt(32.W)
-  val rv_i_address_ip    = UInt(32.W)
-  val rv_i_exception_ip  = UInt(2.W)
-  val rv_i_ecause_ip     = UInt(5.W)
-  val rv_i_interrupt_ip  = UInt(2.W)
-  val rv_i_tval_ip       = UInt(32.W)
+  val rv_i_valid_ip      = Output(UInt(2.W)  )
+  val rv_i_insn_ip       = Output(UInt(32.W) )
+  val rv_i_address_ip    = Output(UInt(32.W) )
+  val rv_i_exception_ip  = Output(UInt(2.W)  )
+  val rv_i_ecause_ip     = Output(UInt(5.W)  )
+  val rv_i_interrupt_ip  = Output(UInt(2.W)  )
+  val rv_i_tval_ip       = Output(UInt(32.W) )
 }
 
 

src/main/scala/lib/param.scala

@@ -21,7 +21,7 @@ trait param {
   val BTB_INDEX3_HI          = 	0x19
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
-  val BUILD_AHB_LITE         = 	0x0
+  val BUILD_AHB_LITE         = 	0x1
   val BUILD_AXI4             = 	0x1
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -296,7 +296,6 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   val obuf_merge_en = WireInit(Bool(), false.B)
   val obuf_merge_in = obuf_merge_en
   val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0)
-  //val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
 
   val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1)
   val obuf_cmd_done = WireInit(Bool(), false.B)

src/main/scala/pic_ctrl.scala

@@ -13,13 +13,14 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
     val clk_override           = Input(Bool () )
     val extintsrc_req          = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
     val lsu_pic = Flipped(new lsu_pic())
-    val meicurpl               = Input(UInt(4.W))
-    val meipt                  = Input(UInt(4.W))
-
-    val mexintpend             = Output(Bool())
-    val claimid                = Output(UInt(8.W))
-    val pl                     = Output(UInt(4.W))
-    val mhwakeup               = Output(Bool())
+    val dec_pic = Flipped(new dec_pic)
+//    val dec_tlu_meicurpl               = Input(UInt(4.W))
+//    val dec_tlu_meipt                  = Input(UInt(4.W))
+//
+//    val mexintpend             = Output(Bool())
+//    val pic_claimid                = Output(UInt(8.W))
+//    val pic_pl                     = Output(UInt(4.W))
+//    val mhwakeup               = Output(Bool())
   })
 
   def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
@@ -33,8 +34,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
   }
 
   // io.mexintpend    := 0.U
-  // io.claimid       := 0.U
-  // io.pl            := 0.U
+  // io.pic_claimid       := 0.U
+  // io.pic_pl            := 0.U
   //io.picm_rd_data  := 0.U
   //io.mhwakeup      := 0.U
 
@@ -255,18 +256,18 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
 
   val pl_in                =      selected_int_priority
   ///////////////////////////////////////////////////////////
-  /// ClaimId  Reg and Corresponding PL
+  /// pic_claimid  Reg and Corresponding pic_pl
   ///////////////////////////////////////////////////////////
   val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt
-  withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)}
-  withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)}
-  val meipt_inv = Mux(intpriord.asBool,~io.meipt,io.meipt)
-  val meicurpl_inv = Mux(intpriord.asBool,~io.meicurpl,io.meicurpl)
+  withClock(io.free_clk){io.dec_pic.pic_claimid := RegNext(claimid_in,0.U)}
+  withClock(io.free_clk){io.dec_pic.pic_pl := RegNext(pl_in_q,0.U)}
+  val meipt_inv = Mux(intpriord.asBool,~io.dec_pic.dec_tlu_meipt,io.dec_pic.dec_tlu_meipt)
+  val meicurpl_inv = Mux(intpriord.asBool,~io.dec_pic.dec_tlu_meicurpl,io.dec_pic.dec_tlu_meicurpl)
   val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv)
-  io.mexintpend := withClock(io.free_clk){RegNext(mexintpend_in,0.U)}
+  io.dec_pic.mexintpend := withClock(io.free_clk){RegNext(mexintpend_in,0.U)}
   val maxint = Mux(intpriord.asBool,0.U,15.U)
   val mhwakeup_in = pl_in_q === maxint
-  io.mhwakeup := withClock(io.free_clk){RegNext(mhwakeup_in,0.U)}
+  io.dec_pic.mhwakeup := withClock(io.free_clk){RegNext(mhwakeup_in,0.U)}
 
   //////////////////////////////////////////////////////////////////////////
   //  Reads of register.

src/main/scala/quasar.scala

@@ -19,13 +19,7 @@ class quasar_bundle extends Bundle with  lib{
   val nmi_int = Input(Bool())
   val nmi_vec = Input(UInt(31.W))
   val core_rst_l = Output(AsyncReset())
-  val trace_rv_i_insn_ip = Output(UInt(32.W))
-  val trace_rv_i_address_ip = Output(UInt(32.W))
-  val trace_rv_i_valid_ip = Output(UInt(2.W))
-  val trace_rv_i_exception_ip = Output(UInt(2.W))
-  val trace_rv_i_ecause_ip = Output(UInt(5.W))
-  val trace_rv_i_interrupt_ip = Output(UInt(2.W))
-  val trace_rv_i_tval_ip = Output(UInt(32.W))
+  val rv_trace_pkt = new trace_pkt_t()
   val dccm_clk_override = Output(Bool())
   val icm_clk_override = Output(Bool())
   val dec_tlu_core_ecc_disable = Output(Bool())
@@ -153,7 +147,7 @@ class quasar extends Module with RequireAsyncReset with lib {
   ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
   ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
   ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
-  ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
+  ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
   ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
 
   // Lets start with Dec
@@ -173,10 +167,8 @@ class quasar extends Module with RequireAsyncReset with lib {
   dec.io.lsu_dec <> lsu.io.lsu_dec
   dec.io.lsu_tlu <> lsu.io.lsu_tlu
   dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
-  dec.io.dma_pmu_dccm_read := dma_ctrl.io.dma_pmu_dccm_read
-  dec.io.dma_pmu_dccm_write := dma_ctrl.io.dma_pmu_dccm_write
-  dec.io.dma_pmu_any_read := dma_ctrl.io.dma_pmu_any_read
-  dec.io.dma_pmu_any_write := dma_ctrl.io.dma_pmu_any_write
+  dec.io.dec_dma <> dma_ctrl.io.dec_dma
+
   dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
   dec.io.lsu_fir_error := lsu.io.lsu_fir_error
   dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
@@ -190,15 +182,10 @@ class quasar extends Module with RequireAsyncReset with lib {
   dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
   dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
   dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
-  dec.io.dma_dccm_stall_any := dma_ctrl.io.dma_dccm_stall_any
-  dec.io.dma_iccm_stall_any := dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any
   dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
   dec.io.exu_flush_final := exu.io.exu_flush_final
-  dec.io.mexintpend := pic_ctrl_inst.io.mexintpend
+
   dec.io.soft_int := io.soft_int
-  dec.io.pic_claimid := pic_ctrl_inst.io.claimid
-  dec.io.pic_pl := pic_ctrl_inst.io.pl
-  dec.io.mhwakeup := pic_ctrl_inst.io.mhwakeup
   dec.io.dbg_halt_req := dbg.io.dbg_halt_req
   dec.io.dbg_resume_req := dbg.io.dbg_resume_req
   dec.io.exu_i0_br_way_r := exu.io.exu_bp.exu_i0_br_way_r
@@ -263,7 +250,6 @@ class quasar extends Module with RequireAsyncReset with lib {
   dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
   dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
   dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
-  dma_ctrl.io.dec_tlu_dma_qos_prty := dec.io.dec_tlu_dma_qos_prty
   dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
 
   // PIC lets go
@@ -274,16 +260,9 @@ class quasar extends Module with RequireAsyncReset with lib {
   pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
   pic_ctrl_inst.io.extintsrc_req := io.extintsrc_req
   pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
-  pic_ctrl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
-  pic_ctrl_inst.io.meipt := dec.io.dec_tlu_meipt
+  pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic
   // Trace Packet
-  io.trace_rv_i_insn_ip := dec.io.rv_trace_pkt.rv_i_insn_ip
-  io.trace_rv_i_address_ip := dec.io.rv_trace_pkt.rv_i_address_ip
-  io.trace_rv_i_valid_ip := dec.io.rv_trace_pkt.rv_i_valid_ip
-  io.trace_rv_i_exception_ip := dec.io.rv_trace_pkt.rv_i_exception_ip
-  io.trace_rv_i_ecause_ip := dec.io.rv_trace_pkt.rv_i_ecause_ip
-  io.trace_rv_i_interrupt_ip := dec.io.rv_trace_pkt.rv_i_interrupt_ip
-  io.trace_rv_i_tval_ip := dec.io.rv_trace_pkt.rv_i_tval_ip
+  io.rv_trace_pkt := dec.io.rv_trace_pkt
 
   // Outputs
   io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override

src/main/scala/quasar_wrapper.scala

@@ -12,14 +12,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
     val nmi_vec = Input(UInt(31.W))
     val jtag_id = Input(UInt(31.W))
 
-    val trace_rv_i_insn_ip = Output(UInt(32.W))
-    val trace_rv_i_address_ip = Output(UInt(32.W))
-    val trace_rv_i_valid_ip = Output(UInt(2.W))
-    val trace_rv_i_exception_ip = Output(UInt(2.W))
-    val trace_rv_i_ecause_ip = Output(UInt(5.W))
-    val trace_rv_i_interrupt_ip = Output(UInt(2.W))
-    val trace_rv_i_tval_ip = Output(UInt(32.W))
-
     // AXI Signals
     val lsu_axi = new axi_channels(LSU_BUS_TAG)
     val ifu_axi = new axi_channels(IFU_BUS_TAG)
@@ -79,6 +71,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
     val o_cpu_run_ack = Output(Bool())
     val mbist_mode = Input(Bool())
 
+    val rv_trace_pkt = new trace_pkt_t()
     val scan_mode = Input(Bool())
 
 })
@@ -193,13 +186,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
 
   // Outputs
   val core_rst_l = swerv.io.core_rst_l
-  io.trace_rv_i_insn_ip := swerv.io.trace_rv_i_insn_ip
-  io.trace_rv_i_address_ip := swerv.io.trace_rv_i_address_ip
-  io.trace_rv_i_valid_ip := swerv.io.trace_rv_i_valid_ip
-  io.trace_rv_i_exception_ip := swerv.io.trace_rv_i_exception_ip
-  io.trace_rv_i_ecause_ip := swerv.io.trace_rv_i_ecause_ip
-  io.trace_rv_i_interrupt_ip := swerv.io.trace_rv_i_interrupt_ip
-  io.trace_rv_i_tval_ip := swerv.io.trace_rv_i_tval_ip
+  io.rv_trace_pkt := swerv.io.rv_trace_pkt
 
   // external halt/run interface
   io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack