Divider 5 added
This commit is contained in:
Laraib Khan
parent
6b63669e0c
commit
c874128938
|
|
@ -0,0 +1,30 @@
|
||||||
|
[
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~exu_div_new_4bit_fullshortq|exu_div_new_4bit_fullshortq>io_valid_out",
|
||||||
|
"sources":[
|
||||||
|
"~exu_div_new_4bit_fullshortq|exu_div_new_4bit_fullshortq>io_cancel"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.EmitCircuitAnnotation",
|
||||||
|
"emitter":"firrtl.VerilogEmitter"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||||
|
"target":"exu_div_new_4bit_fullshortq.gated_latch",
|
||||||
|
"resourceId":"/vsrc/gated_latch.sv"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.TargetDirAnnotation",
|
||||||
|
"directory":"."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||||
|
"file":"exu_div_new_4bit_fullshortq"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||||
|
"targetDir":"."
|
||||||
|
}
|
||||||
|
]
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -628,23 +628,13 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
|
||||||
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
|
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
|
||||||
|
|
||||||
val r_adder_sel = (0 to 7 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
|
val r_adder_sel = (0 to 7 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
|
||||||
|
val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
|
||||||
// val r_restore_sel = running_state & (quotient_new === 0.U) & !shortq_enable_ff
|
val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
|
||||||
// val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff
|
val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
|
||||||
// val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff
|
val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
|
||||||
// val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff
|
val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
|
||||||
// val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff
|
val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
|
||||||
// val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff
|
val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
|
||||||
// val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff
|
|
||||||
// val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff
|
|
||||||
|
|
||||||
val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
|
|
||||||
val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
|
|
||||||
val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
|
|
||||||
val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
|
|
||||||
val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
|
|
||||||
val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
|
|
||||||
val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
|
|
||||||
quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
|
quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
|
||||||
(!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
|
(!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
|
||||||
(!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
|
(!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
|
||||||
|
|
@ -761,167 +751,200 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib
|
||||||
val data_out = Output(UInt(32.W))
|
val data_out = Output(UInt(32.W))
|
||||||
val valid_out = Output(UInt(1.W))
|
val valid_out = Output(UInt(1.W))
|
||||||
})
|
})
|
||||||
io.data_out := 0.U
|
|
||||||
io.valid_out :=0.U
|
val valid_ff = WireInit(Bool(),init=false.B)
|
||||||
|
val finish_ff = WireInit(Bool(),init=false.B)
|
||||||
|
val control_ff = WireInit(0.U(3.W))
|
||||||
|
val count_ff = WireInit(0.U(7.W))
|
||||||
|
val smallnum = WireInit(0.U(4.W))
|
||||||
|
val a_ff = WireInit(0.U(32.W))
|
||||||
|
val b_ff1 = WireInit(0.U(33.W))
|
||||||
|
val b_ff = WireInit(0.U(38.W))
|
||||||
|
val q_ff = WireInit(0.U(32.W))
|
||||||
|
val r_ff = WireInit(0.U(33.W))
|
||||||
|
val quotient_raw = WireInit(0.U(16.W))
|
||||||
|
val quotient_new = WireInit(0.U(4.W))
|
||||||
|
val shortq_enable = WireInit(Bool(),init=false.B)
|
||||||
|
val shortq_enable_ff = WireInit(Bool(),init=false.B)
|
||||||
|
val by_zero_case_ff = WireInit(Bool(),init=false.B)
|
||||||
|
val ar_shifted = WireInit(0.U(65.W))
|
||||||
|
val shortq_shift = WireInit(0.U(5.W))
|
||||||
|
val shortq_decode = WireInit(0.U(5.W))
|
||||||
|
val shortq_shift_ff = WireInit(0.U(5.W))
|
||||||
|
val valid_ff_in = io.valid_in & !io.cancel
|
||||||
|
val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
|
||||||
|
val dividend_sign_ff = control_ff(2)
|
||||||
|
val divisor_sign_ff = control_ff(1)
|
||||||
|
val rem_ff = control_ff(0)
|
||||||
|
val by_zero_case = valid_ff & (b_ff(31,0) === 0.U)
|
||||||
|
|
||||||
|
val smallnum_case = ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
|
||||||
|
((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
|
||||||
|
val running_state = count_ff.orR() | shortq_enable_ff
|
||||||
|
val misc_enable = io.valid_in | valid_ff | io.cancel | running_state | finish_ff
|
||||||
|
val finish_raw = smallnum_case | by_zero_case | (count_ff === 32.U)
|
||||||
|
val finish = finish_raw & !io.cancel
|
||||||
|
val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
|
||||||
|
val count_in = Fill(7,count_enable) & (count_ff + 4.U(7.W) + Cat(0.U(2.W),shortq_shift_ff))
|
||||||
|
val a_enable = io.valid_in | running_state
|
||||||
|
val a_shift = running_state & !shortq_enable_ff
|
||||||
|
ar_shifted := Cat (Fill(33,dividend_sign_ff),a_ff(31,0)) << shortq_shift_ff
|
||||||
|
val b_twos_comp = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
|
||||||
|
val twos_comp_b_sel = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
|
||||||
|
val twos_comp_q_sel = !valid_ff & !rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
|
||||||
|
val b_enable = io.valid_in | b_twos_comp
|
||||||
|
val rq_enable = io.valid_in | valid_ff | running_state
|
||||||
|
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
|
||||||
|
val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
|
||||||
|
|
||||||
|
val adder1_out = Cat(r_ff(30,0),a_ff(31,28)) + b_ff(34,0)
|
||||||
|
val adder2_out = Cat(r_ff(31,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U)
|
||||||
|
val adder3_out = Cat(r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U) + b_ff(36,0)
|
||||||
|
val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W))
|
||||||
|
val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff
|
||||||
|
val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U)
|
||||||
|
val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff
|
||||||
|
val adder8_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W))
|
||||||
|
val adder9_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + b_ff
|
||||||
|
val adder10_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U)
|
||||||
|
val adder11_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U) + b_ff
|
||||||
|
val adder12_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W))
|
||||||
|
val adder13_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff
|
||||||
|
val adder14_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U)
|
||||||
|
val adder15_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff
|
||||||
|
quotient_raw := Cat(
|
||||||
|
(!adder15_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder15_out === 0.U)),
|
||||||
|
(!adder14_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder14_out === 0.U)),
|
||||||
|
(!adder13_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder13_out === 0.U)),
|
||||||
|
(!adder12_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder12_out === 0.U)),
|
||||||
|
(!adder11_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder11_out === 0.U)),
|
||||||
|
(!adder10_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder10_out === 0.U)),
|
||||||
|
(!adder9_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder9_out === 0.U)),
|
||||||
|
(!adder8_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder8_out === 0.U)),
|
||||||
|
(!adder7_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder7_out === 0.U)),
|
||||||
|
(!adder6_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder6_out === 0.U)),
|
||||||
|
(!adder5_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder5_out === 0.U)),
|
||||||
|
(!adder4_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder4_out === 0.U)),
|
||||||
|
(!adder3_out(36) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder3_out === 0.U)),
|
||||||
|
(!adder2_out(35) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder2_out === 0.U)),
|
||||||
|
(!adder1_out(34) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder1_out === 0.U)), 0.U)
|
||||||
|
|
||||||
|
quotient_new := Cat(
|
||||||
|
((quotient_raw(15)===1.U) | Mux1H((8 to 14).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U))),
|
||||||
|
|
||||||
|
( quotient_raw(15,4) === "b000000000001".U(12.U))| ( quotient_raw(15,5) === "b00000000001".U(11.U)) | ( quotient_raw(15,6) === "b0000000001".U(10.U)) |
|
||||||
|
( quotient_raw(15,7) === "b000000001".U(9.U)) | ( quotient_raw(15,12)=== "b0001".U(4.U)) | ( quotient_raw(15,13)=== "b001".U(3.U)) |
|
||||||
|
( quotient_raw(15,14)=== "b01".U(2.U)) | ( quotient_raw(15) === "b1".U),
|
||||||
|
|
||||||
|
( quotient_raw(15,2) === "b00000000000001".U(14.U))| ( quotient_raw(15,3) === "b0000000000001".U(13.U)) | ( quotient_raw(15,6) === "b0000000001".U(10.U)) |
|
||||||
|
( quotient_raw(15,7) === "b0000000_01".U(9.U)) | ( quotient_raw(15,10)=== "b000001".U(6.U)) | ( quotient_raw(15,11)=== "b00001".U(5.U)) |
|
||||||
|
( quotient_raw(15,14)=== "b01".U(2.U)) | ( quotient_raw(15) === "b1".U),
|
||||||
|
|
||||||
|
((quotient_raw(15)===1.U) | Mux1H((1 to 13 by 2).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U))))
|
||||||
|
|
||||||
|
val twos_comp_in = Mux1H(Seq (
|
||||||
|
twos_comp_q_sel -> q_ff,
|
||||||
|
twos_comp_b_sel -> b_ff(31,0)
|
||||||
|
))
|
||||||
|
val twos_comp_out = rvtwoscomp(twos_comp_in)
|
||||||
|
val a_in = Mux1H(Seq (
|
||||||
|
(!a_shift & !shortq_enable_ff).asBool -> io.dividend_in(31,0),
|
||||||
|
a_shift -> Cat(a_ff(27,0),0.U(4.W)),
|
||||||
|
shortq_enable_ff -> ar_shifted(31,0)
|
||||||
|
))
|
||||||
|
val b_in = Mux1H(Seq (
|
||||||
|
!b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
|
||||||
|
b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
|
||||||
|
))
|
||||||
|
val r_in = Mux1H (Seq(
|
||||||
|
r_sign_sel -> Fill(33,1.U),
|
||||||
|
r_adder_sel(0) -> Cat(r_ff(28,0),a_ff(31,28)),
|
||||||
|
r_adder_sel(1) -> adder1_out(32,0),
|
||||||
|
r_adder_sel(2) -> adder2_out(32,0),
|
||||||
|
r_adder_sel(3) -> adder3_out(32,0),
|
||||||
|
r_adder_sel(4) -> adder4_out(32,0),
|
||||||
|
r_adder_sel(5) -> adder5_out(32,0),
|
||||||
|
r_adder_sel(6) -> adder6_out(32,0),
|
||||||
|
r_adder_sel(7) -> adder7_out(32,0),
|
||||||
|
r_adder_sel(8) -> adder8_out(32,0),
|
||||||
|
r_adder_sel(9) -> adder9_out(32,0),
|
||||||
|
r_adder_sel(10) -> adder10_out(32,0),
|
||||||
|
r_adder_sel(11) -> adder11_out(32,0),
|
||||||
|
r_adder_sel(12) -> adder12_out(32,0),
|
||||||
|
r_adder_sel(13) -> adder13_out(32,0),
|
||||||
|
r_adder_sel(14) -> adder14_out(32,0),
|
||||||
|
r_adder_sel(15) -> adder15_out(32,0),
|
||||||
|
shortq_enable_ff -> ar_shifted(64,32),
|
||||||
|
by_zero_case -> Cat(0.U,a_ff(31,0))
|
||||||
|
))
|
||||||
|
val q_in = Mux1H (Seq(
|
||||||
|
!valid_ff -> Cat(q_ff(27,0),quotient_new),
|
||||||
|
smallnum_case -> Cat(0.U(28.W),smallnum),
|
||||||
|
by_zero_case -> Fill(32,1.U)
|
||||||
|
))
|
||||||
|
io.valid_out := finish_ff & !io.cancel
|
||||||
|
io.data_out := Mux1H(Seq(
|
||||||
|
(!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
|
||||||
|
rem_ff -> r_ff(31,0),
|
||||||
|
twos_comp_q_sel -> twos_comp_out
|
||||||
|
))
|
||||||
|
def pat1(x : List[Int], y : List[Int]) = {
|
||||||
|
val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
|
||||||
|
val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
|
||||||
|
pat_a & pat_b
|
||||||
|
}
|
||||||
|
smallnum := Cat(
|
||||||
|
pat1(List(3),List(-3, -2, -1)),
|
||||||
|
|
||||||
|
pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
|
||||||
|
|
||||||
|
pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1)) | pat1(List(3),List(-3, -1))& !b_ff(0) |
|
||||||
|
pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0) |
|
||||||
|
pat1(List(3, 2),List(-3, 2, -1)) | pat1(List(3, 1),List(-3,-1)) | pat1(List(3, 2, 1),List(-3, 2)),
|
||||||
|
|
||||||
|
pat1(List(2, 1, 0),List(-3, -1)) | pat1(List(3, -2, 0),List(-3, 1, 0)) | pat1(List(2),List(-3, -1))& !b_ff(0) |
|
||||||
|
pat1(List(1),List(-3, -2))& !b_ff(0) | pat1(List(0),List(-3, -2, -1)) | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
|
||||||
|
pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0) | pat1(List(3, -2),List(-3, 2, 1)) |
|
||||||
|
pat1(List(-3, 2, 1),List(-3, 2, -1)) | pat1(List(-3, 2, 0),List(-3, -1)) | pat1(List(3, -2, -1),List(-3, 2, 0)) |
|
||||||
|
pat1(List(-2, 1, 0),List(-3, -2)) | pat1(List(3, 2),List(-1)) & !b_ff(0) | pat1(List(-3, 2, 1, 0),List(-3, 2)) |
|
||||||
|
pat1(List(3, 2),List(3, -2)) | pat1(List(3, 1),List(3,-2,-1)) | pat1(List(3, 0),List(-2, -1)) |
|
||||||
|
pat1(List(3, -1),List(-3, 2, 1, 0)) | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1)) |
|
||||||
|
pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) |
|
||||||
|
pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0))
|
||||||
|
|
||||||
|
|
||||||
|
val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0))
|
||||||
|
val a_enc = Module(new exu_div_cls)
|
||||||
|
a_enc.io.operand := shortq_dividend
|
||||||
|
val dw_a_enc1 = a_enc.io.cls
|
||||||
|
val b_enc = Module(new exu_div_cls)
|
||||||
|
b_enc.io.operand := b_ff(32,0)
|
||||||
|
val dw_b_enc1 = b_enc.io.cls
|
||||||
|
val dw_a_enc = Cat (0.U, dw_a_enc1)
|
||||||
|
val dw_b_enc = Cat (0.U, dw_b_enc1)
|
||||||
|
val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
|
||||||
|
val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
|
||||||
|
shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel
|
||||||
|
val list = Array(28,28,28,28,24,24,24,24,20,20,20,20,16,16,16,16,12,12,12,12,8,8,8,8,4,4,4,4,0,0,0,0)
|
||||||
|
shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
|
||||||
|
shortq_shift := Mux(!shortq_enable,0.U,shortq_decode)
|
||||||
|
b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
|
||||||
|
valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
|
||||||
|
control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode)
|
||||||
|
by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
|
||||||
|
shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
|
||||||
|
shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
|
||||||
|
finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
|
||||||
|
count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
|
||||||
|
|
||||||
|
a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
|
||||||
|
b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
|
||||||
|
r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
|
||||||
|
q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
|
||||||
|
|
||||||
}
|
}
|
||||||
// val valid_ff = WireInit(Bool(),init=false.B)
|
object div_main5 extends App {
|
||||||
// val finish_ff = WireInit(Bool(),init=false.B)
|
println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_4bit_fullshortq()))
|
||||||
// val control_ff = WireInit(0.U(3.W))
|
|
||||||
// val count_ff = WireInit(0.U(7.W))
|
|
||||||
// val smallnum = WireInit(0.U(4.W))
|
|
||||||
// val a_ff = WireInit(0.U(32.W))
|
|
||||||
// val b_ff1 = WireInit(0.U(33.W))
|
|
||||||
// val b_ff = WireInit(0.U(38.W))
|
|
||||||
// val q_ff = WireInit(0.U(32.W))
|
|
||||||
// val r_ff = WireInit(0.U(33.W))
|
|
||||||
// val quotient_raw = WireInit(0.U(16.W))
|
|
||||||
// val quotient_new = WireInit(0.U(4.W))
|
|
||||||
// val shortq_enable = WireInit(Bool(),init=false.B)
|
|
||||||
// val shortq_enable_ff = WireInit(Bool(),init=false.B)
|
|
||||||
// val by_zero_case_ff = WireInit(Bool(),init=false.B)
|
|
||||||
// val ar_shifted = WireInit(0.U(65.W))
|
|
||||||
// val shortq_shift = WireInit(0.U(5.W))
|
|
||||||
// val shortq_decode = WireInit(0.U(5.W))
|
|
||||||
// val shortq_shift_ff = WireInit(0.U(5.W))
|
|
||||||
// val valid_ff_in = io.valid_in & !io.cancel
|
|
||||||
// val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
|
|
||||||
// val dividend_sign_ff = control_ff(2)
|
|
||||||
// val divisor_sign_ff = control_ff(1)
|
|
||||||
// val rem_ff = control_ff(0)
|
|
||||||
// val by_zero_case = valid_ff & (b_ff(31,0) === 0.U)
|
|
||||||
//
|
|
||||||
// val smallnum_case = ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
|
|
||||||
// ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
|
|
||||||
// val running_state = count_ff.orR() | shortq_enable_ff
|
|
||||||
// val misc_enable = io.valid_in | valid_ff | io.cancel | running_state | finish_ff
|
|
||||||
// val finish_raw = smallnum_case | by_zero_case | (count_ff === 32.U)
|
|
||||||
// val finish = finish_raw & !io.cancel
|
|
||||||
// val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
|
|
||||||
// val count_in = Fill(7,count_enable) & (count_ff + 4.U(7.W) + Cat(0.U(2.W),shortq_shift_ff))
|
|
||||||
// val a_enable = io.valid_in | running_state
|
|
||||||
// val a_shift = running_state & !shortq_enable_ff
|
|
||||||
// ar_shifted := Cat (Fill(33,dividend_sign_ff),a_ff(31,0)) << shortq_shift_ff
|
|
||||||
// val b_twos_comp = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
|
|
||||||
// val twos_comp_b_sel = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
|
|
||||||
// val twos_comp_q_sel = !valid_ff & !rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
|
|
||||||
// val b_enable = io.valid_in | b_twos_comp
|
|
||||||
// val rq_enable = io.valid_in | valid_ff | running_state
|
|
||||||
// val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
|
|
||||||
//
|
|
||||||
// val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & ~shortq_enable_ff))
|
|
||||||
//
|
|
||||||
// val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
|
|
||||||
// val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
|
|
||||||
// val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
|
|
||||||
// val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
|
|
||||||
// val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
|
|
||||||
// val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
|
|
||||||
// val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
|
|
||||||
// quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
|
|
||||||
// (!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
|
|
||||||
// (!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
|
|
||||||
// (!adder4_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder4_out === 0.U)),
|
|
||||||
// (!adder3_out(35) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)),
|
|
||||||
// (!adder2_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)),
|
|
||||||
// (!adder1_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)), 0.U)
|
|
||||||
// quotient_new := Cat ((quotient_raw(7) | quotient_raw(6) | quotient_raw(5) | quotient_raw(4)),
|
|
||||||
// (quotient_raw(7) | quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))),
|
|
||||||
// (quotient_raw(7) | (!quotient_raw(6) & quotient_raw(5)) | (!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1))))
|
|
||||||
// val twos_comp_in = Mux1H(Seq (
|
|
||||||
// twos_comp_q_sel -> q_ff,
|
|
||||||
// twos_comp_b_sel -> b_ff(31,0)
|
|
||||||
// ))
|
|
||||||
// val twos_comp_out = rvtwoscomp(twos_comp_in)
|
|
||||||
// val a_in = Mux1H(Seq (
|
|
||||||
// (!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)),
|
|
||||||
// a_shift -> Cat(a_ff(29,0),0.U(3.W)),
|
|
||||||
// shortq_enable_ff -> ar_shifted(32,0)
|
|
||||||
// ))
|
|
||||||
// val b_in = Mux1H(Seq (
|
|
||||||
// !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
|
|
||||||
// b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
|
|
||||||
// ))
|
|
||||||
// val r_in = Mux1H (Seq(
|
|
||||||
// r_sign_sel -> Fill(33,1.U),
|
|
||||||
// r_restore_sel -> Cat(r_ff(29,0),a_ff(32,30)),
|
|
||||||
// r_adder1_sel -> adder1_out(32,0),
|
|
||||||
// r_adder2_sel -> adder2_out(32,0),
|
|
||||||
// r_adder3_sel -> adder3_out(32,0),
|
|
||||||
// r_adder4_sel -> adder4_out(32,0),
|
|
||||||
// r_adder5_sel -> adder5_out(32,0),
|
|
||||||
// r_adder6_sel -> adder6_out(32,0),
|
|
||||||
// r_adder7_sel -> adder7_out(32,0),
|
|
||||||
// shortq_enable_ff -> ar_shifted(65,33),
|
|
||||||
// by_zero_case -> Cat(0.U,a_ff(31,0))
|
|
||||||
// ))
|
|
||||||
// val q_in = Mux1H (Seq(
|
|
||||||
// !valid_ff -> Cat(q_ff(28,0),quotient_new),
|
|
||||||
// smallnum_case -> Cat(0.U(28.W),smallnum),
|
|
||||||
// by_zero_case -> Fill(32,1.U)
|
|
||||||
// ))
|
|
||||||
// io.valid_out := finish_ff & !io.cancel
|
|
||||||
// io.data_out := Mux1H(Seq(
|
|
||||||
// (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
|
|
||||||
// rem_ff -> r_ff(31,0),
|
|
||||||
// twos_comp_q_sel -> twos_comp_out
|
|
||||||
// ))
|
|
||||||
// def pat1(x : List[Int], y : List[Int]) = {
|
|
||||||
// val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
|
|
||||||
// val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
|
|
||||||
// pat_a & pat_b
|
|
||||||
// }
|
|
||||||
// smallnum := Cat(
|
|
||||||
// pat1(List(3),List(-3, -2, -1)),
|
|
||||||
//
|
|
||||||
// pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
|
|
||||||
//
|
|
||||||
// pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1)) | pat1(List(3),List(-3, -1))& !b_ff(0) |
|
|
||||||
// pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0) |
|
|
||||||
// pat1(List(3, 2),List(-3, 2, -1)) | pat1(List(3, 1),List(-3,-1)) | pat1(List(3, 2, 1),List(-3, 2)),
|
|
||||||
//
|
|
||||||
// pat1(List(2, 1, 0),List(-3, -1)) | pat1(List(3, -2, 0),List(-3, 1, 0)) | pat1(List(2),List(-3, -1))& !b_ff(0) |
|
|
||||||
// pat1(List(1),List(-3, -2))& !b_ff(0) | pat1(List(0),List(-3, -2, -1)) | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
|
|
||||||
// pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0) | pat1(List(3, -2),List(-3, 2, 1)) |
|
|
||||||
// pat1(List(-3, 2, 1),List(-3, 2, -1)) | pat1(List(-3, 2, 0),List(-3, -1)) | pat1(List(3, -2, -1),List(-3, 2, 0)) |
|
|
||||||
// pat1(List(-2, 1, 0),List(-3, -2)) | pat1(List(3, 2),List(-1)) & !b_ff(0) | pat1(List(-3, 2, 1, 0),List(-3, 2)) |
|
|
||||||
// pat1(List(3, 2),List(3, -2)) | pat1(List(3, 1),List(3,-2,-1)) | pat1(List(3, 0),List(-2, -1)) |
|
|
||||||
// pat1(List(3, -1),List(-3, 2, 1, 0)) | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1)) |
|
|
||||||
// pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) |
|
|
||||||
// pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0))
|
|
||||||
//
|
|
||||||
// val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0))
|
|
||||||
// val a_enc = Module(new exu_div_cls)
|
|
||||||
// a_enc.io.operand := shortq_dividend
|
|
||||||
// val dw_a_enc1 = a_enc.io.cls
|
|
||||||
// val b_enc = Module(new exu_div_cls)
|
|
||||||
// b_enc.io.operand := b_ff(32,0)
|
|
||||||
// val dw_b_enc1 = b_enc.io.cls
|
|
||||||
// val dw_a_enc = Cat (0.U, dw_a_enc1)
|
|
||||||
// val dw_b_enc = Cat (0.U, dw_b_enc1)
|
|
||||||
//
|
|
||||||
// val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
|
|
||||||
// val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
|
|
||||||
// shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel
|
|
||||||
// val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0)
|
|
||||||
// shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
|
|
||||||
// shortq_shift := Mux(!shortq_enable,0.U,shortq_decode)
|
|
||||||
// b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
|
|
||||||
// valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
|
|
||||||
// control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode)
|
|
||||||
// by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
|
|
||||||
// shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
|
|
||||||
// shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
|
|
||||||
// finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
|
|
||||||
// count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
|
|
||||||
//
|
|
||||||
// a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
|
|
||||||
// b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
|
|
||||||
// r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
|
|
||||||
// q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
|
|
||||||
//
|
|
||||||
//}
|
|
||||||
object div_main4 extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_3bit_fullshortq()))
|
|
||||||
}
|
}
|
||||||
|
|
||||||
class exu_div_cls extends Module{
|
class exu_div_cls extends Module{
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue