axi to ahb update
This commit is contained in:
Laraib Khan
parent
ea912f6dee
commit
cd13b88467
|
|
@ -21,7 +21,9 @@
|
|||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -33,13 +35,6 @@
|
|||
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
|
||||
|
|
@ -60,6 +55,24 @@
|
|||
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
|
||||
"sources":[
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
|
||||
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
|
||||
|
|
|
|||
1866
axi4_to_ahb.fir
1866
axi4_to_ahb.fir
File diff suppressed because it is too large
Load Diff
929
axi4_to_ahb.v
929
axi4_to_ahb.v
File diff suppressed because it is too large
Load Diff
|
|
@ -57,9 +57,17 @@ class axi4_to_ahb_IO extends Bundle with Config {
|
|||
|
||||
class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
|
||||
val io = IO(new axi4_to_ahb_IO)
|
||||
val buf_rst = WireInit(Bool(), init = false.B)
|
||||
val buf_state_en = WireInit(Bool(), init = false.B)
|
||||
val ahbm_clk = Wire(Clock())
|
||||
val ahbm_addr_clk = Wire(Clock())
|
||||
val ahbm_data_clk = Wire(Clock())
|
||||
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
|
||||
val buf_state = WireInit(idle)
|
||||
val buf_nxtstate = WireInit(idle)
|
||||
buf_state := withClock(ahbm_clk) {
|
||||
RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
|
||||
}
|
||||
//logic signals
|
||||
val slave_valid = WireInit(Bool(), init = false.B)
|
||||
val slave_ready = WireInit(Bool(), init = false.B)
|
||||
|
|
@ -99,7 +107,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
val buf_data = WireInit(0.U(64.W)) // [63:0]
|
||||
val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
|
||||
//Miscellaneous signals
|
||||
val buf_rst = WireInit(Bool(), init = false.B)
|
||||
// val buf_rst = WireInit(Bool(), init = false.B)
|
||||
val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0]
|
||||
val buf_addr_in = WireInit(0.U(32.W)) // [31:0]
|
||||
val buf_byteen_in = WireInit(0.U(8.W)) // [7:0]
|
||||
|
|
@ -108,7 +116,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
val buf_aligned_in = WireInit(Bool(), init = false.B)
|
||||
val buf_size_in = WireInit(0.U(3.W)) // [2:0]
|
||||
|
||||
val buf_state_en = WireInit(Bool(), init = false.B)
|
||||
// val buf_state_en = WireInit(Bool(), init = false.B)
|
||||
val buf_wr_en = WireInit(Bool(), init = false.B)
|
||||
val buf_data_wr_en = WireInit(Bool(), init = false.B)
|
||||
val slvbuf_error_en = WireInit(Bool(), init = false.B)
|
||||
|
|
@ -149,9 +157,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
val ahbm_data_clken = WireInit(Bool(), init = false.B)
|
||||
val buf_clk = Wire(Clock())
|
||||
//val slvbuf_clk = Wire(Clock())
|
||||
val ahbm_clk = Wire(Clock())
|
||||
val ahbm_addr_clk = Wire(Clock())
|
||||
val ahbm_data_clk = Wire(Clock())
|
||||
// val ahbm_clk = Wire(Clock())
|
||||
// val ahbm_addr_clk = Wire(Clock())
|
||||
// val ahbm_data_clk = Wire(Clock())
|
||||
|
||||
def get_write_size(byteen: UInt) = {
|
||||
|
||||
|
|
@ -217,10 +225,10 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
|
||||
//State machine
|
||||
io.ahb_htrans := 0.U
|
||||
//master_ready := 0.U
|
||||
master_ready := 1.U
|
||||
buf_state_en := false.B
|
||||
buf_nxtstate := idle
|
||||
buf_wr_en := 0.U
|
||||
//buf_wr_en := 0.U
|
||||
buf_data_wr_en := 0.U
|
||||
slvbuf_error_in := 0.U
|
||||
slvbuf_error_en := 0.U
|
||||
|
|
@ -236,11 +244,11 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
|
||||
switch(buf_state) {
|
||||
is(idle) {
|
||||
val master_ready = 1.U
|
||||
// master_ready := 1.U
|
||||
buf_write_in := (master_opc(2, 1) === "b01".U)
|
||||
val buf_nxtstate = Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
|
||||
buf_state_en := master_valid & master_ready
|
||||
buf_wr_en := buf_state_en
|
||||
buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
|
||||
buf_state_en := master_valid & 1.U
|
||||
// buf_wr_en := buf_state_en
|
||||
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
|
||||
buf_cmd_byte_ptr_en := buf_state_en
|
||||
// ---------------------FROM FUNCTION CHECK LATER
|
||||
|
|
@ -251,21 +259,21 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
}
|
||||
|
||||
is(cmd_rd) {
|
||||
val buf_nxtstate = Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
|
||||
buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
|
||||
buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
|
||||
cmd_done := buf_state_en & !master_valid
|
||||
slvbuf_wr_en := buf_state_en
|
||||
val master_ready = (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
|
||||
buf_wr_en := master_ready
|
||||
master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) === stream_rd) ////////////TBD////////
|
||||
// buf_wr_en := master_ready
|
||||
bypass_en := master_ready & master_valid
|
||||
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
|
||||
io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
|
||||
}
|
||||
|
||||
is(stream_rd) {
|
||||
val master_ready = (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
|
||||
buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
|
||||
val buf_nxtstate = Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
|
||||
master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
|
||||
// buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
|
||||
buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
|
||||
buf_state_en := (ahb_hready_q | ahb_hresp_q)
|
||||
buf_data_wr_en := buf_state_en
|
||||
slvbuf_error_in := ahb_hresp_q
|
||||
|
|
@ -275,7 +283,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
|
||||
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
|
||||
io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
|
||||
slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases
|
||||
slvbuf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // shifting the contents from the buf to slv_buf for streaming cases
|
||||
}
|
||||
|
||||
is(stream_err_rd) {
|
||||
|
|
@ -309,7 +317,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
|
||||
is(data_wr) {
|
||||
buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
|
||||
val master_ready = ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
|
||||
master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
|
||||
buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle))
|
||||
slvbuf_error_in := ahb_hresp_q
|
||||
slvbuf_error_en := buf_state_en
|
||||
|
|
@ -389,9 +397,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())
|
||||
}
|
||||
//sc
|
||||
buf_state := withClock(ahbm_clk) {
|
||||
RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
|
||||
}
|
||||
// buf_state := withClock(ahbm_clk) {
|
||||
// RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
|
||||
// }
|
||||
//s
|
||||
buf_write := withClock(buf_clk) {
|
||||
RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue