axi to ahb update
This commit is contained in:
Laraib Khan
parent
ea912f6dee
commit
cd13b88467
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@ -21,7 +21,9 @@
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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@ -33,13 +35,6 @@
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
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@ -60,6 +55,24 @@
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
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1864
axi4_to_ahb.fir
1864
axi4_to_ahb.fir
File diff suppressed because it is too large
Load Diff
919
axi4_to_ahb.v
919
axi4_to_ahb.v
File diff suppressed because it is too large
Load Diff
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@ -57,9 +57,17 @@ class axi4_to_ahb_IO extends Bundle with Config {
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class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
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val io = IO(new axi4_to_ahb_IO)
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val buf_rst = WireInit(Bool(), init = false.B)
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val buf_state_en = WireInit(Bool(), init = false.B)
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val ahbm_clk = Wire(Clock())
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val ahbm_addr_clk = Wire(Clock())
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val ahbm_data_clk = Wire(Clock())
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val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
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val buf_state = WireInit(idle)
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val buf_nxtstate = WireInit(idle)
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buf_state := withClock(ahbm_clk) {
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RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
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}
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//logic signals
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val slave_valid = WireInit(Bool(), init = false.B)
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val slave_ready = WireInit(Bool(), init = false.B)
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@ -99,7 +107,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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val buf_data = WireInit(0.U(64.W)) // [63:0]
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val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
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//Miscellaneous signals
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val buf_rst = WireInit(Bool(), init = false.B)
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// val buf_rst = WireInit(Bool(), init = false.B)
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val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0]
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val buf_addr_in = WireInit(0.U(32.W)) // [31:0]
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val buf_byteen_in = WireInit(0.U(8.W)) // [7:0]
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@ -108,7 +116,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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val buf_aligned_in = WireInit(Bool(), init = false.B)
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val buf_size_in = WireInit(0.U(3.W)) // [2:0]
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val buf_state_en = WireInit(Bool(), init = false.B)
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// val buf_state_en = WireInit(Bool(), init = false.B)
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val buf_wr_en = WireInit(Bool(), init = false.B)
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val buf_data_wr_en = WireInit(Bool(), init = false.B)
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val slvbuf_error_en = WireInit(Bool(), init = false.B)
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@ -149,9 +157,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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val ahbm_data_clken = WireInit(Bool(), init = false.B)
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val buf_clk = Wire(Clock())
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//val slvbuf_clk = Wire(Clock())
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val ahbm_clk = Wire(Clock())
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val ahbm_addr_clk = Wire(Clock())
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val ahbm_data_clk = Wire(Clock())
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// val ahbm_clk = Wire(Clock())
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// val ahbm_addr_clk = Wire(Clock())
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// val ahbm_data_clk = Wire(Clock())
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def get_write_size(byteen: UInt) = {
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@ -217,10 +225,10 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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//State machine
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io.ahb_htrans := 0.U
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//master_ready := 0.U
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master_ready := 1.U
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buf_state_en := false.B
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buf_nxtstate := idle
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buf_wr_en := 0.U
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//buf_wr_en := 0.U
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buf_data_wr_en := 0.U
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slvbuf_error_in := 0.U
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slvbuf_error_en := 0.U
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@ -236,11 +244,11 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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switch(buf_state) {
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is(idle) {
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val master_ready = 1.U
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// master_ready := 1.U
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buf_write_in := (master_opc(2, 1) === "b01".U)
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val buf_nxtstate = Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
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buf_state_en := master_valid & master_ready
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buf_wr_en := buf_state_en
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buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
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buf_state_en := master_valid & 1.U
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// buf_wr_en := buf_state_en
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buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
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buf_cmd_byte_ptr_en := buf_state_en
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// ---------------------FROM FUNCTION CHECK LATER
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@ -251,21 +259,21 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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}
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is(cmd_rd) {
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val buf_nxtstate = Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
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buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
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buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
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cmd_done := buf_state_en & !master_valid
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slvbuf_wr_en := buf_state_en
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val master_ready = (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
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buf_wr_en := master_ready
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master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) === stream_rd) ////////////TBD////////
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// buf_wr_en := master_ready
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bypass_en := master_ready & master_valid
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buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
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io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
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}
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is(stream_rd) {
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val master_ready = (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
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buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
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val buf_nxtstate = Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
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master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
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// buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
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buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
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buf_state_en := (ahb_hready_q | ahb_hresp_q)
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buf_data_wr_en := buf_state_en
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slvbuf_error_in := ahb_hresp_q
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@ -275,7 +283,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
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buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
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io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
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slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases
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slvbuf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // shifting the contents from the buf to slv_buf for streaming cases
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}
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is(stream_err_rd) {
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@ -309,7 +317,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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is(data_wr) {
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buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
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val master_ready = ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
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master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
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buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle))
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slvbuf_error_in := ahb_hresp_q
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slvbuf_error_en := buf_state_en
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@ -389,9 +397,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())
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}
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//sc
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buf_state := withClock(ahbm_clk) {
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RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
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}
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// buf_state := withClock(ahbm_clk) {
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// RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
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// }
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//s
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buf_write := withClock(buf_clk) {
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RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())
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