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el2_exu.anno.json

@@ -0,0 +1,131 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_exu|el2_exu>io_exu_div_wren",
+    "sources":[
+      "~el2_exu|el2_exu>io_dec_div_cancel"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_exu|el2_exu>io_exu_mp_fghr",
+    "sources":[
+      "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_exu|el2_exu>io_exu_lsu_rs1_d",
+    "sources":[
+      "~el2_exu|el2_exu>io_gpr_i0_rs1_d",
+      "~el2_exu|el2_exu>io_dec_extint_stall",
+      "~el2_exu|el2_exu>io_dec_tlu_meihap",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d",
+      "~el2_exu|el2_exu>io_exu_i0_result_x",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_exu|el2_exu>io_exu_flush_final",
+    "sources":[
+      "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
+      "~el2_exu|el2_exu>io_dec_i0_alu_decode_d",
+      "~el2_exu|el2_exu>io_i0_ap_jal",
+      "~el2_exu|el2_exu>io_i0_ap_predict_t",
+      "~el2_exu|el2_exu>io_i0_ap_predict_nt",
+      "~el2_exu|el2_exu>io_i0_ap_bge",
+      "~el2_exu|el2_exu>io_i0_ap_sub",
+      "~el2_exu|el2_exu>io_i0_ap_blt",
+      "~el2_exu|el2_exu>io_i0_ap_beq",
+      "~el2_exu|el2_exu>io_i0_ap_bne",
+      "~el2_exu|el2_exu>io_i0_ap_unsign",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_prett",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall",
+      "~el2_exu|el2_exu>io_gpr_i0_rs1_d",
+      "~el2_exu|el2_exu>io_gpr_i0_rs2_d",
+      "~el2_exu|el2_exu>io_dec_i0_immed_d",
+      "~el2_exu|el2_exu>io_dbg_cmd_wrdata",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
+      "~el2_exu|el2_exu>io_exu_i0_result_x",
+      "~el2_exu|el2_exu>io_dec_i0_pc_d",
+      "~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
+      "~el2_exu|el2_exu>io_dec_i0_select_pc_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_exu|el2_exu>io_exu_flush_path_final",
+    "sources":[
+      "~el2_exu|el2_exu>io_dec_tlu_flush_path_r",
+      "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
+      "~el2_exu|el2_exu>io_i0_ap_jal",
+      "~el2_exu|el2_exu>io_i0_ap_sub",
+      "~el2_exu|el2_exu>io_dec_i0_pc_d",
+      "~el2_exu|el2_exu>io_dec_i0_br_immed_d",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja",
+      "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall",
+      "~el2_exu|el2_exu>io_gpr_i0_rs2_d",
+      "~el2_exu|el2_exu>io_dec_i0_immed_d",
+      "~el2_exu|el2_exu>io_gpr_i0_rs1_d",
+      "~el2_exu|el2_exu>io_dbg_cmd_wrdata",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
+      "~el2_exu|el2_exu>io_exu_i0_result_x",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
+      "~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
+      "~el2_exu|el2_exu>io_dec_i0_select_pc_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d",
+    "sources":[
+      "~el2_exu|el2_exu>io_gpr_i0_rs2_d",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
+      "~el2_exu|el2_exu>io_dec_extint_stall",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
+      "~el2_exu|el2_exu>io_exu_i0_result_x",
+      "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d"
+    ]
+  },
+  {
+    "class":"logger.LogLevelAnnotation",
+    "globalLogLevel":{
+      
+    }
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"el2_exu.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_exu"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

src/main/scala/el2_dma_ctrl.scala

@@ -1,4 +1,3 @@
-package dma
 import chisel3._
 import chisel3.util._
 import scala.collection._

src/main/scala/el2_swerv.scala

@@ -0,0 +1,662 @@
+import chisel3._
+import chisel3.util._
+import ifu._
+import dec._
+import exu._
+import lsu._
+import lib._
+import include._
+import dmi._
+import dbg._
+
+class el2_swerv extends Module with RequireAsyncReset with el2_lib {
+  val io = IO (new Bundle{
+    val dbg_rst_l = Input(Bool())
+    val rst_vec = Input(UInt(31.W))
+    val nmi_int = Input(Bool())
+    val nmi_vec = Input(UInt(31.W))
+    val core_rst_l = Output(Bool())
+    val trace_rv_i_insn_ip = Output(UInt(32.W))
+    val trace_rv_i_address_ip = Output(UInt(32.W))
+    val trace_rv_i_valid_ip = Output(UInt(2.W))
+    val trace_rv_i_exception_ip = Output(UInt(2.W))
+    val trace_rv_i_ecause_ip = Output(UInt(5.W))
+    val trace_rv_i_interrupt_ip = Output(UInt(2.W))
+    val trace_rv_i_tval_ip = Output(UInt(32.W))
+    val dccm_clk_override = Output(Bool())
+    val icm_clk_override = Output(Bool())
+    val dec_tlu_core_ecc_disable = Output(Bool())
+    val i_cpu_halt_req = Input(Bool())
+    val i_cpu_run_req = Input(Bool())
+    val o_cpu_halt_ack = Output(Bool())
+    val o_cpu_halt_status = Output(Bool())
+    val o_cpu_run_ack = Output(Bool())
+    val o_debug_mode_status = Output(Bool())
+    val core_id = Input(UInt(28.W))
+    val mpc_debug_halt_req = Input(Bool())
+    val mpc_debug_run_req = Input(Bool())
+    val mpc_reset_run_req = Input(Bool())
+    val mpc_debug_halt_ack = Output(Bool())
+    val mpc_debug_run_ack = Output(Bool())
+    val debug_brkpt_status = Output(Bool())
+    val dec_tlu_perfcnt0 = Output(Bool())
+    val dec_tlu_perfcnt1 = Output(Bool())
+    val dec_tlu_perfcnt2 = Output(Bool())
+    val dec_tlu_perfcnt3 = Output(Bool())
+    val dccm_wren = Output(Bool())
+    val dccm_rden = Output(Bool())
+    val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
+    val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
+    val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
+    val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
+
+    val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
+    val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
+    val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
+    val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
+
+    val iccm_rw_addr = Output(UInt(ICCM_BITS.W))
+    val iccm_wren = Output(Bool())
+    val iccm_rden = Output(Bool())
+    val iccm_wr_size = Output(UInt(3.W))
+    val iccm_wr_data = Output(UInt(78.W))
+    val iccm_buf_correct_ecc = Output(Bool())
+    val iccm_correction_state = Output(Bool())
+
+    val iccm_rd_data = Input(UInt(64.W))
+    val iccm_rd_data_ecc = Input(UInt(78.W))
+
+    val ic_rw_addr = Output(UInt(31.W))
+    val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_en = Output(Bool())
+    val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
+    val ic_rd_data = Input(UInt(64.W))
+    val ic_debug_rd_data = Input(UInt(71.W))
+    val ictag_debug_rd_data = Input(UInt(26.W))
+    val ic_debug_wr_data = Output(UInt(71.W))
+
+    val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
+    val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
+    val ic_premux_data = Output(UInt(64.W))
+    val ic_sel_premux_data = Output(Bool())
+
+    val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
+    val ic_debug_rd_en = Output(Bool())
+    val ic_debug_wr_en = Output(Bool())
+    val ic_debug_tag_array = Output(Bool())
+    val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_perr = Input(Bool())
+
+    // AXI Signals
+    val lsu_axi_awvalid = Output(Bool())
+    val lsu_axi_awready = Input(Bool())
+    val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
+    val lsu_axi_awaddr = Output(UInt(32.W))
+    val lsu_axi_awregion = Output(UInt(4.W))
+    val lsu_axi_awlen = Output(UInt(8.W))
+    val lsu_axi_awsize = Output(UInt(3.W))
+    val lsu_axi_awburst = Output(UInt(2.W))
+    val lsu_axi_awlock = Output(Bool())
+    val lsu_axi_awcache = Output(UInt(4.W))
+    val lsu_axi_awprot = Output(UInt(3.W))
+    val lsu_axi_awqos = Output(UInt(4.W))
+    val lsu_axi_wvalid = Output(Bool())
+    val lsu_axi_wready = Input(Bool())
+    val lsu_axi_wdata = Output(UInt(64.W))
+    val lsu_axi_wstrb = Output(UInt(8.W))
+    val lsu_axi_wlast = Output(Bool())
+    val lsu_axi_bvalid = Input(Bool())
+    val lsu_axi_bready = Output(Bool())
+    val lsu_axi_bresp = Input(UInt(2.W))
+    val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
+
+
+    val lsu_axi_arvalid = Output(Bool())
+    val lsu_axi_arready = Input(Bool())
+    val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
+    val lsu_axi_araddr = Output(UInt(32.W))
+    val lsu_axi_arregion = Output(UInt(4.W))
+    val lsu_axi_arlen = Output(UInt(8.W))
+    val lsu_axi_arsize = Output(UInt(3.W))
+    val lsu_axi_arburst = Output(UInt(2.W))
+    val lsu_axi_arlock = Output(Bool())
+    val lsu_axi_arcache = Output(UInt(4.W))
+    val lsu_axi_arprot = Output(UInt(3.W))
+    val lsu_axi_arqos = Output(UInt(4.W))
+    val lsu_axi_rvalid = Input(Bool())
+    val lsu_axi_rready = Output(Bool())
+    val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
+    val lsu_axi_rdata = Input(UInt(64.W))
+    val lsu_axi_rresp = Input(UInt(2.W))
+    val lsu_axi_rlast = Input(Bool())
+
+
+    // AXI IFU Signals
+    val ifu_axi_awvalid = Output(Bool())
+    val ifu_axi_awready = Input(Bool())
+    val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
+    val ifu_axi_awaddr = Output(UInt(32.W))
+    val ifu_axi_awregion = Output(UInt(4.W))
+    val ifu_axi_awlen = Output(UInt(8.W))
+    val ifu_axi_awsize = Output(UInt(3.W))
+    val ifu_axi_awburst = Output(UInt(2.W))
+    val ifu_axi_awlock = Output(Bool())
+    val ifu_axi_awcache = Output(UInt(4.W))
+    val ifu_axi_awprot = Output(UInt(3.W))
+    val ifu_axi_awqos = Output(UInt(4.W))
+    val ifu_axi_wvalid = Output(Bool())
+    val ifu_axi_wready = Output(Bool())
+    val ifu_axi_wdata = Input(UInt(64.W))
+    val ifu_axi_wstrb = Output(UInt(8.W))
+    val ifu_axi_wlast = Output(Bool())
+    val ifu_axi_bvalid = Input(Bool())
+    val ifu_axi_bready = Output(Bool())
+    val ifu_axi_bresp = Input(UInt(2.W))
+    val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
+    val ifu_axi_arvalid = Output(Bool())
+    val ifu_axi_arready = Output(Bool())
+    val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
+    val ifu_axi_araddr = Output(UInt(32.W))
+    val ifu_axi_arregion = Output(UInt(4.W))
+    val ifu_axi_arlen = Output(UInt(8.W))
+    val ifu_axi_arsize = Output(UInt(3.W))
+    val ifu_axi_arburst = Output(UInt(2.W))
+    val ifu_axi_arlock = Output(Bool())
+    val ifu_axi_arcache = Output(UInt(4.W))
+    val ifu_axi_arprot = Output(UInt(3.W))
+    val ifu_axi_arqos = Output(UInt(4.W))
+    val ifu_axi_rvalid = Input(Bool())
+    val ifu_axi_rready = Output(Bool())
+    val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
+    val ifu_axi_rdata = Input(UInt(64.W))
+    val ifu_axi_rresp = Input(UInt(2.W))
+    val ifu_axi_rlast = Input(Bool())
+
+    // SB AXI Signals
+    val sb_axi_awvalid = Output(Bool())
+    val sb_axi_awready = Input(Bool())
+    val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
+    val sb_axi_awaddr = Output(UInt(32.W))
+    val sb_axi_awregion = Output(UInt(4.W))
+    val sb_axi_awlen = Output(UInt(8.W))
+    val sb_axi_awsize = Output(UInt(3.W))
+    val sb_axi_awburst = Output(UInt(2.W))
+    val sb_axi_awlock = Output(Bool())
+    val sb_axi_awcache = Output(UInt(4.W))
+    val sb_axi_awprot = Output(UInt(3.W))
+    val sb_axi_awqos = Output(UInt(4.W))
+    val sb_axi_wvalid = Output(Bool())
+    val sb_axi_wready = Input(Bool())
+    val sb_axi_wdata = Output(UInt(64.W))
+    val sb_axi_wstrb = Output(UInt(8.W))
+    val sb_axi_wlast = Output(Bool())
+    val sb_axi_bvalid = Input(Bool())
+    val sb_axi_bready = Output(Bool())
+    val sb_axi_bresp = Input(UInt(2.W))
+    val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
+    val sb_axi_arvalid = Output(Bool())
+    val sb_axi_arready = Input(Bool())
+    val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
+    val sb_axi_araddr = Output(UInt(32.W))
+    val sb_axi_arregion = Output(UInt(4.W))
+    val sb_axi_arlen = Output(UInt(8.W))
+    val sb_axi_arsize = Output(UInt(3.W))
+    val sb_axi_arburst = Output(UInt(2.W))
+    val sb_axi_arlock = Output(Bool())
+    val sb_axi_arcache = Output(UInt(4.W))
+    val sb_axi_arprot = Output(UInt(3.W))
+    val sb_axi_arqos = Output(UInt(4.W))
+    val sb_axi_rvalid = Input(Bool())
+    val sb_axi_rready = Output(Bool())
+    val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
+    val sb_axi_rdata = Input(UInt(64.W))
+    val sb_axi_rresp = Input(UInt(2.W))
+    val sb_axi_rlast = Input(Bool())
+    // DMA signals
+    val dma_axi_awvalid       = Input(Bool())
+    val dma_axi_awready       = Output(Bool())
+    val dma_axi_awid          = Input(UInt(DMA_BUS_TAG.W))
+    val dma_axi_awaddr        = Input(UInt(32.W))
+    val dma_axi_awsize        = Input(UInt(3.W))
+    val dma_axi_awprot        = Input(UInt(3.W))
+    val dma_axi_awlen = Input(UInt(8.W))
+    val dma_axi_awburst = Input(UInt(2.W))
+    val dma_axi_wvalid        = Input(Bool())
+    val dma_axi_wready        = Output(Bool())
+    val dma_axi_wdata         = Input(UInt(64.W))
+    val dma_axi_wstrb         = Input(UInt(8.W))
+    val dma_axi_wlast   = Input(Bool())
+    val dma_axi_bvalid        = Output(Bool())
+    val dma_axi_bready        = Input(Bool())
+    val dma_axi_bresp         = Output(UInt(2.W))
+    val dma_axi_bid           = Output(UInt(DMA_BUS_TAG.W))
+
+    // AXI Read Channels
+    val dma_axi_arvalid       = Input(Bool())
+    val dma_axi_arready       = Output(Bool())
+    val dma_axi_arid          = Input(UInt(DMA_BUS_TAG.W))
+
+    val dma_axi_araddr        = Input(UInt(32.W))
+    val dma_axi_arsize        = Input(UInt(3.W))
+
+    val dma_axi_arprot = Input(UInt(3.W))
+    val dma_axi_arlen = Input(UInt(8.W))
+    val dma_axi_arburst = Input(UInt(2.W))
+    val dma_axi_rvalid        = Output(Bool())
+    val dma_axi_rready        = Input(Bool())
+
+    val dma_axi_rid           = Output(UInt(DMA_BUS_TAG.W))
+    val dma_axi_rdata         = Output(UInt(64.W))
+    val dma_axi_rresp         = Output(UInt(2.W))
+    val dma_axi_rlast         = Output(Bool())
+
+    // AHB Lite Bus
+    val haddr = Output(UInt(32.W))
+    val hburst = Output(UInt(3.W))
+    val hmastlock = Output(Bool())
+    val hprot = Output(UInt(4.W))
+    val hsize = Output(UInt(3.W))
+    val htrans = Output(UInt(2.W))
+    val hwrite = Output(Bool())
+    val hrdata = Input(UInt(64.W))
+    val hready = Input(Bool())
+    val hresp = Input(Bool())
+
+    // AHB Master
+    val lsu_haddr = Output(UInt(32.W))
+    val lsu_hburst = Output(UInt(3.W))
+    val lsu_hmastlock = Output(Bool())
+    val lsu_hprot = Output(UInt(4.W))
+    val lsu_hsize = Output(UInt(3.W))
+    val lsu_htrans = Output(UInt(2.W))
+    val lsu_hwrite = Output(Bool())
+    val lsu_hwdata = Output(UInt(64.W))
+    val lsu_hrdata = Input(UInt(64.W))
+    val lsu_hready = Input(Bool())
+    val lsu_hresp = Input(Bool())
+
+    // System Bus Debug Master
+    val sb_haddr = Output(UInt(32.W))
+    val sb_hburst = Output(UInt(3.W))
+    val sb_hmastlock = Output(Bool())
+    val sb_hprot = Output(UInt(4.W))
+    val sb_hsize = Output(UInt(3.W))
+    val sb_htrans = Output(UInt(2.W))
+    val sb_hwrite = Output(Bool())
+    val sb_hwdata = Output(UInt(64.W))
+    val sb_hrdata = Input(UInt(64.W))
+    val sb_hready = Input(Bool())
+    val sb_hresp = Input(Bool())
+
+    // DMA slave
+    val dma_hsel = Input(Bool())
+    val dma_haddr = Input(UInt(32.W))
+    val dma_hburst = Input(UInt(3.W))
+    val dma_hmastlock = Input(Bool())
+    val dma_hprot = Input(UInt(4.W))
+    val dma_hsize = Input(UInt(3.W))
+    val dma_htrans = Input(UInt(2.W))
+    val dma_hwrite = Input(Bool())
+    val dma_hwdata = Input(UInt(64.W))
+    val dma_hreadyin = Input(Bool())
+    val dma_hrdata = Output(UInt(64.W))
+    val dma_hreadyout = Output(Bool())
+    val dma_hresp = Output(Bool())
+    val lsu_bus_clk_en = Input(Bool())
+    val ifu_bus_clk_en = Input(Bool())
+    val dbg_bus_clk_en = Input(Bool())
+    val dma_bus_clk_en = Input(Bool())
+    val dmi_reg_en = Input(Bool())
+    val dmi_reg_addr = Input(UInt(7.W))
+    val dmi_reg_wr_en = Input(Bool())
+    val dmi_reg_wdata = Input(UInt(32.W))
+    val dmi_reg_rdata = Output(UInt(32.W))
+    val dmi_hard_reset = Input(Bool())
+    val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
+    val timer_int = Input(Bool())
+    val soft_int = Input(Bool())
+    val scan_mode = Input(Bool())
+  })
+
+
+  val ifu = Module(new el2_ifu)
+  val dec = Module(new el2_dec)
+  val dbg = Module(new el2_dbg)
+  val exu = Module(new el2_exu)
+  val lsu = Module(new el2_lsu)
+  val pic_ctl_inst = Module(new el2_pic_ctrl)
+  val dma_ctrl = Module(new el2_dma_ctrl)
+  val lsu_axi4_to_ahb = Module(new axi4_to_ahb)
+  val ifu_axi4_to_ahb = Module(new axi4_to_ahb)
+  val sb_axi4_to_ahb = Module(new axi4_to_ahb)
+
+  val core_reset = (!(reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode))).asAsyncReset()
+  val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
+  val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
+  val active_clk = rvclkhdr(clock, active_state, io.scan_mode)
+  val core_dbg_cmd_done = dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
+  val core_dbg_cmd_fail = dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
+  val core_dbg_rddata = Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
+
+  // AHB to AXI-4 still remaining
+
+
+  // Lets start with IFU
+  ifu.reset := core_reset
+  ifu.io.free_clk := free_clk
+  ifu.io.active_clk := active_clk
+  ifu.io.dec_i0_decode_d := dec.io.dec_i0_decode_d
+  ifu.io.exu_flush_final := dec.io.exu_flush_final
+  ifu.io.dec_tlu_i0_commit_cmt := dec.io.dec_tlu_i0_commit_cmt
+  ifu.io.dec_tlu_flush_err_wb := dec.io.dec_tlu_flush_err_r
+  ifu.io.dec_tlu_flush_noredir_wb := dec.io.dec_tlu_flush_noredir_r
+  ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
+  ifu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
+  ifu.io.dec_tlu_fence_i_wb := dec.io.dec_tlu_fence_i_r
+  ifu.io.dec_tlu_flush_leak_one_wb := dec.io.dec_tlu_flush_leak_one_r
+  ifu.io.dec_tlu_bpred_disable := dec.io.dec_tlu_bpred_disable
+  ifu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
+  ifu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt
+  ifu.io.ifu_axi_arready := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_arready)
+  ifu.io.ifu_axi_rvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rvalid)
+  ifu.io.ifu_axi_rid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rid)
+  ifu.io.ifu_axi_rdata := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rdata)
+  ifu.io.ifu_axi_rresp := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rresp)
+  ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
+  ifu.io.dma_iccm_req := dma_ctrl.io.dma_iccm_req
+  ifu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr
+  ifu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz
+  ifu.io.dma_mem_write := dma_ctrl.io.dma_mem_write
+  ifu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata
+  ifu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag
+  ifu.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any
+  ifu.io.ic_rd_data := io.ic_rd_data
+  ifu.io.ic_debug_rd_data := io.ic_debug_rd_data
+  ifu.io.ictag_debug_rd_data := io.ictag_debug_rd_data
+  ifu.io.ic_eccerr := io.ic_eccerr
+  ifu.io.ic_parerr := io.ic_parerr
+  ifu.io.ic_rd_hit := io.ic_rd_hit
+  ifu.io.ic_tag_perr := io.ic_tag_perr
+  ifu.io.iccm_rd_data := io.iccm_rd_data
+  ifu.io.exu_mp_pkt <> exu.io.exu_mp_pkt
+  ifu.io.exu_mp_eghr := exu.io.exu_mp_eghr
+  ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr
+  ifu.io.exu_mp_index := exu.io.exu_mp_index
+  ifu.io.exu_mp_btag := exu.io.exu_mp_btag
+  ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt
+  ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r
+  ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r
+  ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r
+  ifu.io.dec_tlu_ic_diag_pkt <> dec.io.dec_tlu_ic_diag_pkt
+
+  // Lets start with Dec
+  dec.reset := core_reset
+  dec.io.free_clk := free_clk
+  dec.io.active_clk := active_clk
+  dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
+  dec.io.rst_vec := io.rst_vec
+  dec.io.nmi_int := io.nmi_int
+  dec.io.nmi_vec := io.nmi_vec
+  dec.io.i_cpu_halt_req := io.i_cpu_halt_req
+  dec.io.i_cpu_run_req := io.i_cpu_run_req
+  dec.io.core_id := io.core_id
+  dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
+  dec.io.mpc_debug_run_req := io.mpc_debug_run_req
+  dec.io.mpc_reset_run_req := io.mpc_reset_run_req
+  dec.io.exu_pmu_i0_br_misp := exu.io.exu_pmu_i0_br_misp
+  dec.io.exu_pmu_i0_br_ataken := exu.io.exu_pmu_i0_br_ataken
+  dec.io.exu_pmu_i0_pc4 := exu.io.exu_pmu_i0_pc4
+  dec.io.lsu_nonblock_load_valid_m := lsu.io.lsu_nonblock_load_valid_m
+  dec.io.lsu_nonblock_load_tag_m := lsu.io.lsu_nonblock_load_tag_m
+  dec.io.lsu_nonblock_load_inv_r := lsu.io.lsu_nonblock_load_inv_r
+  dec.io.lsu_nonblock_load_inv_tag_r := lsu.io.lsu_nonblock_load_inv_tag_r
+  dec.io.lsu_nonblock_load_data_valid := lsu.io.lsu_nonblock_load_data_valid
+  dec.io.lsu_nonblock_load_data_error := lsu.io.lsu_nonblock_load_data_error
+  dec.io.lsu_nonblock_load_data_tag := lsu.io.lsu_nonblock_load_data_tag
+  dec.io.lsu_nonblock_load_data := lsu.io.lsu_nonblock_load_data
+  dec.io.lsu_pmu_bus_trxn := lsu.io.lsu_pmu_bus_trxn
+  dec.io.lsu_pmu_bus_misaligned := lsu.io.lsu_pmu_bus_misaligned
+  dec.io.lsu_pmu_bus_error := lsu.io.lsu_pmu_bus_error
+  dec.io.lsu_pmu_bus_busy := lsu.io.lsu_pmu_bus_busy
+  dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
+  dec.io.lsu_pmu_load_external_m := lsu.io.lsu_pmu_load_external_m
+  dec.io.lsu_pmu_store_external_m := lsu.io.lsu_pmu_store_external_m
+  dec.io.dma_pmu_dccm_read := dma_ctrl.io.dma_pmu_dccm_read
+  dec.io.dma_pmu_dccm_write := dma_ctrl.io.dma_pmu_dccm_write
+  dec.io.dma_pmu_any_read := dma_ctrl.io.dma_pmu_any_read
+  dec.io.dma_pmu_any_write := dma_ctrl.io.dma_pmu_any_write
+  dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
+  dec.io.lsu_fir_error := lsu.io.lsu_fir_error
+  dec.io.ifu_pmu_instr_aligned := ifu.io.ifu_pmu_instr_aligned
+  dec.io.ifu_pmu_fetch_stall := ifu.io.ifu_pmu_fetch_stall
+  dec.io.ifu_pmu_ic_miss := ifu.io.ifu_pmu_ic_miss
+  dec.io.ifu_pmu_ic_hit := ifu.io.ifu_pmu_ic_hit
+  dec.io.ifu_pmu_bus_error := ifu.io.ifu_pmu_bus_error
+  dec.io.ifu_pmu_bus_busy := ifu.io.ifu_pmu_bus_busy
+  dec.io.ifu_pmu_bus_trxn := ifu.io.ifu_pmu_bus_trxn
+  dec.io.ifu_ic_error_start := ifu.io.ifu_ic_error_start
+  dec.io.ifu_iccm_rd_ecc_single_err := ifu.io.ifu_iccm_rd_ecc_single_err
+  dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
+  dec.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid
+  dec.io.dbg_cmd_write := dbg.io.dbg_cmd_write
+  dec.io.dbg_cmd_type := dbg.io.dbg_cmd_type
+  dec.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr
+  dec.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
+  dec.io.ifu_i0_icaf := ifu.io.ifu_i0_icaf
+  dec.io.ifu_i0_icaf_type := ifu.io.ifu_i0_icaf_type
+  dec.io.ifu_i0_icaf_f1 := ifu.io.ifu_i0_icaf_f1
+  dec.io.ifu_i0_dbecc := ifu.io.ifu_i0_dbecc
+  dec.io.lsu_idle_any := lsu.io.lsu_idle_any
+  dec.io.i0_brp := ifu.io.i0_brp
+  dec.io.ifu_i0_bp_index := ifu.io.ifu_i0_bp_index
+  dec.io.ifu_i0_bp_fghr := ifu.io.ifu_i0_bp_fghr
+  dec.io.ifu_i0_bp_btag := ifu.io.ifu_i0_bp_btag
+  dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
+  dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
+  dec.io.lsu_imprecise_error_load_any := lsu.io.lsu_imprecise_error_load_any
+  dec.io.lsu_imprecise_error_store_any := lsu.io.lsu_imprecise_error_store_any
+  dec.io.lsu_imprecise_error_addr_any := lsu.io.lsu_imprecise_error_addr_any
+  dec.io.exu_div_result := exu.io.exu_div_result
+  dec.io.exu_div_wren := exu.io.exu_div_wren
+  dec.io.exu_csr_rs1_x := exu.io.exu_csr_rs1_x
+  dec.io.lsu_result_m := lsu.io.lsu_result_m
+  dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
+  dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
+  dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
+  dec.io.dma_dccm_stall_any := dma_ctrl.io.dma_dccm_stall_any
+  dec.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any
+  dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
+  dec.io.exu_flush_final := exu.io.exu_flush_final
+  dec.io.exu_npc_r := exu.io.exu_npc_r
+  dec.io.exu_i0_result_x := exu.io.exu_i0_result_x
+  dec.io.ifu_i0_valid := ifu.io.ifu_i0_valid
+  dec.io.ifu_i0_instr := ifu.io.ifu_i0_instr
+  dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc
+  dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4
+  dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x
+  dec.io.mexintpend := pic_ctl_inst.io.mexintpend
+  dec.io.soft_int := io.soft_int
+  dec.io.pic_claimid := pic_ctl_inst.io.claimid
+  dec.io.pic_pl := pic_ctl_inst.io.pl
+  dec.io.mhwakeup := pic_ctl_inst.io.mhwakeup
+  dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data
+  dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid
+  dec.io.dbg_halt_req := dbg.io.dbg_halt_req
+  dec.io.dbg_resume_req := dbg.io.dbg_resume_req
+  dec.io.ifu_miss_state_idle := ifu.io.ifu_miss_state_idle
+  dec.io.exu_i0_br_hist_r := exu.io.exu_i0_br_hist_r
+  dec.io.exu_i0_br_error_r := exu.io.exu_i0_br_error_r
+  dec.io.exu_i0_br_start_error_r := exu.io.exu_i0_br_start_error_r
+  dec.io.exu_i0_br_valid_r := exu.io.exu_i0_br_valid_r
+  dec.io.exu_i0_br_mp_r := exu.io.exu_i0_br_mp_r
+  dec.io.exu_i0_br_middle_r := exu.io.exu_i0_br_middle_r
+  dec.io.exu_i0_br_way_r := exu.io.exu_i0_br_way_r
+  dec.io.ifu_i0_cinst := ifu.io.ifu_i0_cinst
+  dec.io.scan_mode := io.scan_mode
+
+  // EXU lets go
+  exu.reset := core_reset
+  exu.io.scan_mode := io.scan_mode
+  exu.io.dec_data_en := dec.io.dec_data_en
+  exu.io.dec_ctl_en := dec.io.dec_ctl_en
+  exu.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
+  exu.io.i0_ap := dec.io.i0_ap
+  exu.io.dec_debug_wdata_rs1_d := dec.io.dec_debug_wdata_rs1_d
+  exu.io.dec_i0_predict_p_d <> dec.io.dec_i0_predict_p_d
+  exu.io.i0_predict_fghr_d := dec.io.i0_predict_fghr_d
+  exu.io.i0_predict_index_d := dec.io.i0_predict_index_d
+  exu.io.i0_predict_btag_d := dec.io.i0_predict_btag_d
+  exu.io.dec_i0_rs1_en_d := dec.io.dec_i0_rs1_en_d
+  exu.io.dec_i0_rs2_en_d := dec.io.dec_i0_rs2_en_d
+  exu.io.gpr_i0_rs1_d := dec.io.gpr_i0_rs1_d
+  exu.io.gpr_i0_rs2_d := dec.io.gpr_i0_rs2_d
+  exu.io.dec_i0_immed_d := dec.io.dec_i0_immed_d
+  exu.io.dec_i0_rs1_bypass_data_d := dec.io.dec_i0_rs1_bypass_data_d
+  exu.io.dec_i0_rs2_bypass_data_d := dec.io.dec_i0_rs2_bypass_data_d
+  exu.io.dec_i0_br_immed_d := dec.io.dec_i0_br_immed_d
+  exu.io.dec_i0_alu_decode_d := dec.io.dec_i0_alu_decode_d
+  exu.io.dec_i0_select_pc_d := dec.io.dec_i0_select_pc_d
+  exu.io.dec_i0_pc_d := dec.io.dec_i0_pc_d
+  exu.io.dec_i0_rs1_bypass_en_d := dec.io.dec_i0_rs1_bypass_en_d
+  exu.io.dec_i0_rs2_bypass_en_d := dec.io.dec_i0_rs2_bypass_en_d
+  exu.io.dec_csr_ren_d := dec.io.dec_csr_ren_d
+  exu.io.mul_p <> dec.io.mul_p
+  exu.io.div_p <> dec.io.div_p
+  exu.io.dec_div_cancel := dec.io.dec_div_cancel
+  exu.io.pred_correct_npc_x := dec.io.pred_correct_npc_x
+  exu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r
+  exu.io.dec_tlu_flush_path_r := dec.io.dec_tlu_flush_path_r
+  exu.io.dec_extint_stall := dec.io.dec_extint_stall
+  exu.io.dec_tlu_meihap := dec.io.dec_tlu_meihap
+
+
+  // LSU Lets go
+  lsu.reset := core_reset
+  lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
+  lsu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r
+  lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
+  lsu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt
+  lsu.io.dec_tlu_external_ldfwd_disable := dec.io.dec_tlu_external_ldfwd_disable
+  lsu.io.dec_tlu_wb_coalescing_disable := dec.io.dec_tlu_wb_coalescing_disable
+  lsu.io.dec_tlu_sideeffect_posted_disable := dec.io.dec_tlu_sideeffect_posted_disable
+  lsu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
+  lsu.io.exu_lsu_rs1_d := exu.io.exu_lsu_rs1_d
+  lsu.io.exu_lsu_rs2_d := exu.io.exu_lsu_rs2_d
+  lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
+  lsu.io.lsu_p <> dec.io.lsu_p
+  lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
+  lsu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
+  lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
+  lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo
+  lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi
+  lsu.io.lsu_axi_awready := io.lsu_axi_awready
+  lsu.io.lsu_axi_wready := io.lsu_axi_wready
+  lsu.io.lsu_axi_bvalid := io.lsu_axi_bvalid
+  lsu.io.lsu_axi_bresp := io.lsu_axi_bresp
+  lsu.io.lsu_axi_bid := io.lsu_axi_bid
+  lsu.io.lsu_axi_arready := io.lsu_axi_arready
+  lsu.io.lsu_axi_rvalid := io.lsu_axi_rvalid
+  lsu.io.lsu_axi_rid := io.lsu_axi_rid
+  lsu.io.lsu_axi_rdata := io.lsu_axi_rdata
+  lsu.io.lsu_axi_rresp := io.lsu_axi_rresp
+  lsu.io.lsu_axi_rlast := io.lsu_axi_rlast
+  lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
+  lsu.io.dma_dccm_req := dma_ctrl.io.dma_dccm_req
+  lsu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag
+  lsu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr
+  lsu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz
+  lsu.io.dma_mem_write := dma_ctrl.io.dma_mem_write
+  lsu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata
+  lsu.io.scan_mode := io.scan_mode
+  lsu.io.free_clk := free_clk
+
+  // Debug lets go
+  dbg.reset := core_reset
+  dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
+  dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
+  dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
+  dbg.io.dma_dbg_ready := dma_ctrl.io.dma_dbg_ready
+  dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
+  dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
+  dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
+  dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
+  dbg.io.dmi_reg_en := io.dmi_reg_en
+  dbg.io.dmi_reg_addr := io.dmi_reg_addr
+  dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
+  dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
+  dbg.io.sb_axi_awready := io.sb_axi_awready
+  dbg.io.sb_axi_wready := io.sb_axi_wready
+  dbg.io.sb_axi_bvalid := io.sb_axi_bvalid
+  dbg.io.sb_axi_bresp := io.sb_axi_bresp
+  dbg.io.sb_axi_arready := io.sb_axi_arready
+  dbg.io.sb_axi_rvalid := io.sb_axi_rvalid
+  dbg.io.sb_axi_rdata := io.sb_axi_rdata
+  dbg.io.sb_axi_rresp := io.sb_axi_rresp
+  dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
+  dbg.io.dbg_rst_l := io.dbg_rst_l
+  dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
+  dbg.io.scan_mode := io.scan_mode
+
+
+  // DMA Lets go
+  dma_ctrl.reset := core_reset
+  dma_ctrl.io.free_clk := free_clk
+  dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
+  dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
+  dma_ctrl.io.scan_mode := io.scan_mode
+  dma_ctrl.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr
+  dma_ctrl.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
+  dma_ctrl.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid
+  dma_ctrl.io.dbg_cmd_write := dbg.io.dbg_cmd_write
+  dma_ctrl.io.dbg_cmd_type := dbg.io.dbg_cmd_type
+  dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
+  dma_ctrl.io.dbg_dma_bubble := dbg.io.dbg_dma_bubble
+  dma_ctrl.io.dccm_dma_rvalid := lsu.io.dccm_dma_rvalid
+  dma_ctrl.io.dccm_dma_ecc_error := lsu.io.dccm_dma_ecc_error
+  dma_ctrl.io.dccm_dma_rtag := lsu.io.dccm_dma_rtag
+  dma_ctrl.io.dccm_dma_rdata := lsu.io.dccm_dma_rdata
+  dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
+  dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
+  dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
+  dma_ctrl.io.dccm_ready := lsu.io.dccm_ready
+  dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
+  dma_ctrl.io.dec_tlu_dma_qos_prty := dec.io.dec_tlu_dma_qos_prty
+  dma_ctrl.io.dma_axi_awvalid := io.dma_axi_awvalid
+  dma_ctrl.io.dma_axi_awid := io.dma_axi_awid
+  dma_ctrl.io.dma_axi_awaddr := io.dma_axi_awaddr
+  dma_ctrl.io.dma_axi_awsize := io.dma_axi_awsize
+  dma_ctrl.io.dma_axi_wvalid := io.dma_axi_wvalid
+  dma_ctrl.io.dma_axi_wdata := io.dma_axi_wdata
+  dma_ctrl.io.dma_axi_wstrb := io.dma_axi_wstrb
+  dma_ctrl.io.dma_axi_bready := io.dma_axi_bready
+  dma_ctrl.io.dma_axi_arvalid := io.dma_axi_arvalid
+  dma_ctrl.io.dma_axi_arid := io.dma_axi_arid
+  dma_ctrl.io.dma_axi_araddr := io.dma_axi_araddr
+  dma_ctrl.io.dma_axi_arsize := io.dma_axi_arsize
+  dma_ctrl.io.dma_axi_rready := io.dma_axi_rready
+
+
+  // PIC lets go
+  pic_ctl_inst.reset := core_reset
+  pic_ctl_inst.io.free_clk := free_clk
+  pic_ctl_inst.io.active_clk := active_clk
+  pic_ctl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
+  pic_ctl_inst.io.extintsrc_req := io.extintsrc_req
+  pic_ctl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr
+  pic_ctl_inst.io.picm_wraddr := lsu.io.picm_wraddr
+  pic_ctl_inst.io.picm_wr_data := lsu.io.picm_wr_data
+  pic_ctl_inst.io.picm_wren := lsu.io.picm_wren
+  pic_ctl_inst.io.picm_rden := lsu.io.picm_rden
+  pic_ctl_inst.io.picm_mken := lsu.io.picm_mken
+  pic_ctl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
+  pic_ctl_inst.io.meipt := dec.io.dec_tlu_meipt
+
+
+
+
+
+
+
+}

src/main/scala/exu/el2_exu.scala

@@ -1,5 +1,295 @@
 package exu
+import chisel3._
+import scala.collection._
+import chisel3.util._
+import include._
+import lib._
 
-class el2_exu {
+class el2_exu extends Module with el2_lib with RequireAsyncReset{
+  val io=IO(new el2_exu_IO)
+  val PREDPIPESIZE 			= BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
+  val ghr_x_ns 				= Wire(UInt(BHT_GHR_SIZE.W))
+  val ghr_d_ns 				= Wire(UInt(BHT_GHR_SIZE.W))
+  val ghr_d	 				= Wire(UInt(BHT_GHR_SIZE.W))
+  val i0_taken_d				=Wire(UInt(1.W))
+  val mul_valid_x				=Wire(UInt(1.W))
+  val i0_valid_d				=Wire(UInt(1.W))
+  val flush_lower_ff			=Wire(UInt(1.W))
+  val data_gate_en			=Wire(UInt(1.W))
+  val csr_rs1_in_d			=Wire(UInt(32.W))
+  val i0_predict_newp_d 		=Wire(new el2_predict_pkt_t)
+  val i0_flush_path_d			=Wire(UInt(32.W))
+  val i0_predict_p_d			=Wire(new el2_predict_pkt_t)
+  val i0_pp_r					=Wire(new el2_predict_pkt_t)
+  val i0_predict_p_x			=Wire(new el2_predict_pkt_t)
+  val final_predict_mp		=Wire(new el2_predict_pkt_t)
+  val pred_correct_npc_r		=Wire(UInt(32.W))
+  val i0_pred_correct_upper_d	=Wire(UInt(1.W))
+  val i0_flush_upper_d		=Wire(UInt(1.W))
+  io.exu_mp_pkt.prett			:=0.U
+  io.exu_mp_pkt.br_start_error:=0.U
+  io.exu_mp_pkt.br_error		:=0.U
+  io.exu_mp_pkt.valid			:=0.U
+  val x_data_en                =  io.dec_data_en(1)
+  val r_data_en                =  io.dec_data_en(0)
+  val x_ctl_en                 =  io.dec_ctl_en(1)
+  val r_ctl_en                 =  io.dec_ctl_en(0)
+  val predpipe_d    = Cat(io.i0_predict_fghr_d, io.i0_predict_index_d, io.i0_predict_btag_d)
 
+
+  val i0_flush_path_x 	 	=rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode)
+  io.exu_csr_rs1_x			:=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode)
+  i0_predict_p_x				:=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode)
+  val predpipe_x   		 	=rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode)
+  val predpipe_r			 	=rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode)
+  val ghr_x					=rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode)
+  val i0_pred_correct_upper_x	=rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
+  val i0_flush_upper_x		=rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
+  val i0_taken_x				=rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode)
+  val i0_valid_x				=rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode)
+  i0_pp_r                     :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode)
+  val pred_temp1		        =rvdffe(io.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode)
+  val i0_pred_correct_upper_r	=rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode)
+  val i0_flush_path_upper_r	=rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode)
+  val pred_temp2				=rvdffe(io.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode)
+  pred_correct_npc_r			:=Cat(pred_temp2,pred_temp1)
+
+  when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){
+    ghr_d			:=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool)
+    mul_valid_x		:=RegEnable(io.mul_p.valid,0.U,data_gate_en.asBool)
+    flush_lower_ff	:=RegEnable(io.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)
+  }.otherwise{
+    ghr_d			:=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode)
+    mul_valid_x		:=rvdffe(io.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode)
+    flush_lower_ff	:=rvdffe(io.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode)
+  }
+
+
+  data_gate_en   	:=  (ghr_d_ns =/= ghr_d) | ( io.mul_p.valid  =/= mul_valid_x) | ( io.dec_tlu_flush_lower_r =/= flush_lower_ff)
+  val i0_rs1_bypass_en_d         = io.dec_i0_rs1_bypass_en_d(0) | io.dec_i0_rs1_bypass_en_d(1)
+  val i0_rs2_bypass_en_d         = io.dec_i0_rs2_bypass_en_d(0) | io.dec_i0_rs2_bypass_en_d(1)
+
+  val i0_rs1_bypass_data_d =	Mux1H(Seq(
+    io.dec_i0_rs1_bypass_en_d(0).asBool							-> io.dec_i0_rs1_bypass_data_d,
+    io.dec_i0_rs1_bypass_en_d(1).asBool 						-> io.exu_i0_result_x
+  ))
+
+  val i0_rs2_bypass_data_d =	Mux1H(Seq(
+    io.dec_i0_rs2_bypass_en_d(0).asBool							-> io.dec_i0_rs2_bypass_data_d,
+    io.dec_i0_rs2_bypass_en_d(1).asBool 						-> io.exu_i0_result_x
+  ))
+
+  val i0_rs1_d = Mux1H(Seq(
+    i0_rs1_bypass_en_d.asBool 														-> i0_rs1_bypass_data_d,
+    (~i0_rs1_bypass_en_d &  io.dec_i0_select_pc_d).asBool 							-> Cat(io.dec_i0_pc_d,0.U(1.W)),
+    (~i0_rs1_bypass_en_d &  io.dec_debug_wdata_rs1_d).asBool 						-> io.dbg_cmd_wrdata,
+    (~i0_rs1_bypass_en_d & ~io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool 	-> io.gpr_i0_rs1_d
+  ))
+
+  val i0_rs2_d=Mux1H(Seq(
+    (~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool 	-> io.gpr_i0_rs2_d,
+    (~i0_rs2_bypass_en_d).asBool						-> io.dec_i0_immed_d,
+    (i0_rs2_bypass_en_d).asBool							-> i0_rs2_bypass_data_d
+  ))
+
+  io.exu_lsu_rs1_d:=Mux1H(Seq(
+    (~i0_rs1_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool	 	-> io.gpr_i0_rs1_d,
+    (i0_rs1_bypass_en_d & ~io.dec_extint_stall).asBool								-> i0_rs1_bypass_data_d,
+    (io.dec_extint_stall).asBool													-> Cat(io.dec_tlu_meihap,0.U(2.W))
+  ))
+
+  io.exu_lsu_rs2_d:=Mux1H(Seq(
+    (~i0_rs2_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs2_en_d).asBool 	-> io.gpr_i0_rs2_d,
+    (i0_rs2_bypass_en_d & ~io.dec_extint_stall).asBool							-> i0_rs2_bypass_data_d
+  ))
+
+  val muldiv_rs1_d=Mux1H(Seq(
+    (~i0_rs1_bypass_en_d & io.dec_i0_rs1_en_d).asBool		-> io.gpr_i0_rs1_d,
+    (i0_rs1_bypass_en_d).asBool								-> i0_rs1_bypass_data_d
+  ))
+
+  val muldiv_rs2_d=Mux1H(Seq(
+    (~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool   	-> io.gpr_i0_rs2_d,
+    (~i0_rs2_bypass_en_d).asBool							-> io.dec_i0_immed_d,
+    (i0_rs2_bypass_en_d).asBool								-> i0_rs2_bypass_data_d
+  ))
+
+  csr_rs1_in_d       := Mux( io.dec_csr_ren_d.asBool, i0_rs1_d, io.exu_csr_rs1_x)
+
+
+  val i_alu=Module(new el2_exu_alu_ctl)
+  i_alu.io.scan_mode		:=io.scan_mode
+  i_alu.io.enable			:=x_ctl_en
+  i_alu.io.pp_in			:=i0_predict_newp_d
+  i_alu.io.valid_in		:=io.dec_i0_alu_decode_d
+  i_alu.io.flush_upper_x	:=i0_flush_upper_x
+  i_alu.io.flush_lower_r	:=io.dec_tlu_flush_lower_r
+  i_alu.io.a_in			:=i0_rs1_d.asSInt
+  i_alu.io.b_in			:=i0_rs2_d
+  i_alu.io.pc_in			:=io.dec_i0_pc_d
+  i_alu.io.brimm_in		:=io.dec_i0_br_immed_d
+  i_alu.io.ap				:=io.i0_ap
+  i_alu.io.csr_ren_in		:=io.dec_csr_ren_d
+  val alu_result_x   		 =i_alu.io.result_ff
+  i0_flush_upper_d   		:=i_alu.io.flush_upper_out
+  io.exu_flush_final		:=i_alu.io.flush_final_out
+  i0_flush_path_d			:=i_alu.io.flush_path_out
+  i0_predict_p_d			:=i_alu.io.predict_p_out
+  i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
+  io.exu_i0_pc_x			:=i_alu.io.pc_ff
+
+  val i_mul=Module(new el2_exu_mul_ctl)
+  i_mul.io.scan_mode		:=io.scan_mode
+  i_mul.io.mul_p			:=io.mul_p
+  i_mul.io.rs1_in			:=muldiv_rs1_d
+  i_mul.io.rs2_in			:=muldiv_rs2_d
+  val mul_result_x		 =i_mul.io.result_x
+
+  val i_div=Module(new el2_exu_div_ctl)
+  i_div.io.scan_mode		:=io.scan_mode
+  i_div.io.cancel			:=io.dec_div_cancel
+  i_div.io.dp				:=io.div_p
+  i_div.io.dividend		:=muldiv_rs1_d
+  i_div.io.divisor		:=muldiv_rs2_d
+  io.exu_div_wren			:=i_div.io.finish_dly
+  io.exu_div_result		:=i_div.io.out
+
+  io.exu_i0_result_x    		 := Mux(mul_valid_x.asBool, mul_result_x,  alu_result_x)
+  i0_predict_newp_d            :=  io.dec_i0_predict_p_d
+  i0_predict_newp_d.boffset    :=  io.dec_i0_pc_d(0)  // from the start of inst
+
+  io.exu_pmu_i0_br_misp       :=  i0_pp_r.misp
+  io.exu_pmu_i0_br_ataken     :=  i0_pp_r.ataken
+  io.exu_pmu_i0_pc4           :=  i0_pp_r.pc4
+
+
+  i0_valid_d               :=  i0_predict_p_d.valid  & io.dec_i0_alu_decode_d & ~io.dec_tlu_flush_lower_r
+  i0_taken_d               := (i0_predict_p_d.ataken & io.dec_i0_alu_decode_d)
+
+
+
+  // maintain GHR at D
+  ghr_d_ns:=Mux1H(Seq(
+    (~io.dec_tlu_flush_lower_r &  i0_valid_d).asBool		->  Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d),
+    (~io.dec_tlu_flush_lower_r & ~i0_valid_d).asBool		->	ghr_d,
+    (io.dec_tlu_flush_lower_r).asBool					->  ghr_x
+  ))
+
+  // maintain GHR at X
+  ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x )
+
+  io.exu_i0_br_valid_r             :=  i0_pp_r.valid
+  io.exu_i0_br_mp_r                :=  i0_pp_r.misp
+  io.exu_i0_br_way_r               :=  i0_pp_r.way
+  io.exu_i0_br_hist_r		 		 :=  i0_pp_r.hist
+  io.exu_i0_br_error_r          	 :=  i0_pp_r.br_error
+  io.exu_i0_br_middle_r            :=  i0_pp_r.pc4 ^ i0_pp_r.boffset
+  io.exu_i0_br_start_error_r       :=  i0_pp_r.br_start_error
+  io.exu_i0_br_fghr_r		 		 :=  predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1)
+  io.exu_i0_br_index_r		 	 :=  predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE)
+  final_predict_mp		 		 :=  Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x))
+  val final_predpipe_mp		  	  =  Mux(i0_flush_upper_x===1.U,predpipe_x,0.U)
+
+  val after_flush_eghr              = Mux((i0_flush_upper_x===1.U & ~(io.dec_tlu_flush_lower_r===1.U)),  ghr_d,  ghr_x)
+
+
+  io.exu_mp_pkt.way                :=  final_predict_mp.way
+  io.exu_mp_pkt.misp               :=  final_predict_mp.misp
+  io.exu_mp_pkt.pcall              :=  final_predict_mp.pcall
+  io.exu_mp_pkt.pja                :=  final_predict_mp.pja
+  io.exu_mp_pkt.pret               :=  final_predict_mp.pret
+  io.exu_mp_pkt.ataken             :=  final_predict_mp.ataken
+  io.exu_mp_pkt.boffset            :=  final_predict_mp.boffset
+  io.exu_mp_pkt.pc4                :=  final_predict_mp.pc4
+  io.exu_mp_pkt.hist		 		 :=  final_predict_mp.hist(1,0)
+  io.exu_mp_pkt.toffset		 	 :=  final_predict_mp.toffset(11,0)
+  io.exu_mp_fghr                   :=  after_flush_eghr
+  io.exu_mp_index			 		 :=  final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE)
+  io.exu_mp_btag			 		 :=  final_predpipe_mp(BTB_BTAG_SIZE-1,0)
+  io.exu_mp_eghr                   :=  final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write
+  io.exu_flush_path_final		 	 := Mux(io.dec_tlu_flush_lower_r.asBool, io.dec_tlu_flush_path_r,  i0_flush_path_d)
+  io.exu_npc_r			 		 := Mux(i0_pred_correct_upper_r===1.U,  pred_correct_npc_r, i0_flush_path_upper_r)
+}
+class el2_exu_IO extends Bundle with param{
+  val		scan_mode				=Input(Bool())                              // Scan control
+
+  val   	dec_data_en				=Input(UInt(2.W))                           // Clock enable {x,r}, one cycle pulse
+  val   	dec_ctl_en				=Input(UInt(2.W))                           // Clock enable {x,r}, two cycle pulse
+  val  	dbg_cmd_wrdata			=Input(UInt(32.W))                          // Debug data   to primary I0 RS1
+  val		i0_ap					=Input(new el2_alu_pkt_t)                   // DEC alu {valid,predecodes}
+
+  val		dec_debug_wdata_rs1_d	=Input(UInt(1.W))                           // Debug select to primary I0 RS1
+  val  	dec_i0_predict_p_d		=Input(new el2_predict_pkt_t)               // DEC branch predict packet
+
+  val		i0_predict_fghr_d		=Input(UInt(BHT_GHR_SIZE.W))                // DEC predict fghr
+  val		i0_predict_index_d		=Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))   // DEC predict index
+  val		i0_predict_btag_d		=Input(UInt(BTB_BTAG_SIZE.W))               // DEC predict branch tag
+
+  val		dec_i0_rs1_en_d			=Input(UInt(1.W))                           // Qualify GPR RS1 data
+  val		dec_i0_rs2_en_d			=Input(UInt(1.W))                           // Qualify GPR RS2 data
+  val		gpr_i0_rs1_d			=Input(UInt(32.W))                          // DEC data gpr
+  val		gpr_i0_rs2_d			=Input(UInt(32.W))                          // DEC data gpr
+  val		dec_i0_immed_d			=Input(UInt(32.W))                          // DEC data immediate
+  val		dec_i0_rs1_bypass_data_d=Input(UInt(32.W))                      	// DEC bypass data
+  val		dec_i0_rs2_bypass_data_d=Input(UInt(32.W))                      	// DEC bypass data
+  val		dec_i0_br_immed_d		=Input(UInt(12.W))                          // Branch immediate
+  val		dec_i0_alu_decode_d		=Input(UInt(1.W))                           // Valid to X-stage ALU
+  val		dec_i0_select_pc_d		=Input(UInt(1.W))                           // PC select to RS1
+  val		dec_i0_pc_d				=Input(UInt(31.W))                          // Instruction PC
+  val		dec_i0_rs1_bypass_en_d	=Input(UInt(2.W))                       	// DEC bypass select  1 - X-stage, 0 - dec bypass data
+  val		dec_i0_rs2_bypass_en_d	=Input(UInt(2.W))                        	// DEC bypass select  1 - X-stage, 0 - dec bypass data
+  val		dec_csr_ren_d			=Input(UInt(1.W))                           // Clear I0 RS1 primary
+
+  val		mul_p					=Input(new el2_mul_pkt_t)                   // DEC {valid, operand signs, low, operand bypass}
+  val		div_p					=Input(new el2_div_pkt_t)                   // DEC {valid, unsigned, rem}
+  val		dec_div_cancel			=Input(UInt(1.W))                           // Cancel the divide operation
+
+  val		pred_correct_npc_x		=Input(UInt(31.W))                          // DEC NPC for correctly predicted branch
+
+  val		dec_tlu_flush_lower_r	=Input(UInt(1.W))                         	// Flush divide and secondary ALUs
+  val		dec_tlu_flush_path_r	=Input(UInt(31.W))                          // Redirect target
+
+
+  val		dec_extint_stall		=Input(UInt(1.W))                           // External stall mux select
+  val		dec_tlu_meihap			=Input(UInt(30.W))                          // External stall mux data
+
+
+  val		exu_lsu_rs1_d			=Output(UInt(32.W))                         // LSU operand
+  val		exu_lsu_rs2_d			=Output(UInt(32.W))                         // LSU operand
+
+  val		exu_flush_final			=Output(UInt(1.W))                          // Pipe is being flushed this cycle
+  val		exu_flush_path_final	=Output(UInt(31.W))                         // Target for the oldest flush source
+
+  val		exu_i0_result_x			=Output(UInt(32.W))                         // Primary ALU result to DEC
+  val		exu_i0_pc_x				=Output(UInt(31.W))                         // Primary PC  result to DEC
+  val		exu_csr_rs1_x			=Output(UInt(32.W))                         // RS1 source for a CSR instruction
+
+  val		exu_npc_r				=Output(UInt(31.W))                         // Divide NPC
+  val		exu_i0_br_hist_r		=Output(UInt(2.W))                          // to DEC  I0 branch history
+  val		exu_i0_br_error_r		=Output(UInt(1.W))                          // to DEC  I0 branch error
+  val		exu_i0_br_start_error_r	=Output(UInt(1.W))                       	// to DEC  I0 branch start error
+  val		exu_i0_br_index_r		=Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))  // to DEC  I0 branch index
+  val		exu_i0_br_valid_r		=Output(UInt(1.W))                          // to DEC  I0 branch valid
+  val		exu_i0_br_mp_r			=Output(UInt(1.W))                          // to DEC  I0 branch mispredict
+  val		exu_i0_br_middle_r		=Output(UInt(1.W))                          // to DEC  I0 branch middle
+  val		exu_i0_br_fghr_r		=Output(UInt(BHT_GHR_SIZE.W))               // to DEC  I0 branch fghr
+  val		exu_i0_br_way_r			=Output(UInt(1.W))                          // to DEC  I0 branch way
+  val		exu_mp_pkt				=Output(new el2_predict_pkt_t)              // Mispredict branch packet
+  val		exu_mp_eghr				=Output(UInt(BHT_GHR_SIZE.W))               // Mispredict global history
+  val		exu_mp_fghr				=Output(UInt(BHT_GHR_SIZE.W))               // Mispredict fghr
+  val		exu_mp_index			=Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))  // Mispredict index
+  val		exu_mp_btag				=Output(UInt(BTB_BTAG_SIZE.W))              // Mispredict btag
+
+
+  val		exu_pmu_i0_br_misp		=Output(UInt(1.W))                          // to PMU - I0 E4 branch mispredict
+  val		exu_pmu_i0_br_ataken	=Output(UInt(1.W))                          // to PMU - I0 E4 taken
+  val		exu_pmu_i0_pc4			=Output(UInt(1.W))                          // to PMU - I0 E4 PC
+
+
+  val		exu_div_result			=Output(UInt(32.W))                         // Divide result
+  val		exu_div_wren			=Output(UInt(1.W))                          // Divide write enable to GPR
+}
+
+object exu_gen extends App{
+  println(chisel3.Driver.emitVerilog(new el2_exu()))
 }

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -59,6 +59,8 @@ class mem_ctl_bundle extends Bundle with el2_lib{
   val ifu_pmu_bus_error = Output(Bool())
   val ifu_pmu_bus_busy = Output(Bool())
   val ifu_pmu_bus_trxn = Output(Bool())
+
+
   val ifu_axi_awvalid = Output(Bool())
   val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
   val ifu_axi_awaddr = Output(UInt(32.W))

src/main/scala/lsu/el2_lsu.scala

@@ -27,8 +27,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
     val dec_tlu_mrac_ff                   = Input(UInt(32.W))
 
     //Outputs
-    //  val lsu_result_m                      = Output(UInt(32.W))
+    val lsu_result_m                      = Output(UInt(32.W))
-    //  val lsu_result_corr_r                 = Output(UInt(32.W))
+    val lsu_result_corr_r                 = Output(UInt(32.W))
     val lsu_load_stall_any                = Output(Bool())
     val lsu_store_stall_any               = Output(Bool())
     val lsu_fastint_stall_any             = Output(Bool())
@@ -152,6 +152,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
   val lsu_raw_fwd_hi_r             = WireInit(0.U(1.W))
 
   val lsu_lsc_ctl    = Module(new el2_lsu_lsc_ctl )
+  io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
+  io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
   val dccm_ctl       = Module(new el2_lsu_dccm_ctl )
   val stbuf          = Module(new el2_lsu_stbuf )
   val ecc            = Module(new el2_lsu_ecc )

src/main/scala/lsu/el2_lsu_bus_buffer.scala

@@ -40,7 +40,6 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
     val ldst_dual_m = Input(Bool())
     val ldst_dual_r = Input(Bool())
     val ldst_byteen_ext_m = Input(UInt(8.W))
-    val lsu_axi_awready = Input(Bool())
     val lsu_axi_wready = Input(Bool())
     val lsu_axi_bvalid = Input(Bool())
     val lsu_axi_bresp = Input(UInt(2.W))
@@ -77,7 +76,10 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
     val lsu_pmu_bus_misaligned = Output(Bool())
     val lsu_pmu_bus_error = Output(Bool())
     val lsu_pmu_bus_busy = Output(Bool())
+
+    // AXI Signals
     val lsu_axi_awvalid = Output(Bool())
+    val lsu_axi_awready = Input(Bool())
     val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
     val lsu_axi_awaddr = Output(UInt(32.W))
     val lsu_axi_awregion = Output(UInt(4.W))